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WO2019102073A1 - Structure semi-conductrice photovoltaïque - Google Patents

Structure semi-conductrice photovoltaïque Download PDF

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Publication number
WO2019102073A1
WO2019102073A1 PCT/FI2018/050854 FI2018050854W WO2019102073A1 WO 2019102073 A1 WO2019102073 A1 WO 2019102073A1 FI 2018050854 W FI2018050854 W FI 2018050854W WO 2019102073 A1 WO2019102073 A1 WO 2019102073A1
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Prior art keywords
layer
type
photovoltaic
photovoltaic semiconductor
semiconductor structure
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Inventor
Toni PASANEN
Hele Savin
Ville VÄHÄNISSI
Hannu Laine
Chiara MODANESE
Franziska Wolny
Matthias Wagner
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Aalto Korkeakoulusaatio sr
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Aalto Korkeakoulusaatio sr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
    • H10F77/315—Coatings for devices having potential barriers for photovoltaic cells the coatings being antireflective or having enhancing optical properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/707—Surface textures, e.g. pyramid structures of the substrates or of layers on substrates, e.g. textured ITO layer on a glass substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure concerns the field of semiconductor photovoltaics .
  • this dis closure concerns silicon photovoltaics.
  • Photovoltaics refers to converting light into electrical energy using an active material, such as a semiconductor.
  • silicon is the most commonly used active material for various types of de vices, including solar cells and photodetectors.
  • Photovoltaic structures may utilize textured active material front surfaces in order to increase their overall absorbance.
  • the surface area of any textured front surfaces must be kept reasonably low, since the surface of an active material is gener ally a significant site for carrier recombination. This limits the degree to which the absorbance of con ventional photovoltaic structures may be increased.
  • Another key challenge in conventional Si pho tovoltaics is the degradation of light-to-electricity conversion efficiency over time during operation. This phenomenon is commonly referred to as light-induced degradation or carrier-induced degradation.
  • Some pho tovoltaic structures, such as the passivated emitter and rear cell structure, are especially susceptible to light-induced degradation.
  • a layered photo voltaic semiconductor structure extending in a lateral direction.
  • the photovoltaic semiconductor structure comprises a p-type silicon (Si) layer having a bulk refractive index; an n-type Si layer on the p-type Si layer, the n-type Si layer having a textured surface opposite the p-type Si layer; a first dielec tric layer on the textured surface, the first dielec- trie layer having a front surface opposite the n-type Si layer, the front surface defining a front side of the photovoltaic semiconductor structure; and a second dielectric layer on a side of the p-type Si layer op posite the n-type Si layer.
  • the textured surface comprises high aspect ratio nanostructures extending in a direction substantially perpendicular to the lateral direction, the nanostruc tures forming an optical conversion layer having an effective refractive index gradually changing towards the bulk refractive index to reduce reflection of light incident on the photovoltaic semiconductor structure from the front side thereof.
  • the second dielectric layer is patterned with a through- hole and the photovoltaic semiconductor structure fur ther comprises a conductive back layer on a side of the second dielectric layer opposite the p-type Si layer, a galvanic contact existing between the conduc- tive back layer and the p-type Si layer via the through-hole; and a front contact, for example, a front contact finger, on a side of the first dielec tric layer opposite the n-type Si layer, a galvanic contact existing between the front contact and the n-type Si layer.
  • the photovoltaic semiconductor structure is or forms a part of a passivated emitter and rear cell (PERC) pho tovoltaic device or structure.
  • PERC passivated emitter and rear cell
  • the first dielectric layer covers the nanostructures in a substantially conformal manner.
  • the first die lectric layer is formed by atomic layer deposition (ALD) .
  • the nanostructures are formed by deep reactive ion etching (DRIE) .
  • DRIE deep reactive ion etching
  • a ratio, S f between a surface area of a macro scopic portion of the textured surface and a surface area of a polished surface corresponding to the macro scopic portion, e.g., a highest projected area of the macroscopic portion, is more than 3, or at least 4, or at least 5, or in a range from 5 to 7.
  • the nanostructures are black silicon (b-Si) spikes .
  • the nanostructures may have their average height in a direction perpendicular to the lateral di rection in a range from 500 nanometers (nm) to 1500 nm, or from about 600 nm to 1000 nm, or from 800 nm to 1000 nm, and their average width in the lat eral direction in a range from 50 nm to 400 nm, or from 100 nm to 400 nm, or from 200 nm to 300 nm.
  • the p-type Si layer and the n-type Si layer are multicrystalline silicon (mc-Si) layers or quasi monocrystalline silicon (qm-Si) layers.
  • the p-type Si layer comprises boron as a dopant and/or the n-type Si layer comprises phosphorus as a dopant .
  • the first dielectric layer comprises a trans parent oxide and/or nitride, e.g., silicon oxide (SiCy) , non-stoichiometric silicon oxide (SiO x ) , alu minium oxide (AI2O3) , non-stoichiometric aluminium ox ide (AIO c ) , silicon nitride (Si 3 N 4 ) , and/or non- stoichiometric silicon nitride (SiN x ) .
  • a trans parent oxide and/or nitride e.g., silicon oxide (SiCy) , non-stoichiometric silicon oxide (SiO x ) , alu minium oxide (AI2O3) , non-stoichiometric aluminium ox ide (AIO c ) , silicon nitride (Si 3 N 4 ) , and/or non- stoichiometric silicon n
  • the second dielectric layer comprises a trans parent oxide and/or nitride, e.g., silicon oxide (SiCy) , non-stoichiometric silicon oxide (SiO x ) , alu minium oxide (AI 2 O 3 ) , non-stoichiometric aluminium ox ide (A10 x ) , silicon nitride (Si 3 N 4 ) , and/or non- stoichiometric silicon nitride (SiN x ) .
  • a trans parent oxide and/or nitride e.g., silicon oxide (SiCy) , non-stoichiometric silicon oxide (SiO x ) , alu minium oxide (AI 2 O 3 ) , non-stoichiometric aluminium ox ide (A10 x ) , silicon nitride (Si 3 N 4 ) , and/or non- stoichio
  • the photovoltaic semiconductor structure is configured for use as or in a photovoltaic device, e.g., a photodetector or a solar cell, and configured to receive and absorb light incident on the photovol- taic semiconductor structure from the front side thereof .
  • a photovoltaic device e.g., a photodetector or a solar cell
  • a method for manufacturing a layered photovoltaic semiconductor structure extending in a lateral direction comprises the steps of providing a p-type Si substrate having a bulk refractive index; forming a textured surface on one side of the p-type Si substrate; forming an n-type Si layer in the p-type substrate, the n-type Si layer extending from the tex tured surface, whereby a p-type layer is defined in the p-type substrate; forming a first dielectric layer on the textured surface, the first dielectric layer having a front surface opposite the n-type Si layer, the front surface defining a front side of the semi conductor structure; and forming a second dielectric layer on a side of the p-type Si substrate opposite the n-type Si layer, wherein the textured surface com prises high aspect ratio nanostructures extending in a direction substantially perpendicular to the lateral direction, the nanostructures
  • the method further comprises the steps of forming a through-hole in the second dielectric layer; forming a conductive back layer on a side of the second dielec tric layer opposite the p-type Si layer such that a galvanic contact is formed between the conductive back layer and the p-type Si layer via the through-hole; and forming a front contact, for example, a front con tact finger, on a side of the first dielectric layer opposite the n-type Si layer such that a galvanic con tact is formed between the front contact and the n-type Si layer.
  • the nanostructures are formed by metal-assisted chemical etching (MACE) , atmospheric dry etching (ADE) , or re active ion etching (RIE) , such as deep reactive ion etching (DRIE) .
  • MACE metal-assisted chemical etching
  • ADE atmospheric dry etching
  • RIE re active ion etching
  • DRIE deep reactive ion etching
  • the photovoltaic semicon ductor structure is a photovoltaic semiconductor structure according to the first aspect or any embodi ment of the first aspect. It is specifically to be un derstood that the method according to the second as pect may be used to provide a photovoltaic semiconduc tor structure according to the first aspect and any number of embodiments described in relation to the first aspect.
  • the present dis closure relates to use of high aspect ratio nanostruc tures in a photovoltaic semiconductor structure for reducing light-induced degradation (LID), e.g., boron- oxygen related LID (BO-LID) , sponge LID, copper- related LID (Cu-LID) , hydrogen-induced degrada tion (HID), and/or light and elevated-temperature in Jerusalem degradation (LeTID) .
  • LID light-induced degradation
  • BO-LID boron- oxygen related LID
  • Cu-LID copper- related LID
  • HID hydrogen-induced degrada tion
  • LeTID light and elevated-temperature in Jerusalem degradation
  • the photovoltaic semiconductor structure is configured for use as or in a photovoltaic device, e.g., a photode tector or a solar cell, and configured to receive and absorb light incident on the photovoltaic semiconduc tor structure from a front side thereof.
  • a photovoltaic device e.g., a photode tector or a solar cell
  • the photovoltaic semiconductor structure is a photovoltaic semiconductor structure according to the first aspect or any embodiment of the first aspect. It is specifi cally to be understood that high aspect ratio nanostructures may be used according to the third as pect or any embodiment of the third aspect for reduc ing LID in a photovoltaic semiconductor structure ac cording to the first aspect or any embodiment of the first aspect.
  • FIG. 1 shows a partial cross-sectional view of a part of a photovoltaic semiconductor structure
  • FIG. 2 depicts a partial cross-sectional view of another photovoltaic semiconductor structure as well as a detailed view of certain structural features in said photovoltaic semiconductor structure
  • FIG. 3 illustrates a method for manufacturing a layered photovoltaic semiconductor structure.
  • optional steps are preceded by a dotted arrow and bounded by a dashed box.
  • any drawing of the aforementioned drawings may be not drawn to scale such that any element in said drawing may be drawn with unrealistic proportions with respect to other elements in said drawing in order to empha size certain structural aspects of the embodiment of said drawing.
  • corresponding elements in the em bodiments of any two drawings of the aforementioned drawings may be disproportionate to each other in said two drawings in order to emphasize certain structural aspects of the embodiments of said two drawings.
  • LID Light-induced degradation
  • Carri er-induced degradation may refer to degradation of light-to-electricity conversion efficiency over time during operation of photovoltaics .
  • LID may be quanti fiable, for example, after an illumination time of about 1 hour (h) , about 10 h, about 100 h, and/or about 1000 h .
  • LID may be categorized according to sus pected LID-responsible defects and/or other mechanism- related factors at least as boron-oxygen related LID (BO-LID) , sponge LID, copper-related LID (Cu-LID) , hy drogen-induced degradation (HID) , or light and elevat ed-temperature induced degradation (LeTID) .
  • BO-LID boron-oxygen related LID
  • Cu-LID copper-related LID
  • HID hy drogen-induced degradation
  • LeTID light and elevat ed-temperature induced degradation
  • a "semiconductor” may refer to a material possessing a conductivity interme diate between the conductivity of conductive materi als, such as metals, and the conductivity of insulat ing materials, such as many plastics and glasses.
  • a semiconductor may have, for example, a crystalline, such as monocrystalline, quasi-monocrystalline, or mul ticrystalline; semi-crystalline; or amorphous (i.e., non-crystalline) structure.
  • Silicon (Si) is one exam ple of a semiconductor, or semiconducting, material. As such, Si may have a monocrystalline, quasi- monocrystalline, multicrystalline, semicrystalline, or amorphous structure.
  • qm-Si quadsi monocrystalline silicon
  • qm-Si may refer to a sili con material grown by casting using monocrystalline silicon seeds. Additionally or alternatively, qm-Si may have a dislocation density higher than convention al monocrystalline silicon grown, for example, by a Czochralski process. Additionally or alternatively, qm-Si may comprise small-angle grain boundaries, which may be absent from or atypical for conventional mono crystalline silicon. Additionally or alternatively, qm-Si may have an oxygen concentration lower than a typical oxygen concentration of conventional monocrys talline silicon.
  • photovoltaics may refer to a field of technology aimed at converting light to electrical energy using a light-absorbing active mate rial, such as a semiconductor, and/or to devices and structures configured to convert light to electrical energy using such active material (s) . Consequently, “semiconductor photovoltaics” may refer to photovolta ics, wherein a semiconductor is used as an active ma terial .
  • a “semiconductor structure” may refer to a structure which may comprise all or only part of structural parts, layers, and/or elements of a complete, operational semiconductor com ponent, element, or device such as a solar cell or a photodetector.
  • the term “struc ture” may thus be considered as a structure "for", or a building block of, such component, element, or de vice.
  • a semiconductor structure may generally comprise non-semiconducting materials, such as conductors and/or insulators, in addition to semi conductor materials.
  • a photovoltaic semiconductor structure may herein refer to a semiconductor struc ture configured, when used as or in an operational semiconductor component, element, or device, to con vert light to electrical energy using an active semi conductor material. Additionally or alternatively, a photovoltaic semiconductor structure may refer to a semiconductor structure comprising a functional p-n junction.
  • a "functional p-n junction" may herein refer to a boundary or interface between a p-type and an n-type semiconductor that allows electrical current to flow preferentially in one direction through the boundary or interface. Additionally or alternatively, a p-n junction may refer to a boundary or interface between a p-type and an n-type semiconductor bounded under thermal equilibrium by a space charge region (i.e., a depletion region).
  • a "p-type" semiconductor may refer to a semi conductor having a higher equilibrium concentration of holes than electrons.
  • a p-type semiconductor may be formed by doping an intrinsic semiconductor with an electron-accepting (i.e., p-type) dopant.
  • p-type Si may comprise a significant concentration, such as from 1 0 13 CITT 3 to 1 0 2 1 CITT 3 , of a p-type dopant, e.g., boron (B) or gallium (Ga) .
  • an "n-type" semiconductor may refer to a semiconductor having a higher equilib rium concentration of electrons than holes.
  • An n-type semiconductor may be formed by doping an intrinsic semiconductor with an electron-donating (i.e., n-type) dopant.
  • n-type Si may comprise a signifi cant concentration, such as from 1 0 13 CITT 3 to 1 0 2 1 CITT 3 , of an n-type dopant, e.g., phosphorus (P) or arsenic (As) .
  • An "intrinsic" or “undoped” semiconductor may refer to a semiconductor not comprising a significant concentration of dopant species, such as dopant atoms.
  • a number of electrons in a conduction band may equal a number of holes in a va lence band.
  • P-type or n-type doping of an intrinsic semiconductor, such as pure Si may be achieved, for example, by adding dopant species during semiconductor growth, via diffusion processes, and/or by ion implan tation .
  • FIG. 1 depicts a cross section of a layered photovoltaic semiconductor structure 100 extending in a lateral direction 101.
  • the embodiment of FIG. 1 may generally com prise any features and/or elements of the embodiment of FIG. 2, which are omitted from FIG. 1.
  • a photovoltaic semiconductor structure being "layered” and “extending in a lateral direction” may refer to a generally layer-formed structure of the photovoltaic semiconductor structure having a width in the lateral direction substantially larger than a height in a direction perpendicular to the lateral di- rection. Additionally or alternatively, a photovoltaic semiconductor structure "extending in a lateral direc tion” may herein refer to said structure extending along said lateral direction and/or along a surface, which may be planar, flat, or only slightly curved, said surface extending laterally along said lateral direction .
  • the photovoltaic semiconductor structure 100 is configured for use in a photovoltaic device, e.g., a photodetector or a solar cell, and configured to receive and absorb light inci dent on the photovoltaic semiconductor structure 100 from a front side thereof (see below) .
  • the photovolta ic semiconductor structure 100 is configured for use in a solar cell and configured to receive and absorb solar radiation.
  • light may refer to electromagnetic radiation of any wavelength within a range of relevant wavelengths.
  • the range of relevant wavelengths may overlap or coincide with ultraviolet (wavelength from about 10 nanometers (nm) to about 400 nm) , visible (wavelength from about 400 nm to about 700 nm) , and/or infrared (wavelength from about 700 nm to about 1 millimeter (mm)) parts of electro magnetic spectrum.
  • a photovoltaic semicon ductor structure may be configured and/or suitable for use as and/or in a photovoltaic device and/or any oth er type of photovoltaic semiconductor structure known in the art.
  • said photovol taic semiconductor structure may be configured to re ceive and absorb and/or suitable for receiving and ab sorbing light incident on the photovoltaic semiconduc tor structure from any or all side (s) thereof.
  • a pho tovoltaic semiconductor structure may generally be configured for use in a solar cell and configured to receive and absorb solar radiation.
  • the photovoltaic semiconductor structure 100 comprises a p-type Si lay er 102 having a bulk refractive index n b , and an n-type Si layer 103 is arranged thereon.
  • the p-type Si layer 102 and the n-type Si layer 103 form a function al p-n junction at an interface of the p-type Si lay er 102 and the n-type Si layer 103.
  • a p-type Si layer and an n-type Si layer may form a functional p-n junction at an interface of said p-type Si layer and said n-type Si layer.
  • the interface between the p-type Si layer 102 and the n-type Si lay er 103 is flat.
  • an interface be tween a p-type Si layer and an n-type Si layer may have a flat, curved, or any other suitable shape.
  • the p-type Si layer 102 comprises boron as a dopant and the n-type Si layer 103 comprises phosphorus as a dopant.
  • a p-type Si layer may comprise boron and/or any other suitable p-type dopant.
  • an n-type Si layer may comprise a substantial amount of phosphorus and/or any other suitable n-type dopant. Additionally or alternatively, at least part of an n-type Si layer may comprise a high concentration, i.e., at least 10 18 CITT 3 , or at least 10 19 CITT 3 , or at least 10 20 CITT 3 , of phosphorus as a dopant .
  • At least part of an n-type Si layer comprising a high concentration of phosphorus as a dopant may enhance gettering of LID-responsible defects.
  • gettering may refer to the removal of defects, espe cially LID-responsible defects, such as impurities, for example, impurity atoms (e.g., iron atoms), from an active material of a photovoltaic semiconductor structure, and/or it may refer to gathering defects, especially LID-responsible defects, to grain and/or material boundaries.
  • the p-type Si lay er 102 and the n-type Si layer 103 are multicrystal line silicon (mc-Si) layers.
  • a p-type Si layer may be monocrystalline, quasi-monocrystalline, multicrys talline, semicrystalline, or amorphous.
  • an n-type Si layer may be monocrystal line, quasi-monocrystalline, multicrystalline, semi- crystalline, or amorphous.
  • a p-type Si layer and an n-type Si layer may have identical, corresponding, or similar structures, and/or said p-type Si layer and said n-type Si layer may form a single monolithic Si substrate.
  • a “substrate” may re fer to a solid body providing a surface, which may be flat or only slightly curved, such that material may be arranged, deposited, etched, and/or inscribed on the surface.
  • a substrate may comprise a wafer, comprising a semiconductor material, such as Si, suitable for manufacturing various semiconductor structures and/or devices, e.g., integrated circuits, solar cells, or photodetectors.
  • Si layer being multicrystalline may enable the utili zation of a mc-Si substrate in the fabrication of a photovoltaic semiconductor structure. Utilization of such mc-Si substrates may, for example, improve an En- ergy Return on Energy Invested (ERoEI) metric of a photovoltaic semiconductor structure.
  • a p-type Si layer and an n-type Si layer being quasi-monocrystalline may enable the utilization of a qm-Si substrate, which may provide a balanced trade- off between light-to-electricity efficiency and scala bility.
  • the n-type Si layer 103 has a textured surface 104 opposite the p-type Si layer 102.
  • a "textured" surface may refer to a non-smooth and/or patterned surface.
  • a textured sur face may generally have a regular texture or an irreg ular texture.
  • a textured surface having an irregular texture may improve optical properties of a photovol taic semiconductor structure.
  • the textured sur face 104 has at least a sufficient size in the lateral direction 101 that a macroscopic portion of the tex tured surface 104 may be defined. Additionally, a ra tio, S f , between a surface area of a macroscopic por tion of the textured surface 104 and a surface area of a polished surface corresponding to the macroscopic portion, e.g., a highest projected area of the macro scopic portion, is more than 3, or at least 4, or at least 5, or in a range from 5 to 7.
  • a photovoltaic semiconductor structure with an S f of more than 3, or at least 4, or at least 5, or in a range from 5 to 7, may experience weaker LID than photovoltaic semiconductor structures with lower values of S f . This may be especially so if said photovoltaic semiconductor structure comprises an n-type Si layer comprising phosphorus as a dopant.
  • macroscopic portion may refer to a portion sufficiently large to be visi ble to the naked eye. Additionally or alternatively, a macroscopic portion may have a size such that a high est projected area of the macroscopic portion is at least 0.01 mm 2 , or at least 0.1 mm 2 , or at least 1 mm 2 , or at least 10, or at least 100 mm 2 . Additionally or alternatively, a macroscopic portion may encompass at least 2500, or at least 10000, or at least 1000000 texture units, such as high aspect ratio nanostruc tures (see below) .
  • projected area may refer to an area of a projection of an object onto an arbitrary plane. Consequently, a “highest” projected area may refer to an area of a projection of an object onto a plane such that the projection has an area higher than or equal to the area of any other planar projection of said ob ject. Such plane may extend, for example, along a lat eral direction.
  • the textured surface 104 comprises high aspect ratio nanostruc- tures 105 that extend in a direction substantially perpendicular to the lateral direction 101.
  • the nanostructures 105 have been depicted with greatly exaggerated sizes for illustrative purposes.
  • Nanostructure may herein refer to a struc ture having at least one characteristic dimension in the sub-micron range, i.e., equal to or less than a micrometer. From an optical point of view, such dimen sions fall substantially in the range of, or below, relevant wavelengths in typical photovoltaics .
  • High aspect ratio nanostructures extending in a direction substantially perpendicular to the lat eral direction may refer to nanostructures having their height multiple times their lateral dimensions.
  • Such nanostructures may comprise, for example, cylin drical pillars, conical pillars, or narrow pyramids.
  • a first direction be ing "substantially perpendicular" to a second direc tion may refer to the first direction forming a small- est positive angle of at least 75°, or at least 80°, or at least 85°, or about 90°, with the second direc tion in a vector sense.
  • high aspect ratio nanostructures extending in a direction substantially perpendicular to a lateral direction may reduce, or suppress, LID in a photovoltaic semiconductor structure.
  • the high aspect ratio nanostructures 105 are formed by deep reactive ion etching (DRIE) .
  • DRIE deep reactive ion etching
  • RIE reactive ion etching
  • high aspect ratio nanostructures may be formed by RIE, such as DRIE, or by any other suitable method known in the art.
  • the photovoltaic semiconductor structure 100 further comprises a first dielectric layer 107 on the textured surface 104 oppo site the p-type Si layer 102.
  • the first dielectric layer 107 has a front surface 108 opposite the n-type Si layer 103, the front surface 108 defining the front side of the photovoltaic semiconductor structure 100.
  • a first dielectric layer on a textured surface may passivate said textured surface.
  • a surface becoming “passivated” may refer to a surface, following the provision of a passivating sur face layer (e.g., said first dielectric layer), becom ing less affected by external stimuli and/or causing reduced surface recombination of charge carriers.
  • the first die lectric layer 107 covers the high aspect ratio nanostructures 105 in a substantially conformal man ner.
  • Such conformal coating may be achieved, for exam ple, by forming the first dielectric layer by atomic layer deposition (ALD) .
  • ALD atomic layer deposition
  • a first dielectric layer may cover the textured surface in substantially conformal manner or in any other suita ble manner, and the first dielectric layer may be formed by ALD or by any other suitable method known in the art .
  • a layer covering a nanostructure in a "sub stantially conformal manner” may refer to the layer following the nanostructure with a substantially uni form thickness.
  • a “substantially uniform thickness” may refer to a relative standard deviation in thickness of less than 50 %, or less than 25 %, or less than 15 %, and/or to a standard deviation in thickness of less than 20 nm, or less than 10 nm, or less than 5 nm.
  • a thickness of a first dielectric layer may be measureable from a front surface to a textured surface along a surface normal of the tex tured surface.
  • the thickness may be equal to a length of a shortest line segment extending from a measurement point on the front surface to the tex tured surface along a surface normal of the textured surface .
  • a first dielectric layer covering high aspect ratio nanostructures in a substantially conformal man ner may provide an efficiently passivated textured surface .
  • the thickness of the first dielectric layer 107 is, on average, in a range from about 5 nm to 40 nm, or from about 5 nm to 20 nm, or from about 5 nm to 15 nm, or from about 5 nm to about 10 nm. Such thickness may generally facili tate forming electrical contacts for an n-type Si lay er.
  • a first dielectric layer may have a similar thickness or any other suitable thick ness.
  • a first dielectric layer may generally be sub stantially pinhole-free, comprising an insubstantial number of pinholes per unit area.
  • the first die lectric layer 107 comprises non-stoichiometric alumin ium oxide (AIOc) .
  • a first die lectric layer may comprise A10 x and/or any other suit able material (s) , for example, a transparent oxide and/or nitride, e.g., silicon oxide (Si0 2) , non- stoichiometric silicon oxide (SiO x) , aluminium oxide (AI2O3) , silicon nitride (S 3N 4) , and/or non- stoichiometric silicon nitride (SiN x) .
  • a transparent oxide and/or nitride e.g., silicon oxide (Si0 2) , non- stoichiometric silicon oxide (SiO x) , aluminium oxide (AI2O3) , silicon nitride (S 3N 4) , and/or non- stoichiometric silicon nitrid
  • transparent or “transparency” may refer to a capability of a layer formed of a transpar ent material to transmit a main portion of irradiance of light at a relevant wavelength range incident on such layer.
  • said relevant wavelength range may refer to intended operation wavelengths of said photovoltaic semiconductor structure.
  • a transparent layer may transmit 50 % or more, or 80 % or more, of irradiance of light energy at a relevant wavelength range incident onto it.
  • An increase in transparency of dielectric layers may generally improve a light-to- electricity conversion efficiency of a photovoltaic semiconductor structure.
  • first dielectric layer comprising A10 x may passivate a Si surface, such as a b-Si surface, efficiently due to a high-quality interface with Si.
  • A10 x may passivate b-Si surfaces particu larly efficiently due to a high density of negative fixed charges in A10 x .
  • the high aspect ra tio nanostructures 105 form an optical conversion lay er 106 having an effective refractive index n eff gradu ally changing towards the bulk refractive index n b to reduce reflection of light incident on the photovolta ic semiconductor structure 100 from the front side thereof .
  • An "optical conversion layer” may refer to a layer, which may be indefinable based on continuous material interfaces, such as lateral interfaces, hav ing an effective refractive index n eff which gradually changes from an ambient refractive index n b towards a bulk refractive index n b to reduce reflection of light incident on a photovoltaic semiconductor structure from a front side thereof.
  • the effective refractive index may gradually change from 1 to the bulk refractive index n b .
  • Effective refractive index is an auxiliary definition related to interaction of light with a nanostructured material layer. Sub-wavelength features or features substantially in the range of relevant wavelengths make light behave in such a nanostructured layer differently from a corresponding layer of the same material without the nanostructures. This differ ent behavior can be described by the auxiliary term "effective refractive index"; light behaves in, and interacts with, such a nanostructured material layer as if the layer would be made of a gradually changing bulk material having, at each level of the conversion layer, a refractive index equal to the effective re fractive index n eff at that level.
  • the nanostruc tures 105 are black silicon (b-Si) spikes.
  • black silicon may refer to a class of nanoscale sur face formations on Si, producing an optical conversion layer having a gradually changing effective refractive index.
  • a b-Si surface may comprise a plurality of nee dle- and/or spike-like surface formations. Individual surface formations of such a plurality of surface for mations may be of varying sizes and/or arranged irreg ularly.
  • nanostructures may be b-Si spikes or any other nanostructures suitable for forming an optical conversion layer having an effec tive refractive index gradually changing towards a bulk refractive index.
  • nanostructures being b-Si spikes may, for example, improve efficiency of a photovoltaic semiconductor structure at high incidence angles, such as incidence angles larger than 60°.
  • an "incidence angle”, or “angle of incidence” may refer to a smallest angle between a propagation direction of a ray of light in cident on a surface and a normal of the surface ex tending from a point of incidence of said ray of light. Additionally or alternatively, an incidence an gle may refer to a smallest angle between a propaga tion direction of light incident on a macroscopic por tion of a textured surface and a normal of a polished surface corresponding to the macroscopic portion, e.g., a normal of a plane corresponding to a highest projected area of the macroscopic portion.
  • the nanostruc tures 105 have their average height in a direction perpendicular to the lateral direction in a range from 500 nm to 1500 nm, or from about 600 nm to 1000 nm, or from 800 nm to 1000 nm, and their average width in the lateral direction 101 in a range from 50 nm to 400 nm, or from 100 nm to 400 nm, or from 200 nm to 300 nm.
  • nanostructures may have average heights and/or widths identical, similar, or different to the average height and/or width, respectively, of the nanostructures 105 of the embodiment of FIG. 1.
  • High aspect ratio nanostructures having their average height in a direction perpendicular to the lateral direction in a range from 500 nm to 1500 nm, or from about 600 nm to 1000 nm, or from 800 nm to 1000 nm, and their average width in a lateral direc tion in a range from 50 nm to 400 nm, or from 100 nm to 400 nm, or from 200 nm to 300 nm may yield a solar spectrum-weighted average reflectance that is practi cally negligible, e.g., less than 2 %, or less than 1 %, or less than 0.8 %, without the addition of anti reflection coatings (ARCs) .
  • ARCs anti reflection coatings
  • the photovoltaic semiconductor structure 100 further comprises a second dielectric layer 109 on a side of the p-type Si lay er 102 opposite the n-type Si layer 103.
  • the second dielectric layer 109 is directly coupled to the p-type Si layer 102.
  • a second dielec tric layer may be coupled directly or indirectly, via any appropriate additional layers, to a p-type Si lay er .
  • a second dielectric layer on a side of a p-type Si layer opposite an n-type Si layer may reduce surface recombination of charge carriers and/or increase overall absorbance of light incident on a photovoltaic semiconductor structure.
  • the second die lectric layer 109 comprises A10 x and SiN x .
  • a second dielectric layer may comprise any suitable material (s) , for example, a transparent oxide and/or nitride, e.g., Si0 2 , SiO x , AI 2 O 3 , A10 x , S 3 N 4 , and/or SiN x .
  • a second dielectric lay er comprising A10 x may passivate a Si surface, such as a b-Si surface, efficiently due to a high-quality in terface with Si.
  • A10 x may passivate b-Si surfaces particularly efficiently due to a high densi ty of negative fixed charges in A10 x .
  • a second dielectric layer comprising SiN x may be fabricable rapidly.
  • FIG. 2 shows a cross-sectional view of a lay ered photovoltaic semiconductor structure 200 extend ing in a lateral direction 201.
  • the embodiment of FIG. 2 may gen erally comprise any features and/or elements of the embodiment of FIG. 1, which are omitted from FIG. 2.
  • the embodiment of FIG. 2 may comprise high aspect ratio nanostructures and a first dielec tric layer similar or identical in shape to the high aspect ratio nanostructures and the first dielectric layers, respectively, of any of the embodiments dis cussed above with reference to FIG. 1.
  • the photovoltaic semiconductor structure 200 is configured for use as a photovoltaic device, e.g., a photodetector or a solar cell, and configured to receive and absorb light inci dent on the photovoltaic semiconductor structure 200 from a front side thereof (see below) .
  • the photovolta ic semiconductor structure 200 is configured for use as a solar cell and configured to receive and absorb solar radiation.
  • the photovoltaic semi conductor structure 200 of the embodiment of FIG. 2 forms a part of a passivated emitter and rear cell (PERC) photovoltaic device.
  • PERC passivated emitter and rear cell
  • a photovoltaic semiconductor structure may be, form a part of, and/or be suitable for a PERC photovoltaic device or structure or any other suitable photovoltaic device or structure.
  • a "passivated emitter and rear cell” or “PERC” photovoltaic structure may refer to a photo voltaic structure belonging to a family of structural ly similar photovoltaic structures, wherein any photo voltaic structure of said family of photovoltaic structures may be characterizable at least by a pas sivating dielectric front layer and a dielectrically displaced conductive back layer.
  • a PERC photovoltaic structure may correspond, for example, to a passivated emitter, rear directly contacted (PERD) structure; a passivated emitter, rear locally doped (PERL) struc ture; a passivated emitter, rear totally diffused (PERT) structure; or a passivated emitter, rear float ing junction (PERF) structure.
  • a PERC, PERD, PERL, PERT, or PERF photovoltaic device may refer to a device comprising a PERC, PERD, PERL, PERT, or PERF photovoltaic structure, respectively.
  • the photovoltaic semiconductor structure 200 comprises a p-type Si lay er 202 having a bulk refractive index, and an n-type Si layer 203 is arranged thereon.
  • the n-type Si lay er 203 has a textured surface 204 opposite the p-type Si layer 202, the textured surface 204 comprising high aspect ratio nanostructures 205 that form an optical conversion layer 206 having an effective refractive index gradually changing towards the bulk refractive index to reduce reflection of light incident on the photovoltaic semiconductor structure 200 from the front side thereof, as defined by a front surface 208 of a first dielectric layer 207 on the textured sur face 204 of the n-type Si layer 203.
  • the photovoltaic semiconductor structure 200 further comprises a front contact finger 212, constituting an example of a front contact, on a side of the first dielectric layer oppo site the n-type Si layer 203, a second dielectric lay er 209 on a side of the p-type Si layer 202 opposite the n-type Si layer 203, as well as a conductive back layer 211 on a side of the second dielectric layer 209 opposite the p-type Si layer 202.
  • the second dielec tric layer 209 is patterned with a through-hole 210, and a galvanic contact exists between the conductive back layer 211 and the p-type Si layer 202 via the through-hole 210.
  • a galvanic contact exists also be tween the front contact finger 212 and the n-type Si layer 203.
  • a front contact may be a front contact finger or any other suitable type of front contact known in the art.
  • a galvanic contact exists between a p-type Si layer and a conduc tive back layer in the absence of a through-hole.
  • a "front contact” may refer to a body or layer of non-insulating, or conductive, material, suitable for transmitting electrical current.
  • a front contact may be configured to collect electrical current generated by said photo voltaic device to an external electrical circuit or device. Consequently, a "front contact finger" may re- fer to a front contact shaped as a slim, continuous body. Generally, a front contact may reduce a series resistance of a photovoltaic semiconductor structure.
  • a layer being "patterned with a through-hole” may refer to the shape of said layer be- ing such that said layer comprises a discontinuity.
  • a layer patterned with a through-hole may comprise a hole in a topological (homeomorphism) sense.
  • a second dielectric layer being patterned with a through-hole may facilitate forming an electrical connection with a p-type Si layer.
  • a galvanic contact between two elements may refer to an electri cal connection between said elements that enables a constant flow of direct (i.e., unidirectional) elec- trical current between said elements.
  • a galvanic con tact may refer to an electrical connection between two solid elements that provides an electrical direct cur rent path passing through solid matter only.
  • a galvanic contact may exist between said two elements even if a magnitude of a voltage (i.e., an electrical potential difference) be tween said two elements is 20 volts (V) or less, or 10 V or less, or 5 V or less, or 2 V or less, or 1 V or less.
  • a galvanic contact may exist be tween two non-insulating elements separated by a die lectric element by virtue of charge carrier tunneling.
  • charge carrier tunneling mainly structural and material aspects of photovoltaic semiconductor structures are dis cussed. In the following, more emphasis will lie on manufacturing aspects related to photovoltaic semicon ductor structures. What is said above about the ways of implementation, definitions, details, and ad vantages related to the structural and material as pects apply, mutatis mutandis, to the method aspects discussed below. The same applies vice versa.
  • FIG. 3 illustrates a method 300 for manufac turing a layered photovoltaic semiconductor structure extending in a lateral direction.
  • Such layered photo voltaic semiconductor structure may be in accordance with any of those discussed above with reference to FIGs. 1 and/or 2.
  • optional steps i.e., a step 306 of forming a through-hole, a step 307 of forming a conductive back layer, and a step 308 of forming a front contact
  • OPTIONAL optional steps
  • the method 300 comprises a step 301 of providing a p-type substrate having a bulk refractive index; a step 302 of forming a textured surface on one side of the p-type Si sub strate; a step 303 of forming an n-type Si layer in the p-type substrate, the n-type Si layer extending from the textured surface, whereby a p-type layer is defined in the p-type substrate; a step 304 of forming a first dielectric layer on the textured surface, the first dielectric layer having a front surface opposite the n-type Si layer, and the front surface defining a front side of the semiconductor structure; and a step 305 of forming a second dielectric layer on a side of the p-type Si substrate opposite the n-type Si layer .
  • any steps, corresponding to the step 303 of forming an n-type Si layer, of a method for manufacturing a layered photovoltaic semiconductor structure may comprise a phosphorus diffusion step.
  • Said phosphorus diffusion step may comprise or corre spond to a phosphoryl trichloride (POCI 3 ) diffusion step.
  • POCI 3 phosphoryl trichloride
  • a phosphorus diffusion step may generally yield a high concentration, i.e., at least 10 18 CITT 3 , or at least 10 19 CITT 3 , or at least 10 20 CITT 3 , of dopant phos phorus atoms in at least part of an n-type Si layer, especially if said n-type Si layer has a textured sur face comprising nanostructures with high S f values.
  • the first dielec tric layer is formed in the step 304 by ALD such that the first dielectric layer covers the nanostructures in a substantially conformal manner.
  • a first dielectric layer may be formed by ALD or by any other suitable method known in the art.
  • a first dielectric layer may cover the textured surface in substantially conformal man ner, whereas in other embodiments, a first dielectric layer may cover the textured surface in any other suitable manner.
  • atomic layer deposition may refer to a process, wherein a substrate is alternately ex posed to at least two precursors, one precursor at a time, to form a coating on said substrate by alter nately repeating essentially self-limiting surface re actions between a surface of said substrate (on the later stages, naturally, a surface of an already- formed coating layer on said substrate) and said at least two precursors.
  • coating material is "grown" on said substrate molecule layer by molecule layer. This enables accurate and well-controlled pro duction of thin film coatings.
  • forming a first dielectric layer by ALD may facilitate forming said first dielectric layer in a substantially conformal manner, which may facilitate forming an efficiently passivated textured surface .
  • the textured sur face comprises high aspect ratio nanostructures ex tending in a direction substantially perpendicular to the lateral direction, the nanostructures forming an optical conversion layer having an effective refrac tive index gradually changing towards the bulk refrac tive index to reduce reflection of light incident on the photovoltaic semiconductor structure from the front side thereof.
  • the nanostruc tures are formed by RIE, more specifically by DRIE.
  • nanostructures may be formed by RIE, such as DRIE, or by any other suitable method known in the art, such as metal-assisted chemical etching (MACE) or atmospheric dry etching (ADE) .
  • MACE metal-assisted chemical etching
  • AD atmospheric dry etching
  • forming high aspect ratio nanostructures by RIE may, for exam ple, facilitate making the nanostructures, such as b-Si spikes, deeper, increasing their aspect ratio, which may eliminate a need for any ARCs and/or further improve optical properties. Additionally or alterna tively, forming high aspect ratio nanostructures by RIE, especially DRIE, may facilitate producing lattice defect-free high aspect ratio nanostructures, such as b-Si spikes, eliminating the need for any post-etching polishing steps. On the other hand, forming high as pect ratio nanostructures by MACE or ADE may, for ex ample, facilitate producing said high aspect ratio nanostructures in a highly scalable and/or rapid man ner .
  • the method 300 fur ther comprises the optional step 306 of forming a through-hole in the second dielectric layer, the op tional step 307 of forming a conductive back layer on a side of the second dielectric layer opposite the p-type Si layer such that a galvanic contact is formed between the conductive back layer and the p-type Si layer via the through-hole, and the optional step 308 of forming a front contact, for example, a front con tact finger, on a side of the first dielectric layer opposite the n-type Si layer such that a galvanic con tact is formed between the front contact and the n-type Si layer.
  • a front contact for example, a front con tact finger
  • the front con tact is formed by applying silver metallization paste onto the first dielectric layer and subsequently fir ing said paste at a firing temperature in a range of from about 650°C to about 850°C for a few seconds (s) , e.g., 3, 5, or 8 s.
  • a front con tact for example, a front contact finger, may be formed by applying and firing any suitable metalliza tion paste, e.g., a silver, aluminum, or sil ver-aluminum paste, or by any other suitable method known in the art.
  • a method for manufacturing a layered photovoltaic semiconductor structure extend ing in a lateral direction comprises steps correspond ing to the steps of the method 300 of the embodiment of FIG. 3.
  • a method for manufac turing a layered photovoltaic semiconductor structure extending in a lateral direction may comprise steps corresponding to the compulsory (i.e., non-optional ) steps 301, 302, 303, 304, 305 of the method 300 of the embodiment of FIG. 3.
  • a method for manufacturing a layered photovoltaic semiconductor structure extending in a lateral direction may com- prise steps corresponding to the compulsory steps 301,
  • steps corresponding to the compul sory steps 301, 302, 303, 304, 305 and any steps cor responding to the optional steps 306, 307, 308 of a method for manufacturing a layered photovoltaic semi conductor structure extending in a lateral direction need not be executed in a fixed order or even sequen tially. However, any steps corresponding to the step 301 of providing a p-type substrate are executed prior to any steps corresponding to the steps 302,
  • any steps corre sponding to the step 302 of forming a textured surface are executed prior to any steps corresponding to the steps 304 and 308; any steps corresponding to the step 303 of forming an n-type Si layer may be executed prior to any steps corresponding to the steps 304 and 308; any steps corresponding to the step 304 of form ing a first dielectric layer are executed prior to any steps corresponding to the step 308; any steps corre sponding to the step 305 of forming a second dielec tric layer are executed prior to any steps correspond ing to the step 307 and optionally prior to any steps corresponding to the step 306; and any steps corre sponding to the step 306 of forming a through-hole may be executed prior to any steps corresponding to the step 307.
  • a method for manufacturing a lay ered photovoltaic semiconductor structure extending in a lateral direction may comprise any number of addi tional steps that are not disclosed herein in connec tion to the method 300 of the embodiment of FIG. 3. Such additional steps may comprise, for example, cleaning, annealing, etching, deposition, and/or la beling steps.

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  • Photovoltaic Devices (AREA)

Abstract

La présente invention concerne une structure semi-conductrice photovoltaïque en couches (100, 200) s'étendant dans une direction latérale (101, 201), comprenant une couche de silicium de type p (102, 202) ayant un indice de réfraction volumique; une couche de silicium de type n (103, 203) sur la couche de silicium de type p (102, 202), la couche de silicium de type n (103, 203) ayant une surface texturée (104, 204); une première couche diélectrique (107, 207) sur la surface texturée (104, 204), la première couche diélectrique (107, 207) ayant une surface avant (108, 208) définissant un côté avant de la structure semi-conductrice photovoltaïque (100, 200); et une seconde couche diélectrique (109, 209) sur un côté de la couche de silicium de type p (102, 202) à l'opposé de la couche de silicium de type n (103, 203). Dans la structure semi-conductrice photovoltaïque (100, 200), la surface texturée (104, 204) comprend des nanostructures à rapport de forme élevé (105, 205) s'étendant dans une direction sensiblement perpendiculaire à la direction latérale (101, 201), les nanostructures (105, 205) formant une couche de conversion optique (106, 206) ayant un indice de réfraction efficace changeant progressivement en direction de l'indice de réfraction volumique afin de réduire la réflexion de la lumière incidente sur la structure semi-conductrice photovoltaïque (100, 200) depuis son côté avant.
PCT/FI2018/050854 2017-11-24 2018-11-23 Structure semi-conductrice photovoltaïque Ceased WO2019102073A1 (fr)

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