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WO2019194200A1 - Substrat incorporé dans un composant - Google Patents

Substrat incorporé dans un composant Download PDF

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Publication number
WO2019194200A1
WO2019194200A1 PCT/JP2019/014692 JP2019014692W WO2019194200A1 WO 2019194200 A1 WO2019194200 A1 WO 2019194200A1 JP 2019014692 W JP2019014692 W JP 2019014692W WO 2019194200 A1 WO2019194200 A1 WO 2019194200A1
Authority
WO
WIPO (PCT)
Prior art keywords
main surface
semiconductor element
component
wiring pattern
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2019/014692
Other languages
English (en)
Japanese (ja)
Inventor
杉山　裕一
宮崎　政志
猿渡　達郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP2020512271A priority Critical patent/JPWO2019194200A1/ja
Publication of WO2019194200A1 publication Critical patent/WO2019194200A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H10W70/60—

Definitions

  • the present invention relates to a component-embedded substrate in which a semiconductor element is embedded in a metal core base material.
  • the power circuit easily generates heat because it consumes a large current, and it is difficult to reduce the size because it requires coil components that are larger in size than passive components such as capacitors and resistors.
  • Using a 3D mounting technology such as a component-embedded board to incorporate components other than the coil into the substrate is also effective for the power supply module, but because the heat density increases compared to the surface-mounting substrate, the built-in components are generated. It is required to transfer heat efficiently. For this reason, in recent years, a component-embedded substrate having a metal core base material has been widely used (see, for example, Patent Document 1).
  • a component-embedded substrate having a metal core base material it is required to further improve the heat dissipation efficiency of the built-in component and shorten the wiring length between the electronic component mounted on the mounting surface.
  • an object of the present invention is to provide a component-embedded substrate capable of improving heat dissipation efficiency and shortening the wiring length between a mounting surface and a built-in component.
  • a component-embedded substrate includes a metal core base material, a semiconductor element, a first resin layer, a multilayer wiring layer, and an interlayer connection portion.
  • the core base material penetrates between a first main surface, a second main surface opposite to the first main surface, and the first main surface and the second main surface. And a cavity.
  • the semiconductor element has a thickness smaller than that of the core substrate, is accommodated in the cavity, and is located on the first main surface side with respect to the center of the core substrate.
  • the first resin layer fills the cavity and seals the semiconductor element.
  • the multilayer wiring layer includes a first wiring pattern disposed on the first main surface side and a second wiring pattern disposed on the second main surface side.
  • the interlayer connection portion includes a first via formed at a first height between the first wiring pattern and the semiconductor element, and a gap between the second wiring pattern and the semiconductor element. And a second via formed at a second height greater than the first height.
  • the wiring length with the first wiring pattern can be made relatively short.
  • the second via that communicates with the second wiring pattern can be formed with a larger diameter than the first via, the second via can be made to function as a thermal via. It is possible to improve the heat dissipation efficiency of the element.
  • the second via may include a surface conductor layer that electrically connects the second wiring pattern and the semiconductor element, and a second resin layer filled in the surface conductor layer. Good.
  • the inside of the surface conductor layer may be filled with a conductive paste or Cu plating.
  • the second via may be formed with a larger diameter than the first via.
  • the cavity may have an inner wall surface including an annular protrusion protruding inward, and the semiconductor element may be disposed between the annular protrusion and the first main surface.
  • the component-embedded substrate may further include an electronic component mounted on the first main surface side and electrically connected to the semiconductor element.
  • FIG. 1 is an external perspective view of a circuit module including a component built-in substrate according to an embodiment of the present invention. It is a schematic sectional side view of the principal part of the said circuit module. It is a principal part schematic sectional side view of the said component built-in board
  • FIG. 1 is an external perspective view of a circuit module 100 including a component built-in substrate 10 according to an embodiment of the present invention
  • FIG. 2 is a schematic side sectional view of a main part of the circuit module 100
  • FIG. It is a principal part schematic sectional side view.
  • an X axis, a Y axis, and a Z axis indicate three axial directions orthogonal to each other
  • FIGS. 2 and 3 are cross-sectional views as viewed from the Y axis direction.
  • the circuit module 100 includes a component built-in substrate 10, a plurality of electronic components 21 mounted on the surface (component mounting surface) of the component built-in substrate 10, and built-in components housed in the component built-in substrate 10.
  • the semiconductor element 22 and the mold part 30 that covers the electronic component 21 are provided.
  • circuit module 100 a predetermined electronic circuit including the electronic component 21 and the semiconductor element 22 is three-dimensionally constructed.
  • the circuit module 100 is configured to be capable of being soldered and mounted on a mounting substrate (motherboard) (not shown) via an external connection terminal 31 provided on the back surface (terminal surface) of the component built-in substrate 10.
  • the component-embedded substrate 10 includes a metal core base 110, an exterior part 120, a semiconductor element 22, a multilayer wiring layer 130 (first wiring pattern 131 and second wiring pattern 132), 1 is a substrate module having one resin layer 140 and an interlayer connection 150 (first via 151 and second via 152).
  • the core substrate 110 is a metal plate having a predetermined thickness (for example, 35 to 500 ⁇ m) such as copper, a copper alloy (a metal mainly composed of copper), or an iron alloy such as stainless steel (a metal mainly composed of iron). Composed.
  • the planar shape of the core substrate 110 is rectangular, and has a first main surface 111, a second main surface 112, and four side surfaces 113. Inside the core substrate 110, a plurality of cavities including a first cavity C1 that accommodates the semiconductor element 22 and a second cavity C2 that accommodates a through hole V for interlayer connection are formed.
  • the exterior portion 120 has a stacked structure of a first insulating layer 121, a second insulating layer 122, and a third insulating layer 123.
  • the first insulating layer 121 covers the first main surface 111 of the core base material 110
  • the second insulating layer 122 covers the second main surface 112 of the core base material 110.
  • the third insulating layer 123 covers the side surface 113 of the core substrate 110.
  • the first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 are typically made of the same synthetic resin material.
  • epoxy resin epoxy resin
  • polyimide It is composed of a resin or a composite material in which a filler such as glass fiber is mixed.
  • the first wiring pattern 131 is arranged on the first main surface 111 side, and the second wiring pattern 132 is arranged on the second main surface 12 side. That is, the first wiring pattern 131 is provided on the first main surface 111 of the core substrate 110 via the first insulating layer 121, and the second wiring pattern 132 is interposed via the second insulating layer 122. Provided on the second main surface 112 of the core substrate 110.
  • the first wiring pattern 131 and the second wiring pattern 132 are typically made of copper foil, and are formed in a desired shape.
  • the wiring pattern is composed of pads or electrodes covering vias and through holes, electrodes connected to electronic components, wiring integrated with the pads or electrodes, and the like.
  • a part of the first wiring pattern 131 is connected to the first main surface 111 of the core substrate 110 through a via penetrating the first insulating layer 121.
  • a part of the second wiring pattern 132 is connected to the second main surface 112 of the core substrate 110 through a via penetrating the second insulating layer 122.
  • the connection with the core base material 110 mainly contributes to the grounding of the GND for the purpose of grounding the voltage.
  • the first wiring pattern 131 and the second wiring pattern 132 are covered with an insulating protective film such as solder resist SR1, SR2.
  • the solder resists SR1 and SR2 have openings at appropriate positions, through which the first wiring pattern 131 is connected to the terminal portion of the electronic component 21 and the second wiring pattern 132 is connected to the external connection terminal 31. Connected to each.
  • the substrate surface on which the first wiring pattern 131 is formed is configured as a mounting surface on which the electronic component 21 is surface-mounted.
  • the external connection terminal 31 is made of a brazing material such as solder, for example.
  • the semiconductor element 22 accommodated in the first cavity portion C1 has a thickness that is half or less that of the core substrate 110.
  • the semiconductor element 22 is typically an IC component or a discrete component.
  • a power transistor through which a large current flows is used.
  • the power transistor include a BiP transistor made of Si, a MOSFET, an IGBT, and the like, and a transistor made of SiC, GaN, or the like.
  • the electronic component 21 mounted on the mounting surface an electronic component that is typically larger than the semiconductor element 22 such as a capacitor component or a coil component is used.
  • the semiconductor element 22 is housed in the first cavity portion C1 face-up with its active surface facing the first main surface 111 side.
  • the semiconductor element 22 is located closer to the first main surface 111 than the center of the core substrate 110.
  • the surface or electrode of the semiconductor element 22 is disposed on the same plane as the first main surface 111 of the core substrate 110.
  • the first resin layer 140 is made of an electrically insulating resin material that fills the first cavity portion C1 and the second cavity portion C2 and seals the semiconductor element 22.
  • the first resin layer 140 is typically made of an insulating material containing the same kind or the same organic material as the first to third insulating layers 121 to 123. Thereby, since affinity with the exterior part 120 is improved, the adhesiveness of the 1st resin layer 140 with respect to the exterior part 120 increases.
  • the first resin layer 140 may contain an inorganic filler such as fiber made of glass or carbon, glass cloth, silicon oxide, aluminum oxide, calcium carbonate, etc., similarly to the constituent material of the exterior part 120.
  • the interlayer connection 150 has a first via 151 and a second via 152.
  • the first via 151 is formed between the first wiring pattern 131 and the semiconductor element 22 (active surface thereof).
  • the second via 152 is formed between the second wiring pattern 132 and the semiconductor element 22 (inactive surface thereof).
  • the semiconductor element 22 is located closer to the first main surface 111 side than the center of the core base 110 in the first cavity C1, and in this embodiment, the surface or electrode of the semiconductor element 22 is the first surface.
  • the first main surface 111 is located substantially on the same plane.
  • the first via 151 is connected between the first wiring pattern 131 and the active surface of the semiconductor element 22 via the first insulating layer 121, and the second via 152 includes the second insulating layer 122 and the second insulating layer 122.
  • the second wiring pattern 132 is connected to the non-active surface (back surface electrode) of the semiconductor element 22 through the first resin layer 140.
  • the height (or depth) of the first via 151 is increased. Is smaller (lower) than the height (or depth) of the second via 152.
  • the maximum via diameter tends to increase as the via height (or depth) increases. Therefore, in the present embodiment, the first via 151 can be formed with a finer pitch than the second via 152, and the second via 152 can be formed more than the first via. In addition, a low-resistance via can be formed. Therefore, it is advantageous when a large current flows from the semiconductor element 22 to the second wiring pattern 132 through the second via 152 or when the second via 152 functions as a thermal via for heat dissipation of the semiconductor element 22. It becomes. Further, when the second vias 152 are all formed of a conductor, the peripheral resin and the insulating layer constituting the substrate have a larger coefficient of thermal expansion ( ⁇ ), and thus warp the substrate.
  • ⁇ coefficient of thermal expansion
  • the second via 152 includes a surface conductor layer 521 that electrically connects the second wiring pattern 132 and the semiconductor element 22, and a second conductor 152 that is filled in the surface conductor layer 521. 2 resin layers 522.
  • the surface conductor layer 521 is configured by conductor plating such as copper plating formed on the inner wall surface of the hole formed in the second insulating layer 122 and the first resin layer 140 by a laser processing method or the like.
  • the second resin layer 522 is typically made of a resin material that forms the second insulating layer 122 and is formed simultaneously with the formation of the second insulating layer 122.
  • the number of the second vias 152 is not particularly limited and may be a single number, but typically a plurality of the second vias 152 are provided. All the second vias 152 are not limited to the case where they are connected between the semiconductor element 22 and the second wiring pattern 132, and part of the second vias 152 are formed between the semiconductor element 22 and the core substrate 110. It may be connected between appropriate wiring patterns that are electrically connected to each other.
  • the first via 151 and the second via 152 are provided on the front surface (active surface) and the back surface (inactive surface) of the semiconductor element 22, respectively. Therefore, the conductive path and the heat transfer path are shortened by lowering the resistance value and the thermal resistance as compared with the case where the via is connected to only one side of the component. Moreover, it becomes easy to provide a thermal via, and the heat dissipation of the inactive surface of the semiconductor element 22 can be improved.
  • the semiconductor element 22 is located closer to the first main surface 111 side than the center of the core base material 110 in the first cavity portion C1, fine signal wiring is formed by the first via 151.
  • a wiring and a heat radiation line through which a large current flows can be formed by the second via 152.
  • the substrate can be made smaller and thinner by making the wiring density different between the front and back surfaces of the semiconductor element 22 or by separating the heat radiation line and the fine signal wiring.
  • the second via 152 is constituted by the surface conductor layer 521 and the second resin layer 522, the component-embedded substrate is compared with the case where the second via 152 is filled with a conductor such as metal.
  • a predetermined stress relaxation function can be provided with respect to an external force such as a bending stress acting on 10. Therefore, even when the second via 152 is formed relatively high (or deep), desired connection reliability can be ensured.
  • the second via 152 is filled with a conductor such as a metal, the larger the via height (depth), the more the via is bent. Can keep.
  • the first cavity portion C1 and the second cavity portion C2 are formed by a wet etching method.
  • the cavity portions C1 and C2 are formed by half-etching predetermined regions of the first main surface 111 and the second main surface 112 of the core layer 110, respectively.
  • an annular protrusion (annular protrusion) Cp that protrudes inward of the cavities C1 and C2 may be formed on the inner wall surface corresponding to the confluence of both half-etched regions (see FIG. 3). ).
  • the semiconductor element 22 is located closer to the first main surface 111 side than the center of the core substrate 110 in the first cavity portion C1.
  • the semiconductor element 22 is preferably arranged at a position that does not face the tip of the annular protrusion Cp in a direction orthogonal to the thickness direction (Z-axis direction) of the core layer 110, and typically the annular protrusion Cp and the first Between the first main surface 111 and the first main surface 111.
  • the electronic component 21 is a single product, and the occupation ratio of the area of the core base material surface is from 50% to 100% of the component-embedded substrate. In some cases, the element may have an occupation ratio as close to 50% to 100%. In that case, the connection between the electronic component 21 and the surface of the core substrate 110 leads to a certain degree of reliability due to the rigidity of the electronic component 21 and the mold part 30. On the other hand, the member contributing to this rigidity is not provided on the back surface side of the core substrate 110. Therefore, a large warping force is applied to the back surface side of the core substrate 110.
  • filling the via 152 with the second resin layer 522 generates flexibility in the via 152 itself, and the second via 152 and the second wiring pattern 132 are not connected. Contact failure can be suppressed.
  • the first via 151 is formed to be thin or shallow, the following merit with the electronic component 21 occurs.
  • the electronic component 21 is a capacitor, noise absorption is steep, and malfunction of the semiconductor element 22 can be prevented.
  • the electronic component 21 is a solenoid, it is less likely to pick up noise between the solenoid and the semiconductor element.
  • the current from the power transistor, which is a semiconductor element, to the electronic component has a short path and a small resistance value, which is effective as signal processing. Considering the flow of current, the current flows from the external terminal 31 on the right side to the electronic component through the through hole V in FIG. 2, and then flows from the electronic component 21 to the vertical transistor 22 through the first via 151.
  • the transistor 22 Flows to the left external terminal 31 through the second via 152. Or vice versa, current flows.
  • the transistor 22 generates heat because it flows in the thickness direction of the multilayer substrate, and the second via 152 is deep, and its diameter is larger than that of the first via. Therefore, the transistor 22 greatly contributes as a thermal via.
  • the number of wiring layers (wiring patterns) formed on both main surfaces of the component-embedded substrate 10 is one, but the present invention is not limited to this.
  • a multilayer wiring structure may be employed.
  • a wiring layer is further formed on the wiring patterns 131 and 132 via an interlayer insulating film.
  • the core substrate 110 includes the first cavity portion C1 that houses the semiconductor element 22 .
  • the number of cavity portions that house the built-in components is not limited to one, and a plurality of There may be.
  • the housed component to be accommodated is not limited to a semiconductor element, and may be a passive component such as a capacitor or a resistance element.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

La présente invention aborde le problème de la réalisation d'un substrat incorporé dans un composant qui améliore l'efficacité de dissipation de chaleur et permet de raccourcir la longueur de câblage entre une surface de montage et un composant incorporé. La solution selon un mode de réalisation de l'invention porte sur un substrat incorporé dans un composant qui comprend un matériau de cœur métallique, un élément semi-conducteur, une première couche de résine, une couche de câblage multicouche et une partie de connexion intercouche. L'élément semi-conducteur est plus fin que le matériau de cœur, est logé dans une cavité et est positionné davantage vers un côté de première surface principale que le centre du matériau de cœur. La première couche de résine remplit la cavité et scelle l'élément semi-conducteur. La couche de câblage multicouche présente un premier motif de câblage qui est disposé sur le côté de première surface principale et un deuxième motif de câblage qui est disposé sur un côté de deuxième surface principale. La partie de connexion intercouche comprend un premier trou d'interconnexion qui est formé entre le premier motif de câblage et l'élément semi-conducteur et possède une première hauteur, et un deuxième trou d'interconnexion qui est formé entre le deuxième motif de câblage et l'élément semi-conducteur et possède une deuxième hauteur qui est supérieure à la première hauteur.
PCT/JP2019/014692 2018-04-04 2019-04-02 Substrat incorporé dans un composant Ceased WO2019194200A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2020512271A JPWO2019194200A1 (ja) 2018-04-04 2019-04-02 部品内蔵基板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018072032 2018-04-04
JP2018-072032 2018-04-04

Publications (1)

Publication Number Publication Date
WO2019194200A1 true WO2019194200A1 (fr) 2019-10-10

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PCT/JP2019/014692 Ceased WO2019194200A1 (fr) 2018-04-04 2019-04-02 Substrat incorporé dans un composant

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JP (1) JPWO2019194200A1 (fr)
WO (1) WO2019194200A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024262854A1 (fr) * 2023-06-22 2024-12-26 엘지이노텍 주식회사 Carte de circuit imprimé et boîtier de semi-conducteur la comprenant

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008182184A (ja) * 2006-12-26 2008-08-07 Jtekt Corp 多層回路基板およびモータ駆動回路基板
JP2008288298A (ja) * 2007-05-16 2008-11-27 Toppan Printing Co Ltd 電子部品を内蔵したプリント配線板の製造方法
JP2011522403A (ja) * 2008-05-30 2011-07-28 アーテー・ウント・エス・オーストリア・テヒノロギー・ウント・ジュステームテッヒニク・アクチェンゲゼルシャフト 少なくとも１つの電子構成部品をプリント回路基板に組み込むための方法、およびプリント回路基板
WO2011102561A1 (fr) * 2010-02-22 2011-08-25 三洋電機株式会社 Carte de circuit imprimé multicouche et procédé de fabrication associé
JP2012191204A (ja) * 2011-03-11 2012-10-04 Ibiden Co Ltd プリント配線板の製造方法
JP2014112627A (ja) * 2012-11-07 2014-06-19 Taiyo Yuden Co Ltd 電子回路モジュール

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008182184A (ja) * 2006-12-26 2008-08-07 Jtekt Corp 多層回路基板およびモータ駆動回路基板
JP2008288298A (ja) * 2007-05-16 2008-11-27 Toppan Printing Co Ltd 電子部品を内蔵したプリント配線板の製造方法
JP2011522403A (ja) * 2008-05-30 2011-07-28 アーテー・ウント・エス・オーストリア・テヒノロギー・ウント・ジュステームテッヒニク・アクチェンゲゼルシャフト 少なくとも１つの電子構成部品をプリント回路基板に組み込むための方法、およびプリント回路基板
WO2011102561A1 (fr) * 2010-02-22 2011-08-25 三洋電機株式会社 Carte de circuit imprimé multicouche et procédé de fabrication associé
JP2012191204A (ja) * 2011-03-11 2012-10-04 Ibiden Co Ltd プリント配線板の製造方法
JP2014112627A (ja) * 2012-11-07 2014-06-19 Taiyo Yuden Co Ltd 電子回路モジュール

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024262854A1 (fr) * 2023-06-22 2024-12-26 엘지이노텍 주식회사 Carte de circuit imprimé et boîtier de semi-conducteur la comprenant

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