WO2019183849A1 - Data processing method and device - Google Patents

Abstract

A data processing method and device. The method comprises: writing data in a first matrix into a register; carrying out a reading operation on the data of the first matrix in the register multiple times, wherein at least one piece of data is read every time; and writing at least one piece of data of a second matrix into a target write position in the register after the each reading operation, wherein the target write position is the reading position for each read operation. The method and device according to the embodiments of the present application may avoid the waste of register resources.

Description

Data processing method and device

Copyright statement

The disclosure of this patent document contains material that is subject to copyright protection. This copyright is the property of the copyright holder. The copyright owner has no objection to the reproduction of the patent document or the patent disclosure in the official records and files of the Patent and Trademark Office.

Technical field

The present application relates to the field of information technology and, more particularly, to a data processing method and apparatus.

Background technique

A matrix is a data structure commonly used in computers. In computer applications, for example, in the fields of science and engineering calculations, games, image processing, etc., the transpose operation of the matrix is often required.

When the matrix is transposed, the data needs to be stored in the register row or column, and read from the register in columns or rows, thereby implementing the transpose of the matrix.

The existing processing method is to set two registers, read a set of data that needs to be transposed into the first register in one direction, and then read out from the first register in the other direction, while reading data in the first register, Reading another set of data that needs to be transposed into the second register requires two registers to be used interchangeably. In the process of computer processing, the register resources play an important role. How to avoid register resources during matrix transposition. Waste is an urgent problem to be solved.

Summary of the invention

The embodiment of the present application provides a data processing method and device, which can avoid waste of register resources.

In a first aspect, a data processing method is provided, comprising: writing data in a first matrix to a register; performing a plurality of read operations on data of the first matrix in the register, wherein each read The operation reads at least one data; after each read operation, writes at least one data of the second matrix at a target write position in the register, wherein the target write position is a read of each read operation Take the location.

In a second aspect, a controller is provided, comprising: a write unit and a read unit; wherein the write unit is configured to: write data in the first matrix to a register; the read unit is configured to: target the register Data of the first matrix, performing a plurality of read operations, wherein each read operation reads at least one data; the write unit is further configured to: in each register after each read operation The target write location writes at least one data of the second matrix, wherein the target write location is a read location for each read operation.

In a third aspect, a data processing device is provided, including a controller and a register; wherein the controller is configured to write data to the register and read data in the register; wherein the controller is specifically configured to: Data in the first matrix is written to the register; for the data of the first matrix in the register, a plurality of read operations are performed, wherein each read operation reads at least one data; after each read operation, At least one of the data of the second matrix is written at the target write position in the register, wherein the target write position is the read position of each read operation.

In a fourth aspect, a computer storage medium is provided, the medium storing code for: writing data in a first matrix to a register; performing multiple reads on data of the first matrix in the register Taking operation, wherein each read operation reads at least one data; after each read operation, at least one data of the second matrix is written at a target write position in the register, wherein the target write The position is the reading position for each read operation.

In a fifth aspect, a computer program product is provided, the program product comprising code for: writing data in a first matrix to a register; performing multiple reads on data of the first matrix in the register Taking operation, wherein each read operation reads at least one data; after each read operation, at least one data of the second matrix is written at a target write position in the register, wherein the target write The position is the reading position for each read operation.

Therefore, in the embodiment of the present application, multiple read operations may be performed on the data of the first matrix in the register, and after each read operation, the controller writes the read position in the register to the second matrix again. Data, so that the vacancy of the register after the read operation can be avoided, thereby avoiding waste of register resources

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings to be used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description are only some of the present application. For the embodiments, those skilled in the art can obtain other drawings according to the drawings without any creative work.

1 is a schematic block diagram of a computer system in accordance with an embodiment of the present application.

FIG. 2 is a schematic flowchart of a data processing method according to an embodiment of the present application.

3 is a schematic diagram of data for writing and reading a matrix in a register in accordance with an embodiment of the present application.

4 is a schematic diagram of data for writing and reading a matrix in a register in accordance with an embodiment of the present application.

FIG. 5 is a schematic block diagram of a controller in accordance with an embodiment of the present application.

FIG. 6 is a schematic block diagram of a data processing device according to an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application are described in conjunction with the accompanying drawings in the embodiments of the present application. It is obvious that the described embodiments are a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope are the scope of the present application.

Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning The terminology used in the present application is for the purpose of describing particular embodiments and is not intended to limit the scope of the application.

FIG. 1 is a schematic block diagram of a computer system 100 in accordance with an embodiment of the present application.

As shown in FIG. 1, the system 100 includes a processor 110 and an external storage system 120 (which may be any accessible memory, including external cache and external random access memory (RAM), etc.).

Processor 110 of computer system 100 can include registers 112. Register 112 is not limited to a particular type of memory circuit. The registers of the embodiments of the present application can store and provide matrix data.

Computer system 100 of the present application may include one or more input/output (I/O) devices 130, including display devices such as monitors. The I/O device may also include input devices such as a keyboard and a cursor controller such as a mouse, trackball or trackpad. In addition, the I/O device may further include a network connector such that the computer system 100 becomes part of a local area network (LAN) or a wide area network (WAN), and the I/O device 130 is used for voice recording and/or Or a device for playback, such as an audio digitizer coupled to a microphone for recording voice input for speech recognition. The I/O device 130 may also include a video digitizing device that can be used to capture video images, a hard copy device such as a printer, and a Compact Disc Read-Only Memory (CD-ROM) device.

Optionally, in the embodiment of the present application, the external storage system 120 may include a computer readable medium for storing a computer program product on which a computer (or other electronic device) usable for programming (ie, defining its operation) may be stored. An instruction to perform processing in accordance with the present application. The computer readable medium can include, but is not limited to, a floppy disk, an optical disk, a CD, a CD-ROM and a magneto-optical disk, a Read-Only Memory (ROM), a RAM, an erasable programmable read-only memory (erasable programmable read- Only memory, EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), magnetic or optical card, flash memory, and the like.

Accordingly, computer readable media includes any type of media/machine readable medium suitable for storing electronic instructions. In addition, the present application can also be downloaded as a computer program product. As such, the program can also be transferred from a remote computer (eg, a server) to a requesting computer (eg, a client). The program can be transmitted as a data signal contained in a carrier or other propagation medium over a communication link (e.g., modem, network connection, etc.).

Computer system 100 can be a general purpose computer with a processor of a suitable register structure, or can be configured for a specific purpose or embedded application. The methods of embodiments of the present application can be included in machine executable instructions that are intended to control the operation of a computer system, particularly the operation of a processor and a register. These instructions can be used to cause a general purpose or special purpose processor programmed with instructions to perform the steps of the present application. Alternatively, the steps of the present application can be performed by specific hardware components that comprise hardwired logic for performing the steps, or by a combination of programmed computer components and conventional hardware components.

FIG. 2 is a schematic flowchart of a data processing method 200 according to an embodiment of the present application. As shown in FIG. 2, the method 200 includes at least some of the following.

At 210, the controller writes data in the first matrix to the register for data in the first matrix.

It should be understood that, in this embodiment of the present application, the storage size of each register is not limited, and a storage space storing one data element in a matrix may be referred to as a register, or a storage space storing a complete matrix may be referred to as a register or Register group, etc.

Optionally, in the embodiment of the present application, the number of rows of the first matrix may be equal to the number of columns of the first matrix, or the number of rows of the first matrix is not equal to the number of columns of the first matrix.

At 220, the controller performs a plurality of read operations for the data of the first matrix in the register, wherein each read operation reads at least one of the data.

Optionally, in the embodiment of the present application, the amount of data read by different reading operations may be the same or different.

At 230, after each read operation, the controller writes at least one data of the second matrix at a target write location in the register, wherein the target write location is a read of the each read operation Take the location.

Optionally, in the embodiment of the present application, the number of rows of the second matrix may be equal to the number of columns of the second matrix, or the number of rows of the second matrix is not equal to the number of columns of the second matrix.

Optionally, in the embodiment of the present application, the number of rows of the second matrix may be equal to the number of rows of the first matrix, and the number of columns of the second matrix may be equal to the number of columns of the first matrix.

Alternatively, in the embodiment of the present application, the number of rows of the second matrix may be equal to the number of columns of the first matrix, and the number of columns of the second matrix may be equal to the number of rows of the first matrix.

Optionally, in the embodiment of the present application, the data of the first matrix may also be written step by step after each read operation for other matrices (non-first matrix and non-second matrix). And the writing mode of the second matrix and the utilization of the register after reading may also be as the first matrix.

Specifically, a plurality of read operations are performed for data of the second matrix in the register, wherein each read operation reads at least one data of the second matrix; Thereafter, at least one data of the third matrix is written at a target write location in the register, wherein the target write location is a read location of the each read operation.

In other words, in the processing of the matrix in the embodiment of the present application, the previous matrix can be read in multiple times, and after each read operation, the latter matrix is written at the reading position of the previous matrix. data.

Therefore, in the embodiment of the present application, multiple read operations may be performed on the data of the first matrix in the register, and after each read operation, the controller writes the read position in the register to the second matrix again. The data can avoid the vacancy of the register after the read operation, so that the waste of register resources can be avoided without losing the efficiency of data processing.

Optionally, in the embodiment of the present application, the write operation for writing data of the second matrix after one read operation (reading data in the first matrix) may be performed in the next read operation (reading the first The data in a matrix is executed before.

Optionally, in the embodiment of the present application, at least one data of the second matrix is written in a target write position in the register in the same clock cycle after each read operation.

Specifically, the read operation for the first matrix can be performed at a earlier time of one clock cycle, and the write operation for the data of the second matrix is performed at a later time of the same clock cycle.

Thus, writing data of another matrix at the read position during the same clock cycle of the read operation can further avoid waste of register resources and can improve data processing efficiency.

Optionally, in the embodiment of the present application, the controller writes data in the first matrix to the register according to the first data sequence for the data of the first matrix; for the data of the first matrix in the register, In the second data sequence, multiple read operations are performed.

Optionally, in the embodiment of the present application, the first data sequence may be an order of writing in a row of a matrix, or an order of writing in a column of a matrix.

Optionally, in the embodiment of the present application, the second data sequence may be an order of reading in a matrix of columns, or an order in which rows of the matrix are read.

Optionally, in the embodiment of the present application, the second data sequence may be different from the first data sequence.

Optionally, the embodiments of the present application may be used for a transposition operation of a matrix.

Specifically, when the first data order is an order of writing in a row of a matrix, the second data order is an order of reading in a matrix of the matrix. At this time, optionally, data of one row may be written for each write operation of the first matrix, and data of one column of the matrix may be read for each read operation, so that transposition of the first matrix may be implemented.

Alternatively, when the first data sequence may be in the order of writing in a matrix of columns, the second data sequence is in the order of reading in rows of the matrix. At this time, optionally, one column of data may be written for each write operation of the first matrix, and data of one row of the matrix may be read for each read operation, so that transposition of the first matrix may be implemented.

Certainly, the first data sequence may also be other data sequences, which may be determined according to the processing required for the first matrix, which is not specifically limited in this embodiment of the present application.

Optionally, in the embodiment of the present application, the controller may write the data in the first matrix to the register according to the first storage space order; and the controller may follow the second storage space order for the register The data of the first matrix performs a plurality of read operations.

Optionally, in the embodiment of the present application, the first storage space sequence is different from the second storage space sequence.

Optionally, in the embodiment of the present application, the first storage space sequence is an order of writing in a row of the register, or the first storage space order is an order of writing in a column of the register.

Optionally, in the embodiment of the present application, the second storage space order is an order of reading in a column of the register, or the second storage space order is an order of reading in a row of the register.

Optionally, in the embodiment of the present application, when the first storage space sequence is an order of writing in a row of the register, the second storage space order is an order of reading in a column of the register. At this time, optionally, in each write operation for the first matrix, data of the first matrix is written in one row of the register, and a column of data of the register is read every read operation.

Optionally, in the embodiment of the present application, in the order in which the first storage space is written in a column of the register, the second storage space order is an order of reading in a row of the register. At this time, optionally, in each write operation for the first matrix, data of the first matrix is written in one column of the register, and one row of data of the register is read every read operation.

Optionally, in the embodiment of the present application, the amount of data that can be stored in one row of the register may be equal to the amount of data that can be stored in one column of the register.

Optionally, in the embodiment of the present application, one row of the register can be understood as a row of storage space, and a column of the register can be understood as a column of storage space.

It should be understood that, in the embodiment of the present application, the data of the matrix is read and written according to the data sequence, and the data of the matrix is read and written in the order of the storage space of the register, and the two implementation manners can be used in combination.

For example, in the embodiment of the present application, the number of rows of the register may be equal to the number of rows of the matrix, and the number of columns of the register may be equal to the number of columns of the matrix. In this case, each row of data of the matrix may be separately written to each row of the register, or Each column of data of the matrix can be written to each column of the register.

For example, when processing data of a plurality of matrices, the number of rows of the previous matrix may be equal to the number of columns of the latter matrix and the number of columns of the previous matrix may be equal to the number of rows of the latter matrix. At the same time, the number of rows of the register can be equal to the number of rows of the previous matrix, and the number of columns of the register can be equal to the number of columns of the previous matrix. In this case, each row of the previous matrix can be written to each row of the register, and then according to the column of the register. The data is read, so that the transposition of the previous matrix can be realized. When writing the latter matrix, each row of the latter matrix can be written into each column of the register, and then the data is performed according to the row of the register. Read, so that the transpose of the latter matrix can be achieved.

For example, when processing data of a plurality of matrices, the number of rows of the previous matrix may be equal to the number of columns of the latter matrix and the number of columns of the previous matrix may be equal to the number of rows of the latter matrix. At the same time, the number of rows of the register can be equal to the number of rows of the latter matrix, and the number of columns of the register can be equal to the number of columns of the latter matrix. At this time, each row of the previous matrix can be written into each column of the register, and then by the register. The row reads the data, so that the transposition of the previous matrix can be realized. When writing the latter matrix, each row of the latter matrix can be written into each row of the register, and then the data is performed according to the column of the register. The reading enables the transposition of the latter matrix.

It should be understood that, in the embodiment of the present application, the register may not be divided into columns and rows. For example, each storage space of the register can be numbered, and data of the matrix can be written and read according to the number of the storage space.

For example, the registers can be divided into storage spaces 1 (which can also be referred to as registers) 1, 2, 3, 4, 5, 6, 7, 8, 9. For a 3×3 matrix, the first row of the matrix data can be written to the storage space 1, 2, 3, and the second row of the matrix data is written to the storage space 4, 5, 6, and the third row of the matrix Data is written to the storage space 7, 8, 9, the first read operation can read the data in the storage space 1, 4, 7, and the second read operation can read the data in the storage space 2, 5, 8. The third read operation can read the data in the storage spaces 3, 6, and 9, so that the transposition of the 3 × 3 matrix can be realized.

It should be understood that the matrix mentioned in the embodiments of the present application (for example, the first matrix, the second matrix, and the third matrix) includes a plurality of numbers, which is a matrix in a mathematical sense, and the process of writing to the register and reading from the register may To achieve transposition of the matrix (or other forms of matrix transformation), the transposed matrix can be processed in conjunction with other numbers or matrices. However, when writing to the register, the plurality of numbers may be stored in a matrix arrangement, or may be stored in other forms, and the plurality of numbers may be matrixed when stored before being written to the register. The arrangement is stored and can be stored in other forms.

In order to more clearly understand the present application, a detailed description will be made below with reference to FIG. 3 and a transposition of a plurality of 2×2 matrices.

以及矩阵

)进行转置。 As shown in Figure 3, the register can include register R0, register R1, register R2 and register R3, which need to be used for multiple matrices (including matrices).

And matrix

) Transpose.

First, the initial value of the write address is 0. The controller can write data A0, A1 to the register R0, R1 (first write operation), write the write address to 1, and then write the data A2, A3. In the register R2, R3 (second write operation), the write address becomes 2 after writing.

At this point, the read enable is turned on. According to the fastest case, the controller can read the data in the next clock cycle after writing data A2 and A3, wherein the controller can be based on the next clock cycle. Read, judge whether the register is writable. If it is read, read the data A0, A2 (first read operation), and write the data B0, B1 in matrix 2 to the register group R0, R2 in the same clock cycle. (The third write operation), the write address becomes 3 after writing. And, in the next clock cycle, if read (read address 1), read A1, A3 (second read operation), and write the data of the second matrix B2, B3 to register group R1, R3 (fourth time) Write operation), the write address becomes 0 after writing. Then read address 2, read B0, B2 (third read manipulation), and write the matrix data C0 and C1 to register group R0, R1 (fifth write operation), write address becomes 1, and, in the next clock cycle, if read (read address 3), read B1, B3 (fourth read operation), and write data of matrix 3 C2, C3 to register group R1, R3 (sixth Write operation), write address becomes 2 after writing, and so on.

矩阵

矩阵

矩阵

矩阵

以及矩阵

等)进行转置操作，以及寄存器的地址分别为R0，R1，R2，R3，R4和R5。 For another example, as shown in FIG. 4, it is assumed that a matrix of a plurality of 2 rows and 3 columns (including a matrix) is required.

matrix

matrix

matrix

matrix

And matrix

Etc.) The transpose operation, and the address of the register are R0, R1, R2, R3, R4 and R5, respectively.

The data A0 and A1 of the matrix A (the first write operation) can be stored in the registers R0 and R1, and the data A2 and A3 of the matrix A (the second write operation) can be stored in the registers R2 and R3, and The data A4 and A5 of the matrix A are stored in the registers R4 and R5 (third write operation). At the first read operation, data A0 and A3 in registers R0 and R3 can be read, and data B0 and B1 of matrix B are written at this position (fourth write operation). At the second read operation, data A1 and A4 in R1 and R4 can be read, and data B2 and B3 of matrix B are stored in R1 and R4 (fifth write operation). Data A2 and A5 can be read in registers R2 and R5 at the third read operation, and data B4 and B5 of matrix B are written at the positions of registers R2 and R5 (sixth write operation). At the fourth read operation, data B0 and B3 can be read in registers R0 and R4, as well as data C0 and C1 (seventh write operation) written in matrix C. The data B1 and B4 can be read in the registers R3 and R2, and the data C2 and C3 in the matrix C (the eighth write operation) can be written in the fifth read operation. Data B2 and B5 can be read in registers R1 and R5, as well as data C4 and C5 in matrix C (ninth write operation) at the sixth read operation. At the seventh read operation, data C0 and C3 can be read in registers R0 and R2, and data D0 and D1 (tenth write operation) written in matrix D can be written. At the eighth read operation, data C1 and C4 can be read in registers R4 and R1, and data D2 and D3 in matrix D are written in the register (eleventh write operation). At the ninth read operation, data C2 and C5 can be read in registers R3 and R5, as well as data D4 and D5 written in matrix D (twelfth write operation). At the tenth read operation, the data D0 and D3 can be read in the registers R0 and R1, and the data E0 and E1 (the thirteenth write operation) written in the matrix E can be written. At the eleventh read operation, data D1 and D4 can be read in registers R2 and R3, and data E2 and E3 in the write matrix E (fourteenth write operation) can be read in the twelfth read. At the time of the fetch operation, the data D2 and D5 can be read in the registers R4 and R5, and the data E4 and E5 in the matrix E can be written (the fifteenth write operation). And, in the thirteenth read operation, the data E0 and E3 can be read in the registers R0 and R3, and the data F0 and F1 in the matrix F are written (the sixteenth write operation), and so on. .

It should be understood that the amount of data corresponding to each write operation shown in FIG. 4 is the same, but the amount of data corresponding to each write operation may also be different, for example, may be written in the first write operation. Into the data A0, A1 and A2, the data written in the second write operation is A3, A4 and A5, and the data amount of other write operations can be 2 data or the like.

Optionally, in the embodiment of the present application, when performing a read operation on the first matrix, searching for an entry to determine a target read location based on the current number of read operations, the entry indicating at least one read operation Correspondence with at least one read position; the read operation is performed based on the target read position.

Optionally, the entry may be an entry set based on the second data sequence. In this case, the data of the first matrix may be read in the second data sequence.

Alternatively, the entry may be an entry based on the second storage space order. In this case, the data of the first matrix may be read in the second storage space order.

The current number of read operations may be determined according to the count of the counter, wherein the counter may be cleared when the certain conditions are met, for example, the timer is cleared every time a new matrix of data is read. , or clear the counter when starting a read cycle.

The single read cycle can satisfy the following conditions: for different read cycles, the read positions corresponding to the same number of read operations are the same. And further, in the same reading cycle, the reading positions corresponding to different number of reading operations are different.

For example, in the case of the transposition shown in FIG. 3, the read position corresponding to the first read operation is the registers R0 and R2, and the read positions corresponding to the second read operation are R1 and R3, and the third read is performed. The read position corresponding to the fetch operation is R0 and R1, the read position corresponding to the fourth read operation is R2 and R3, and the read position corresponding to the fifth read operation is the registers R0 and R1, then the The one, two, three, and four read operations are referred to as one read cycle, and the fifth, sixth, seventh, and eighth read operations are referred to as one read cycle.

For example, in the case of the transposition as shown in FIG. 4, the read positions corresponding to the first and thirteenth read operations are the registers R0 and R3, and the second and fourteenth read operations are corresponding. The reading positions are R1 and R4, and the reading positions corresponding to the third and fifteenth reading operations are R2 and R5, etc., thereby showing that in the case of the transposition shown in FIG. 4, the single reading cycle The corresponding read operation is 12 times, and in the 12 read operations, the read positions corresponding to the different read operations are different. And in different read cycles, the read positions corresponding to the same number of read operations are the same, for example, the first read operation of the first read cycle and the first read of the second read cycle The read position corresponding to the fetch operation is the same.

The corresponding relationship between the number of read operations and the read position in a single read cycle may be pre-stored, and may be stored in an entry manner, so that each read operation may be determined by means of a lookup table entry. Read location.

Therefore, in the embodiment of the present application, the reading position corresponding to each reading operation is determined based on the manner of the entry, so that the reading position of the data to be read can be quickly obtained.

Moreover, further, storing the correspondence between the number of at least one read operation and the at least one read position in the single read cycle can reduce the storage amount of information.

Optionally, in the embodiment of the present application, the entry is searched based on the current number of write operations to determine a target write location for writing data of the second matrix, the entry indicating at least one write operation Correspondence with at least one write location.

The current number of writes may be determined according to a count, wherein the counter may be cleared when a certain condition is met, for example, the counter is cleared every time a new matrix is written, or a write is started. The counter is cleared when looping.

The single write cycle can satisfy the following conditions: for different write cycles, the write position corresponding to the same number of write operations is the same. And optionally, in the same write cycle, different write operations correspond to different write locations.

For example, in the case of the transposition shown in FIG. 3, the write positions corresponding to the first write operation are the registers R0 and R1, and the write positions corresponding to the second write operation are R2 and R3, the third time. The write position corresponding to the write operation is R0 and R2, the write position corresponding to the fourth write operation is R21 and R3, and the write position corresponding to the fifth write operation is the registers R0 and R1, then The first, second, third, and fourth write operations are referred to as a write cycle, and the fifth, sixth, seventh, and eighth write operations are referred to as a write cycle.

For example, in the case of the transposition as shown in FIG. 4, the write positions corresponding to the first and thirteenth read write operations are the registers R0 and R1, the second and fourteenth write operations. The corresponding write positions are R2 and R3, and the write positions corresponding to the third and fifteenth write operations are R4 and R5, etc., thereby showing that in the case of the transposition shown in FIG. 4, a single write The write operation corresponding to the loop is 12 times, and in the 12 write operations, the write positions corresponding to the different write operations are different. And in different write cycles, the write positions corresponding to the same number of write operations are the same, for example, the first write operation of the first write cycle and the first write of the second write cycle The write location corresponding to the incoming operation is the same.

Therefore, in the embodiment of the present application, the write location corresponding to each write operation is determined based on the manner of the entry, and the target write location can be quickly obtained.

Moreover, further, in the single write cycle, the correspondence between the number of at least one write operation and the at least one write position can reduce the amount of information stored.

It should be understood that the embodiment of the present application is not limited to the above description. For example, when a read operation is performed on data of the first matrix, a read position may be recorded; and the read position of the record is determined to be used for writing. The data entering the second matrix is the target write location.

That is to say, each time the data in the register is read, the read position can be recorded in real time, and the data of the other matrix is written in the recorded position in the same clock cycle.

Optionally, in the embodiment of the present application, before writing the data of the second matrix in the determined target write position, the controller may determine that the data in the target write location has been read.

Optionally, in the embodiment of the present application, the controller may determine whether the next clock cycle register is readable to determine whether the register is writable.

Optionally, in the embodiment of the present application, it is determined that the data to be read of the first matrix has been written.

Specifically, it may be determined that the data to be read of the first matrix has been written according to the number of write operations that have been performed for the first matrix.

For example, in the case shown in FIG. 3, when two write operations have been performed for the matrix (matrix 1 or matrix 2), the data to be read of the first matrix is considered to have been written. And in the case shown in Fig. 4, when three write operations have been performed for the matrix (matrix A, B, C, D, etc.), the data of the first matrix to be read has been considered to have been written.

Optionally, before the first read operation, it is determined that the data to be read of the first matrix has been written.

Specifically, in the embodiment of the present application, it is used for some matrices (for example, a matrix having the same number of rows and columns, and writing data of one column or one row at a time, and reading data of one row or one column at a time) In the case of transposition, if the data of the first read operation is written, it means that all the data of the matrix is written, so the first matrix can be determined only before the first read operation. The data to be read has been written, and it is not necessary to determine that the data to be read has been written before each read operation.

However, it should be understood that the embodiment of the present application is not limited thereto, and it may be determined that the current data to be read of the first matrix has been written before each read operation.

Optionally, in the embodiment of the present application, the external interface for reading and writing data can be encapsulated as a FIFO interface.

Therefore, in the embodiment of the present application, multiple read operations may be performed on the data of the first matrix in the register, and after each read operation, the controller writes the read position in the register to the second matrix again. The data can avoid the vacancy of the register after the read operation, so that the waste of register resources can be avoided while reducing the data processing speed.

FIG. 5 is a schematic block diagram of a controller 300 in accordance with an embodiment of the present application. The controller 300 includes a writing unit 310 and a reading unit 320;

The writing unit 310 is configured to: write data in the first matrix into the register;

The reading unit 320 is configured to: perform a plurality of read operations on the data of the first matrix in the register, wherein each read operation reads at least one data;

The writing unit 310 is further configured to: write at least one data of the second matrix at a target write position in the register after each read operation, wherein the target write position is each read operation The reading position.

Optionally, in the embodiment of the present application, the writing unit 310 is further configured to: write, in the first data order, data in the first matrix to the register for the data of the first matrix;

The reading unit 320 is further configured to:

The plurality of read operations are performed in the second data order for the data of the first matrix in the register.

Optionally, in the embodiment of the present application, the first data sequence is an order of writing in a matrix, and the second data sequence is an order of reading in a matrix of columns.

Optionally, in the embodiment of the present application, in each write operation for the first matrix, the writing unit 310 writes one row of data of the first matrix; and/or,

The reading unit 320 reads a column of data of the first matrix during each reading operation.

Optionally, in the embodiment of the present application, the first data sequence is an order of writing in columns of a matrix, and the second data sequence is an order of reading in rows of the matrix.

Optionally, in the embodiment of the present application, in each write operation for the first matrix, the writing unit 310 writes a column of data of the first matrix; and/or,

The reading unit 320 reads a row of data of the first matrix during each read operation.

Optionally, in the embodiment of the present application, the writing unit 310 is further configured to:

Writing the data in the first matrix to the register according to the first storage space order;

The reading unit 320 is further configured to:

A plurality of read operations are performed for the data of the first matrix in the register in accordance with the second storage space order.

Optionally, in the embodiment of the present application, the first storage space sequence is an order of writing in a row of the register, and the second storage space order is an order of reading in a column of the register.

Optionally, in the embodiment of the present application, in each write operation for the first matrix, the writing unit 310 writes data of the first matrix in one row of the register; and/or

The read unit 320 reads a column of data of the register during each read operation.

Optionally, in the embodiment of the present application, the first storage space sequence is an order of writing in a column of the register, and the second storage space order is an order of reading in a row of the register.

Optionally, in the embodiment of the present application, in each write operation for the first matrix, the writing unit 310 writes data of the first matrix in a column of the register; and/or,

The reading unit 320 reads one line of data of the register during each read operation.

Optionally, in the embodiment of the present application, the writing unit 310 is further configured to:

At least one of the data of the second matrix is written at the target write location in the register for the same clock cycle after the read operation.

Optionally, in the embodiment of the present application, the reading unit 320 is further configured to:

Recording a read position when performing a read operation for data of the first matrix;

The writing unit 310 is further configured to determine the read position of the record as the target write position for writing data of the second matrix.

Optionally, in the embodiment of the present application, the writing unit 310 is further configured to:

Finding a first entry to determine a target write location for writing data of the second matrix based on a current number of write operations, the first entry indicating at least one write operation and at least one write location Correspondence.

Optionally, in the embodiment of the present application, the first entry indicates a correspondence between the number of at least one write operation and the at least one write location in a single write cycle;

For different write cycles, the write position corresponding to the same number of write operations is the same.

Optionally, in the embodiment of the present application, in the same write cycle, the write positions corresponding to different write operations are different.

Optionally, in the embodiment of the present application, the reading unit 320 is further configured to:

When performing each read operation for the first matrix, searching for a second entry to determine a target read location based on the current number of read operations, the second entry indicating at least one read operation and at least one read Take the corresponding relationship of the location;

Each read operation is performed based on the target read position.

Optionally, in the embodiment of the present application, the second entry indicates a correspondence between the number of at least one read operation and the at least one read position in a single read cycle;

For different read cycles, the same read operation corresponds to the same read position.

Optionally, in the embodiment of the present application, in the same reading cycle, the reading positions corresponding to different reading operations are different.

Optionally, in the embodiment of the present application, the writing unit 310 is further configured to:

At the target write position, before the data of the second matrix is written, it is determined that the data in the target write position has been read.

Optionally, in the embodiment of the present application, the reading unit 320 is further configured to:

Before the first read operation, it is determined that the first data to be read of the first matrix has been written.

Optionally, in the embodiment of the present application, the reading unit 320 is further configured to:

Before each read operation after the first read operation, it is determined that the data to be read currently has been written.

Optionally, in the embodiment of the present application, the reading unit 320 is further configured to:

Based on the number of write operations that have been performed for the first matrix, it is determined that the data to be read of the first matrix has been written.

Optionally, in the embodiment of the present application, the number of rows of the first matrix is equal to the number of rows of the second matrix, and the number of columns of the first matrix is equal to the number of columns of the second matrix.

Optionally, in the embodiment of the present application, the reading unit 320 is further configured to:

Performing a plurality of read operations on the data of the second matrix in the register, wherein each read operation reads at least one data of the second matrix;

The writing unit 310 is further configured to: after each read operation, write at least one data of the third matrix at a target write position in the register, wherein the target write position is each read operation The reading position.

It should be understood that the controller 300 can implement the corresponding operations of the controller in the foregoing method embodiments, and details are not described herein for brevity.

FIG. 6 is a schematic block diagram of a data processing device 400 in accordance with an embodiment of the present application. As shown in FIG. 6, the device 400 includes a controller 410 and a register 420;

The controller 410 is operative to write data to the register 420 and to read data in the register.

Optionally, the data processing device is a central processing unit (CPU), or may be another type of processor, which is not specifically limited in this embodiment of the present application.

It should be understood that the controller 410 can implement the corresponding operations of the controller in the foregoing method embodiments, and details are not described herein for brevity.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

The functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product. Based on such understanding, the technical solution of the present application, which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including The instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

The foregoing is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It should be covered by the scope of protection of this application. Therefore, the scope of protection of the present application should be determined by the scope of the claims.

Claims (52)

A data processing method, comprising: Writing data in the first matrix to the register; Performing a plurality of read operations on data of the first matrix in the register, wherein each read operation reads at least one data; Writing at least one data of the second matrix at the target write position in the register after the each read operation, wherein the target write position is the read of the read operation position. The method according to claim 1, wherein said writing data in said first matrix to said register comprises: for said data of said first matrix, said first matrix in accordance with said first data order Data is written to the register; Performing a plurality of read operations on the data of the first matrix in the register, including: The plurality of read operations are performed in accordance with the second data order for the data of the first matrix in the register. The method according to claim 2, wherein the first data order is an order of writing in a matrix of rows, and the second data order is an order of reading in a matrix of columns. The method according to claim 3, wherein in each write operation for said first matrix, one row of data of said first matrix is written; and/or, The read operation reads a column of data of the first matrix. The method according to claim 2, wherein said first data order is an order of writing in columns of a matrix, and said second data order is an order of reading in rows of a matrix. The method according to claim 5, wherein in each write operation for said first matrix, a column of data of said first matrix is written; and/or, The read operation reads a row of data of the first matrix. The method of claim 1 wherein said writing data in said first matrix to said register comprises: Writing data in the first matrix to the register in a first storage space order; Performing a plurality of read operations on the data of the first matrix in the register, including: A plurality of read operations are performed for the data of the first matrix in the register in accordance with the second storage space order. The method according to claim 7, wherein said first storage space order is an order of writing in a row of said register, said second storage space order being read in a column of said register order of. The method of claim 8 wherein, in each write operation for said first matrix, data of said first matrix is written in a row of said register; and/or The read operation reads a column of data of the register. The method according to claim 7, wherein said first storage space order is an order of writing in a column of said register, said second storage space order being read in a row of said register order of. The method according to claim 10, wherein in each write operation for said first matrix, data of said first matrix is written in a column of said register; and/or said Each row of data reads a row of the register. The method according to any one of claims 1 to 11, wherein at least one data of the second matrix is written at a target write position in the register after the each read operation, include: At least one of the data of the second matrix is written at the target write location in the register for the same clock cycle after the read operation. The method according to any one of claims 1 to 12, further comprising: Recording the read position when performing the each read operation on the data of the first matrix; The read position of the record is determined as the target write position of data for writing to the second matrix. The method according to any one of claims 1 to 13, wherein the method further comprises: Finding the first entry to determine the target write location for writing data of the second matrix based on a current number of write operations, the first entry indicating at least one write operation and at least one The correspondence of the write locations. The method according to claim 14, wherein the first entry indicates a correspondence between the number of at least one write operation and at least one write position in a single write cycle; For different write cycles, the write position corresponding to the same number of write operations is the same. The method according to claim 15, wherein in the same write cycle, the write positions corresponding to different number of write operations are different. The method according to any one of claims 1 to 16, wherein performing a plurality of read operations for the data of the first matrix in the register comprises: When performing the each read operation for the first matrix, searching for a second entry to determine a target read location based on the current number of read operations, the second entry indicating at least one read operation Correspondence with at least one reading position; The each read operation is performed based on the target read position. The method according to claim 17, wherein the second entry indicates a correspondence between the number of at least one read operation and the at least one read position in a single read cycle; For different read cycles, the same read operation corresponds to the same read position. The method according to claim 17, wherein in the same reading cycle, the reading positions corresponding to the different number of reading operations are different. The method according to any one of claims 1 to 19, further comprising: At the target write position, before writing the data of the second matrix, it is determined that the data in the target write location has been read. The method according to any one of claims 1 to 20, wherein the method further comprises: Before the first read operation, it is determined that the first data to be read of the first matrix has been written. The method of claim 21, wherein the method further comprises: Before each read operation after the first read operation, it is determined that the data to be read currently has been written. The method according to claim 21 or 22, wherein the determining that the data to be read of the first matrix has been written comprises: It is determined that the data to be read of the first matrix has been written according to the number of write operations that have been performed for the first matrix. The method according to any one of claims 1 to 23, wherein the number of rows of the first matrix is equal to the number of rows of the second matrix, and the number of columns of the first matrix is equal to the second The number of columns in the matrix. The method according to any one of claims 1 to 24, wherein the method further comprises: Performing a plurality of read operations on data of the second matrix in the register, wherein each read operation reads at least one data of the second matrix; Writing at least one data of the third matrix at the target write position in the register after the each read operation, wherein the target write position is the read of the read operation position. A controller, comprising: a writing unit and a reading unit; wherein The writing unit is configured to: write data in the first matrix into a register; The reading unit is configured to: perform a plurality of read operations on data of the first matrix in the register, wherein each read operation reads at least one data; The writing unit is further configured to: after the each read operation, write at least one data of the second matrix at a target write position in the register, wherein the target write location is The reading position of each read operation. The controller according to claim 26, wherein the writing unit is further configured to: write data in the first matrix according to a first data order for data of the first matrix Register The reading unit is further configured to: The plurality of read operations are performed in accordance with the second data order for the data of the first matrix in the register. The controller according to claim 27, wherein said first data order is an order of writing in rows of a matrix, and said second data order is an order of reading in columns of a matrix. The controller according to claim 28, wherein in each write operation for said first matrix, said write unit writes one row of data of said first matrix; and/or The reading unit reads a column of data of the first matrix during the each reading operation. The controller according to claim 27, wherein said first data order is an order of writing in a matrix of columns, and said second data order is an order of reading in a row of a matrix. The controller according to claim 30, wherein in each write operation for said first matrix, said write unit writes a column of data of said first matrix; and/or The reading unit reads a row of data of the first matrix during the each reading operation. The controller according to claim 26, wherein said writing unit is further configured to: Writing data in the first matrix to the register in a first storage space order; The reading unit is further configured to: A plurality of read operations are performed for the data of the first matrix in the register in accordance with the second storage space order. The controller according to claim 32, wherein said first storage space order is an order of writing in a row of said register, said second storage space order being read in a column of said register The order of taking. The controller according to claim 33, wherein in each write operation for said first matrix, said writing unit writes data of said first matrix in one row of said register; and / or The reading unit reads a column of data of the register during the each read operation. The controller according to claim 32, wherein said first storage space order is an order of writing in a column of said register, said second storage space order being read in a row of said register The order of taking. The controller according to claim 35, wherein in each write operation for said first matrix, said write unit writes data of said first matrix in a column of said register; and / or, The reading unit reads a row of data of the register during the each read operation. The controller according to any one of claims 26 to 36, wherein the writing unit is further configured to: At least one of the data of the second matrix is written at the target write location in the register for the same clock cycle after the read operation. The controller according to any one of claims 26 to 37, wherein the reading unit is further configured to: Recording the read position when performing the each read operation on the data of the first matrix; The writing unit is further configured to: determine the read position of the record as the target write position for writing data of the second matrix. The controller according to any one of claims 26 to 38, wherein the writing unit is further configured to: Finding the first entry to determine the target write location for writing data of the second matrix based on a current number of write operations, the first entry indicating at least one write operation and at least one The correspondence of the write locations. The controller according to claim 39, wherein the first entry indicates a correspondence between the number of at least one write operation and the at least one write position in a single write cycle; For different write cycles, the write position corresponding to the same number of write operations is the same. The controller according to claim 40, wherein in the same write cycle, the write positions corresponding to the different number of write operations are different. The controller according to any one of claims 26 to 41, wherein the reading unit is further configured to: When performing the each read operation for the first matrix, searching for a second entry to determine a target read location based on the current number of read operations, the second entry indicating at least one read operation Correspondence with at least one reading position; The each read operation is performed based on the target read position. The controller according to claim 42, wherein the second entry indicates a correspondence between the number of at least one read operation and the at least one read position in a single read cycle; For different read cycles, the same read operation corresponds to the same read position. The controller according to claim 42, wherein in the same reading cycle, the reading positions corresponding to the different number of reading operations are different. The controller according to any one of claims 26 to 44, wherein the writing unit is further configured to: At the target write position, before writing the data of the second matrix, it is determined that the data in the target write location has been read. The controller according to any one of claims 26 to 45, wherein the reading unit is further configured to: Before the first read operation, it is determined that the first data to be read of the first matrix has been written. The controller according to claim 46, wherein said reading unit is further configured to: Before each read operation after the first read operation, it is determined that the data to be read currently has been written. The controller according to claim 46 or 47, wherein the reading unit is further configured to: It is determined that the data to be read of the first matrix has been written according to the number of write operations that have been performed for the first matrix. The controller according to any one of claims 26 to 48, wherein the number of rows of the first matrix is equal to the number of rows of the second matrix, and the number of columns of the first matrix is equal to the number of The number of columns in the two matrix. The controller according to any one of claims 26 to 49, wherein the reading unit is further configured to: Performing a plurality of read operations on data of the second matrix in the register, wherein each read operation reads at least one data of the second matrix; The writing unit is further configured to: after the each read operation, write at least one data of the third matrix at a target write position in the register, wherein the target write location is The reading position of each read operation. A data processing device, comprising: the controller and the register according to any one of claims 26 to 50; wherein The controller is operative to write data to the register and to read data in the register. The device according to claim 51, characterized in that the data processing device is a central processing unit CPU.

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