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WO2019177268A1 - Procédé de fabrication d'une cellule solaire à semi-conducteur composé - Google Patents

Procédé de fabrication d'une cellule solaire à semi-conducteur composé Download PDF

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Publication number
WO2019177268A1
WO2019177268A1 PCT/KR2019/001226 KR2019001226W WO2019177268A1 WO 2019177268 A1 WO2019177268 A1 WO 2019177268A1 KR 2019001226 W KR2019001226 W KR 2019001226W WO 2019177268 A1 WO2019177268 A1 WO 2019177268A1
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Prior art keywords
layer
compound semiconductor
solution
mesa etching
forming
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Korean (ko)
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권구한
김수현
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LG Electronics Inc
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LG Electronics Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/12—Active materials
    • H10F77/124—Active materials comprising only Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/12—Active materials
    • H10F77/124—Active materials comprising only Group III-V materials, e.g. GaAs
    • H10F77/1248—Active materials comprising only Group III-V materials, e.g. GaAs having three or more elements, e.g. GaAlAs, InGaAs or InGaAsP
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • H10P50/00—
    • H10P50/642—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing a compound semiconductor solar cell, and more particularly, it is possible to improve the yield by securing the stability in the mesa etching (mesa etching) process, manufactured by forming a back electrode using an inexpensive electrode material
  • the present invention relates to a method for manufacturing a compound semiconductor solar cell capable of lowering the cost.
  • Compound semiconductors act as semiconductors by combining two or more elements rather than a single element such as silicon or germanium.
  • Various kinds of compound semiconductors are currently developed and used in various fields, and typically, light emitting devices such as light emitting diodes and laser diodes using photoelectric conversion effects, solar cells, and thermoelectric conversion devices using Peltier effect. Is used.
  • compound semiconductor solar cells are gallium arsenide (hereinafter referred to as GaAs), gallium indium phosphorus (hereinafter referred to as GaInP), gallium aluminum arsenide (hereinafter referred to as GaAlAs), gallium indium arsenide (hereinafter referred to as GaInAs).
  • III-V compound semiconductors such as aluminum indium arsenide (hereinafter referred to as AlInP), II-VI compound semiconductors such as cadmium sulfur (CdS), cadmium tellurium (CdTe), and zinc sulfur (ZnS),
  • Various layers are formed using an I-III-VI compound semiconductor or the like represented by copper indium selenium (CuInSe2).
  • the various layers formed of the compound semiconductor are mosquitoes by metal organic chemical vapor deposition (MOCVD) method, molecular beam epitaxy (MBE) method or any other suitable method for forming an epitaxial layer.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the substrate is formed on a mother substrate, and then a front surface electrode of a grid pattern is formed on the front surface of the compound semiconductor layer, and a rear surface electrode having a sheet shape is formed on the rear surface of the compound semiconductor layer.
  • an etching prevention film is formed on the entire surface of the compound semiconductor layer, and an etching solution (acid / base) for etching the compound semiconductor forming the compound semiconductor layer is formed.
  • a back electrode exposed by mesa etching is scribed to manufacture a plurality of compound semiconductor solar cells.
  • mesa etching means an etching process for manufacturing several compound semiconductor solar cells from one compound semiconductor layer by separating one compound semiconductor layer into several.
  • the metal forming the back electrode of the compound semiconductor solar cell has a low contact resistance with a lowermost layer of the compound semiconductor layer, for example, a back contact layer formed of GaAs, and a mesa etching process. And it is not etched through the EPO (Epotaxial Lift Off) process, and must meet the conditions such as having a high back reflectivity.
  • EPO Electrode Lift Off
  • gold (Au) is usually used as a metal for forming the back electrode.
  • the present invention provides a method for manufacturing a compound semiconductor solar cell that can ensure the stability in the mesa etching process (mea etching) to improve the yield, and can reduce the manufacturing cost by manufacturing the back electrode using an inexpensive metal material The purpose is.
  • Method of manufacturing a compound semiconductor solar cell comprises the steps of forming a sacrificial layer on the mother substrate; Forming a compound semiconductor layer on the sacrificial layer; Primary mesa etching is performed to form a first region of the compound semiconductor layer as a first portion having a first thickness, and to form a second region of the compound semiconductor layer having a second thickness smaller than the first thickness.
  • Forming into a second portion Forming a protective layer on the first surface of the compound semiconductor layer; Separating the compound semiconductor layer from the mother substrate; Forming a back electrode on a second side of the compound semiconductor layer opposite to the first side; Removing the protective layer; Performing a second mesa etch to remove the second portion of the compound semiconductor layer in the second region; And scribing the back electrode of the second region.
  • the forming of the back electrode may include forming a first electrode layer made of silver (Ag) in direct contact with the second surface of the compound semiconductor layer; And forming a second electrode layer of copper (Cu) on a rear surface of the first electrode layer.
  • the thickness of the second electrode layer may be formed to 70% or more of the total thickness of the rear electrode.
  • the compound semiconductor layer can be formed in a single junction structure or multiple junction structures.
  • the compound semiconductor layer may include a first light absorbing layer based on indium phosphorus (InP); At least one first peripheral layer on the first surface of the first light absorbing layer and based on indium phosphorus (InP) and / or gallium arsenide (GaAs); And at least one second peripheral layer on the second surface of the first light absorbing layer and based on indium phosphorus (InP) and / or gallium arsenide (GaAs).
  • InP indium phosphorus
  • GaAs gallium arsenide
  • the first mesa etching step is a mixture of a first solution containing hydrochloric acid (HCl) and / or ammonium hydroxide (NH 4 OH) / hydrogen peroxide (H 2 O 2 ) / deionized water (DI).
  • HCl hydrochloric acid
  • DI deionized water
  • a first mesa etch step of removing the first peripheral layer of the second region using a second solution wherein the second mesa etch step comprises the first solution of the second region using the first solution
  • a second mesa etching step of removing the light absorbing layer And removing the second peripheral layer in the second region using a third solution mixed with the second solution and / or phosphoric acid (H 3 PO 4 ) / hydrogen peroxide (H 2 O 2 ) / deionized water (DI).
  • a third mesa etching step may be included.
  • the compound semiconductor layer includes a second light absorbing layer based on gallium arsenide (GaAs); At least one third peripheral layer on the first surface of the second light absorbing layer and based on indium phosphorus (InP) and / or gallium arsenide (GaAs); And at least one fourth peripheral layer positioned on a second surface of the second light absorbing layer and based on indium phosphorus (InP) and / or gallium arsenide (GaAs).
  • the light absorbing layer may be located between the first light absorbing layer and the back electrode.
  • the first mesa etching step is a mixture of a first solution containing hydrochloric acid (HCl) and / or ammonium hydroxide (NH 4 OH) / hydrogen peroxide (H 2 O 2 ) / deionized water (DI).
  • the lowermost layer in direct contact with the rear electrode among the second peripheral layer in the case of a single junction structure and the fourth peripheral layer in the case of the multiple junction structure is based on gallium arsenide (GaAs).
  • GaAs gallium arsenide
  • the bottom layer may be removed using the third solution.
  • the third solution may be formed by mixing phosphoric acid (H 3 PO 4 ) / hydrogen peroxide (H 2 O 2 ) / deionized water (DI) in a ratio of 1: 0.3 to 3: 5 to 20.
  • the forming of the protective layer may include forming a first protective layer based on indium phosphorus (InP) on the first peripheral layer, and forming a second protective layer formed of copper (Cu) on the first protective layer.
  • the step of performing the first mesa etching and the step of performing the second mesa etching may be performed using the same etch stop layer.
  • the etch stop layer for performing the primary mesa etching is not removed after completing the primary mesa etching, it can be removed after performing the secondary mesa etching.
  • the step of performing the first mesa etching and the step of performing the second mesa etching may be performed using different etching prevention layers.
  • the etch stop layer is removed, and another etch stop layer for the second mesa etch may be formed in the second region.
  • the method for manufacturing a compound semiconductor solar cell according to the present invention it is not necessary to use expensive gold (Au) when forming the back electrode, and the back side using copper (Cu) / silver (Ag) which is very inexpensive compared to gold. Since the electrode can be formed, the manufacturing cost of the compound semiconductor solar cell can be reduced.
  • the first mesa etching is performed before forming the back electrode and the second mesa etching after forming the back electrode, copper having a higher tendency of oxidation than the light absorbing layer or the peripheral layer based on indium phosphorus (InP).
  • InP indium phosphorus
  • the first electrode layer of the rear electrode is the third solution as soon as the bottom layer is removed. Even if exposed to the first electrode layer can be prevented from etching.
  • FIG. 1 is a block diagram illustrating a method of manufacturing a compound semiconductor solar cell according to a first embodiment of the present invention.
  • FIG. 2 is a process diagram illustrating a sacrificial layer forming step and a compound semiconductor layer forming step shown in FIG. 1.
  • FIG. 3 is a process diagram showing a first embodiment of the first mesa etching step shown in FIG.
  • FIG. 4 is a process diagram illustrating the protective layer forming step illustrated in FIG. 1.
  • FIG. 5 is a process diagram showing the separation step shown in FIG. 1.
  • FIG. 6 is a process chart illustrating a step of forming a rear electrode illustrated in FIG. 1.
  • FIG. 7 is a process diagram showing a first embodiment of the second mesa etching step shown in FIG. 1.
  • FIG. 8 is a process diagram illustrating the scribing step shown in FIG. 1.
  • FIG. 9 is a cross-sectional view of a compound semiconductor solar cell having a compound semiconductor layer of a single junction structure manufactured by the manufacturing method shown in FIG. 1.
  • FIG. 11 is a process diagram illustrating a second embodiment of the first mesa etching step illustrated in FIG. 1.
  • FIG. 12 is a process diagram showing a second embodiment of the secondary mesa etching step shown in FIG.
  • FIG. 13 is a cross-sectional view of a compound semiconductor solar cell having a compound semiconductor layer having a double junction structure manufactured by the manufacturing method shown in FIG. 1.
  • first and second may be used to describe various components, but the components may not be limited by the terms. The terms may be used only for the purpose of distinguishing one component from another component.
  • the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.
  • the term "and / or” may include a combination of a plurality of related items or any of a plurality of related items.
  • FIG. 1 is a block diagram illustrating a method of manufacturing a compound semiconductor solar cell according to a first embodiment of the present invention
  • FIG. 2 is a process diagram illustrating a sacrificial layer forming step and a compound semiconductor layer forming step shown in FIG. 1
  • FIG. 3. 1 is a process chart showing a first embodiment of the first mesa etching step shown in FIG.
  • FIG. 4 is a process chart showing the protective layer forming step shown in FIG. 1
  • FIG. 5 is a process chart showing the separating step shown in FIG. 1
  • FIG. 6 is a process chart showing the back electrode forming step shown in FIG.
  • FIG. 7 is a process chart showing a first embodiment of the second mesa etching step shown in FIG. 1
  • FIG. 8 is a process chart showing the scribing step shown in FIG.
  • FIG. 9 is a cross-sectional view of a compound semiconductor solar cell having a compound semiconductor layer having a single junction structure manufactured by the manufacturing method illustrated in FIG. 1, and FIG. 10 is a graph comparing light reflectance of each wavelength of the back electrode forming material. .
  • a compound semiconductor solar cell having a compound semiconductor layer having a single junction structure includes only one cell, that is, the first cell C1, and each layer forming the first cell C1 is formed of a compound semiconductor.
  • the first cell C1 may include a first light absorbing layer PV1 and a first window layer WD1 and a first light absorbing layer positioned on a first surface of the first light absorbing layer PV1, for example, a front surface.
  • the first rear electric field layer BSF1 disposed on the second surface of the PV1, for example, the rear surface, the front contact layer FC disposed on the front surface of the first window layer WD1, and the first rear electric field layer And a rear contact layer (BC) located at the rear of the BSF1).
  • the front window layer WD1 and the front contact layer FC form the first peripheral layer BL1
  • the rear electric field layer BSF1 and the rear contact layer BC form the second peripheral layer BL2.
  • the compound semiconductor solar cell including the compound semiconductor layer having a single junction structure includes a grid-shaped front electrode 100 and a rear contact layer BC positioned on the front contact layer FC in addition to the first cell C1. It further comprises a sheet-shaped rear electrode 200 located on the rear of the).
  • the first light absorbing layer PV1 includes the first base layer PV1-1 including n-type impurities and in contact with the first window layer WD1, and the first base layer PV1-1 including p-type impurities.
  • the first emitter layer PV1-2 is formed on the rear surface of the first base layer PV1-1 to form a pn junction with the first base layer PV1-1 and the first emitter layer PV1 -1. 2) is formed of a compound semiconductor based on indium phosphorus (hereinafter referred to as InP).
  • the first base layer PV1-1 is formed of n-type GaInP
  • the first emitter layer PV1-2 is formed of p-type GaInP.
  • the p-type impurity doped in the first emitter layer PV1-2 may be selected from carbon (C), magnesium (Mg), zinc (Zn), or a combination thereof, and may be selected from the first base layer PV1-1.
  • the doped n-type impurity may be selected from silicon (Si), selenium (Se), tellurium (Te), or a combination thereof.
  • the first base layer PV1-1 may be positioned in an area adjacent to the front electrode 100, and the first emitter layer PV1-2 is directly below the first base layer PV1-1. It may be located in an area adjacent to).
  • the distance between the first base layer PV1-1 and the front electrode 100 is smaller than the distance between the first emitter layer PV1-2 and the front electrode 100, and the first base layer PV1-1.
  • the distance between 1) and the back electrode 200 is greater than the distance between the first emitter layer PV1-2 and the back electrode 200.
  • a pn junction in which the first emitter layer PV1-2 and the first base layer PV1-1 are joined to each other is formed in the first light absorbing layer PV1, and thus, the first light absorbing layer PV1 is incident on the first light absorbing layer PV1.
  • the electron-hole pair generated by the generated light is separated into electrons and holes by the internal potential difference formed by the pn junction of the first light absorption layer PV1, and the electrons move toward the n-type, and the holes move toward the p-type.
  • holes generated in the first light absorbing layer PV1 move to the rear electrode 200 through the back contact layer BC, and electrons generated in the first light absorbing layer PV1 are the first window layer WD1. And move to the front electrode 100 through the front contact layer FC.
  • the first rear electric field layer BSF1 has the same conductivity type as that of the upper layer that is in direct contact, that is, the first emitter layer PV1-2. It may be formed of the same material as the first window layer (WD1).
  • the first rear electric field layer BSF1 is an upper layer that is in direct contact, that is, to effectively block the movement of charges (holes or electrons) to be moved toward the front electrode 100 toward the rear electrode 200. It is formed entirely on the rear surface of the first emitter layer PV1-2.
  • the first rear electric field layer BSF1 when the first rear electric field layer BSF1 is formed on the rear surface of the first emitter layer PV1-2, the first rear electric field layer BSF1 is formed of electrons having a rear electrode ( The first rear electric field layer BSF1 is disposed on the entire rear surface of the first emitter layer PV1-2 in order to block the movement toward the 200 and to effectively block the movement of electrons toward the rear electrode 200. Located.
  • the first emitter layer PV1-2 and the first base layer PV1-1 may be made of the same material having the same bandgap (homogeneous junction), and different materials having different bandgaps may be different. It may consist of (heterojunction).
  • the first base layer PV1-1 may be formed of n-type GaInP
  • the first emitter layer PV1-2 may be formed of p-type GaInP.
  • the first window layer WD1 may be formed between the first light absorbing layer PV1 and the front electrode 100.
  • the first window layer WD1 may be doped with a fourth conductive group III-VI semiconductor compound by doping with a second conductive type, that is, n-type impurities. Can be formed.
  • the first window layer ( WD1) may include impurities of a first conductivity type, that is, p-type.
  • the first window layer WD1 functions to passivate the front surface of the first light absorbing layer PV1. Therefore, when the carrier (electrons or holes) move to the surface of the first light absorption layer PV1, the first window layer WD1 may prevent the carrier from recombining on the surface of the first light absorption layer PV1.
  • the first window layer WD1 is disposed on the entire surface of the first light absorbing layer PV1, that is, on the light incident surface, the first light absorbing layer hardly absorbs the light incident on the first light absorbing layer PV1. It is necessary to have an energy band gap higher than the energy band gap of (PV1).
  • the first window layer WD1 it is necessary to form the first window layer WD1 using a material that is difficult to dissolve in an ELO process using hydrofluoric acid.
  • the first window layer WD1 may be formed of AlInP or AlGaInP.
  • AlGaInP may exhibit a bandgap similar to that of AlInP by appropriately adjusting the content of aluminum (Al), and unlike AlInP, AlGaInP may suppress dissolution due to hydrofluoric acid used in an ELO process.
  • the direct / indirect transition occurs when the aluminum content is 53%, and in the section where the aluminum content is 53% or less, the band gap decreases rapidly as the aluminum content decreases. It can be seen that the content of 53% or more has a bandgap almost similar to that of AlInP.
  • AlGaInP has a bandgap of 2.22Ev similar to 2.3eV, which is a bandgap of AlInP.
  • the aluminum content within a range that can suppress defects caused by hydrofluoric acid while having a bandgap similar to that of AlInP, for example, 2.2 eV or more, and an aluminum content satisfying the above conditions. It can be seen that the content of aluminum is 45 to 70 when the content of aluminum and gallium is in the range of 100.
  • the reason for limiting the minimum content of aluminum to 45 is to form a bandgap of AlGaInP of 2.2 ev or more, and the reason for limiting the maximum content of aluminum to 70 is for suppressing dissolution by hydrofluoric acid.
  • the first window layer WD1 may be formed of n-type Al x Ga 1 - x InP having X of 0.45 to 0.7.
  • the first window layer WD1 formed of AlGaInP may be formed to a thickness of 20 to 35 nm, and the first back surface field layer BSF1 may be formed of the same material as the first window layer WD1.
  • the first rear electric field layer BSF1 may be formed thicker than the thickness of the first window layer WD1.
  • the first back surface field layer BSF1 may be formed to a thickness of 50 to 100 nm.
  • the anti-reflection film (not shown) may be located in the remaining areas except the area where the front electrode 100 and / or the front contact layer FC are positioned on the front surface of the first window layer WD1.
  • the anti-reflection film may be disposed not only on the first window layer WD1 but also on the front contact layer FC and the front electrode 100.
  • the antireflection film having such a configuration may include magnesium fluoride, zinc sulfide, titanium oxide, silicon oxide, derivatives thereof, or a combination thereof.
  • the compound semiconductor solar cell may further include a busbar electrode that physically connects the plurality of front electrodes 100, and the busbar electrode may be exposed to the outside without being covered by an anti-reflection film. .
  • the front electrode 100 may be formed to extend in a first direction, and the plurality of front electrodes 100 may be spaced apart at regular intervals along a second direction Y-Y ′ perpendicular to the first direction.
  • the front electrode 100 having such a configuration may be formed by including an electrically conductive material.
  • the front electrode 100 may include at least one of gold (Au), germanium (Ge), and nickel (Ni).
  • the front contact layer FC positioned between the first window layer WD1 and the front electrode 100 is doped with a group III-VI semiconductor compound with impurities of a second conductivity type higher than that of the first base layer PV1-1. It can be formed by doping at a concentration.
  • the front contact layer FC may be formed of n + type GaAs.
  • the front contact layer FC forms an ohmic contact between the first window layer WD1 and the front electrode 100. That is, when the front electrode 100 directly contacts the first window layer WD1, the impurity doping concentration of the first window layer WD1 is low, and thus, the front electrode 100 and the first light absorbing layer PV1 may be in contact with each other. Ohmic contact is not well formed.
  • the carrier moved to the first window layer WD1 may disappear easily rather than move to the front electrode 100.
  • the front contact layer FC is formed between the front electrode 100 and the first window layer WD1, carrier movement is prevented by the front contact layer FC forming the ohmic contact with the front electrode 100. It is made smoothly increases the short-circuit current density (Jsc) of the compound semiconductor solar cell. Accordingly, the efficiency of the solar cell can be further improved.
  • Jsc short-circuit current density
  • the front contact layer FC may be formed in the same planar shape as the front electrode 100.
  • the rear contact layer BC disposed on the rear surface of the first rear electric field layer BSF1 is generally located at the rear of the first rear electric field layer BSF1 and doped with impurities of the first conductivity type to the group III-VI semiconductor compound. Can be formed.
  • the back contact layer BC may be formed of p-type GaAs.
  • the back contact layer BC may form an ohmic contact with the back electrode 200, thereby further improving the short circuit current density Jsc of the compound semiconductor solar cell. Accordingly, the efficiency of the solar cell can be further improved.
  • the thickness of the front contact layer FC and the back contact layer BC may be formed to have a thickness of 100 nm to 300 nm, respectively.
  • the front contact layer FC may be formed to a thickness of 100 nm and the rear contact layer BC may be formed to a thickness of 300 nm.
  • the rear electrode 200 positioned on the rear surface of the rear contact layer BC may be formed of a sheet-shaped conductor positioned entirely on the rear surface of the rear contact layer BC. . That is, the rear electrode 200 may be referred to as a sheet electrode positioned on the entire rear surface of the rear contact layer BC.
  • the back electrode 200 may be formed in the same plane as the first light absorbing layer PV1, and may include the first electrode layer 200A and the second electrode layer 200B.
  • the first electrode layer 200A is positioned at the bottom of the second peripheral layer BL2 of the first cell C1, for example, at the rear of the rear contact layer BC, and directly contacts the rear surface of the rear contact layer BC.
  • the carrier is transmitted, and the second electrode layer 200B is positioned on the rear surface of the first electrode layer 200A to support the first electrode layer 200A.
  • the first electrode layer 200A that transmits a carrier is formed of a material having a high reflectivity while forming a conventional back electrode forming material, that is, a material having a level of contact resistance similar to that of gold (Au). It is desirable to.
  • zinc (Zn) is According to check the contact resistance with the p + GaAs layer doped with a high concentration of 1e19 / cm3 level, gold (Au) is approximately 3.5 ⁇ 10 - has a contact resistance of ⁇ cm2 3, is ( Ag) is approximately 3.6 ⁇ 10 - it can be seen that it has a contact resistance of 2 ⁇ cm2 - has a contact resistance of 3 ⁇ cm2, copper (Cu) is about 5.2 ⁇ 10.
  • silver (Ag) has an average reflectivity of 95% or more at a wavelength of 600 nm to 950 nm, which is a wavelength range of interest, but copper (Cu) is higher than silver (Ag). It can be seen that the reflectivity is low.
  • the first electrode layer 200A which is in direct contact with the back contact layer 200A has excellent electrical bonding characteristics with the back contact layer BC and physically contains silver (Ag) having an average reflectivity of 95% or more in the wavelength range of 600 nm to 950 nm. It can be formed by vapor deposition to a thickness of 50 to 500 nm by physical vapor deposition (physical vapor deposition).
  • the second electrode layer 200B is electroplated with copper (Cu), which has a high contact resistance and low reflectivity in the wavelength range of 600 nm to 950 nm, but a low material cost, compared to silver (Ag) forming the first electrode layer 200B.
  • Cu copper
  • the rear contact layer BC is used.
  • photon recycling photon recycling
  • the compound semiconductor solar cell of such a structure can be manufactured using an ELO process.
  • Crying may include a step (S90).
  • a sacrificial layer (1) on one side of a mother substrate 300 serves as a base layer for providing an appropriate lattice structure in which the first compound semiconductor layer CS1 is formed.
  • the first compound semiconductor layer CS1 is formed on the sacrificial layer 400.
  • the sacrificial layer 400 and the first compound semiconductor layer CS1 may be formed by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or any other suitable method for forming an epitaxial layer. have.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the mother substrate 300 has a size capable of manufacturing a plurality of compound semiconductor solar cells, the first compound semiconductor layer CS1 also formed on the sacrificial layer 400 of the mother substrate 300 and the mother substrate 300. Have the same size as).
  • the planar area of the mother substrate 300 and the planar area of the first compound semiconductor layer CS1 are the same.
  • FIGS. 2 to 9 illustrate that one first compound semiconductor layer CS1 separated from the mother substrate 300 forms two compound semiconductor solar cells as an example, but a compound semiconductor solar cell The number of can be suitably selected as needed.
  • the first compound semiconductor layer CS1 sequentially forms a rear contact layer BC formed of p-type GaAs and a first rear electric field layer BSF1 formed of p-type AlGaInP to form a second peripheral layer BL2.
  • the first light emitting layer PV1 is formed by sequentially forming the first emitter layer PV1-2 formed of p-type GaInP and the first base layer PV1-1 formed of n-type GaInP, and formed of n-type AlGaInP.
  • the front contact layer FC formed of the first window layer WD1 and the n + type GaAs may be sequentially formed to form the first peripheral layer BL1.
  • At least one layer of the plurality of layers constituting the first peripheral layer BL1 may be omitted, and at least one layer of the plurality of layers constituting the second peripheral layer BL2 may be omitted.
  • an etch barrier 500A exposing the second region A2 of the first compound semiconductor layer CS1 is formed on the first peripheral layer BL1 of the first region A1, and the etch barrier 500A is formed.
  • Primary mesa etching is performed using it as a mask (S30).
  • the reason for performing the first mesa etching before forming the back electrode 200 is that InP such as GaInP, AlInP, or AlGaInP is formed in the first peripheral layer BL1 forming the first cell C1.
  • InP such as GaInP, AlInP, or AlGaInP is formed in the first peripheral layer BL1 forming the first cell C1.
  • HCl hydrochloric acid
  • Cu copper
  • the portion of the first compound semiconductor layer CS1 to be removed of the layer formed of GaInP, AlInP, or AlGaInP can be effectively removed using the first solution. Can be.
  • the first mesa etching step S30 may include a first solution including hydrochloric acid (HCl) and / or ammonium hydroxide (NH 4 OH) / hydrogen peroxide (H). And a first mesa etching step of removing the first peripheral layer BD1 of the second region A2 using a second solution mixed with 2 O 2 ) / deionized water DI.
  • HCl hydrochloric acid
  • NH 4 OH ammonium hydroxide
  • H hydrogen peroxide
  • the portion located in the second region A2 may have ammonium hydroxide, hydrogen peroxide and deionized water in a ratio of 1: 2: 10.
  • the second solution formed by mixing is removed using a second solution, and then a portion of the first window layer WD1 formed of n-type AlInP or n-type AlGaInP located in the second region A2 is removed using the first solution. do.
  • the first mesa etching step may remove the layer using only one of the first solution and the second solution.
  • the first region A1 of the first compound semiconductor layer CS1 is formed of the first portion P1 having the first thickness T1, and the first compound semiconductor layer CS1 is formed.
  • the second area A2 of) is formed of the second portion P2 of the second thickness T2 smaller than the first thickness T1.
  • the etch stop film 500A for performing the first mesa etching step S30 is removed after performing the first mesa etching step. However, after performing the first mesa etching step, it is also possible to use it as a mask in the second mesa etching step without removing the etch stop layer 500A.
  • the protective layer PL is formed on the first surface of the first compound semiconductor layer CS1 (S40).
  • the forming of the protective layer PL may include forming a first protective layer PL1 based on indium phosphorus (InP) on the first peripheral layer BL1 and forming a second protective layer formed of copper (Cu).
  • PL2 is formed on the first passivation layer PL1, and a metal capable of preventing the surface of the second passivation layer PL2 from being oxidized, for example, silver (Ag), gold (Au), and platinum (Pt)
  • a fourth protective layer PL3 formed of at least one selected from palladium (Pd), nickel (Ni), and molybdenum (Mo) or an alloy thereof on the second protective layer PL2 and then formed of a lamination film.
  • the protective layer PL4 may be attached onto the third protective layer PL3.
  • the first compound semiconductor layer CS1 and the protective layer ( PL) can effectively prevent the first compound semiconductor layer CS1 and the second protective layer PL2 from being peeled off, and during the process of removing the protective layer PL, the first compound semiconductor layer ( Partial etching of CS1) can be effectively prevented.
  • the third passivation layer PL3 may be formed between the first passivation layer PL1 and the second passivation layer PL2.
  • the third passivation layer PL3 may be formed between the layers.
  • the lamination film forming the fourth protective layer PL4 may be formed of a PET film serving as a support substrate and an EVA film positioned on one side of the PET film and acting as an adhesive.
  • the thickness of the PET film and EVA film is formed to a thickness of 25 ⁇ m to 75 ⁇ m, respectively, and attaching the fourth protective layer (PL4) at a temperature of 70 °C to 150 °C, the fourth protection when performing the ELO process Since the PET film is condensed and greatly deformed due to the temperature drop of the layer PL4, the time for performing the ELO process can be shortened, and the productivity of a large-area compound semiconductor solar cell can be improved.
  • each of the PET film and the EVA film may have a thickness of 50 ⁇ m, and the fourth protective layer PL4 may be attached at a temperature of 100 ° C.
  • FIG. 1 each of the PET film and the EVA film may have a thickness of 50 ⁇ m, and the fourth protective layer PL4 may be attached at a temperature of 100 ° C.
  • the first compound semiconductor layer CS1 is separated from the mother substrate 300 by performing an epitaxial lift off (ELO) process to remove the sacrificial layer 400 (S50).
  • ELO epitaxial lift off
  • hydrofluoric acid HF
  • the sacrificial layer 400 is removed by the hydrofluoric acid (HF).
  • the first compound semiconductor layer CS1 and the protective layer PL may be removed.
  • the mother substrate 300 may be separated from each other, and the fourth protective layer PL4 may be deformed due to the condensation of the PET film, thereby completing the separation process in a short time.
  • the back electrode 200 is formed on the second surface of the first compound semiconductor layer CS1 opposite to the first surface (S60).
  • the first electrode layer 200A and the first electrode layer 200A directly contacting the rear contact layer BC of the second peripheral layer BL2 are formed on the rear surface of the first compound semiconductor layer CS1.
  • a back electrode 200 having a sheet shape including a second electrode layer 200B positioned at a rear surface of the bottom surface is formed.
  • the first electrode layer 200A may be formed by depositing silver (Ag) to a thickness of 50 to 500 nm using physical vapor deposition
  • the second electrode layer 200B may be formed using an electroplating method ( It can be formed by plating copper (Cu) to a thickness of 1 to 10 mu m using electroplating.
  • the thickness of the second electrode layer 200B is preferably 70% or more of the total thickness of the rear electrode 200.
  • reference numeral 600 denotes a supporting substrate attached to the rear surface of the rear electrode 200.
  • the third protective layer PL3 When the third protective layer PL3 is removed, an etching solution in which the metal material forming the second protective layer PL2 has etching resistance is used. According to this process, the second protective layer PL2 is not removed while the third protective layer PL3 is removed.
  • the first passivation layer PL1 may be removed by the first solution having the etching resistance of the front contact layer FC formed of GaAs.
  • an etch stop film 500B exposing the second region A2 of the first compound semiconductor layer CS1 is formed in the first region A1 of the first compound semiconductor layer CS1. Subsequently, secondary mesa etching is performed using the etch stop film 500B as a mask (S80).
  • the step of performing the first mesa etching and the step of performing the second mesa etching may be performed using different etching prevention films.
  • the etching prevention film 500A may be removed, and another etching prevention film 500B for performing the second mesa etching may be formed in the second region.
  • the step of performing the first mesa etching and the step of performing the second mesa etching may be performed using the same etching prevention film.
  • the etch stopper 500A for performing the primary mesa etching is not removed after the primary mesa etching is completed, and can be removed after the secondary mesa etching.
  • Secondary mesa etching step (S80) is a second mesa etching step to remove the first light absorbing layer (PV1) formed of GaInP in the second region (A2) using a first solution, and the first solution and / or A third mesa that removes the second peripheral layer BL2 of the second region A2 using a third solution of phosphoric acid (H 3 PO 4 ) / hydrogen peroxide (H 2 O 2 ) / deionized water (DI)
  • An etching step may be included.
  • the first backside electric field layer BSF1 positioned in the second region A2 and formed of AlGaInP is removed using the first solution, and the backside contact formed of GaAs in the second region A2 is removed.
  • Layer BC is removed using a third solution.
  • the bottom layer of the second peripheral portion BL2 in direct contact with the back electrode 200 is a back contact layer BC formed of GaAs or AlGaAs.
  • the first electrode layer 200A is exposed to the second solution at the moment of removing the back contact layer BC.
  • Silver (Ag) forming the first electrode layer 200A is dissolved by the second solution.
  • the present invention it is possible to remove the back contact layer (BC) formed of GaAs or AlGaAs, while using a third solution that can prevent the first electrode layer 200A formed of silver (Ag) from being dissolved.
  • the bottom layer (eg, back contact layer) of the second peripheral layer BL2 is etched using a mesa etching step.
  • a mixed solution of phosphoric acid (H 3 PO 4 ) / hydrogen peroxide (H 2 O 2 ) / deionized water (DI) having silver (Ag) forming the first electrode layer 200A may be used.
  • the third solution may be formed by mixing phosphoric acid: hydrogen peroxide: deionized water in a ratio of 1: 0.3 to 3: 5 to 20.
  • the third mesa etching step using the third solution may be performed as the last step in the mesa etching process, as described above.
  • the first electrode layer 200A is first formed when the bottom layer BC is removed. 3 is exposed to the solution.
  • silver (Ag) forming the first electrode layer 200A has etching resistance with respect to the third solution, the first electrode layer 60 is not dissolved by the third solution.
  • the second peripheral layer BL2 may be removed by one etching process using the third solution.
  • the back electrode portion positioned in the second area A2 is scribed (S90). Scribing can be performed using a cutting device, such as a laser.
  • the front electrode 100 may be formed before the scribing step S90 or after the scribing step S90, and the front contact layer FC masks the front electrode 100. It can be removed by the etching process used. Accordingly, as shown in FIG. 9, the front contact layer FC may be formed in the same pattern as the front electrode 100.
  • the compound semiconductor solar cell manufactured according to the method described above is manufactured of the compound semiconductor solar cell while forming the back electrode 200 using silver (Ag) and copper (Cu), which are very inexpensive as raw materials. Problems occurring during the process, for example, a phenomenon in which the layer based on indium phosphorus (InP) is not etched in the first compound semiconductor layer CS1 and a phenomenon in which part of the rear electrode 200 is dissolved can be effectively suppressed.
  • Ag silver
  • Cu copper
  • Table 1 below shows a conventional compound semiconductor solar cell having a back electrode formed of gold (Au), and a back surface including a first electrode layer 200A formed of silver (Ag) and a second electrode layer 200B formed of copper. Electrical properties of the compound semiconductor solar cells of Examples 1 and 2 including the electrode 200 were measured.
  • the compound semiconductor solar cell of Example 1 and the compound semiconductor solar cell of Example 2 are two solar cells selected from a plurality of solar cells manufactured by the manufacturing method of the present invention.
  • the compound semiconductor solar cell includes the first compound semiconductor layer CS1 having a single junction structure as an example, but the compound semiconductor solar cell may include the second compound semiconductor layer having a multiple junction structure.
  • the manufacturing method of this invention can be used also when manufacturing a compound semiconductor solar cell provided with the 2nd compound semiconductor layer of a multiple junction structure.
  • a compound semiconductor solar cell having a second compound semiconductor layer (CS2) having a double junction structure will be described as an example, but the manufacturing method of the present invention provides a compound semiconductor solar cell having a compound semiconductor layer having a structure of triple junction or more. It is obvious that it can also be used when manufacturing.
  • a compound semiconductor solar cell having a second compound semiconductor layer CS2 having a double junction structure will be described with reference to FIGS. 1 and 11 to 13.
  • the compound semiconductor solar cell of the present embodiment may include a first cell C1-1. ), The second cell C2 located on the rear surface of the first cell C1-1, and the first tunnel layer TRJ1 located between the first cell C1-1 and the second cell C2. ) May be included.
  • the first cell C1-1 has the remaining configuration except that the second peripheral layer BL2-1 does not include the rear contact layer BC. Since the same, the detailed description of the first cell (C1-1) is omitted.
  • the front contact layer FC is positioned only in the top cell, and the back contact layer BC is the bottom cell. located only on the bottom cell).
  • a top cell is a first cell C1-1, and a bottom cell is a second cell C2.
  • the second cell C2 of the compound semiconductor solar cell having the second compound semiconductor layer CS2 having the double junction structure is formed of the second light absorbing layer PV2 and the first light absorbing layer PV2 based on GaAs.
  • the first tunnel layer TRJ1 positioned between the first cell C1-1 and the second cell C2 is a component of the second peripheral layer BL2 of the first cell C1-1. It may be defined as a component of the third peripheral layer BL3 of the second cell C2, and may be defined as a layer separate from the second peripheral layer BL2 and the third peripheral layer BL3. You may.
  • the first tunnel layer TRJ is defined and described as a component of the third peripheral layer BL3.
  • the second cell C2 forms a pn junction with a second base layer PV2-1 and a second base layer PV2-1 formed of a GaAs-based compound semiconductor, for example, n-type GaAs. It is formed between the second light absorbing layer PV2 including the second emitter layer PV2-2, the first tunnel layer TRJ1 and the second base layer PV2-1 and formed of n-type GaInP.
  • a fourth peripheral layer BL4 including a rear contact layer BSF2 and a rear contact layer BC positioned between the second rear electric field layer BSF2 and the rear electrode 200.
  • the second cell C2 is positioned at the rear of the first cell C1-1 in order to absorb light having a long wavelength transmitted through the first cell C1-1 without being absorbed by the first cell C1-1. .
  • the second base layer PV2-1 and the second emitter layer PV2-2 are formed of the first base layer PV1-1 and the first emitter layer PV1-2 of the first cell C1-1. It is formed of a material having a bandgap lower than the bandgap of GaInP (approximately 1.9Ev), for example, GaAs having a bandgap of approximately 1.42 eV.
  • the second window layer WD2 and the second back surface field layer BSF2 of the second cell C2 have a higher bandgap than the second base layer PV2-1 and the second emitter layer PV2-2. It can be formed of a material having, for example, GaInP or AlGaInP.
  • the second window layer WD2 and the second rear electric field layer BSF2 of the second cell C2 do not contain aluminum.
  • the band gap between the second base layer PV2-1 and the second emitter layer PV2-2 of the second cell C2 may be formed in the first base layer of the first cell C1. This is because it is lower than the band gap of (PV1-1) and the first emitter layer (PV1-2).
  • the first tunnel layer TRJ1 is formed of p + type AlGaAs doped with a higher concentration of p-type impurities than the first back surface field layer BSF1, and the first layer TRJ1 is in direct physical contact with the first back surface field layer BSF1.
  • -1) and a second layer (TRJ1-2) in which n-type impurities are formed of n + type GaInP doped at a higher concentration than the second window layer WD2 and in direct physical contact with the second window layer WD2. can do.
  • the rest of the configuration is a first compound semiconductor layer (CS1 of a single junction structure) Since it is the same as the manufacturing method of the compound semiconductor solar cell provided with), detailed description is abbreviate
  • the sacrificial layer forming step (S10) is the same as the configuration shown in Figure 2
  • the protective layer forming step (S40) is the same as the configuration shown in Figure 4
  • the separation step is shown in FIG. It is the same as the structure shown in 5.
  • the back electrode forming step is the same as the configuration shown in FIG. 6, and the scribing step is the same as the configuration shown in FIG. 8.
  • the protective layer removing step S70 is also the same as that of the above-described embodiment.
  • the first cell C1-1 is formed from a plurality of layers forming the second compound semiconductor layer CS2 by performing a first mesa etching step before forming the back electrode 200.
  • a second mesa etching step is performed to mesa-etch a plurality of layers forming the second cell C2 in the second compound semiconductor layer CS2. Characterized in that.
  • the first mesa etching step of mesa etching the compound semiconductor layer forming the first cell C1-1 may be performed.
  • the third peripheral layer BL3 of the second region A2 may be formed using the first solution and / or the second solution.
  • a sixth mesa etching step of removing the fourth peripheral layer BL4 of the second region A2 may be performed.
  • 11 and 12 illustrate that two compound semiconductor solar cells are formed using one second compound semiconductor layer CS2 separated from the mother substrate 300 as an example, but the number of compound semiconductor solar cells is required. It can select suitably according to.
  • the second compound semiconductor layer CS2 having the double junction structure is formed on the sacrificial layer 400.
  • the second compound semiconductor layer CS2 having the double junction structure forms a fourth peripheral layer BL4 including the rear contact layer BC and the second rear electric field layer BSF2 on the sacrificial layer 400, and the second The third peripheral layer including the second light absorbing layer PV2 including the emitter layer PV2-2 and the second base layer PV2-1, the second window layer WD2 and the first tunnel layer TRJ1.
  • BL3, a second peripheral layer BL2 including the first backside field layer BSF1, a first light absorbing layer including the first emitter layer PV1-2 and the first base layer PV1-1. PV1) and the first peripheral layer BL1 including the first window layer WD1 and the front contact layer FC may be sequentially formed on the fourth peripheral layer BL4.
  • At least one layer may be omitted in the case of the peripheral layer including a plurality of layers among the first peripheral layer BL1 to the fourth peripheral layer BL4.
  • first mesa etching is performed using the etch stop layer 500A exposing the second region A2 of the second compound semiconductor layer CS2. .
  • the reason for performing the first mesa etching before forming the back electrode 200 is to remove the layer formed on the basis of InP in the compound semiconductor layer CS forming the second cell C2.
  • the oxidation tendency of silver (Ag) / copper (Cu) which is a material forming the back electrode 200, is higher than that of InP-based layers (GaInP, AlInP, AlGaInP, etc.). This is to prevent the etching of the layers due to the high.
  • GaInP is formed in the compound semiconductor layer CS forming the second cell C2.
  • the portion to be removed of the layer formed of, AlInP, or AlGaInP can be effectively removed.
  • the first mesa etching step of mesa etching the first cell C1-1 may be performed by using a first solution and / or a second solution to remove a portion of the first peripheral layer BL1 positioned in the second area A2.
  • the front contact layer FC positioned in the second region A2 and formed of n + type GaAs is removed using the second solution, and the first window layer WD1 formed of n type AlGaInP is removed from the first solution. Removal (first mesa etching step to remove the first peripheral layer).
  • the first light absorbing layer PV1 formed of GaInP and the first backside electric field layer BSF1 formed of p-type AlGaInP are sequentially removed using the first solution (second mesa etching for removing the first light absorbing layer). And a third mesa etch step to remove the second peripheral layer.
  • the compound semiconductor layer positioned in the second region A2 of the second compound semiconductor layer CS2 and forming the first cell C1-1 is removed.
  • the first region A1 is formed of the first portion P1 of the first thickness T1
  • the second region A2 of the second compound semiconductor layer CS2 is smaller than the first thickness T1.
  • the third portion P3 of the thickness T3 is formed.
  • the etching prevention film 500A for performing the first mesa etching step S30 may be removed after the first mesa etching step S30, the etching prevention film 500A after the first mesa etching step S30 is performed. It may be used as a mask in the second mesa etching step (S80) without removing.
  • the protective layer PL is formed on the first surface of the second compound semiconductor layer CS2 (S40), and the second compound semiconductor layer is removed by performing an epitaxial lift off (ELO) process.
  • CS2 is separated from the mother substrate 300 (S50).
  • a portion of the third peripheral layer BL3 positioned in the second region A2 may be formed into a first solution and / or a first solution.
  • the first layer TRJ1-1 of the first tunnel layer TRJ1 positioned in the second region A2 is removed using the second solution, and the second region A2 is removed.
  • the third peripheral layer BL3 is removed by removing the portion of the second layer TRJ1-2 and the portion of the second window layer WD2 of the located first tunnel layer TRJ1 using the first solution (third Fourth mesa etching step to remove the peripheral layer).
  • the portion of the second light absorbing layer PV2 positioned in the second region A2 is removed using the second solution (a fifth mesa etching step for removing the second light absorbing layer).
  • the second backside field layer BSF2 is removed using the second solution, and the backside contact layer BC is removed using the third solution (sixth mesa etching step to remove the fourth peripheral layer). ).
  • a portion of the back electrode 200 positioned in the second area A2 is scribed (S90), before the scribing step S90 is performed, or after the scribing step S90 is performed.
  • the front electrode 100 is formed, and the front contact layer FC is patterned by an etching process using the front electrode 100 as a mask.

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Abstract

La présente invention concerne un procédé de fabrication d'une cellule solaire à semi-conducteur composé. Un procédé de fabrication d'une cellule solaire à semi-conducteur composé selon un aspect de la présente invention comprend les étapes consistant à : former une couche sacrificielle sur un substrat mère; former une couche de semi-conducteur composé sur la couche sacrificielle; réaliser une gravure mesa primaire pour former une première partie ayant une première épaisseur au niveau d'une première région de la couche de semi-conducteur composé et une seconde partie ayant une seconde épaisseur inférieure à la première épaisseur au niveau d'une seconde région de la couche de semi-conducteur composé; former une couche protectrice sur une première surface de la couche de semi-conducteur composé; séparer la couche de semi-conducteur composé du substrat mère; former une électrode côté arrière sur une seconde surface de la couche de semi-conducteur composé, qui est opposée à la première surface; retirer la couche protectrice; réaliser une gravure mesa secondaire pour retirer la seconde partie de la couche de semi-conducteur composé au niveau de la seconde région; et tracer l'électrode côté arrière dans la seconde région.
PCT/KR2019/001226 2018-03-16 2019-01-29 Procédé de fabrication d'une cellule solaire à semi-conducteur composé Ceased WO2019177268A1 (fr)

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JP2014017366A (ja) * 2012-07-09 2014-01-30 Sharp Corp 薄膜化合物太陽電池セルおよびその製造方法
KR20140043805A (ko) * 2011-07-06 2014-04-10 더 리젠츠 오브 더 유니버시티 오브 미시간 에피택셜 리프트 오프 및 냉간 용접 결합된 반도체 태양 전지를 사용한 일체형 태양열 집열기
KR20140138340A (ko) * 2012-03-28 2014-12-03 소이텍 다중접합 태양 전지 소자들의 제조
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KR101840800B1 (ko) * 2017-01-31 2018-03-22 엘지전자 주식회사 화합물 반도체 태양전지 및 이의 제조 방법

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KR20140043805A (ko) * 2011-07-06 2014-04-10 더 리젠츠 오브 더 유니버시티 오브 미시간 에피택셜 리프트 오프 및 냉간 용접 결합된 반도체 태양 전지를 사용한 일체형 태양열 집열기
US20150255668A1 (en) * 2011-09-30 2015-09-10 Microlink Devices, Inc. Thin film inp-based solar cells using epitaxial lift-off
JP2013084784A (ja) * 2011-10-11 2013-05-09 Nippon Telegr & Teleph Corp <Ntt> タンデム太陽電池セルおよびその製造方法
KR20140138340A (ko) * 2012-03-28 2014-12-03 소이텍 다중접합 태양 전지 소자들의 제조
JP2014017366A (ja) * 2012-07-09 2014-01-30 Sharp Corp 薄膜化合物太陽電池セルおよびその製造方法

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