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WO2019167275A1 - Égaliseur à retour de décision et récepteur l'utilisant - Google Patents

Égaliseur à retour de décision et récepteur l'utilisant Download PDF

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Publication number
WO2019167275A1
WO2019167275A1 PCT/JP2018/008129 JP2018008129W WO2019167275A1 WO 2019167275 A1 WO2019167275 A1 WO 2019167275A1 JP 2018008129 W JP2018008129 W JP 2018008129W WO 2019167275 A1 WO2019167275 A1 WO 2019167275A1
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Prior art keywords
output
signal
threshold
decision feedback
flop
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PCT/JP2018/008129
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English (en)
Japanese (ja)
Inventor
崇泰 乗松
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Hitachi Ltd
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Hitachi Ltd
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Priority to PCT/JP2018/008129 priority Critical patent/WO2019167275A1/fr
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/06—Control of transmission; Equalising by the transmitted signal

Definitions

  • the present invention relates to a receiver for high-speed wired transmission and a semiconductor integrated circuit that can be used for the receiver, and more particularly to a technique for increasing error resistance with respect to circuit linearity.
  • the gain varies depending on the signal amplitude due to the influence of the linearity of the circuit. Therefore, the gain becomes small in a pattern in which the minimum voltage is changed to the maximum voltage. Furthermore, when a decision feedback equalizer is used, an error in the previous data affects the next data, resulting in a lack of equalization, and a burst error in which the next data also becomes an error occurs.
  • an object of the present invention is to reduce bit errors caused by circuit linearity and data patterns.
  • One aspect of the present invention includes a first adder that adds a correction value to an input signal, a determiner that determines the output of the first adder as a logical value according to a first determination threshold, and a determiner A flip-flop that samples and holds the output of the flip-flop at the clock timing, and has a shift register that receives the output of the flip-flop and the clock and delays the output of the flip-flop every clock cycle.
  • a multiplier that multiplies the output by a correction coefficient and outputs a correction value
  • a correction coefficient calculator that calculates a correction coefficient for each clock timing from the output of the first adder and the output of the flip-flop
  • a determination threshold calculator that calculates a second determination threshold for each clock timing from the output of the first adder and the output of the flip-flop
  • a decision feedback equalizer having a second adder for outputting a first determination threshold the threshold value offset added to the determination threshold.
  • Another aspect of the present invention includes a linear equalizer that receives a received signal, performs waveform equalization and signal amplification, and the above-described decision feedback equalizer that uses an output of the linear equalizer as an input signal. It is a receiver equipped.
  • FIG. 3 is a block diagram showing a decision feedback equalizer according to the first embodiment. The graph which shows the effect of an Example.
  • Notations such as “first”, “second”, and “third” in this specification and the like are attached to identify the constituent elements, and do not necessarily limit the number, order, or contents thereof. is not.
  • a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.
  • the outline of the representative example of the embodiment described below includes the following features.
  • One example is to adjust the decision threshold so that an error does not occur even if the amplitude decreases due to linearity in a specific data transition pattern by giving an offset to the result of automatic convergence of the decision threshold of the value in a PAM modulated signal It is a receiver with means to do.
  • the linearity is greatly affected when the data transition is large and the voltage transitions from minimum to maximum or vice versa. At that time, the gain becomes smaller than other conditions, and the amplitude becomes smaller. Therefore, it is mistaken to be smaller or larger than the determination threshold. Therefore, it is possible to prevent such an error by adding an offset to the determination threshold value itself to make it smaller.
  • Fig. 1 shows an example of an electric signal transmission device.
  • a signal processing semiconductor integrated device for example, a substrate 101 on which a signal transmission ASIC (Application Specific Integrated Circuit) 102 is mounted and a data rate conversion semiconductor integrated device, for example, a substrate 106 on which a signal transmission ASIC 107 is mounted, are connected to a connector 103, communication A signal is transmitted and received between the signal transmission ASIC 102 and the signal transmission ASIC 107 by being connected via the medium 104 and the connector 105.
  • the communication medium 104 may be a line on a substrate or a communication cable. There may be a plurality of communication media 104 signals.
  • Fig. 2 shows another example of an electric signal transmission device.
  • a substrate 201 on which a signal transmission ASIC 202 and a rate conversion ASIC 203 are mounted and a substrate 207 on which a signal transmission ASIC 208 is mounted are connected via a connector 204, a communication medium 205, and a connector 206.
  • the signal rate of the signal transmission ASIC 202 is changed by the rate conversion ASIC 203.
  • the signal transmission ASIC 202 outputs two 28 Gbps signals
  • the rate conversion ASIC 203 converts the signal into one 56 Gbps signal, thereby converting the number of signals.
  • the signal output from the ASIC 202 is input to the rate conversion ASIC 203, and the data rate is converted and output.
  • the output of the rate conversion ASIC 203 is input to the ASIC 208 through the connector 204, the communication medium 205, and the connector 206.
  • the output of the ASIC 208 is input to the rate conversion ASIC 203 through the connector 206, the communication medium 205, and the connector 204.
  • the input signal is converted in data rate by the rate conversion ASIC 203, and the output of the rate conversion ASIC 203 is input to the signal transmission ASIC 202.
  • FIG. 3 is a block diagram of the signal transmission ASIC 102, the signal transmission ASIC 107, the signal transmission ASIC 202, and the signal transmission ASIC 208.
  • the signal transmission ASIC 102 when a configuration common to these signal transmission ASICs is described, it will be referred to as the signal transmission ASIC 102.
  • the signal transmission ASIC 102 includes a signal processing unit 301, a transmission unit 302, and a reception unit 303.
  • a signal processing unit 301 When the signal transmission ASIC 102 has a plurality of lanes, a plurality of transmission units 302 and reception units 303 are configured.
  • the transmission / reception is possible. However, the reception only or the transmission only may be used.
  • the transmission parallel data signal 311 from the signal processing unit 301 is sent to a MUX (Multiplexer) 304 in the transmission unit 302, and parallel-serial conversion is performed using a transmission unit clock 312 from a CDR (Clock and Data Recovery) 308.
  • the transmission serial data signal 313 subjected to the parallel-serial conversion is sent to an FFE (Feed Forward Equalizer) 305, and the FFE 305 equalizes the input signal and outputs a transmission signal 314.
  • FFE eed Forward Equalizer
  • the linear equalizer 306 in the receiving unit 303 receives the received signal 315 that has received the loss of the communication path, and performs waveform equalization and signal amplification.
  • the linear equalizer 306 operates to compensate for the high frequency region attenuated in the communication path.
  • the signal 316 amplified by the linear equalizer 306 is input to a decision feedback equalizer (DFE: Decision Feedback Equalizer) 307.
  • the decision feedback equalizer 307 operates so as to cancel the intersymbol interference component of data.
  • the DFE output 317 of the decision feedback equalizer 307 is input to the CDR 308, and the CDR 308 synchronizes the clock phase with the phase of the DFE output 317 and outputs the phase synchronization clock 318 and the transmission unit clock 312.
  • the CDR 308 serial-parallel converts the DFE output 317, and the parallel received parallel data signal 319 is input to the signal processing unit 301.
  • FIG. 4 shows a block diagram of the rate conversion ASIC 203.
  • the rate conversion ASIC 203 includes a receiving unit 401 and a transmitting unit 404 on the slow data rate side, a transmitting unit 403 and a receiving unit 405 on the fast data rate side, and a signal processing unit 402.
  • FIG. 4 shows an example in which the data rate is doubled.
  • Conversion from a low data rate to a high data rate is performed as follows.
  • the low-speed side upper bit received signal 421 is input to the linear equalizer 406, and the low-speed side lower bit received signal 422 is input to the linear equalizer 407, where waveform equalization and amplification are performed.
  • the linear equalizer 406 outputs the low speed side upper bit linear equalizer output signal 423 to the decision feedback equalizer 408, and the linear equalizer 407 outputs the low speed side lower bit linear equalizer output signal 424 to the decision feedback type. Output to the equalizer 409.
  • the decision feedback equalizer 408 cancels the intersymbol interference component of the low-speed high-order bit linear equalizer output signal 423 in synchronization with the low-speed high-order bit phase synchronization clock 426 received from the CDR 410, and determines the determined low-speed high-order bit.
  • a feedback equalizer output signal (upper bit data) 425 is transmitted to the CDR 410.
  • the decision feedback equalizer 409 cancels the intersymbol interference component of the low-speed upper bit linear equalizer output signal 423 in synchronization with the low-speed low-order bit phase synchronization clock 428 received from the CDR 410, and determines the determined low-speed low-order bit.
  • a feedback equalizer output signal (lower bit data) 427 is transmitted to CDR 410.
  • the CDR 410 receives the upper bit data 425 and the lower bit data 427, and synchronizes the clock phase with the data phase. Then, the upper bit data 425 and the lower bit data 427 are serial-parallel converted, and the low speed side upper bit reception parallel data 429 and the low speed side lower bit reception parallel data 430 are transmitted to the signal processing unit 402.
  • the signal processing unit 402 adjusts the bit positions of the low-speed side upper bit reception parallel data 429 and the low-speed side lower bit reception parallel data 430 and combines them into the high-speed side transmission parallel data 431.
  • the MUX 411 receives the high-speed transmission parallel data 431, performs parallel-serial conversion on the high-speed transmission parallel data 431 using the high-speed transmission clock 432 from the CDR 415, and outputs the high-speed transmission serial data 433.
  • the FFE 412 receives the high-speed transmission serial data 433, equalizes the waveform, and outputs a high-speed transmission signal 434.
  • Conversion from a high data rate to a low data rate is performed as follows.
  • the high-speed side received signal 435 is input to the linear equalizer 413, where the waveform is equalized and amplified.
  • the high speed side linear equalizer output signal 436 of the linear equalizer 413 is input to the decision feedback equalizer 414, and the decision feedback equalizer 414 is synchronized with the high speed side phase synchronization clock 438 received from the CDR 415.
  • the intersymbol interference component of the side linear equalizer output signal 436 is canceled, and the determined fast side decision feedback equalizer output signal 437 is transmitted to the CDR 415.
  • the CDR 415 receives the high-speed decision feedback equalizer output signal 437 and synchronizes the clock phase with the phase of the high-speed decision feedback equalizer output signal. Then, the high-speed side decision feedback equalizer output signal 437 is serial-parallel converted, and the high-speed side reception parallel data 439 is transmitted to the signal processing unit 402.
  • the signal processing unit 402 divides the high-speed side reception parallel data 439 into the low-speed side upper bit transmission parallel data 440 and the low-speed side lower bit transmission parallel data 441 and transmits them to the MUX 416 and the MUX 417, respectively.
  • the MUX 416 receives the low-speed side transmission unit clock 442 from the CDR 410, uses the low-speed side transmission unit clock 442 to perform parallel-serial conversion on the low-speed side upper bit transmission parallel data 440, and outputs the low-speed side upper bit transmission serial data signal 443 to the FFE 418. .
  • the MUX 417 receives the low-speed side transmission unit clock 442 from the CDR 410, uses the low-speed side transmission unit clock 442 to perform parallel-serial conversion on the low-speed side low-order bit transmission parallel data 441, and outputs the low-speed side low-order bit transmission serial data signal 444 to the FFE 419.
  • the FFE 418 equalizes the waveform of the low-speed upper bit transmission serial data signal 443 and outputs the low-speed upper bit transmission signal 445.
  • the FFE 419 equalizes the waveform of the low-speed low-order bit transmission serial data signal 444 and outputs a low-speed low-order bit transmission signal 446.
  • FIG. 5 shows an example of the linear equalizers 306, 406, 407, and 413.
  • the linear equalizer 306 will be cited.
  • the linear equalizer 306 has a differential amplifier configuration, and a pair of signal amplification transistor 1201, signal amplification transistor 1202, load resistors 1207, 1208, and degeneration.
  • a resistor 1203, a degeneration capacitor 1204, a constant current source 1205, and a constant current source 1206 are included.
  • the load resistor 1207 and the load resistor 1208 have the same size, and the transistor 1201 and the transistor 1202 have the same size.
  • the positive input signal 1209 is input to the transistor 1201 and amplified, and the negative output signal 1211 is output.
  • the negative input signal 1210 is input to the transistor 1202 and amplified, and the positive output signal 1212 is output.
  • the source 1213 of the transistor 1201 and the source 1214 of the transistor 1202 are connected by a degeneration resistor 1203 and a degeneration capacitor 1204 so that the voltage difference between the positive output signal 1212 and the negative output signal 1211 is positive.
  • the gain divided by the voltage difference between the input signal 1209 and the negative input signal 1210 is a value obtained by dividing the values of the load resistor 1207 and the load resistor 1208 by the parallel impedance of the degeneration resistor 1203 and the degeneration capacitor 1204. Therefore, the frequency characteristic of the gain in the linear equalizer is a high-pass filter characteristic, and the high frequency has a higher gain than the low frequency. Therefore, it is possible to correct the signal by amplifying the amplitude on the high frequency side with respect to the signal whose amplitude decreases as the frequency increases.
  • the linear equalizer 306 due to the effect of element miniaturization or the like, there may be a nonlinear characteristic that the gain decreases as the input signal increases. For this reason, when a multilevel signal is handled, the gain may vary depending on the state of data transition. For example, when a four-value symbol of 0, 1, 2, 3 is transmitted with an analog signal of 0, 1, 2, 3 mV by amplitude modulation, a sufficient gain is obtained at the transition from 0 to 1, but 0 to 3 There may be cases where the gain to the transition is not sufficient. When the linear equalizer 306 has insufficient equalization or non-linearity, the larger the transition between symbols, the more likely it is affected, and the upper and lower sides of the symbol are crushed. When multi-level determination is performed on the output of the linear equalizer 306 using a decision feedback equalizer, the conventional decision feedback equalizer drags an error in the previous data. Becomes even more prominent.
  • FIG. 6 shows the configuration of the decision feedback equalizer of the comparative example.
  • a decision feedback equalizer refers to an equalizer that includes a decision in a feedback loop.
  • the waveform is passed through a delay circuit and optimized by the least square method so that the error between the equalized waveform and the ideal waveform is minimized.
  • Intersymbol interference is reduced by multiplying the coefficient and adding it to the waveform immediately before the determined waveform.
  • a phenomenon in which the influence of the decision error does not converge to the equalized state may occur around the loop.
  • the decision feedback equalizer 307 includes an adder 501, a determiner 502, a flip-flop 503, a shift register (SR) 504, a tap coefficient multiplier 505, a tap coefficient multiplier 506, a tap coefficient multiplier 507, and a tap coefficient multiplier. 508, a tap coefficient multiplier 509, a tap coefficient calculator (TAPC) 510, and a determination threshold value calculator (THC) 511.
  • the tap coefficient calculator 510 and the determination threshold calculator 511 can be configured in a digital configuration, and can be realized by hardware such as an FPGA (Field Programmable Gate Array) or an ASIC.
  • the adder 501 adds the output of the tap coefficient multipliers 505, 506, 507, 508, and 509 to the input signal (IN) 521, and cancels the intersymbol interference component of the input signal 521.
  • the determiner 502 compares the output of the adder 501 with the determination threshold value 523 to determine a logical value. For example, in the case of a PAM4 determiner, the input value is determined as 0, 1, 2, or 3. The output of the determiner 502 is sampled and held by the flip-flop 503 at the edge timing of the clock (CLK) 522.
  • CLK clock
  • the output of the flip-flop 503 is output as a decision feedback equalizer output signal 524 which is an output of the decision equalizer, and is input to the tap coefficient multiplier 505 and the shift register 504.
  • the shift register 504 takes in the decision feedback equalizer output signal 524 and outputs data obtained by delaying the time for each cycle of the clock 522.
  • the signal delayed by one clock is input to the tap coefficient multiplier 506 of the second tap
  • the signal delayed by two clocks is input to the tap coefficient multiplier 507 of the third tap
  • the signal delayed by three clocks is the tap coefficient of the fourth tap.
  • a signal input to the multiplier 508 and delayed by 4 clocks is input to the tap coefficient multiplier 508 of the fifth tap.
  • the tap coefficient multipliers 505, 506, 507, 508, and 509 multiply the input data by the tap coefficients and output the results to the adder 501.
  • the tap coefficients of the tap coefficient multipliers 505, 506, 507, 508, and 509 are the tap coefficient calculator 510 and the output of the adder 501 and the output of the determination threshold calculator 511, and the determination feedback type equalizer output. Based on the signal 524, it is calculated at each timing of the clock 522.
  • the determination threshold value 523 is calculated at each timing of the clock 522 based on the output of the adder 501 and the determination feedback equalizer output signal 524 in the determination threshold calculator 511.
  • the waveform shaping that could not be equalized by the linear equalizer 306 by feeding back the output of the decision equalizer multiplied by the tap coefficient It is possible to do. However, since the output of the equalizer multiplied by the tap coefficient is fed back, once there is an error in the output, the influence of the error propagates to the subsequent data.
  • Fig. 7 shows the EYE waveform of the PAM4 modulation signal when circuit nonlinearity is affected.
  • signals that transition between “0”, “1”, “2”, and “3” symbols are superimposed.
  • Such a signal can be obtained as the output of the linear equalizers 306, 406, 407, 413.
  • These signals can be identified using determination threshold values 602, 603, and 604, and four values can be obtained.
  • the determination threshold 602 is, for example, + aV
  • the determination threshold 603 is, for example, -aV
  • the determination threshold 604 is, for example, 0V.
  • “3” can be determined when the input signal exceeds the determination threshold 602, and “2” can be determined between the determination thresholds 602 and 604.
  • the gain varies depending on the input amplitude.
  • a multilevel modulation signal such as PAM4
  • the signal amplitude is reduced as shown in FIG. 7 due to the data transition pattern, and the EYE aperture is narrowed.
  • the data pattern 601 transitioning from 0 ⁇ 3, 3 ⁇ there is no voltage difference between the determination threshold 602 and the determination threshold 603, and an error is likely to occur due to noise. In this way, errors tend to occur depending on the data pattern.
  • the margin above the determination threshold 602 and the margin below the determination threshold 603 are reduced, but the margin below the determination threshold 602 and the margin above the determination threshold 603 are It does not change. For this reason, it is considered that noise tolerance can be increased by moving the determination threshold value 602 and the determination threshold value 603 toward the margin. In a typical example, when a transition is made from the symbol x to the furthest symbol y, it is considered that the noise tolerance can be increased by moving the determination threshold for determining the symbol y so as to approach the symbol x.
  • the determination threshold value 602 is moved downward, the possibility of erroneous determination of symbol 3 as symbol 2 is reduced, but the possibility of erroneous determination of symbol 2 as symbol 3 is increased. Is required.
  • FIG. 8 shows an example of decision feedback equalizers 307, 408, 409, and 414 that realize a configuration in which noise tolerance is increased by moving the decision threshold.
  • the decision feedback equalizer 307 is referred to.
  • a threshold adder 701 is added to the configuration of FIG. 6, and a threshold offset (OS) 702 is added from an external register or the like.
  • the threshold adder 701 adds the threshold offset 702 to the determination threshold 523 and changes the determination threshold of the determiner 502. Thereby, an offset is added to the determination threshold value 602 and the determination threshold value 603 of FIG.
  • the determination threshold 602 When the determination threshold 602 is + aV, the determination threshold 603 is ⁇ aV, and the determination threshold 604 is 0V, if the offset (OS) is a negative value, the determination threshold 602 is + (a ⁇ OS) V and the determination threshold 603 is -(A-OS) V. As a result, as indicated by an arrow 700 in FIG. 7, the determination threshold 602 is lowered, the determination threshold 603 is increased, and the margin for the data pattern 601 that is easily affected by the nonlinearity of the circuit can be increased.
  • Figure 9 shows the simulation result of BER (Bit ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ Error ⁇ ⁇ Rate) when an offset is added to the threshold under the condition that the circuit has nonlinearity.
  • BER Bit ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ Error ⁇ ⁇ Rate
  • the offset is ⁇ 20 mV
  • the BER is improved by about one digit compared to when no offset is added.
  • an appropriate threshold value offset 702 is determined in advance from such simulation results and experimental results, and is input to the decision feedback equalizer 307 from the outside.
  • FIG. 10 shows a second embodiment.
  • a predetermined threshold offset 702 is input to the decision feedback equalizer 307.
  • the second embodiment when the signal correction amount in the decision feedback equalizer 307 is large, automatic adjustment is performed so as to apply a threshold offset.
  • the decision feedback equalizer 307 when the signal correction amount is large, the influence of the decision error is easily propagated and an error is likely to occur. For this reason, an error-prone state is determined, and a threshold offset is applied or a large threshold offset is applied.
  • the threshold offset to be added is automatically calculated based on the tap coefficient of the first tap of the decision feedback equalizer.
  • a fixed value is given.
  • a threshold offset can be adapted to the received loss to give a threshold offset according to conditions. Since only a fixed value is given in the first embodiment, it is necessary to take a margin for the optimum value. However, in the second embodiment, an optimum threshold offset can be given even if the conditions change.
  • the magnitude of the absolute value of the tap coefficient obtained by the tap coefficient calculator 510 of the decision feedback equalizer 307 is determined by the amplitude of the output of the decision equalizer. Since the threshold offset is preferably set to a larger value as the amplitude is larger, the magnitude relationship can be determined by the tap coefficient.
  • the tap coefficient of the first tap of the decision feedback equalizer is a coefficient for the immediately preceding signal, and the larger the tap coefficient of the first tap, the larger the signal correction amount by the decision feedback equalizer. For this reason, when the tap coefficient of the first tap is large, there is a high possibility that an error will occur in the next determination result when there is an error in the previous determination result.
  • the presence or absence of the threshold offset or the magnitude can be determined based on the absolute value of the tap coefficient.
  • the threshold offset based on the tap coefficient of the first tap, it is possible to improve the error by adding the threshold offset under the condition that the error is likely to occur.
  • the second embodiment includes a threshold offset determiner 901 that determines a threshold offset from a tap coefficient.
  • the threshold offset determiner 901 In response to the input of the tap coefficient 525, the threshold offset determiner 901 outputs a threshold offset 902 according to an internal function.
  • the threshold offset 902 is added to the determination threshold 523 in the threshold adder 701, and the addition result is used as the determination threshold of the determiner 502.
  • the simplest example of the internal function of the threshold offset determiner 901 is to truncate after the decimal point to discard the lower bits of the tap coefficient 525. Moreover, you may combine functions, such as a linear function and a quadratic function, and truncation after a decimal point. Further, it is possible to prevent the threshold offset from being added or output unless the absolute value of the tap coefficient 525 is a certain value or more. There is also a method in which the output of the threshold offset determiner 901 is also inclined according to the tap coefficient.
  • FIG. 11 shows a third embodiment.
  • a function selection signal (SL) 1001 is input to the threshold value offset determiner 901 compared to the second embodiment.
  • the internal function of the threshold offset determiner 901 can be selected from a register or the like outside the decision feedback equalizer.
  • the formula for calculating the threshold offset from the tap coefficient can be changed after the LSI is manufactured. This makes it possible to select an effective function based on the evaluation without redesign even if there is a defect in the function parameters at the design stage. Therefore, the design period can be shortened, leading to cost reduction.
  • FIG. 12 shows a fourth embodiment.
  • An analog-to-digital converter (ADC) 1101 is added to the second embodiment of FIG. 10, and the flip-flop 503 is deleted.
  • ADC analog-to-digital converter
  • the decision feedback equalizer includes an ADC 1101, an adder 501, a determiner 502, a shift register 504, a tap coefficient multiplier 505, a tap coefficient multiplier 506, a tap coefficient multiplier 507, and a tap coefficient multiplier. 508, a tap coefficient multiplier 509, a tap coefficient calculator 510, a determination threshold calculator 511, and a threshold offset determiner 901.
  • the ADC 1101 samples and holds the input signal 521 at the timing of the edge of the clock 522, and converts the analog signal into a digital code.
  • the adder 501 adds the outputs of the tap coefficient multipliers 505, 506, 507, 508, and 509 to the ADC output signal 1102, and cancels the intersymbol interference component of the ADC output signal 1102.
  • the determiner 502 compares the output of the adder 501 with the result obtained by adding the threshold offset 902 to the determination threshold 523 in the threshold adder 701, and determines the logical value. For example, in the case of a PAM4 determiner, the input value is determined as 0, 1, 2, or 3.
  • the output of the decision unit 502 is outputted as a decision feedback equalizer output signal 524 which is the output of the decision equalizer, while being inputted to the tap coefficient multiplier 505 and the shift register 504.
  • the shift register 504 takes in the decision feedback equalizer output signal 524 and outputs data delayed in time for each cycle of the clock 522.
  • the signal delayed by one clock is input to the tap coefficient multiplier 506 of the second tap
  • the signal delayed by two clocks is input to the tap coefficient multiplier 507 of the third tap
  • the signal delayed by three clocks is the tap coefficient of the fourth tap.
  • a signal input to the multiplier 508 and delayed by 4 clocks is input to the tap coefficient multiplier 508 of the fifth tap.
  • the tap coefficient multipliers 505, 506, 507, 508, and 509 multiply the input data by the tap coefficients and output the results to the adder 501.
  • the tap coefficients of the tap coefficient multipliers 505, 506, 507, 508, and 509 are output from the adder 501 by the tap coefficient calculator 510, the determination threshold value 523 from the determination threshold calculator 511, and the determination feedback equalizer output signal 524, respectively. Calculated based on The determination threshold 523 is calculated by the determination threshold calculator 511 based on the output of the adder 501 and the determination feedback equalizer output signal 524.
  • the threshold offset determiner 901 receives the tap coefficient 525 and calculates the threshold offset 902 according to the internal function.
  • the ADC 1101 in the decision equalizer by having the ADC 1101 in the decision equalizer, everything after the ADC output can be handled as a digital signal, and the operation of the internal block can be easily changed by software. Thus, it is the structure which can improve versatility.
  • an electric signal transmission device that corrects a data error caused by data transition of a multilevel signal in a PAM (Pulse Amplitude Modulation) signal and expands the EYE width.
  • PAM Pulse Amplitude Modulation
  • the present invention is not limited to the above-described embodiment, and includes various modifications.
  • a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment.
  • It can be used for receivers for high-speed wired transmission and semiconductor integrated circuits that can be used for them.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'objectif de l'invention est de réduire les erreurs de bits provoquées par une linéarité de circuit et un motif de données. Un aspect de l'invention est un égaliseur à retour de décision comprenant : un premier additionneur qui ajoute une valeur de correction à un signal d'entrée; une unité de décision qui décide d'une valeur logique à partir d'une sortie du premier additionneur selon une première valeur de seuil de décision; une bascule qui échantillonne et maintient une sortie de l'unité de décision au rythme d'une horloge; un registre à décalage qui reçoit une sortie de la bascule bistable et de l'horloge et retarde la sortie de la bascule dans chaque période d'horloge; un multiplicateur qui multiplie la sortie de la bascule bistable et une sortie du registre à décalage par un coefficient de correction et délivre une valeur de correction; un calculateur de coefficient de correction qui calcule, à partir de la sortie du premier additionneur et de la sortie de la bascule, le coefficient de correction à chaque instant de l'horloge; un calculateur de valeur de seuil de décision qui calcule, à partir de la sortie du premier additionneur et de la sortie de la bascule, une seconde valeur de seuil de décision à chaque instant de l'horloge; et un second additionneur qui ajoute une valeur de seuil décalée à la seconde valeur de seuil de décision et délivre la première valeur de seuil de décision.
PCT/JP2018/008129 2018-03-02 2018-03-02 Égaliseur à retour de décision et récepteur l'utilisant Ceased WO2019167275A1 (fr)

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