WO2019153343A1 - Matrix capacitor board and chip test method - Google Patents

Abstract

Provided are a matrix capacitor board and a chip test method, the matrix capacitor board comprising: a plurality of first signal lines, a plurality of second signal lines, and a capacitor matrix formed by capacitors disposed at intersections of each of the first signal lines and each of the second signal lines, wherein the capacitor matrix comprises at least two kinds of capacitors. The chip test method comprises: disposing capacitors having at least two kinds of capacitance values in a capacitor matrix of a matrix capacitor board, thereby having a function of being capable of simulating a normal state (i.e. an untouched state) and a touched state, and being capable of implementing the testing of different performance conditions of a chip based on the function of the matrix capacitor board.

Description

Matrix capacitor board and chip test method Technical field

The present application relates to the field of testing technologies, and in particular, to a matrix capacitor board and a chip testing method.

Background technique

With the wide application of touch screens in the fields of smart phones, automobiles and home appliances, the demand for touch chips has also exploded. For the touch chip, its functionality and stability are very important, so in the mass production test, the performance of the touch chip needs to be tested. At present, in the touch chip test, an automatic built-in self test (Abist) loop is used to test whether the touch chip is normal.

The inventors have found that at least the following problems exist in the prior art: in the prior art, when the Abist loop is used to test whether the various paths of the touch chip are normal, there are some paths that cannot be covered by the Abist loop, and the test state of the touch chip is deviated from the actual state. Larger, resulting in insufficient test coverage.

Summary of the invention

The purpose of some embodiments of the present application is to provide a matrix capacitor board and a chip testing method. The capacitance matrix of the matrix capacitor board is provided with at least two capacitances, so that the simulated normal state (ie, the untouched state) and the touch state can be realized. The function and ability to test different performance conditions of the chip based on this function of the matrix capacitor plate.

The embodiment of the present application provides a matrix capacitor plate, including: a plurality of first signal lines, a plurality of second signal lines, and a capacitance matrix formed by a capacitance disposed at an intersection of each of the first signal lines and each of the second signal lines The capacitor matrix includes capacitors of at least two capacitance values.

The embodiment of the present application further provides a chip testing method, which provides the matrix capacitor board as described above, and connects the matrix capacitor board to the chip to be tested; one of the first signal line and the second signal line is used as the signal line. The transmission channel is used, and another signal line is used as the receiving channel; the scanning voltage is sequentially applied to each transmitting channel, and the output voltage is received from each receiving channel; and the performance state of the chip is analyzed according to the output voltage received by each receiving channel.

The embodiment of the present application further provides a chip testing method, which provides the matrix capacitor board as described above, and connects the matrix capacitor board to the chip to be tested; the first signal line or the second signal line is used as the current test channel; The current test channel sequentially applies a scan voltage and receives an output voltage from each current test channel; and analyzes the performance of the chip according to the output voltage received by each current test channel.

Compared with the prior art, the capacitors of the matrix capacitor plate are provided with capacitances of at least two kinds of capacitance values, thereby realizing the functions of simulating a normal state (ie, an untouched state) and a touch state, and can be based on a matrix. This function of the capacitor board enables testing of different performance conditions of the chip; the chip test is designed by using the function of the matrix capacitor board, which can highly simulate the working environment of the touch chip, thereby improving the test coverage and improving the test speed. .

In addition, in the matrix capacitor plate, the capacitance values of the capacitors sequentially arranged on each of the first signal lines form a capacitance distribution pattern corresponding to the first signal line; the capacitance values of the capacitors sequentially arranged on each of the second signal lines Forming a capacitance distribution pattern corresponding to the second signal line; the capacitance distribution pattern corresponding to each of the first signal lines satisfies the first preset condition; or the capacitance distribution pattern corresponding to each second signal line satisfies the second preset Alternatively, the capacitance distribution pattern corresponding to each of the first signal lines satisfies the first preset condition and the capacitance distribution pattern corresponding to each of the second signal lines satisfies the second preset condition. This embodiment provides different design schemes of the capacitance matrix.

In addition, in the matrix capacitor plate, the first preset condition is: the capacitance distribution patterns corresponding to the first signal lines of the respective strips are different; the second preset condition is: the capacitance distribution pattern corresponding to each of the second signal lines They are all different. This embodiment provides a specific content of a preset condition, that is, a specific design manner of the capacitor matrix is provided.

In addition, each capacitor located on the diagonal line and the diagonal side of the capacitor matrix has a first capacitance value, and each capacitor located on the other side of the diagonal line has a second capacitance value. This embodiment provides another specific design of the capacitance matrix.

In addition, the number of first signal lines is equal to the number of second signal lines.

In addition, in the matrix capacitor plate, the first preset condition is that the capacitance distribution patterns corresponding to the m first signal lines that are consecutively arranged are different, wherein m is an integer greater than or equal to 2 and m is smaller than the first signal line. The second predetermined condition is that the density distribution patterns corresponding to the n second signal lines that are consecutively arranged are different; wherein n is an integer greater than or equal to 2 and n is smaller than the total strip of the second signal line number. This embodiment provides another specific content of the preset condition, that is, another specific design manner of the capacitor matrix is provided.

In addition, in the matrix capacitor plate, capacitors with different capacitance values. This embodiment provides a specific selection manner of different capacitance values, so that the functions of the normal state (ie, the untouched state) and the touch state can be more accurately simulated.

In addition, in the matrix capacitor plate, the capacitance matrix includes two capacitance values, and the two capacitance values are 1.5 picofarads and 1.0 picofarads, respectively.

In addition, in the chip testing method, each transmitting channel corresponds to a set of output voltages and the set of output voltages is an output voltage received from each receiving channel when a scanning voltage is applied to the transmitting channel; the transmitting channel is used as a current test channel; The performance status of the chip is analyzed according to the output voltage received by each receiving channel, including: for each current test channel, the voltage value of each output voltage of a set of output voltages corresponding to the current test channel is used as the voltage distribution corresponding to the current test channel. a pattern; determining whether a voltage distribution pattern corresponding to the current test channel matches a capacitance distribution pattern corresponding to the current test channel; wherein, a capacitance value of each capacitor sequentially arranged on each current test channel forms a capacitance distribution pattern corresponding to the current test channel; If the judgment result of each current test channel is a match, it is determined that the touch detection function of the chip is normal. This embodiment provides a specific implementation manner of detecting whether the touch detection function of the chip is normal.

In addition, in the chip test method, the matrix capacitor plate is the above-mentioned matrix capacitor plate, and the capacitance distribution pattern corresponding to each of the first signal lines satisfies the first preset condition and the capacitance distribution pattern corresponding to each of the second signal lines. Each of the transmitting channels corresponds to a set of output voltages and the set of output voltages is an output voltage received from each receiving channel when a scanning voltage is applied to the transmitting channel; the transmitting channel is used as a current test channel; According to the output voltage received by each receiving channel, the performance status of the chip is analyzed, including: for each current test channel, the theoretical test channel is identified according to a set of output voltages corresponding to the current test channel; determining whether the theoretical test channel and the current test channel are Consistent; if not, it is determined that there is a wire abnormality inside the pin corresponding to the current test channel of the chip. This embodiment provides a specific implementation manner for detecting whether a chip has a wire abnormality.

In addition, the theoretical test channel is identified according to a set of output voltages corresponding to the current test channel, including: for each current test channel, the voltage value of each output voltage of the set of output voltages corresponding to the current test channel is used as the current test channel. The voltage distribution pattern is obtained according to a preset correspondence relationship between the voltage distribution pattern and the theoretical test channel, and obtains a theoretical test channel corresponding to the voltage distribution pattern corresponding to the current test channel. This embodiment provides a specific implementation manner of acquiring a theoretical test channel corresponding to a voltage distribution pattern corresponding to a current test channel.

In addition, in the chip test method, the performance status of the chip is analyzed according to the output voltage received by each current test channel, including: for each current test channel, determining the output voltage received from the current test channel and each of the current test channels Whether the sum of capacitance values of the capacitors matches; if the judgment result corresponding to each current test channel is matched, it is determined that the touch detection function of the chip is normal. This embodiment provides a specific implementation manner of detecting whether the touch detection function of the chip is normal.

In addition, in the chip test method, the matrix capacitor plate is the above-mentioned matrix capacitor plate, and the capacitance distribution pattern corresponding to each of the first signal lines satisfies the first preset condition and the capacitance distribution pattern corresponding to each of the second signal lines. The second preset condition is met; the performance status of the chip is analyzed according to the output voltage received by each current test channel, including: for each current test channel, determining the output voltage received from the current test channel and each of the current test channels Whether the sum of the capacitance values of the capacitors matches; if there is no match, it is determined that there is a wire abnormality inside the pin corresponding to the current test channel of the chip. This embodiment provides a specific implementation manner for detecting whether a chip has a wire abnormality.

In addition, in the chip test method, whether the output voltage received from the current test channel matches the capacitance of each capacitor on the current test channel, includes: querying a preset correspondence relationship between the output voltage and the sum of the capacitance values, and obtaining the output voltage. The sum of the corresponding capacitance values; query the preset correspondence between the test channel and the sum of the capacitance values, and obtain the sum of the capacitance values corresponding to the current test channel; determine whether the sum of the capacitance values corresponding to the output voltage is consistent with the sum of the capacitance values corresponding to the current test channel; Where, if consistent, the output voltage received from the current test channel is matched to the sum of the capacitances of the capacitors on the current test channel. This embodiment provides a specific implementation manner for determining whether the output voltage received by the current test channel matches the sum of the capacitances of the current capacitors on the current test channel.

DRAWINGS

The one or more embodiments are exemplified by the accompanying drawings in the accompanying drawings, and FIG. The figures in the drawings do not constitute a scale limitation unless otherwise stated.

1 is a schematic diagram of a matrix capacitor plate according to a first embodiment of the present application, wherein the matrix capacitor plate includes capacitors of two capacitance values;

2 is a schematic diagram of a matrix capacitor plate according to a first embodiment of the present application, wherein the matrix capacitor plate includes capacitors of three capacitance values;

3 is a schematic diagram of a matrix capacitor plate according to a second embodiment of the present application, wherein the first signal lines correspond to different capacitance distribution patterns;

4 is a schematic diagram of a matrix capacitor plate according to a second embodiment of the present application, wherein each of the second signal lines has a different capacitance distribution pattern;

5A is a schematic diagram of a matrix capacitor plate in which a capacitance distribution pattern corresponding to each first signal line and a capacitance distribution pattern corresponding to each second signal line satisfy a preset condition according to the second embodiment of the present application, wherein The number of the first signal lines is greater than the number of the second signal lines;

5B is a schematic diagram of a matrix capacitor plate in which a capacitance distribution pattern corresponding to each first signal line and a capacitance distribution pattern corresponding to each second signal line satisfy a preset condition according to the second embodiment of the present application, wherein The number of the second signal lines is greater than the number of the first signal lines;

6 is a first capacitance value on the diagonal line and the diagonal side of the capacitance matrix according to the second embodiment of the present application, and the capacitances on the other side of the diagonal line are second. A schematic diagram of a matrix capacitor plate of a capacitance value, wherein the number of first signal lines is greater than the number of second signal lines;

7 is a first capacitance value on the diagonal line and the diagonal side of the capacitance matrix according to the second embodiment of the present application, and the capacitances on the other side of the diagonal line are second. A schematic diagram of a matrix capacitor plate of a capacitance value, wherein the number of first signal lines is equal to the number of second signal lines;

FIG. 8A is a schematic diagram of a matrix capacitor plate according to a third embodiment of the present invention, wherein the two first signal lines that are consecutively arranged have corresponding capacitance distribution patterns;

FIG. 8B is a schematic diagram of a matrix capacitor plate according to a third embodiment of the present invention, wherein the two first signal lines that are consecutively arranged have different capacitance distribution patterns, and the two second signal lines that are consecutively arranged correspond to The capacitance distribution patterns are all different;

9 is a specific flowchart of a chip testing method in a fourth embodiment of the present application;

10 is a circuit diagram of a mutual capacitance detection model in a fourth embodiment of the present application;

11 is a specific flowchart of a chip testing method according to a fourth embodiment of the present application, where the touch detection function of the touch chip is detected;

FIG. 12 is a specific flowchart of a chip testing method according to a fifth embodiment of the present application; FIG.

FIG. 13 is a specific flowchart of a chip testing method according to a sixth embodiment of the present application; FIG.

14 is a circuit diagram of a self-capacity detection model in a sixth embodiment of the present application;

15 is a specific flowchart of a chip testing method according to a sixth embodiment of the present application, where the touch detection function of the touch chip is detected;

16 is a specific flowchart of a chip testing method in a seventh embodiment of the present application;

FIG. 17 is a specific flowchart of determining whether the output voltage received from the current test channel matches the capacitance of each capacitor on the current test channel according to the seventh embodiment of the present application.

Specific embodiment

In order to make the objects, technical solutions and advantages of the present application more clear, some embodiments of the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the application and are not intended to be limiting.

The first embodiment of the present application relates to a matrix capacitor plate. The matrix capacitor plate includes: the capacitor matrix includes a plurality of first signal lines, a plurality of second signal lines, and the first signal lines and the second signals disposed in each of the first signal lines a capacitance matrix formed by the capacitance at the intersection of the lines; in this embodiment, the first signal lines are parallel to each other, and the second signal lines are parallel to each other, and each of the first signal lines and each of the second signals The lines are perpendicular to each other and intersect. It should be noted that when the matrix capacitor plate is connected to the chip, one of the first signal line and the second signal line may serve as a transmission channel of the matrix capacitor plate, and the other serves as a receiving channel; in this embodiment, the first signal is used. The line is the transmitting channel (TX channel), and the second signal line is the receiving channel (RX channel) as an example for description.

In this embodiment, the capacitor matrix includes capacitors of at least two capacitance values. In one example, referring to FIG. 1, the capacitance matrix includes two capacitance capacitors, and the two capacitance values are 1.5 picofarads and 1.0 picofarads, respectively, and the capacitance matrix includes five first signal lines (TX0 to TX4) and 5 second signal lines (RX0 to RX4), the capacitance of the intersection of RX0, RX1 and each of the first signal lines (TX0 to TX4) is 1.0 picofarad, RX2 to RX4 and the first signal line (TX0) The capacitance of the junction to TX4) has a capacitance of 1.5 picofarads.

In another example, as shown in FIG. 2, the capacitance matrix includes capacitors of three capacitance values (three, for example, not limited thereto), and the three capacitance values are 2.0 picofarads, 1.5 picofarads, respectively. And 1.0 picofarad (as an example, but not limited to this), the capacitor matrix includes 5 first signal lines (TX0 to TX4) and 5 second signal lines (RX0 to RX4), TX0, TX1 and each The capacitance of the capacitance at the intersection of the second signal lines (RX0 to RX4) is 1.0 picofarad, and the capacitance of the capacitance at the intersection of TX2, TX3 and each of the second signal lines (RX0 to RX4) is 1.5 picofarads. The capacitance of the intersection of TX4 and each of the second signal lines (RX0 to RX4) has a capacitance of 2.0 picofarads.

It should be noted that, in FIG. 1 and FIG. 2, the capacitor matrix includes five first signal lines and five second signal lines, but the embodiment does not make any number of the first signal line and the second signal line. limit.

In the existing capacitive touch screen, the capacitance of the touched area becomes smaller in the touch state. The matrix capacitor plate in this embodiment can simulate a capacitive touch screen. The capacitance matrix of the matrix capacitor plate includes at least two capacitances of capacitance values, so that a capacitor with a small capacitance value can simulate a touched area, that is, a function of simulating a touch state; A capacitor with a large capacitance can simulate an untouched area, that is, a function that simulates a normal state (ie, a touch state).

Preferably, the capacitances of different capacitances satisfy the following conditions: the capacitance difference of any two capacitance values is greater than or equal to one third of the larger capacitance value, so that the normal state (ie, the untouched state) can be more accurately simulated. The function of touching the status.

Compared with the prior art, the capacitor of the matrix capacitor plate is provided with at least two kinds of capacitance values, thereby realizing the functions of simulating a normal state (ie, an untouched state) and a touch state, and can be based on a matrix capacitor. This function of the board enables testing of different performance conditions of the chip; the chip test is designed by using the function of the matrix capacitor board, which can highly simulate the working environment of the touch chip, thereby improving the test coverage and improving the test speed.

The second embodiment of the present application relates to a matrix capacitor plate. The embodiment is an improvement on the basis of the first embodiment. The main improvement is that a specific design scheme of the matrix capacitor plate is provided, and the first preset condition is The capacitance distribution patterns corresponding to the first signal lines are different. The second preset condition is that the capacitance distribution patterns corresponding to the second signal lines are different.

In this embodiment, the capacitance values of the capacitors sequentially arranged on each of the first signal lines form a capacitance distribution pattern corresponding to the first signal lines; and the capacitance values of the capacitors sequentially arranged on each of the second signal lines form a second value. The value distribution pattern corresponding to the signal line.

In this embodiment, three design schemes of the matrix capacitor board are provided, as follows:

First, the capacitance distribution pattern corresponding to each of the first signal lines satisfies the first preset condition.

Second, the capacitance distribution pattern corresponding to each of the second signal lines satisfies the second preset condition.

The third type, the capacitance distribution pattern corresponding to each of the first signal lines satisfies the first preset condition, and the capacitance distribution patterns corresponding to the second signal lines satisfy the second preset condition.

The first preset condition is: the capacitance distribution patterns corresponding to the first signal lines are different; the second preset condition is: the capacitance distribution patterns corresponding to the second signal lines are different, based on the above The three design schemes can be obtained as follows.

In the first type, the capacitance distribution pattern corresponding to each of the first signal lines satisfies the first preset condition, that is, the capacitance distribution patterns corresponding to the first signal lines of the respective first signal lines are different. Referring to FIG. 3, the capacitance matrix includes five The first signal lines (TX0 to TX4) are different from the seven second signal lines (RX0 to RX6), and the capacitance distribution patterns corresponding to TX0 to TX4 are different. As shown in FIG. 3, the capacitance values of the capacitors sequentially arranged on the first signal line TX0 are 1.5 pF, 1.0 pF, 1.0 pF, 1.0 pF, 1.0 pF, 1.0 pF, and 1.0 pF; that is, the capacitance corresponding to the first signal line TX0. The value distribution pattern is: (3, 2, 2, 2, 2, 2, 2); wherein the capacitance distribution pattern herein is expressed by a ratio of capacitance values, but is not limited thereto. In this way, the capacitance distribution pattern corresponding to each of the first signal lines (TX0 to TX4) is obtained, as shown in Table 1 below.

Table 1

Secondly, the capacitance distribution pattern corresponding to each of the second signal lines satisfies the second preset condition, that is, the capacitance distribution patterns corresponding to the second signal lines are different, please refer to FIG. 4, and the capacitance matrix includes 7 The first signal lines (TX0 to TX6) are different from the five second signal lines (RX0 to RX4), and the capacitance distribution patterns corresponding to TX0 to TX7 are different.

Third, the capacitance distribution pattern corresponding to each of the first signal lines satisfies the first preset condition, and the capacitance distribution patterns corresponding to the second signal lines satisfy the second preset condition, that is, each of the first signal lines The corresponding capacitance distribution patterns are different, and the capacitance distribution patterns corresponding to the second signal lines are different. Referring to FIG. 5A (an example), the number of first signal lines is smaller than the number of second signal lines; the capacitance matrix includes five first signal lines (TX0 to TX4) and seven second signal lines (RX0 to RX6), The capacitance distribution patterns corresponding to the first signal lines (TX0 to TX4) are different, and the capacitance distribution patterns corresponding to the second signal lines (RX0 to RX6) are different. Referring to FIG. 5B (another example), the number of first signal lines is greater than the number of second signal lines; the capacitance matrix includes 7 first signal lines (TX0 to TX6) and 5 second signal lines (RX0 to RX4) The capacitance distribution patterns corresponding to the first signal lines (TX0 to TX6) are different, and the capacitance distribution patterns corresponding to the second signal lines (RX0 to RX4) are different.

In one example, the capacitance matrix includes two capacitance values, and the two capacitance values are the first capacitance value and the second capacitance value, respectively, on the diagonal line of the capacitance matrix and the capacitances on one side of the diagonal line. The first capacitance value is the second capacitance value. The capacitor matrix includes five first signal lines (TX0 to TX4) and seven second signal lines. (RX0 to RX6), the capacitance distribution patterns corresponding to the first signal lines (TX0 to TX4) are different, and the dotted line is the diagonal of the capacitance matrix, which is located on the diagonal and on the diagonal side. The capacitances are both 1.5pF, and the capacitances on the other side of the diagonal are all the second capacitance value of 1.0pF. It can be seen that the capacitance distribution pattern corresponding to each of the first signal lines in the figure satisfies the first preset condition, that is, each The capacitance distribution patterns corresponding to the first signal lines of the strips are all different; correspondingly, the second signal lines are used as the transmitting channels and the first signal lines are used as the receiving channels, so that the capacitance distribution patterns corresponding to the second signal lines can be made. Satisfying the second preset condition, that is, the capacitance distribution patterns corresponding to the second signal lines of each strip are not in phase , Not discussed here.

Preferably, the number of the first signal lines is equal to the number of the second signal lines. Referring to FIG. 7, the capacitance matrix includes five first signal lines (TX0 to TX4) and five second signal lines (RX0 to RX4). The first value is 1.5 picofarads, and the second volume is 1.0 picofarads (as an example, but not limited to this). The dashed line is the diagonal of the capacitor matrix, located on the diagonal of the capacitor matrix and Each capacitor on the side of the corner line has a first capacitance of 1.5 picofarads, and each capacitor on the other side of the diagonal of the capacitor matrix has a second capacitance value of 1.0 picofarads, and each of the first signal lines (TX0 to TX4) The corresponding capacitance distribution patterns are different, and the capacitance distribution patterns corresponding to the second signal lines (RX0 to RX4) are different.

Compared with the first embodiment, this embodiment provides different design schemes of the capacitance matrix, and a matrix capacitor plate that satisfies the first preset condition and the second preset condition.

The third embodiment of the present application relates to a matrix capacitor plate. The embodiment is an improvement on the basis of the first embodiment. The main improvement is that in the embodiment, the first preset condition is: consecutively arranged m strips. The capacitance distribution patterns corresponding to the first signal lines are different; the second preset condition is that the capacitance distribution patterns corresponding to the n second signal lines that are consecutively arranged are different.

In this embodiment, the first preset condition is that the capacitance distribution patterns corresponding to the m first signal lines that are consecutively arranged are different, where m is an integer greater than or equal to 2 and m is smaller than the total strip of the first signal line. The second preset condition is that the density distribution patterns corresponding to the n second signal lines that are consecutively arranged are different; wherein n is an integer greater than or equal to 2 and n is smaller than the total number of second signal lines. Based on the three design schemes in the second embodiment, the following matrix capacitor plates can be obtained.

The first type, the capacitance distribution pattern corresponding to each of the first signal lines, the capacitance distribution patterns corresponding to the m first signal lines that are consecutively arranged are different; referring to FIG. 8A, the capacitance matrix includes six first signals. The line (TX0 to TX5) and the four second signal lines (RX0 to RX3) have different capacitance distribution patterns corresponding to the two first signal lines that are consecutively arranged, that is, the capacitance distribution patterns corresponding to TX0 and TX1 are Different, the capacitance distribution patterns corresponding to TX2 and TX3 are different, and the capacitance distribution patterns corresponding to TX4 and TX5 are different; among them, the capacitance distribution pattern corresponding to TX0 and TX1, and the capacitance distribution pattern corresponding to TX2 and TX3 And the capacitance distribution patterns corresponding to TX4 and TX5 are the same, but are not limited thereto, the capacitance distribution pattern corresponding to TX0 and TX1, the capacitance distribution pattern corresponding to TX2 and TX3, and the capacitance distribution pattern corresponding to TX4 and TX5 are also applicable. Not the same.

Secondly, in the capacitance distribution pattern corresponding to each of the second signal lines, the capacitance distribution patterns corresponding to the n first signal lines that are consecutively arranged are different, and the specific matrix capacitor plate is similar to FIG. 8A, and only needs to be The two signal lines are used as the transmitting channel and the first signal line is used as the receiving channel, and details are not described herein again.

In the third type, the capacitance distribution patterns corresponding to the m first signal lines that are consecutively arranged are different, and the capacitance distribution patterns corresponding to the n first signal lines that are consecutively arranged are different, please refer to FIG. 8B, the capacitance matrix. The six first signal lines (TX0 to TX5) and the four second signal lines (RX0 to RX3) are arranged, and the two first signal lines that are consecutively arranged have different capacitance distribution patterns, and the two consecutively arranged The capacitance distribution patterns corresponding to the two signal lines are different, that is, the capacitance distribution patterns corresponding to TX0 and TX1 are different, and the capacitance distribution patterns corresponding to TX2 and TX3 are different, and the capacitance distribution patterns corresponding to TX4 and TX5 are different. The values of the capacitance distribution patterns of RX0 and RX1 are different, and the distribution patterns of RX2 and RX3 are different.

It should be noted that, in this embodiment, a capacitance including two capacitance values in the capacitance matrix, and two capacitance values of the capacitance are respectively 1.5 skin method and 1.0 skin method, and the present embodiment includes the capacitor matrix. There is no restriction on the type of capacitance and the magnitude of the capacitance.

It should be noted that the present embodiment only schematically describes the number of the first signal line and the second signal line included in the capacitor matrix. However, this embodiment does not impose any limitation, and may be specifically set according to actual needs.

Compared with the first embodiment, the present embodiment provides a matrix capacitor plate that satisfies the first preset condition and the second preset condition.

The fourth embodiment of the present invention relates to a chip testing method, which is applied to testing a touch chip; as shown in FIG. 9 , the chip testing method includes: Step 101 : providing any one of the first embodiment to the third embodiment a matrix capacitor plate, and the matrix capacitor plate is connected to the chip to be tested; one of the first signal line and the second signal line is used as a transmission channel, and the other signal line is used as a receiving channel; Step 102: sequentially apply scanning voltages to the respective transmitting channels, and receive output voltages from the respective receiving channels. Step 103: Analyze the performance status of the chip according to the output voltage received by each receiving channel.

Compared with the prior art, the capacitor of the matrix capacitor plate is provided with at least two kinds of capacitance values, thereby realizing the functions of simulating a normal state (ie, an untouched state) and a touch state, and can be based on a matrix capacitor. This function of the board enables testing of different performance conditions of the chip; the chip test is designed by using the function of the matrix capacitor board, which can highly simulate the working environment of the touch chip, thereby improving the test coverage and improving the test speed.

The implementation details of the chip test method of this embodiment are specifically described below. The following content is only for the convenience of understanding the implementation details provided, and is not necessary to implement the solution. The embodiment is specifically configured to detect a touch detection function of the touch chip.

The chip test method in this embodiment is based on the mutual capacitance model. Please refer to FIG. 10, which is a circuit diagram of the mutual capacitance detection model. Cx represents the capacitance of the capacitance on the matrix capacitor plate, V _TX represents the input signal, and W represents the frequency of the input signal. V _RX represents the output signal, and R represents the resistance of the circuit, which can be obtained as follows:

V _RX =R*W*Cx*V _TX formula (1)

Wherein, the input signal is unchanged, that is, W and V _{TX are} unchanged, and the resistance R of the circuit is unchanged; according to formula (1), the output signal V _RX is proportional to the capacitance Cx on the matrix capacitor plate.

Since the chip test method of the embodiment is implemented based on the principle of the mutual capacitance model, the output signal V _RX is proportional to the capacitance Cx on the matrix capacitor plate, and will be used as a principle basis for subsequent chip test analysis.

For the specific flow of the chip test method of this embodiment, please refer to FIG. 9 and FIG.

In step 101, a matrix capacitor plate as in the first embodiment or the second embodiment is provided, and a matrix capacitor plate is connected to the chip to be tested. The matrix capacitor plate is a matrix capacitor plate provided in any one of the first to third embodiments.

Specifically, each of the first signal lines and each of the second signal lines are respectively connected to pins of the touch chip, and each of the signal lines is connected to one pin. Wherein, one of the first signal line and the second signal line in the capacitance matrix of the matrix capacitor plate is used as a transmission channel, and the other signal line is used as a receiving channel; that is, the touch chip and each The pin connected to the first signal line serves as a pin for transmitting a scan signal, and the pin connected to each second signal line of the touch chip is used as a pin for receiving an output signal.

In step 102, scan voltages are sequentially applied to the respective transmit channels, and output voltages are received from the respective receive channels.

Specifically, the touch chip applies a scanning voltage to each of the transmitting channels in turn through a pin connected to the transmitting channel, and receives an output voltage through a pin connected to the receiving channel.

Step 103: Analyze the performance status of the chip according to the output voltage received by each receiving channel. Referring to FIG. 11, the following sub-steps are specifically included:

Sub-step 1031, for each transmitting channel, a voltage value of each output voltage of a set of output voltages corresponding to the transmitting channel is used as a voltage distribution pattern corresponding to the transmitting channel.

Specifically, for one transmitting channel, a set of output voltage voltage values can be obtained, and the voltage value of the set of output voltages is used as a voltage distribution pattern corresponding to the emission, and the matrix capacitor plate of FIG. 1 is taken as an example, and 5 The voltage values of the five sets of output voltages corresponding to the strip transmission channels (TX0 to TX4) are used as five voltage distribution patterns corresponding to the five transmission channels.

Sub-step 1032, determining whether the voltage distribution pattern corresponding to the transmitting channel matches the capacitance distribution pattern corresponding to the transmitting channel.

Specifically, taking the transmitting channel TX0 as an example, the touch chip applies a scanning voltage to the transmitting channel TX0, and uses the voltage value of each output voltage in the set of output voltages corresponding to the transmitting channel TX0 as the voltage corresponding to the transmitting channel TX0. Distribution pattern, if the voltage values of the received output voltages are: (4V, 4V, 6V, 6V, 6V), the voltage distribution pattern corresponding to the transmission channel TX0 is (2, 2, 3, 3, 3); It can be seen from FIG. 1 that the capacitance distribution pattern corresponding to the transmission channel TX0 is (2, 2, 3, 3, 3); by comparison, the voltage distribution pattern corresponding to the transmission channel TX0 matches the capacitance distribution pattern corresponding to the transmission channel TX0. If the voltage values of the received output voltages are: (4V, 4V, 4V, 6V, 6V), the voltage distribution pattern corresponding to the transmission channel TX0 is (2, 2, 2, 3, 3), by comparison It can be seen that the voltage distribution pattern corresponding to the transmission channel TX0 does not match the capacitance distribution pattern corresponding to the transmission channel TX0. Based on the similar principle, it can be determined whether the voltage distribution pattern corresponding to each of the transmitting channels matches the capacitance distribution pattern. Wherein, for convenience of observation, the voltage distribution pattern and the capacitance distribution pattern corresponding to the emission channel are expressed in a proportional form.

Sub-step 1033, if the judgment result of each of the transmission channels is a match, it is determined that the touch detection function of the chip is normal.

Specifically, when the voltage distribution pattern corresponding to each of the transmitting channels matches the capacitance distribution pattern corresponding to each of the transmitting channels, the touch detection function of the touch chip is normal; when there is one or more transmitting channels corresponding to When the voltage distribution pattern does not match the corresponding capacitance distribution pattern, the touch detection function of the touch chip is abnormal.

The fifth embodiment of the present invention relates to a chip testing method. The present embodiment is substantially the same as the fourth embodiment. The main difference is that in the third embodiment, the touch detection function of the touch chip is detected. In the example, whether there is a wire abnormality inside the pin of the touch chip is detected.

In this embodiment, a specific process of the chip testing method is shown in FIG. The matrix capacitor plate is the matrix capacitor plate in the second embodiment or the third embodiment, and the capacitance distribution pattern corresponding to each of the first signal lines satisfies the first preset condition and the corresponding capacity of each second signal line. The value distribution pattern satisfies the second preset condition.

Step 201, step 202 and step 101 are substantially the same as step 102. The main difference is that the transmitting channel is used as the current test channel. In this embodiment, in step 203, the chip is analyzed according to the output voltage received by each receiving channel. The performance status includes:

Sub-step 2031, for each current test channel, the theoretical test channel is identified according to a set of output voltages corresponding to the current test channel.

Specifically, for each current test channel, the voltage value of each output voltage in a set of output voltages corresponding to the current test channel is used as a voltage distribution pattern corresponding to the current test channel. According to the preset correspondence relationship between the voltage distribution pattern and the theoretical test channel, and thus the theoretical test channel corresponding to the voltage distribution pattern corresponding to the current test channel can be obtained.

The specific method is: comparing each output voltage of a set of output voltages corresponding to the current test channel, and identifying a voltage trip point in the set of output voltages, and determining a capacitance jump of the capacitor characterized by the voltage trip point Variable position; then according to the preset correspondence relationship between the value jump position, the capacitance distribution pattern and the theoretical test channel, the theoretical test channel corresponding to the capacitance jump position can be obtained. Taking the matrix capacitor board in FIG. 7 as an example, as shown in Table 2 below, it is a preset correspondence table of capacitance value jump position, capacitance distribution pattern, and theoretical test channel.

Table 2

It should be noted that if there are multiple voltage trip points in a set of output voltages corresponding to the current test channel, it is necessary to identify the value jump positions corresponding to the plurality of voltage trip points, so that multiple The value jumps the position, obtains the corresponding capacitance distribution pattern, and then obtains the theoretical test channel corresponding to the capacitance distribution pattern, that is, obtains the theoretical test channel corresponding to the current test channel, taking the matrix capacitor plate of FIG. 3 as an example. If there are two values of the value jump position, and the fourth capacitor and the fifth capacitor are respectively, the capacitance distribution pattern corresponding to the two capacitance jump positions is (3, 3, 3, 3, 2 , 3, 3), the theoretical test channel corresponding to the capacitance distribution pattern is TX3, that is, the theoretical test channel corresponding to the current test channel is TX3.

Sub-step 2032, determining whether the theoretical test channel is consistent with the current test channel.

Specifically, when the theoretical test channel is the same as the current test channel, that is, the two are consistent, it indicates that there is no wire abnormality inside the pin corresponding to the current test channel of the touch chip.

Sub-step 2033, if not, it is determined that there is a wire-line abnormality inside the pin corresponding to the current test channel of the chip.

Specifically, when the theoretical test channel and the current test channel are different transmission channels, that is, the two are inconsistent, it indicates that there is a wire abnormality inside the pin corresponding to the current test channel of the touch chip, that is, an external pin of the chip. The line is abnormal with the Pad inside the chip.

Compared with the fourth embodiment, this embodiment provides a specific implementation manner for detecting whether there is a wire abnormality inside the pin of the touch chip.

The sixth embodiment of the present application relates to a chip testing method, which is applied to test a touch chip. As shown in FIG. 13 , the chip testing method includes: Step 301, providing any one of the first embodiment to the third embodiment. a matrix capacitor plate, and connecting the matrix capacitor plate to the chip to be tested; step 302, sequentially applying a scan voltage to each current test channel, and receiving an output voltage from each current test channel; step 303, receiving according to each current test channel The output voltage is analyzed to analyze the performance of the chip.

Compared with the prior art, the capacitor of the matrix capacitor plate is provided with at least two kinds of capacitance values, thereby realizing the functions of simulating a normal state (ie, an untouched state) and a touch state, and can be based on a matrix capacitor. This function of the board enables testing of different performance conditions of the chip; the chip test is designed by using the function of the matrix capacitor board, which can highly simulate the working environment of the touch chip, thereby improving the test coverage and improving the test speed.

The implementation details of the chip test method of this embodiment are specifically described below. The following content is only for the convenience of understanding the implementation details provided, and is not necessary to implement the solution. The embodiment is specifically configured to detect a touch detection function of the touch chip.

The chip test method in this embodiment is based on the self-capacity detection model. Please refer to FIG. 14 , which is a circuit diagram of the self-capacity detection model. C _Tx represents the sum of the capacitance values of the capacitances of one transmission channel on the matrix capacitor plate, and V _TX represents the input. Signal, W represents the frequency of the input signal, V _RX represents the output signal, and R represents the resistance of the circuit, which can be obtained as follows:

V _RX =V _TX /(1+R*W*C _Tx ) Formula (2)

Wherein, the input signal is unchanged, that is, W and V _{TX are} unchanged, and the resistance R of the circuit is unchanged; according to formula (2), the output signal V _{RX is} proportional to the capacitance C _Tx on the matrix capacitor plate.

Since the chip testing method of the present embodiment is based on the principle of the self-contained embodiment of the model, the sum of the capacitance C of the capacitance value of the channel is proportional to a _Tx output signal V _RX matrix capacitive plate and emission, as will follow The rationale for the analysis of the chip test.

For the specific flow of the chip testing method of this embodiment, please refer to FIG. 13 and FIG. 15.

In step 301, matrix capacitor plates as in the first to third embodiments are provided, and a matrix capacitor plate is connected to the chip to be tested. The matrix capacitor plate is a matrix capacitor plate provided in any one of the first to third embodiments.

Specifically, the first signal line or the second signal line in the capacitance matrix of the matrix capacitor plate is used as the current test channel, and the current test channel is respectively connected to each pin of the touch chip, and each signal line is connected to one Pin.

In step 302, a scan voltage is sequentially applied to each current test channel, and an output voltage is received from each current test channel.

Specifically, the touch chip sequentially applies a scan voltage to each current test channel through a pin connected to each current test channel, and receives an output voltage from each current test channel through a pin connected to each current test channel.

In step 303, the performance status of the chip is analyzed according to the output voltage received by each receiving channel. Referring to FIG. 15, the following sub-steps are specifically included:

Sub-step 3031, for each current test channel, determines whether the output voltage received from the current test channel matches the capacitance of each capacitor on the current test channel.

Specifically, the preset relationship between the voltage value of the output voltage and the sum of the capacitance values is pre-stored in the touch chip; for each current test channel, a voltage value of the output voltage can be obtained, according to the voltage value and the capacitance value of the output voltage. The preset correspondence relationship of the sum determines whether the voltage value of the output voltage received from the current test channel matches the sum of the capacitance values of the capacitors on the current test channel, and the specific judgment mode is: under the input voltage V _TX , on the current test channel The sum of the capacitance values of the capacitors and the output voltage corresponding to C _TX is V _RX . If the voltage value of the output voltage received from the current test channel is not equal to V _RX , the voltage value of the output voltage received from the current test channel is compared with the current test. The sum of the capacitance values of the capacitors on the channel does not match; otherwise, the two match.

Sub-step 3032, if the judgment result corresponding to each current test channel is matched, it is determined that the touch detection function of the chip is normal.

Specifically, when the output voltage received by each test channel matches the sum of the capacitances of the capacitors on each test channel, it is determined that the touch detection function of the touch chip is normal; when one or more test channels are received, If the output voltage does not match the sum of the capacitances of the respective capacitors on the corresponding test channel, it is determined that the touch detection function of the touch chip is abnormal.

The seventh embodiment of the present application relates to a chip testing method. The present embodiment is substantially the same as the sixth embodiment. The main difference is that in the third embodiment, the touch detection function of the touch chip is detected. In the example, whether there is a wire abnormality inside the pin of the touch chip is detected.

In this embodiment, a specific process of the chip testing method is shown in FIG. 16. The matrix capacitor plate is the matrix capacitor plate in the second embodiment or the third embodiment, and the capacitance distribution pattern corresponding to each of the first signal lines satisfies the first preset condition and the corresponding capacity of each second signal line. The value distribution pattern satisfies the second preset condition.

Step 401, step 402 and step 301 are substantially the same as step 302. The main difference is that, in this embodiment, step 403 analyzes the performance status of the chip according to the output voltage received by each receiving channel, which specifically includes:

Sub-step 4031, for each current test channel, determining whether the output voltage received from the current test channel matches the capacitance of each capacitor on the current test channel. Referring to FIG. 17, the following sub-steps are included:

Sub-step 40311, querying a preset correspondence relationship between the output voltage and the sum of the capacitance values, and obtaining a sum of capacitance values corresponding to the output voltage.

Specifically, the preset correspondence between the output voltage and the sum of the capacitance values is pre-stored in the touch chip, and the preset correspondence relationship between the output voltage and the sum of the capacitance values is queried according to the output voltage received from the current test channel, and the current correspondence can be obtained from the current The sum of the capacitance values corresponding to the output voltage received by the test channel.

In sub-step 40312, the preset correspondence between the test channel and the sum of the capacitance values is queried, and the sum of the capacitance values corresponding to the current test channel is obtained.

Specifically, the preset correspondence between the test channel and the sum of the capacitance values is pre-stored in the touch chip, and the preset correspondence relationship between the test channel and the sum of the capacitance values is queried, so that the sum of the capacitance values corresponding to the current test channel can be obtained.

Sub-step 40313 determines whether the sum of the capacitance values corresponding to the output voltage is consistent with the sum of the capacitance values corresponding to the current test channel.

Specifically, determining whether the sum of the capacitance values corresponding to the output voltage received from the current test channel is equal to the sum of the capacitance values corresponding to the current test channel, and when the two are equal, characterizing the output voltage received from the current test channel and the current test channel The sum of the capacitance values of the capacitors on the first one is matched; if the two are different, the output voltage received from the current test channel does not match the sum of the capacitance values of the capacitors on the current test channel, and the process proceeds to step 4032.

Sub-step 4032, if there is no match, it is determined that there is a wire-line abnormality inside the pin corresponding to the current test channel of the chip.

Specifically, if the output voltage received from the current test channel does not match the sum of the capacitances of the capacitors on the current test channel, it indicates that there is a wire abnormality inside the chip corresponding to the current test channel, that is, the external part of the chip. The wire is abnormal between the pin and the pad inside the chip; based on the above principle, it can be detected whether there is a wire abnormality inside each pin of the touch chip, that is, each external pin of the touch chip and each inside of the chip can be detected. Is there a wire mismatch between the Pads?

Compared with the sixth embodiment, this embodiment provides a specific implementation manner for detecting whether there is a wire abnormality inside the pin of the touch chip.

A person skilled in the art can understand that the above embodiments are specific embodiments of the present application, and various changes can be made in the form and details without departing from the spirit and scope of the application. range.

Claims (16)

A matrix capacitor plate, comprising: a plurality of first signal lines, a plurality of second signal lines, formed by a capacitance disposed at an intersection of each of the first signal lines and each of the second signal lines Capacitor matrix The capacitor matrix includes capacitors of at least two capacitance values. The matrix capacitor plate according to claim 1, wherein a capacitance value of each of the capacitors sequentially arranged on each of the first signal lines forms a capacitance distribution pattern corresponding to the first signal line; The capacitance values of the capacitors sequentially arranged on the second signal line form a capacitance distribution pattern corresponding to the second signal line; The capacitance distribution pattern corresponding to each of the first signal lines satisfies a first preset condition; or the capacitance distribution pattern corresponding to each of the second signal lines satisfies a second preset condition; or, each of the The capacitance distribution pattern corresponding to the first signal line satisfies the first preset condition and the capacitance distribution pattern corresponding to each of the second signal lines meets the second preset condition. The matrix capacitor plate according to claim 2, wherein The first preset condition is that the capacitance distribution patterns corresponding to the first signal lines of the strips are different; The second preset condition is that the capacitance distribution patterns corresponding to the second signal lines of the strips are different. The matrix capacitor plate according to claim 3, wherein Each of the capacitors on a diagonal line of the capacitance matrix and on one side of the diagonal line has a first capacitance value, and each of the capacitors on the other side of the diagonal line has a second capacitance value . The matrix capacitor plate according to claim 4, wherein the number of the first signal lines is equal to the number of the second signal lines. The matrix capacitor plate according to claim 2, wherein The first preset condition is that: the consecutively arranged m pieces of the first signal lines have different capacitance distribution patterns, wherein m is an integer greater than or equal to 2 and m is smaller than the total of the first signal lines. Number of articles; The second preset condition is: the capacity distribution patterns corresponding to the n pieces of the second signal lines that are consecutively arranged are different; wherein n is an integer greater than or equal to 2 and n is smaller than the total of the second signal lines The number of articles. The matrix capacitor plate according to claim 1, wherein the capacitances of different capacitances satisfy a condition that a capacitance difference of any two kinds of capacitances is greater than or equal to one third of a larger capacitance. The matrix capacitor plate according to claim 1, wherein the capacitance matrix includes capacitances of two capacitance values, and the two capacitance values are 1.5 picofarads and 1.0 picofarads, respectively. A chip testing method, comprising: Providing the matrix capacitor plate according to any one of claims 1 to 8, and connecting the matrix capacitor plate to a chip to be tested; and one of the first signal line and the second signal line The signal line acts as a transmitting channel and the other signal line serves as a receiving channel; And applying a scanning voltage to each of the transmitting channels, and receiving an output voltage from each of the receiving channels; The performance status of the chip is analyzed according to an output voltage received by each of the receiving channels. The chip testing method according to claim 9, wherein each of said transmitting channels corresponds to a set of output voltages and said set of output voltages are from said each of said transmitting channels when said scanning voltage is applied Receiving an output voltage received by the channel; using the transmitting channel as a current test channel; The analyzing the performance status of the chip according to the output voltage received by each of the receiving channels, including: For each of the current test channels, a voltage value of each of the output voltages corresponding to the current test channel is used as a voltage distribution pattern corresponding to the current test channel; Determining whether a voltage distribution pattern corresponding to the current test channel matches a capacitance distribution pattern corresponding to the current test channel; wherein a capacitance value of each of the capacitors sequentially arranged on each of the current test channels forms the current test a capacitance distribution pattern corresponding to the channel; If the judgment result of each of the current test channels is a match, it is determined that the touch detection function of the chip is normal. The chip test method according to claim 9, wherein the matrix capacitor plate is the matrix capacitor plate according to any one of claims 3 to 6, and a capacitance value corresponding to each of the first signal lines And the distribution pattern satisfying the first preset condition and the capacitance distribution pattern corresponding to each of the second signal lines satisfy the second preset condition; Each of the transmitting channels corresponds to a set of output voltages and the set of output voltages is an output voltage received from each of the receiving channels when the scanning channel is applied with the scanning voltage; the transmitting channel is used as a current test aisle; The analyzing the performance status of the chip according to the output voltage received by each of the receiving channels, including: For each of the current test channels, a theoretical test channel is identified according to a set of output voltages corresponding to the current test channel; Determining whether the theoretical test channel is consistent with the current test channel; If not, it is determined that there is a wire abnormality inside the pin corresponding to the current test channel of the chip. The chip testing method according to claim 11, wherein the identifying the theoretical test channel according to the set of output voltages corresponding to the current test channel comprises: For each of the current test channels, a voltage value of each of the output voltages corresponding to the current test channel is used as a voltage distribution pattern corresponding to the current test channel; And according to a preset correspondence relationship between the voltage distribution pattern and the theoretical test channel, and acquiring a theoretical test channel corresponding to the voltage distribution pattern corresponding to the current test channel. A chip testing method, comprising: Providing the matrix capacitor plate according to any one of claims 1 to 8, and connecting the matrix capacitor plate to a chip to be tested; using the first signal line or the second signal line as a current test channel ; And sequentially applying a scan voltage to each of the current test channels, and receiving an output voltage from each of the current test channels; The performance status of the chip is analyzed according to the output voltage received by each of the current test channels. The chip testing method according to claim 13, wherein the analyzing the performance status of the chip according to the output voltage received by each of the current test channels comprises: For each of the current test channels, determining whether the output voltage received from the current test channel matches the sum of the capacitances of the capacitors on the current test channel; If the judgment result corresponding to each of the current test channels is a match, it is determined that the touch detection function of the chip is normal. The chip test method according to claim 13, wherein the matrix capacitor plate is the matrix capacitor plate according to any one of claims 3 to 6, and a capacitance value corresponding to each of the first signal lines And the distribution pattern satisfying the first preset condition and the capacitance distribution pattern corresponding to each of the second signal lines satisfy the second preset condition; The analyzing the performance status of the chip according to the output voltage received by each of the current test channels, including: For each of the current test channels, determining whether the output voltage received from the current test channel matches the sum of capacitance values of the capacitors on the current test channel; If there is no match, it is determined that there is a wire abnormality inside the pin corresponding to the current test channel of the chip. The chip testing method according to claim 15, wherein the sum of the output voltage received from the current test channel and the capacitance of each of the capacitors on the current test channel, including: Querying a preset correspondence between the output voltage and the sum of the capacitance values, and obtaining a sum of capacitance values corresponding to the output voltage; Querying a preset correspondence between the test channel and the sum of the capacitance values, and obtaining a sum of capacitance values corresponding to the current test channel; Determining whether the sum of the capacitance values corresponding to the output voltage is consistent with the sum of the capacitance values corresponding to the current test channel; wherein, if consistent, characterizing the output voltage received from the current test channel and the current test channel The sum of the capacitance values of the respective capacitors is matched.

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