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WO2019151022A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2019151022A1
WO2019151022A1 PCT/JP2019/001709 JP2019001709W WO2019151022A1 WO 2019151022 A1 WO2019151022 A1 WO 2019151022A1 JP 2019001709 W JP2019001709 W JP 2019001709W WO 2019151022 A1 WO2019151022 A1 WO 2019151022A1
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WIPO (PCT)
Prior art keywords
etching
conductive material
semiconductor
fin
region
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English (en)
Japanese (ja)
Inventor
和雄 吉備
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10P14/40—
    • H10P50/00—
    • H10P50/242—
    • H10W20/01—
    • H10W20/40—
    • H10W20/48—

Definitions

  • An exemplary embodiment of the present disclosure relates to a semiconductor device including a fin-type field effect transistor (Fin-FET) and a manufacturing method thereof.
  • Fin-FET fin-type field effect transistor
  • Recent logic standard cells include a plurality of fin-type field effect transistors (hereinafter referred to as FETs), and attempts have been made to reduce the minimum unit height (cell height) of logic circuits. Yes. This is because when the cell height is reduced, the power consumption is reduced and the operation speed of the circuit is increased based on the scaling law.
  • FETs fin-type field effect transistors
  • Patent Document 1 discloses a structure in which a plurality of power rails (power supply lines / ground lines) are embedded in a logic standard cell having fin-type FETs. The dimension between two adjacent power rails is the cell height. Other fin-type FETs are disclosed in Patent Document 5, for example.
  • Patent Document 2 discloses a technique for embedding a bit line of a memory
  • Patent Document 3 and Patent Document 4 disclose a capacitor as related technologies.
  • a method for manufacturing a semiconductor device that can easily form a power rail and a semiconductor device that can be formed by such a method are required.
  • a first semiconductor device manufacturing method includes a first fin group including a pair of semiconductor fins, and a first fin group including a pair of semiconductor fins spaced apart from the first fin group.
  • the second fin group includes: A semiconductor device comprising: a second semiconductor fin constituting a fin-type N-type field effect transistor including a source region, a gate region, and a drain region, and a fixed potential line to which the source region of the first semiconductor fin is connected
  • the method includes a first step of preparing an intermediate and a second step of leaving a conductive material, and the intermediate in the first step is separated from a substrate.
  • the first semiconductor fins and the third semiconductor fins are provided, and are higher than any of the top surfaces of the first and third semiconductor fins in a region between the adjacent first and third semiconductor fins.
  • a conductive material for the fixed potential line is provided up to a position, a protective material is provided on a region outside the region between the first and third semiconductor fins, and the second step includes the steps of Etching the conductive material to a position lower than any of the top surfaces of the third semiconductor fins, removing the conductive material on the protective material, and in the region between the first and third semiconductor fins, The conductive material is left behind.
  • a power rail including a fixed potential line made of a conductive material can be easily formed. Can be formed.
  • the conductive material includes a first conductive material separated by a first distance d1 from the first semiconductor fin, and a first distance d1 ⁇ a second distance d2.
  • the first conductive material is TiN or TaN
  • the second conductive material is at least one metal selected from the group consisting of Co, W, and Ru.
  • the etching gas contains CF 4 or a mixed gas of oxygen and Cl 2 .
  • a mixed gas of oxygen (O 2 ) and Cl 2 can etch the selected metal such as Ru, but a metal nitride such as TiN (titanium nitride) or TaN (tantalum nitride). Has etching resistance against this mixed gas.
  • the etching gas is a mixed gas of oxygen and Cl 2 , and Cl with respect to the volume molar concentration C (O 2 + Cl 2 ) (mol / L) of the mixed gas in a unit volume.
  • the ratio of the volume molarity C (Cl 2 ) (mol / L) of the two gases has the following inequality: 1% ⁇ C (Cl 2 ) / C (O 2 + Cl 2 ) ⁇ 100 (%) ⁇ 20% It is characterized by satisfying.
  • the etching gas is a mixed gas of oxygen and Cl 2 , and Cl with respect to the volume molar concentration C (O 2 + Cl 2 ) (mol / L) of the mixed gas in a unit volume.
  • the ratio of the volume molarity C (Cl 2 ) (mol / L) of the two gases has the following inequality: 9% ⁇ C (Cl 2 ) / C (O 2 + Cl 2 ) ⁇ 100 (%) ⁇ 11% It is characterized by satisfying.
  • the semiconductor device includes a pair of semiconductor fins erected from a substrate, and the semiconductor semiconductor is located in a region between adjacent semiconductor fins up to a position higher than any of the top surfaces of the semiconductor fins.
  • a semiconductor device includes a first fin group including a pair of semiconductor fins, and a second fin group including a pair of semiconductor fins spaced apart from the first fin group, and the first fin group.
  • a first semiconductor fin constituting a fin-type P-type field effect transistor including a source region, a gate region, and a drain region
  • the second fin group includes a fin-type including a source region, a gate region, and a drain region.
  • a fixed potential line can be easily formed, and a semiconductor device with a small cell height can be manufactured. Therefore, power consumption can be reduced and an operation speed can be increased.
  • a fixed potential line can be easily formed, and a semiconductor device with a small cell height can be manufactured, so that power consumption can be reduced and an operation speed can be increased.
  • FIG. 1 is a circuit diagram of a logic standard cell.
  • FIG. 2 is a truth table of logic standard cells.
  • FIG. 3 is a circuit showing connection of FET groups in the logic standard cell.
  • FIG. 4 is a perspective view of the FET group in the logic standard cell.
  • 5A and 5B are a longitudinal sectional view in the vicinity of the gate of the FET and a longitudinal sectional view in the vicinity of the source / drain of the FET.
  • FIG. 6 is a longitudinal sectional view of an intermediate body of the logic standard cell.
  • FIG. 7 is a plan view of an intermediate body of the logic standard cell.
  • FIG. 8 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 9 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 10 is a longitudinal sectional view of an intermediate body of the logic standard cell.
  • FIG. 11 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 12 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 13 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 14 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 15 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 16 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 17 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 18 is a longitudinal sectional view of an intermediate body of the logic standard cell.
  • FIG. 19 is a plan view of an intermediate of the logic standard cell.
  • FIG. 20 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 21 is a longitudinal sectional view of an intermediate body of the logic standard cell.
  • FIG. 22 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 23 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 24 is a plan view of an intermediate body of the logic standard cell.
  • FIG. 25 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 26 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 27 is a longitudinal sectional view of an intermediate body of the logic standard cell.
  • FIG. 28 is a longitudinal sectional view of an intermediate body of the logic standard cell.
  • FIG. 29 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 30 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 31 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 32 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 33 is a plan view of an intermediate of the logic standard cell.
  • FIG. 34 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 35 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 36 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 37 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 38 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • FIG. 39 is a plan view of an intermediate of the logic standard cell.
  • FIG. 40 is a block diagram of the etching apparatus.
  • Fin-FET fin-type field effect transistor
  • Fig. 1 is a circuit diagram of a logic standard cell.
  • This logic circuit is a NAND circuit with 3 inputs and 1 output.
  • the input signals Vin1, Vin2, and Vin3 are voltage signals, and the output signal Vout is output from the output terminal Tout according to the input values to the input terminals Tin1, Tin2, and Tin3 of the NAND circuit.
  • the NAND circuit includes a first P-type FET (P-FET 1), a second P-type FET (P-FET 2), a third P-type FET (P-FET 3), and a first N-type FET. (N-FET 1), a second N-type FET (N-FET 2), and a third N-type FET (N-FET 3).
  • P-FET 1 P-type FET
  • N-FET 2 a second N-type FET
  • N-FET 3 a third N-type FET
  • an enhancement type FET is shown in the figure, it may be a depletion type FET.
  • the structure of the FET in the figure is a MOS type,
  • the source S of the P-type FET is electrically connected to the power supply potential V +
  • the drain D is electrically connected to the output terminal Tout.
  • the P-type FET is connected in parallel between terminals (power rails) that supply the power supply potential V + and the ground potential GND.
  • Input terminals Tin1, Tin2, and Tin3 are connected to the gates of the P-type FETs, respectively, and input signals Vin1, Vin2, and Vin3 are applied thereto.
  • the three N-type FETs are connected in series between the output terminal Tout and the ground potential GND.
  • the source S of the N-type FET located at the bottom in the figure is electrically connected to the ground potential GND.
  • Input terminals Tin1, Tin2, and Tin3 are connected to the gates of the N-type FETs, respectively, and input signals Vin1, Vin2, and Vin3 are applied thereto.
  • This NAND circuit is composed of a complementary logic circuit (CMOS), and power consumption is suppressed as a characteristic of the CMOS logic circuit.
  • CMOS complementary logic circuit
  • Fig. 2 is a truth table of logic standard cells.
  • the level of the output signal Vout is determined according to the voltage level (H: high level, L: low level) of the input signals Vin1, Vin2, and Vin3. Since it is a NAND circuit, the output signal Vout is at a low level when all three input signals are at a high level, and the output signal Vout is at a high level in other combinations.
  • FIG. 3 is a circuit showing the connection of FET groups in the logic standard cell.
  • Each FET has a source S, a gate G, and a drain D, and a semiconductor region corresponding to each element (electrode) is a source region, a gate region, and a drain region.
  • the source electrode is in contact with the source region
  • the gate electrode is provided on the gate region via an insulating film
  • the drain electrode is in contact with the drain region.
  • the electrical connection is as shown in FIG. 1.
  • the first switch Q1 is interposed between the P-FET 1 and the P-FET 2, and the P-FET 2 Since the second switch Q2 is interposed between the P-FET 3 and a high level is given to these switches (P channel gate), these switches are turned OFF, and between the transistors in the fin for the P-type FET Is prohibited.
  • an additional switch QP P channel gate
  • this drain D is connected to another potential (eg, reset potential) as necessary.
  • a third switch Q3 is interposed between N-FET1 and N-FET2, and a fourth switch Q4 is interposed between N-FET2 and N-FET3, and these switches (N-channel gates) are connected.
  • these switches are turned OFF, and conduction between transistors in the fin for the N-type FET is permitted.
  • an additional switch QN N channel gate
  • this source S is connected to another potential (eg, reset potential) as necessary.
  • FIG. 4 is a perspective view of the FET group in the logic standard cell.
  • Each FET is opposed to a pair of dummy FETs. That is, for the P-FET1, P-FET2, and P-FET3, the first P-type dummy FET (DP-FET1), the second P-type dummy FET (DP-FET2), Third P-type dummy FETs (DP-FETs 3) face each other. Between these P-type FET pairs, a fixed potential line (power supply potential V + ) is arranged.
  • V + power supply potential
  • N-FET1 N-type dummy FET
  • DN-FET2 N-type dummy FET
  • DN-FET3 a third N-type dummy FETs
  • GND ground potential
  • an XYZ three-dimensional orthogonal coordinate system is set, the thickness direction of each layer in the laminated structure is set as the Z-axis direction, and two axes orthogonal to the Z-axis are set as the X-axis and the Y-axis.
  • the height direction of each fin is the positive direction of the Z axis
  • the longitudinal direction is the positive direction of the Y axis
  • the width direction is the X axis direction.
  • the cell height CHT is a distance between the center lines of the fixed potential lines (V + / GND) that are adjacently spaced along the X-axis direction. In this example, the cell height CHT is assumed to be 120 nm or less.
  • FIG. 5- (A) is a longitudinal sectional view near the gate of the FET (Y1 section), and FIG. 5- (B) (Y2 section) near the source / drain of the FET.
  • FIG. 5A In the vicinity of the gate in FIG. 5A, a plurality of semiconductor fins 2 are provided on the semiconductor substrate 1, and conductive materials (7, 8) are embedded between these semiconductor fins 2.
  • FIG. The conductive material 8 constitutes a fixed potential line and is supplied with a power supply potential or a ground potential.
  • a gate electrode 21 is provided on the semiconductor fin 2 via a gate insulating film 18.
  • An oxide film 27 and an interlayer insulating film 29 are deposited on the gate electrode 21, and the gate electrode 21 is interposed via a contact electrode 28. And connected to a specific signal wiring 30.
  • a plurality of semiconductor fins 2 are provided on the semiconductor substrate 1, and these semiconductor fins 2 are formed of P-type conductive regions 14 and N-type conductive regions 14.
  • a conductive region 15 is formed, one conductive region 14 (source region) is electrically connected to the conductive material 8 via the electrode material ELEC1 (Ru), and the other conductive region 15 (drain region) is connected to another location.
  • the electrode material ELEC1 is electrically connected, and an oxide film 27 and an interlayer insulating film 29 are deposited thereon, and the drain region is connected to another signal wiring 30.
  • FIG. 6 is a longitudinal sectional view of the intermediate body of the logic standard cell
  • FIG. 7 is a plan view of the intermediate body of the logic standard cell.
  • FIG. 6 is a vertical cross section along the dotted line Y1 in FIG. 7, but the mask MSK1 shown in FIG. 6 is omitted.
  • a semiconductor substrate 1 made of Si is prepared, a striped mask MSK1 is patterned on the surface of the semiconductor substrate 1, and the semiconductor substrate 1 is etched through the mask MSK1.
  • photolithography using photoresist coating / development is used.
  • the etching method of the semiconductor substrate (Si) is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.
  • CCP capacitively coupled plasma
  • Etching gas CF 4 ⁇ Etching temperature: 20 ⁇ 100 °C ⁇ Etching time: 10-60sec
  • etching gas O 2 , N 2, or H 2 can be used instead of CF 4 , and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings is used.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • the semiconductor fins 2 remain directly under the mask, and a plurality of semiconductor fins 2 are erected from above the semiconductor substrate 1.
  • the longitudinal direction of the stripe-shaped mask is the Y-axis direction
  • the distance between the centers of adjacent semiconductor fins 2 in the X-axis direction is 24 nm
  • the height of the semiconductor fins 2 in the Z-axis direction is 120 nm.
  • the width of the top surface of the semiconductor fin 2 in the X-axis direction is 8 nm
  • the width of the bottom surface between the semiconductor fins 2 is 12 nm.
  • the upper part (part with a height of 50 nm from the top) of the semiconductor fin 2 constitutes a transistor, and the lower part (part with a thickness of 70 nm from the bottom) functions as a side wall adjacent to the fixed potential line.
  • the depth of the semiconductor fin 2 in FIG. 8 in the Y-axis direction is set to 38 nm, for example.
  • FIG. 8 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • the upper mask is removed with an organic solvent such as acetone, and then the semiconductor fins 2 are thinned out. That is, in FIG. 6, the second, fourth, fifth, and seventh semiconductor fins 2 from the left are removed. As a result, the first, third, sixth, and eighth semiconductor fins 2 from the left remain.
  • the removal of the semiconductor fin 2 in FIG. 8 is performed as follows. First, a photoresist is applied on a semiconductor substrate, and only the first, third, sixth, and eighth semiconductor fins 2 from the left are protected, and a mask having an opening in the remaining region is used to pattern the photoresist by photolithography. The semiconductor fin in the opening of the mask is etched. A dry etching method can be used for the etching.
  • the etching method of the semiconductor fin (Si) is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.
  • CCP capacitively coupled plasma
  • Etching gas CF 4 ⁇ Etching temperature: 20 ⁇ 100 °C ⁇ Etching time: 10-60sec
  • etching gas O 2, N 2 or H 2 can be used instead of CF 4 , and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings is used.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • a wet etching method can also be used as a method for etching semiconductor fins (Si).
  • Si semiconductor fins
  • HNO 3 + HF and KOH + IPA (isopropyl alcohol) + H 2 O 2 are known for adjusting the etching rate.
  • the etching temperature is set to 20 to 100 ° C. and the etching time is set to 10 to 60 sec. can do.
  • FIG. 9 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • the semiconductor fin 2 is heated in an oxygen atmosphere to form an oxide film (SiO 2 ) on the entire surface of the substrate.
  • the temperature for forming the thermal oxide film is set to 400 ° C. to 1000 ° C., and the thickness of the oxide film 4 covering the semiconductor fin 2 is set to 3 to 6 nm.
  • a protective film 5 (protective material) is formed on the entire surface of the substrate.
  • the material of the protective film 5 is amorphous carbon, and the formation method is CVD / PVD or spin coating.
  • the protective film 5 is filled between the adjacent semiconductor fins 2, and the thickness of the protective film 5 is set so as to cover the top surface of the semiconductor fin 2 and the surface thereof is positioned higher than this.
  • FIG. 10 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • the protection film 5 is removed by etching through a mask. That is, a photoresist is applied on the protective film 5, the first and second regions are opened, and a mask for protecting the remaining regions is formed by patterning the photoresist by photolithography,
  • the protective film 5 is etched.
  • the etching method of the protective film (amorphous carbon) is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.
  • Etching gas CO ⁇ Etching temperature: 100-350 °C ⁇ Etching time: 20-60sec
  • N 2 or H 2 can be used instead of CO, and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings can also be used.
  • a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings can also be used.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • the oxide film 4 located at the bottom between the semiconductor fins 2 is exposed.
  • the oxide film or nitride film in the description is an insulating film.
  • FIG. 11 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • the liner film 7 is formed on the substrate surface.
  • the liner film 7 covers the oxide film 4 and the protective film 5 located on the side surface of the semiconductor fin 2.
  • the formation method of the liner film 7 is a well-known atomic layer deposition (ALD) method, and specific formation conditions are as follows.
  • -Material of liner film 7 TiN -Formation temperature: 200-600 ° C ⁇ Thickness: 0.5nm to 2.0nm
  • Source gas TiCl 4 + N 2 / N 2 (Alternate supply on substrate surface)
  • TaN can be used instead of TiN, and a chemical vapor deposition (CVD) method can be used instead of the ALD method.
  • CVD chemical vapor deposition
  • a conductive material 8 for forming the above-described fixed potential line is formed on the substrate.
  • Ruthenium (Ru) can be used as the conductive material.
  • Ru is a platinum group element and has a characteristic of dissolving in acid.
  • tungsten (W) or the like can be used as the conductive material 8. However, when Ru is used, it has an advantage of low resistance over these metals.
  • the conductive material 8 is located not only in the region between the semiconductor fins 2 but also above the uppermost surface of the protective film 5.
  • the formation method of the conductive material 8 is a CVD method, and specific formation conditions are as follows.
  • -Material of conductive material 8 Ru -Formation temperature: 200-500 ° C ⁇ Maximum thickness in the Z-axis direction: 30 to 60 nm
  • Source gas Ruthenium carbonyl (Ru 3 (CO) 12 ) ⁇ Carrier gas: Ar
  • the conductive material 8 (Ru) can also be formed by a physical vapor deposition (PVD) method such as a sputtering method.
  • PVD physical vapor deposition
  • W can be used for the conductive material 8, but in this case, the conductive material 8 (W) can be formed by a CVD method or a sputtering method.
  • FIG. 12 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • the conductive material 8 is etched back again to remove a part.
  • the thickness (height) of the conductive material 8 is reduced to 50 nm, and the surface thereof is located below the top surface of the semiconductor fin 2.
  • the liner film 7 (TiN) is an etching barrier film for the etching gas or etching liquid for the conductive material 8.
  • the etching back method of the conductive material 8 is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.
  • CCP capacitively coupled plasma
  • Etching gas CF 4 ⁇ Etching temperature: 20 ⁇ 100 °C ⁇ Etching time: 30sec ⁇ 240sec
  • etch back gas a mixed gas of O 2 and Cl 2 can be used instead of CF 4 .
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • a wet etching method can be used as a method for etching the conductive material 8 (Ru).
  • the liner film 7 (TiN) is etched by wet etching.
  • etching solution for Ru H 2 O 2 , FPM (hydrofluoric acid hydrogen peroxide mixed solution) and the like are known.
  • the etching temperature is set to 20 to 100 ° C.
  • the etching time is set to 30 to 240 sec. Can do.
  • TiN etching solution a mixed solution of H 2 O 2 and ammonium hydroxide is also known.
  • the liner film 7 is etched to the same height as the conductive material 8.
  • FIG. 13 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • a cap film 101 is formed on the exposed surface of the conductive material 8.
  • the material of the cap film 101 is an antioxidant film of the conductive material 8, and is also a barrier film for protecting the conductive material 8 from etching. Since the cap film 101 is not etched when the material to be etched formed on the cap film 101 is etched, the cap film 101 also functions as an etching stop film.
  • the material of the cap film 101 is Si 3 N 4 , but TiN, TaN, AlOx (such as Al 2 O 3 ), or the like can be used instead.
  • FIG. 14 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • the protective film 5 is removed. Since the protective film 5 is made of amorphous carbon, ashing is used to remove the amorphous carbon. Ashing is a technique for removing a carbon-based compound such as a photoresist. For example, an oxygen (O 2 ) plasma is generated by a plasma generator, and the amorphous carbon is irradiated with this oxygen plasma. Remove. In addition, photoexcited ashing that irradiates ultraviolet rays in an atmosphere of ozone (O 3 ) gas is also known.
  • O 2 oxygen
  • O 3 ozone
  • FIG. 15 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • an oxide film 9 (SiO 2 ) is formed on the entire surface of the substrate.
  • the thickness of the oxide film 9 is higher than the height of the semiconductor fin 2.
  • a method for forming the oxide film 9 an ALD method, a CVD method, a coating method, or the like is applicable.
  • a batch processing apparatus or a single-wafer film forming apparatus can be employed as a mode of transporting and processing the substrate to the processing apparatus, and spin coating can be employed as the film forming apparatus when a coating method is used. it can.
  • the specific formation condition of the silicon oxide film 9 is a CVD method as follows.
  • Deposit material TEOS (tetraethyl orthosilicate), O 2 ⁇
  • Deposition time 10sec ⁇ 1800sec -Formation temperature: 400-900 ° C ⁇
  • the formation temperature is 150 to 400 ° C.
  • FIG. 16 is a longitudinal sectional view of an intermediate of the logic standard cell.
  • the entire surface of the substrate on which the oxide film 9 is formed is etched again, and the oxide film 4 provided on the semiconductor fin 2 is removed together with the oxide film 9. As a result, the semiconductor portion of the semiconductor fin 2 is exposed, and part of the oxide film 4 and the oxide film 9 remains.
  • the etching method of the oxide film 4 and the oxide film 9 is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.
  • Etching gas C 4 F 8 ⁇ Etching temperature: 20 ⁇ 100 °C ⁇ Etching time: 5-60sec
  • etching gas CF 2 , CF 3 , C 2 F 2 , C 2 F 4, C 2 F 6, Ar, CHF 3, O 2, or O 3 may be used instead of C 4 F 8. It is also possible to use a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings.
  • an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • a gate oxide film 10 is formed so as to cover the exposed surface of the semiconductor fin 2.
  • the gate oxide film 10 is composed of two layers of oxide films.
  • the exposed portion of the semiconductor fin 2 is heated in an oxygen atmosphere to form a thermal oxide film having a thickness of 1.4 nm on the surface.
  • a CVD oxide film having a thickness of 2 nm is formed so as to cover the thermal oxide film. Therefore, oxide film 10 having a thickness of 3.4 nm in total is formed.
  • the thickness of the oxidized semiconductor fin 2 in the X-axis direction is 6.5 nm at the position of the top surface and 8.5 nm at the position of the upper end portion of the oxide film 4.
  • FIG. 18 is a longitudinal sectional view of an intermediate body of the logic standard cell (near the gate), and FIG. 19 is a plan view of the intermediate body of the logic standard cell.
  • FIG. 18 is a longitudinal section taken along the dotted line Y1 in FIG.
  • a dummy gate electrode 11 is formed on the semiconductor fin 2 via the oxide film 10.
  • the dummy gate electrode 11 is provided only in a region that functions as a gate region of a transistor or a switch.
  • the method for forming the dummy gate electrode 11 is as follows.
  • a conductive material (polysilicon) for a dummy gate is formed on a substrate by a CVD method using SiH 4 -based source gas.
  • an inorganic insulator mask 12 is formed on the conductive material layer, in which a stripe-shaped region is protected along the X-axis direction and the remainder is opened.
  • the inorganic insulator mask 12 is made of an inorganic insulator such as a silicon nitride film.
  • an inorganic insulating layer Si 3 N 4
  • a conductive material polysilicon
  • a photoresist is applied on the inorganic insulating layer.
  • an organic resin mask having the same pattern as that of the inorganic insulator mask 12 is formed.
  • the organic resin mask is formed by patterning a photoresist by photolithography.
  • the inorganic insulating mask 12 is formed by etching the inorganic insulating layer (Si 3 N 4 ) in the opening using the organic resin mask. Sputtering can also be employed as a method for depositing the inorganic insulating layer.
  • the etching method of the inorganic insulating layer (Si 3 N 4 ) is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.
  • CCP capacitively coupled plasma
  • Etching gas CF 4 and O 2 ⁇ Etching temperature: 20 ⁇ 100 °C ⁇ Etching time: 5 to 120 sec
  • etching gas As the etching gas, SF 6 , SF 5 , SF 4 , SF 3 , SF 2 , Ar, or N 2 can be used instead of CF 4 and O 2. From the etching gas group consisting of these etchings A mixed gas containing two or more selected gases can also be used.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • the conductive material (polysilicon) located in the opening of the inorganic insulator mask 12 is etched, so that the conductive material remains only on the gate region, and the dummy gate electrode 11 is formed. It is formed.
  • the etching method of the conductive material is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.
  • Etching gas Cl 2 and HBr ⁇ Etching temperature: 20 ⁇ 120 °C ⁇ Etching time: 5 to 300 sec
  • etching gas Cl 2 or SF 6 can be used instead of Cl 2 and HBr, and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings is used. You can also.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • FIG. 20 is a vertical cross-sectional view (Y2 cross section) of the intermediate body (in the vicinity of the source / drain) of the logic standard cell.
  • the source / drain of the transistor is located at the position of the dotted line Y2.
  • the oxide film 10 is formed on the upper portion of the semiconductor fin 2. However, in forming the source region and the drain region, the oxide film 10 shown in FIG. 18 is removed. The oxide film 10 can be removed in the polysilicon etching step when forming the dummy gate electrode 11 shown in FIG.
  • a sidewall 13 made of SiCN is formed on the surface so as to cover the semiconductor fin 2.
  • the side wall 13 is formed using a PE-CVD (Plasma Enhanced-Chemical Vapor Deposition) method, specifically as follows. Reaction gas: (SiH 4 , CH 4 , H 2 , N 2 ) or (N 2 , (CH 3 ) 3 Si—NH—Si (CH 3 ) 3 (hexamethyldisilazane (HMDS))) -Formation temperature: 200-600 ° C ⁇ Formation time: 10 to 300 sec
  • the initial sidewall 13 covers the entire upper portion of the semiconductor fin 2 and covers the side surface and top surface of the semiconductor fin 2 and the bottom portion between the fins, but the substrate surface is sputter etched with a rare gas such as argon.
  • the upper side wall of the semiconductor fin 2 and the bottom film between the fins are removed, the upper side is opened, and the side wall 13 is formed.
  • a protective film PN is formed on the region where the N-FET is to be formed (the region where the semiconductor fin 2 is formed on the right side of the drawing).
  • the material and forming method of the protective film PN are as follows. ⁇ Material: Resist ⁇ Formation method: Spin coating
  • the sidewall 13 in the region where the P-FET is to be formed (the region where the semiconductor fin 2 is formed on the left side of the drawing) is etched.
  • the side wall 13 on the left side of the drawing has a desired height.
  • the side wall 13 may be formed by crystal growth of the constituent material.
  • the side wall 13 (SiCN) etching method is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.
  • CCP capacitively coupled plasma
  • Etching gas CF 4 and H 2 O ⁇
  • Etching temperature 20 ⁇ 100 °C ⁇
  • Etching time 5 to 300 sec
  • COF 2 , OF 2 , O 2 F 2 can be used instead of CF 4 and H 2 O, and two or more gases selected from an etching gas group consisting of these etchings can be used.
  • a mixed gas containing can also be used.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • the semiconductor fin 2 in the region where the P-FET is to be formed is etched to a position near the upper end of the side wall 13.
  • the etching method of the semiconductor fin 2 (Si) is dry etching, and the specific conditions of etching at this time are as follows.
  • Etching gas CF 4 ⁇ Etching temperature: 20 ⁇ 100 °C ⁇ Etching time: 10-60sec
  • etching gas in place of CF 4, O 2, N 2 or H 2 can be used, a mixed gas containing two or more gases selected from the etching gas group consisting of etching You can also.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • the conductive region 14 made of SiGe containing boron at a high concentration is epitaxially grown on the exposed surface of the semiconductor fin 2 for P-FET whose upper portion is etched.
  • the conductive region 14 (SiGe) functions as a conductive source region or drain region in the P-FET, but a CVD (chemical vapor deposition) method is adopted as a crystal growth method.
  • CVD chemical vapor deposition
  • Source gas SiH 4 , GeH 4 -Impurity gas: B (boron) -containing gas-Growth temperature: 550-700 ° C ⁇ Growth time: 15-60 min
  • Boron (B) is a P-type (first conductivity type) impurity in Si, and phosphorus (P) or arsenic (As) is an N-type (second conductivity type) impurity.
  • Si 2 H 6 can be used instead of SiH 4 as a source gas.
  • the conductive region 15 on the N-FET side is formed.
  • FIG. 21 is a vertical cross-sectional view (Y2 cross section) of the intermediate body of the logic standard cell (in the vicinity of the source / drain).
  • the protective film PN on the region where the N-FET is to be formed (the region where the semiconductor fin 2 is formed on the right side of the drawing) is removed by ashing, and the region where the P-FET is to be formed (the semiconductor fin 2 on the left side of the drawing is formed)
  • the protective film PP on the region) is formed.
  • the material and forming method of the protective film PP are the same as the material and forming method of the protective film PN.
  • the sidewall 13 in the region where the N-FET is to be formed (the region where the semiconductor fin 2 is formed on the right side of the drawing) is etched.
  • the side wall 13 on the right side of the drawing has a desired height.
  • the side wall 13 may be formed by crystal growth of the constituent material.
  • the etching method for the right side wall 13 (SiCN) is the same as the etching method for the left side wall 13 described above.
  • the semiconductor fin 2 in the region where the N-FET is to be formed is etched to a position near the upper end of the side wall 13.
  • the etching method for the right semiconductor fin 2 (Si) at this time is the same as the etching method for the left semiconductor fin 2 described above.
  • a conductive region 15 made of Si containing nitrogen, phosphorus, arsenic or the like at a high concentration is epitaxially grown on the exposed surface of the semiconductor fin 2 for N-FET whose upper portion is etched. Si grows epitaxially with aligned crystal axes.
  • the conductive region 15 functions as a conductive source region or drain region in the N-FET, but a CVD (chemical vapor deposition) method is adopted as a crystal growth method.
  • the specific conditions for crystal growth at this time are as follows.
  • the impurity gas in addition to N 2 , a gas containing P, As, Sb, or the like that becomes N-type impurities can be used.
  • a P-type impurity such as B or Al is used.
  • the protective film PP is removed by ashing. Further, as shown in FIG. 22, a nitride film (Si 3 N 4 ) 161 and an oxide film 16 (SiO 2 ) are sequentially formed so as to cover the entire surface of the substrate.
  • a method for forming the nitride film 161 for example, the same CVD method as that for the insulator 17 can be used.
  • FIG. 22 is a vertical cross-sectional view (Y2 cross section) of the intermediate body (in the vicinity of the source / drain) of the logic standard cell.
  • the surface position of the oxide film 16 is higher than the height of the conductive region 14 and the conductive region 15.
  • the formation method of the oxide film 16 is film formation or coating, and CVD / PVD or spin coating can be adopted as the forming apparatus.
  • a specific method for forming the oxide film 16 is a CVD method as follows.
  • Raw materials TEOS (tetraethyl orthosilicate), O 2 -Formation temperature: 400-900 ° C ⁇ Formation time: 5-12hours
  • the oxide film 16 can also be formed by using the PVD method or spin coating.
  • the formation temperature of the CVD method can be set to 300 to 1200 ° C., and O 3 can be used instead of O 2 .
  • Perhydropolysilazane can be used in a coating method by spin coating. After the oxide film 16 is formed, the surface of the oxide film 16 is planarized by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • FIG. 23 is a longitudinal sectional view (Y1 cross section) of the intermediate body of the logic standard cell (near the gate), and FIG. 24 is a plan view of the intermediate body of the logic standard cell.
  • the gate of the transistor is located at the position of the dotted line Y1.
  • the inorganic insulator mask 12 (protective film) in FIG. 18 is also removed, and the surface of the dummy gate electrode 11 is flattened to expose the surface.
  • a contact hole is formed in a region of the dummy gate electrode 11 immediately above the conductive material 8, and an insulating film 17 (Si 3 N 4 ) is formed in the contact hole.
  • the contact hole is formed by forming a mask having this portion opened and etching the dummy gate electrode 11.
  • the etching method of the dummy gate electrode 11 is dry etching, and the specific conditions of etching at this time are as follows.
  • Etching gas CF 4 ⁇ Etching temperature: 20 ⁇ 120 °C ⁇ Etching time: 5 to 300 sec
  • etching gas O 2, N 2 or H 2 can be used instead of CF 4 , and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings is used.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • the insulating film 17 (Si 3 N 4 ) is formed by vapor phase growth, and a CVD apparatus or a PVD apparatus can be adopted as a forming apparatus.
  • the specific formation conditions of the insulating film 17 are as follows in the case of the CVD method. Raw materials: SiH 2 Cl 2 and NH 3 -Formation temperature: 300-1200 ° C -Formation time: 10 sec to 1800 sec
  • the insulating film 17 is CMPed to embed the insulating film 17 (insulator) in the contact hole. As shown in FIG. 24, the insulating film 17 is buried at 10 locations with respect to the five dummy gate electrodes 11. The insulator 17 is used to separate functions between various elements.
  • FIG. 25 is a longitudinal sectional view (Y1 cross section) of the intermediate body (near the gate) of the logic standard cell.
  • the dummy gate electrode 11 shown in FIG. 23 is removed.
  • the dummy gate electrode 11 is made of polysilicon, and the etching method of the dummy gate electrode 11 at this time is dry etching, and the specific conditions of the etching at this time are as follows.
  • Etching gas CF 4 ⁇ Etching temperature: 20 ⁇ 120 °C ⁇ Etching time: 5 to 300 sec
  • etching gas O 2 or H 2 can be used instead of CF 4 , and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings can also be used.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • the thin oxide film 10 (SiO 2 ) shown in FIG. 23 is removed.
  • the etching method of the oxide film 10 is dry etching, and the specific conditions of the etching at this time are as follows.
  • Etching gas C 4 F 8 ⁇ Etching temperature: 20 ⁇ 100 °C ⁇ Etching time: 5 to 100 sec
  • etching gas CF 2 , CF 3 , C 2 F 2 , C 2 F 4, C 2 F 6, Ar, CHF 3, O 2, or O 3 may be used instead of C 4 F 8. It is also possible to use a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings.
  • an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted.
  • FIG. 26 is a longitudinal sectional view (Y1 cross section) of the intermediate body (near the gate) of the logic standard cell.
  • the gate insulating film 18 is a thermal oxide film of Si, and is formed by heating in an oxygen atmosphere at 800 ° C. to 1100 ° C.
  • the gate insulating film 18 can also be formed at temperatures of about 400 to 900 ° C. (CVD) and 150 to 400 ° C. (ALD).
  • a conductive material 19 made of metal is deposited and formed on the entire surface of the substrate.
  • the deposition method is a sputtering method in which the target metal is decomposed or reacted, and the target metal (specifically, W (tungsten)) is sputtered with plasma-generated argon by a high-frequency plasma sputtering apparatus, and this metal is allowed to reach room temperature. Deposited on the substrate surface.
  • the conductive material 19 becomes the gate electrode of the FET and switch in the P-FET formation region.
  • FIG. 27 is a longitudinal sectional view (Y1 cross section) of the intermediate body (near the gate) of the logic standard cell.
  • the conductive material 19 located on the N-FET formation scheduled region (right region) is selectively removed by etching.
  • a photoresist is applied on the region where the N-FET is to be formed, and this is exposed and developed to form a mask in which only the region where the N-FET is to be formed is opened.
  • the etching is stopped.
  • the etching method of the conductive material 19 (W) is dry etching, and the specific conditions of the etching at this time are as follows. Etching gas: CF 4 , O 2 ⁇ Etching temperature: 100-350 °C ⁇ Etching time: 20-60sec
  • etching gas a mixed gas of O 2 gas, CF 4 gas and HBr can be used instead of CF 4 and O 2 , and two or more kinds selected from an etching gas group consisting of these etchings can be used.
  • a mixed gas containing a gas can also be used.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • the deposition method is a sputtering method in which a target metal is decomposed or reacted, and a target metal (W) is sputtered with argon converted into plasma by a high-frequency plasma sputtering apparatus, and this metal is deposited on the substrate surface at room temperature.
  • the conductive material 20 becomes the gate electrode of the FET and switch in the N-FET formation region. Thereafter, the surface of the conductive material 20 is planarized by CMP.
  • the P-side gate electrode (conductive material 19) and the N-side gate electrode (conductive material 20) are in physical contact and are electrically connected to function as an integrated gate electrode 21.
  • the conductive material 19 and the conductive material 20 may be changed to different metals when the work function is controlled.
  • FIG. 28 is a longitudinal sectional view (Y1 cross section) of the intermediate body (near the gate) of the logic standard cell.
  • a protective nitride film 22 (SiNx) is formed on the gate electrode 21.
  • the nitride film 22 is formed on the gate electrode 21 by a CVD method using SiH 2 Cl 2 and NH 3 as source gases.
  • the forming temperature is set to room temperature, and the thickness is set to 20 nm, for example.
  • the oxide film 16 on the source region (P-type conductive region 14) and the drain region (N-type conductive region 15) is anisotropically etched as shown. ,Remove.
  • a mask pattern is formed on the oxide film 16 before etching, and only the portions adjacent to the source region and the drain region in the X-axis direction remain.
  • the etching method of the oxide film 16 is dry etching, and the specific conditions of the etching at this time are as follows.
  • Etching gas C 4 F 8 ⁇ Etching temperature: 20 ⁇ 100 °C ⁇ Etching time: 5 to 100 sec
  • etching gas CF 2 , CF 3 , C 2 F 2 , C 2 F 4, C 2 F 6, Ar, CHF 3, O 2, or O 3 may be used instead of C 4 F 8. It is also possible to use a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings.
  • an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted.
  • a protective film CA as an insulating layer is formed on the entire surface of the substrate.
  • the material of the protective film CA is amorphous carbon, and the formation method is CVD / PECVD or spin coating.
  • the protective film CA is filled between the adjacent semiconductor fins 2.
  • the thickness of the protective film CA is higher than the top surface of the semiconductor fin 2, and the surface of the protective film CA is higher than the source region 14 and the drain region 15. Set to be located.
  • a hard mask HM is formed on the protective film CA.
  • a CVD method at room temperature, a PVD method, or an ALD method can be used.
  • a material of the hard mask HM a nitride film, a titanium-based film, a silicon-based film, a silicon oxide film, or the like is used. Can do.
  • a silicon nitride film Si 3 N 4 is used.
  • the hard mask HM is patterned by etching using photolithography, and focusing on one Y2 cross section, the central region in the X direction and the fixing of the N-FET A pattern is formed in which the region immediately above the potential line 8 is opened (see FIG. 33).
  • the protective film CA in the region immediately below the opening is removed.
  • dry etching methods such as CCP, ECR, HWP, ICP, SWP can be used.
  • an oxide film OX SiO 2
  • CMP CMP
  • the protective film CA is removed, and the first contact hole CH10 in which the fixed potential line 8, the nitride film 161 on the surface of the source region 14 and the drain region 15 are exposed, Two contact holes CH20 and a third contact hole CH30 are formed simultaneously.
  • a removing method dry etching is used.
  • the first contact hole CH10 is formed in a region where the protective film CA (insulating layer) is present in the oxide film OX (insulating layer), and extends toward the source region 14 and the fixed potential line 8 to form the second contact.
  • the hole CH20 and the third contact hole CH30 are formed in a region where the protective film CA (insulating layer) exists in the oxide film OX (insulating layer), and extend to the two drain regions 15 respectively.
  • the shape of the contact hole reaching the drain region is the same as the shape of the contact hole reaching the drain region of the N-FET shown in the Y2 cross section.
  • the shape of the contact hole reaching the source region is the same as that of the contact hole reaching the source region of the P-FET in the N-FET 3 (see FIG. 3), and in other N-FETs
  • the shape of the contact hole reaching the drain region of the N-FET in the Y2 cross section is the same (see FIG. 33).
  • the plurality of contact holes include the first contact hole CH10 and the second and third contact holes, and the first contact hole CH10 is a source region. 14 and the fixed potential line 8, and the second contact hole and the third contact hole extend toward two drain regions in the same XZ section of the P-FET, respectively, and the first contact hole The second contact hole and the third contact hole are opened simultaneously.
  • the plurality of contact holes are the first contact hole extending toward the source region of the N-FET 3 (see FIG. 3), the second contact hole CH20 and the third contact hole in the Y2 cross section being CH30.
  • the second contact hole CH20 and the third contact hole CH30 extend toward the drain regions 15 located at two positions on the Y2 cross section, and the first contact hole of the N-FET 3
  • the first contact hole, the second contact hole, and the third contact hole are opened simultaneously, extending toward the source region and the fixed potential line 8 (GND).
  • the first contact hole only needs to extend toward the source region, and does not need to extend to the fixed potential line 8.
  • the etching method of the hard mask HM and the protective film CA at this time is reactive ion etching (RIE: reactive ion etching) of dry etching, and the hard mask HM (Si 3 N 4 ) and the protective film CA (amorphous carbon). ) Can be continuously processed by changing the gas and conditions for supplying the gas. It is also possible to process both etchings continuously in the same etching vessel.
  • RIE reactive ion etching
  • CCP capacitively coupled plasma
  • etching gas O 2 , O 3 , SF 6 , SF 5 , SF 4 , SF 3 , SF 2 , Ar, or N 2 can be used instead of CF 4.
  • Etching made of these etchings A mixed gas containing two or more gases selected from a gas group can also be used.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • N 2 or H 2 can be used instead of CO, and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings can also be used.
  • this etching is performed by using electron cyclotron resonance plasma (ECR plasma) type, helicon wave plasma (HWP) type, inductively coupled plasma (ICP) type, and surface wave plasma. (SWP) type can be adopted, and continuous etching is possible only by changing the etching gas and conditions in the same chamber as the etching chamber (container) of the hard mask HM. Productivity is improved if processing is possible in the same chamber.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • the processing time becomes long, it is possible to perform processing in different chambers connected in a vacuum environment in consideration of throughput.
  • the protective film CA is etched by RIE, the side walls below the source region and the drain region become the oxide film 16. In this ALE, the etching selectivity between the protective film CA and the oxide film 16 is sufficient. The protective film CA is selectively removed.
  • a part of the nitride film 161 as an insulating layer formed in advance is removed by etching to expose the source region 14 and the drain region 15, and in the Y2 cross section, P
  • the portion of the nitride film 101 on the conductive material 8 that is a fixed potential line on the FET side is also removed simultaneously with the nitride film 161.
  • the etching method of the nitride film 161 and the nitride film 101 is ALE (Atomic Layer Etching), and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.
  • the surface of the conductive material 8 as the fixed potential line is exposed and can be connected thereto.
  • a structure obtained by horizontally inverting FIG. 37 may be employed.
  • first gas is C 5 F 8
  • second gas is CF 4 ⁇
  • Etching temperature -20 ⁇ 100 °C ⁇
  • Etching time 30 to 120 sec
  • C 5 HF 9 , C 4 HF 7 , and C 3 HF 5 can be used as the first etching gas instead of C 5 F 8 , and CF 4 is used as the second etching gas.
  • C 2 F 6 , C 3 F 8 , CH 3 F, CH 2 F 2 , and CHF 3 can be used.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • nitride films 161 and 101 can be etched in the same chamber (container) in which the hard mask HM and the protective film CA are etched. Alternatively, it is possible to perform processing in different chambers connected in a vacuum environment in consideration of throughput.
  • wet etching can be adopted as the etching of the nitride film, and a batch type can be adopted as the etching apparatus. Specific conditions for etching at this time are as follows. Etching solution: H 3 PO 4 ⁇ Etching temperature: 80-200 °C ⁇ Etching time: 5-60 min
  • a mask having the pattern opened is formed by photolithography using a photoresist, and a desired region is etched using the mask.
  • plasma etching may be employed as an etching method for the nitride film 161 and the nitride film 101 (Si 3 N 4 ).
  • plasma etching using the following gas species in a CCP type plasma etching apparatus may be employed as an etching method for the nitride film 161 and the nitride film 101 (Si 3 N 4 ).
  • Etching gas CF 4 ⁇ Etching temperature: 20 ⁇ 100 °C ⁇ Etching time: 5 to 120 sec
  • etching gas O 2 , O 3 , SF 6 , SF 5 , SF 4 , SF 3 , SF 2 , Ar, or N 2 can be used instead of CF 4.
  • Etching made of these etchings A mixed gas containing two or more gases selected from a gas group can also be used.
  • ECR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • SWP surface wave plasma
  • the surface of the left conductive material 8 that is a fixed potential line is exposed in the Y2 cross section. Further, although the upper surfaces of the source region 14 and the drain region 15 are exposed, the ground potential conductive material 8 which is a fixed potential line on the N-FET side is not exposed.
  • the insulating layer that is opened when the contact hole is formed includes a plurality of insulating layers including the hard mask HM (nitride film), the protective layer CA (amorphous carbon layer), and the nitride films (161, 101). Consists of layers.
  • the insulating layer includes at least a first nitride film (hard mask HM), a protective film CA (amorphous carbon layer), and second nitride films (nitride films 161 and 101).
  • the step of opening the contact hole includes a step of etching the first nitride film (hard mask HM) and the protective film CA (amorphous carbon layer) and a part of the second nitride film (nitride films 161 and 101). And a process of performing. Further, the step of etching the first nitride film (hard mask HM) and the protective film CA (amorphous carbon layer) can be carried out continuously by reactive ion etching (RIE) to increase productivity. Moreover, the damage to the source and drain can be minimized by executing the second nitride film by atomic layer etching.
  • RIE reactive ion etching
  • the step of etching the first nitride film (hard mask HM) and the protective film CA (amorphous carbon layer) and the step of etching the part of the second nitride film are performed continuously in the same chamber (container). You can also This enables processing with high productivity and less damage.
  • a liner film LF2 (TiN or TaN) is formed on the entire surface of the substrate
  • an electrode material ELEC1 is formed on the substrate surface so as to cover the entire surface.
  • a CVD method, a PVD method, a plating method, or a coating method can be used, but a sputtering method can also be used.
  • the liner film LF2 is located at the boundary between the electrode material ELEC1 and the substrate.
  • TaN can be used instead of TiN.
  • Electrode material ELEC1 Ru, Co, or W can be used.
  • ELEC1 and a third contact electrode (electrode material ELEC1) are formed.
  • the source region 14 and the drain region 15 are electrically connected to the electrode ELEC1 well by annealing at about 450 ° C. Thereafter, the exposed surface of the electrode material ELEC1 (Ru) filled in the contact hole on the substrate surface is etched back by dry etching or wet etching to remove excess ruthenium metal R and planarize the surface. . If necessary, the substrate surface may be subjected to CMP treatment.
  • an oxide film 27 (SiO 2 ) is formed on the planarized substrate surface. That is, in the Y2 cross section, the oxide film 27 is formed on the electrode material ELEC1 and the oxide film OX.
  • the method for forming the oxide film 27 is vapor phase growth, and an ALD apparatus or a CVD apparatus can be employed as the forming apparatus.
  • the oxide film 16 can also be formed by using an ALD method, a PVD method, or spin coating.
  • the formation temperature of the CVD method can be set to 300 to 1200 ° C., and O 3 can be used instead of O 2 .
  • Perhydropolysilazane can be used in a coating method by spin coating.
  • a contact hole is formed in the oxide film 27, and a contact electrode 28 is formed in the contact hole.
  • the contact hole is formed by forming a mask on the oxide film 27 and etching through the mask. In this mask, a photoresist is applied on the exposed surface of the oxide film 27, and this is exposed and developed to open only the source region and drain region in the N-FET formation scheduled region and the region on the gate electrode 21. To form.
  • the oxide film 27 is etched through this mask, and the etching is stopped when the electrode material is exposed.
  • the etching method for the oxide film 27 (SiO 2 ) at this time may be dry etching similar to the oxide film 16 and the oxide film 9 described above.
  • an electron cyclotron resonance is used as an etching apparatus.
  • a plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type can also be adopted.
  • the material of the contact electrode 28 is made of ruthenium, Co or W, and can be formed by CVD or PVD.
  • the forming temperature is 200 to 600 ° C.
  • SiOC which is a low-k (low dielectric constant material)
  • SiOC which is a low-k (low dielectric constant material)
  • the formation method of the interlayer insulating film 29 is a PE-CVD method, and a PE-CVD apparatus can be adopted as the formation apparatus.
  • the etching method of SiOC constituting the interlayer insulating film is dry etching, and a capacitively coupled plasma (CCP) type can be adopted as an etching apparatus.
  • CCP capacitively coupled plasma
  • Etching gas C 4 F 8 ⁇ Etching temperature: 20 ⁇ 100 °C ⁇ Etching time: 5 to 300 sec
  • the etching gas is CF 2 , CF 3 , C 2 F 2 , C 2 instead of C 4 F 8.
  • F 4, C 2 F 6, Ar, N 2, O 2, or O 3 can be used, and a mixed gas containing two or more gases selected from an etching gas group consisting of these etchings can also be used.
  • an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, an inductively coupled plasma (ICP) type, and a surface wave plasma (SWP) type are adopted. You can also
  • the material of the signal wiring 30 is made of Cu, the forming method is plating, the forming temperature is room temperature, and the deposition of the material is finished when the signal wiring is filled with this material. Thereafter, the surface of the interlayer insulating film 29 is CMPed to remove excess material.
  • the electrode material ELEC1 (Ru) formed on the drain region and the source region on the N-FET side is connected to the signal wiring 30 via the contact electrode 28, and the gate electrode 21 is connected via the contact electrode 28. It is connected to another signal wiring 30.
  • the number of signal wirings 30 is plural, and can be connected to various elements as necessary. Note that, in the Y2 cross section, the source region in the P-FET and the drain region in the N-FET are shown, but this cross sectional structure is the same in the XZ cross section passing through the source region in the P-FET.
  • the XZ cross section passing through the drain region of the P-FET and the source region of the N-FET is the same as the cross section passing through the drain region of the N-FET forming region of the Y2 cross section.
  • the XZ cross section passing through the source region of the N-FET 3 is a cross section obtained by inverting the left and right of the Y2 cross section, and the source region of the N-FET 3 is connected to a fixed potential line (GND) made of the conductive material 8. .
  • GND fixed potential line
  • a plurality of P-type fin-type transistors P-FET1, P-FET2, and P-FET3, and a P-type fin-type dummy FET, DP-FET1, DP-FET2, and DP-FET3 are formed, and a plurality of N-type fin-type transistors N-FET1, N-FET2, and N-FET3, and an N-type fin-type dummy FET, DN- FET1, DN-FET2, and DN-FET3 are formed.
  • input signals Vin1, Vin2, Vin3 and a high-level control signal (High) are input to the signal wiring 30 in FIG. 39, and the output signals Vout are P-FET1, P-FET2, P Although it is taken out from the signal wiring 30 connected to the drain region of the FET 3, the drain region of the N-FET 1 is electrically connected to the signal wiring 30 of the output signal Vout. Since different signal wirings 30 are connected to the gate electrode of the transistor and the gate electrodes of the switches Q1 to Q4, different signals or biases can be given to them.
  • the control device in the plasma processing apparatus has a semiconductor fin including a source region and a drain region constituting a field effect transistor, and a fixed potential line provided along with the semiconductor fin.
  • Conductive material 8 a first step of preparing an intermediate body in which an insulating layer CA is provided over a source region, a drain region, and a fixed potential line, and an insulating layer
  • the CA includes a second step of simultaneously opening a plurality of contact holes respectively extending to the source region, the drain region, and the fixed potential line.
  • This method further includes a step of forming a plurality of contact electrodes (electrode material ELEC1 (FIG. 38)) in the plurality of contact holes, respectively.
  • FIG. 40 is a block diagram of an etching apparatus using plasma.
  • Controller CONT controls power source BV to generate plasma from plasma generation source PG.
  • the generated plasma is an etching gas plasma supplied from the gas supply source 100 into the processing container 102, and the amount of the etching gas is controlled by the controller CONT.
  • the plasma gas moves toward the substrate W (wafer) and etches various materials on the substrate W.
  • the substrate W is fixed by an electrostatic chuck CK, and the temperature of the substrate W is adjusted by the heater 105.
  • the electrostatic chuck CK is connected to the ground in the controller CONT via the matching unit MG, and the heater 105 is connected to the controller CONT via the heater power source 104.
  • An exhaust pipe 111 is connected to the processing container 102 and is connected to an exhaust device 110 (vacuum pump) via a pressure control valve PCV.
  • the apparatus shown in the figure includes a CCP type etching apparatus, an electron cyclotron resonance plasma (ECR plasma) type, a helicon wave plasma (HWP) type, and an inductively coupled plasma (ICP) depending on the form of the plasma generation source PG. It functions as a type, surface wave plasma (SWP) type plasma processing apparatus, and can perform the etching described above.
  • CCR plasma electron cyclotron resonance plasma
  • HWP helicon wave plasma
  • ICP inductively coupled plasma
  • the control device in the plasma processing apparatus includes the first semiconductor fin (for P-FET) and the third semiconductor fin (for P-FET) erected from the substrate.
  • a conductive material 8 for a fixed potential line is provided in a region between the adjacent first and third semiconductor fins up to a position higher than any of the top surfaces of the first and third semiconductor fins.
  • Control to The control method of this embodiment is executed by such a control device.
  • the proportion of Cl 2, i.e. Cl 2 / (O 2 + Cl 2 ) ⁇ 100 value (%) is controlled to be 1% to 20%. It is preferably controlled to be 7% to 15%. More preferably, it is controlled to be 9% to 11%.
  • the etching gas for the second conductive material is oxygen (O 2 ) is a mixed gas of Cl 2 and the flow rate ratio of the Cl 2 gas to the total gas, that is, to the molar concentration C (O 2 + Cl 2 ) (mol / L) of the mixed gas in a unit volume in the processing vessel. It is preferable that the ratio of the volume molar concentration C (Cl 2 ) (mol / L) of the Cl 2 gas satisfies the following inequality.
  • the etching rate tends to be inferior. If the upper limit is exceeded, it is considered that the selectivity tends to be impaired. Since the etching rate and the selectivity can be obtained at the same time, there is an effect that these problems are unlikely to occur.
  • the power rail can be easily formed in the semiconductor device including the fin-type FET for the reason of self-alignment.
  • a power rail including a fixed potential line made of a conductive material can be easily formed. Can be formed.
  • the conductive material includes the first conductive material (liner film 7) separated from the first semiconductor fin 2 by the first distance d ⁇ b> 1 and the first semiconductor fin 2, where the first distance d ⁇ b> 1 is equal to the second distance d ⁇ b> 2. And a second conductive material (conductive material 8) separated by a second distance d2, and the first conductive material has an etching resistance higher than that of the second conductive material against the etching gas of the second conductive material. It is. Since the first conductive material is an etching barrier film, it functions as an etching stopper, and the semiconductor fin 2 is protected by the first conductive material (liner film 7).
  • the first conductive material 7 is TiN or TaN
  • the second conductive material 8 is at least one metal selected from the group consisting of Co, W, and Ru
  • the etch-back gas of the second conductive material 8 is , (1) CF 4 , or (2) a mixed gas of oxygen and Cl 2 .
  • a mixed gas of oxygen (O 2 ) and Cl 2 can etch the selected metal such as Ru, but a metal nitride such as TiN (titanium nitride) or TaN (tantalum nitride).
  • a mixed gas of oxygen (O 2 ) and Cl 2 can etch the selected metal such as Ru
  • a metal nitride such as TiN (titanium nitride) or TaN (tantalum nitride).
  • etching stopper function and the electrical conductivity required for the fixed power supply line can be achieved.
  • the above manufacturing method includes a pair of semiconductor fins 2 erected from the substrate, and the semiconductor fins 2 are located in a region between the adjacent semiconductor fins 2 to a position higher than any of the top surfaces of the semiconductor fins 2.
  • the conductive material 8 is etched to a position lower than any of the top surfaces, the conductive material on the protective material is removed, and a second step of leaving the conductive material in the region between the semiconductor fins is provided. .
  • the first fin group (P-FET) composed of a pair of semiconductor fins 2 and the second fin composed of a pair of semiconductor fins separated from the first fin group.
  • a fin group (N-FET), and the first fin group (P-FET) includes a first semiconductor fin constituting a fin-type P-type field effect transistor including a source region, a gate region, and a drain region.
  • the second fin group (N-FET) includes a second semiconductor fin constituting a fin-type N-type field effect transistor including a source region, a gate region, and a drain region, and includes a first fin group (P-FET).
  • the region between the semiconductor fins 2 includes a conductive material 8 embedded up to a position lower than any of the top surfaces of the semiconductor fins, and is fixed to the source region of the semiconductor fins 2. It has a potential line 8.
  • a fixed potential line can be easily formed, and a semiconductor device with a small cell height can be manufactured. Therefore, power consumption can be reduced and an operation speed can be increased.

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  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé de fabrication, dans lequel une paire d'ailettes semi-conductrices se dressant verticalement à partir d'un substrat sont fournies et un matériau conducteur de ligne de potentiel fixe, auquel des zones de source des ailettes semi-conductrices sont connectées, est disposé, dans une zone entre les ailettes semi-conductrices adjacentes, jusqu'à un emplacement plus élevé que l'une quelconque des surfaces de sommet des ailettes semi-conductrices, comprend : une première étape de préparation d'un corps intermédiaire dans lequel un matériau de protection est disposé sur une zone à l'extérieur de la zone entre les ailettes semi-conductrices ; et une seconde étape consistant à retirer le matériau conducteur sur le matériau protecteur par gravure du matériau conducteur jusqu'à un emplacement inférieur à l'une quelconque des surfaces de sommet des ailettes semi-conductrices, et à laisser le matériau conducteur à l'intérieur de la zone entre les ailettes semi-conductrices.
PCT/JP2019/001709 2018-02-02 2019-01-21 Dispositif à semi-conducteur et son procédé de fabrication Ceased WO2019151022A1 (fr)

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WO2021187006A1 (fr) * 2020-03-18 2021-09-23 富士フイルム株式会社 Procédé de traitement de substrat

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JPH0371666A (ja) * 1989-08-10 1991-03-27 Oki Electric Ind Co Ltd 半導体装置
JP2011129771A (ja) * 2009-12-18 2011-06-30 Elpida Memory Inc 半導体装置及びその製造方法
WO2013111592A1 (fr) * 2012-01-25 2013-08-01 東京エレクトロン株式会社 Procédé de fabrication de dispositif semi-conducteur
US20150287795A1 (en) * 2014-04-03 2015-10-08 GlobalFoundries, Inc. Processes for preparing integrated circuits with improved source/drain contact structures and integrated circuits prepared according to such processes
US20170062421A1 (en) * 2015-09-01 2017-03-02 Imec Vzw Buried interconnect for semiconductor circuits
JP2017208469A (ja) * 2016-05-19 2017-11-24 東京エレクトロン株式会社 酸化膜除去方法および除去装置、ならびにコンタクト形成方法およびコンタクト形成システム
WO2017208807A1 (fr) * 2016-05-30 2017-12-07 東京エレクトロン株式会社 Procédé de gravure

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Publication number Priority date Publication date Assignee Title
JPH0371666A (ja) * 1989-08-10 1991-03-27 Oki Electric Ind Co Ltd 半導体装置
JP2011129771A (ja) * 2009-12-18 2011-06-30 Elpida Memory Inc 半導体装置及びその製造方法
WO2013111592A1 (fr) * 2012-01-25 2013-08-01 東京エレクトロン株式会社 Procédé de fabrication de dispositif semi-conducteur
US20150287795A1 (en) * 2014-04-03 2015-10-08 GlobalFoundries, Inc. Processes for preparing integrated circuits with improved source/drain contact structures and integrated circuits prepared according to such processes
US20170062421A1 (en) * 2015-09-01 2017-03-02 Imec Vzw Buried interconnect for semiconductor circuits
JP2017208469A (ja) * 2016-05-19 2017-11-24 東京エレクトロン株式会社 酸化膜除去方法および除去装置、ならびにコンタクト形成方法およびコンタクト形成システム
WO2017208807A1 (fr) * 2016-05-30 2017-12-07 東京エレクトロン株式会社 Procédé de gravure

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021187006A1 (fr) * 2020-03-18 2021-09-23 富士フイルム株式会社 Procédé de traitement de substrat

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