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WO2019033306A1 - Procédé et appareil de réglage dynamique de signaux de modulation de largeur d'impulsion - Google Patents

Procédé et appareil de réglage dynamique de signaux de modulation de largeur d'impulsion Download PDF

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Publication number
WO2019033306A1
WO2019033306A1 PCT/CN2017/097693 CN2017097693W WO2019033306A1 WO 2019033306 A1 WO2019033306 A1 WO 2019033306A1 CN 2017097693 W CN2017097693 W CN 2017097693W WO 2019033306 A1 WO2019033306 A1 WO 2019033306A1
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Prior art keywords
value
bit
dynamic
bits
cache
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PCT/CN2017/097693
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English (en)
Chinese (zh)
Inventor
王青岗
胡喜
胡庚
卓越
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Siemens AG
Siemens Corp
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Siemens AG
Siemens Corp
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Priority to PCT/CN2017/097693 priority Critical patent/WO2019033306A1/fr
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses

Definitions

  • the present application relates to the field of signal processing technologies, and in particular, to a dynamic adjustment method and apparatus for a Pulse Width Modulation (PWM) signal.
  • PWM Pulse Width Modulation
  • PWM is an effective technique for controlling analog circuits by using the digital output of a microprocessor. It is widely used in many fields such as measurement, communication, power control and conversion. For example, PWM technology can be used in industrial field devices with current output control, especially for related devices that can be addressed by High Speed Addressable Remote Transit (HART).
  • HART High Speed Addressable Remote Transit
  • the output current accuracy of the PWM control is determined by factors such as the CPU clock frequency, the PWM control bit length, and the corner frequency of the low-pass filter.
  • the CPU clock frequency is especially critical.
  • CPU clock frequencies for low-power devices are typically low, such as 1 to 2 megahertz (MHz), making it difficult to provide a large number of PWM control bits.
  • the main object of embodiments of the present invention is to provide a method and apparatus for dynamically adjusting a PWM signal.
  • a method for dynamically adjusting a PWM signal comprising:
  • Determining a base value based on the target duty ratio storing the base value in a PWM control bit, storing accuracy compensation data of a base value in a buffer bit, and storing a dynamic compensation parameter in a dynamic compensation bit;
  • the determining the target duty cycle comprises:
  • the quotient is determined as the target duty cycle.
  • the embodiment of the present invention can quickly determine the target duty ratio by establishing a function relationship between the target output current value and the maximum output current value, which is convenient for implementation in an industrial field.
  • the determining the base value based on the target duty ratio comprises:
  • the maximum value of the control bit is determined based on the number of bits of the PWM control bit
  • the embodiment of the present invention can conveniently determine the basic value according to the number of bits of the PWM control bit, and is applicable to various specific control environments.
  • the precision compensation data is the number of base values stored in the cache, and the remaining portion of the cache is padded with a base value plus one, and the number of base values in the cache is increased by one The sum of the number is equal to the maximum value of the cache bit determined based on the number of bits of the cache bit; or
  • the precision compensation data is a number of base values stored in the cache, and the remaining portion of the cache is filled with a base value, and the sum of the number of base values in the cache and the base value plus one is Equal to the maximum value of the cache bit determined based on the number of bits of the cache bit.
  • the embodiment of the present invention can determine the specific storage structure of the cache based on the number of base values, and can also determine the specific storage structure of the cache based on the number of base values plus one.
  • the cache storage structure has multiple implementation manners.
  • the generating the PWM signal using the base value and the precision compensation data comprises:
  • An actual duty cycle is determined using the third value and a PWM signal is generated based on the actual duty cycle.
  • the specific storage structure of the cache determines the actual duty ratio and generates a PWM signal, and the calculation process is simple, and the PWM signal generation speed is fast.
  • the dynamic compensation parameter includes a step value
  • the dynamically adjusting the precision compensation data based on the dynamic compensation parameter includes:
  • the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically false
  • the base value stored in the cache is changed to the base value plus one, and the dynamic adjustment flag is set to logically true.
  • the step value is subtracted from the maximum value of the dynamic compensation bit.
  • the embodiment of the present invention adds one base value stored in the cache to the base value plus one, that is, increases the base value in the cache.
  • the number of ones is increased, and the number of additions is strictly limited to one, and the number of base values in the cache is reduced, wherein the number of reductions is strictly limited to one, thus finely compensating for loss accuracy.
  • the dynamic compensation parameter includes a step value
  • the dynamically adjusting the precision compensation data based on the dynamic compensation parameter includes:
  • step value is less than the dynamic compensation bit maximum value and the preset dynamic adjustment flag is logically true, one of the base values stored in the buffer is incremented to a base value, and the dynamic adjustment flag is set to logical false.
  • the embodiment of the present invention adds one base value stored in the cache to the base value, that is, reduces the base value in the cache.
  • the dynamic compensation parameter includes a step value
  • the dynamically adjusting the precision compensation data based on the dynamic compensation parameter includes:
  • the step value is increased when the step value is greater than or equal to the dynamic compensation bit maximum value and the preset dynamic adjustment flag is logically true.
  • the embodiment of the present invention re-adds the step value to constitute a new complete cycle.
  • the dynamic compensation parameter includes a step value
  • the dynamically adjusting the precision compensation data based on the dynamic compensation parameter includes:
  • the step value is increased when the step value is less than the dynamic compensation bit maximum value and the preset dynamic adjustment flag is logically false.
  • the embodiment of the present invention can re-add the step value to form a new complete cycle.
  • a dynamic adjustment device for a PWM signal comprising:
  • a duty cycle and accuracy determination module for determining a target duty cycle and a number of control precision bits
  • a bit determining module configured to determine respective digits of the PWM control bit, the buffer bit, and the dynamic compensation bit, wherein a sum of the number of bits of the PWM control bit, the buffer bit, and the dynamic compensation bit is equal to the control precision bit number;
  • a bit determining module configured to determine a base value based on the target duty ratio, store the base value in a PWM control bit, store accuracy compensation data of a base value in a buffer bit, and store a dynamic compensation parameter in a dynamic compensation bit;
  • a dynamic adjustment module configured to generate a PWM signal by using the base value and the precision compensation data, and dynamically adjust the precision compensation data based on the dynamic compensation parameter to dynamically adjust the PWM signal.
  • a duty cycle and accuracy determination module is configured to determine a target output current value and a maximum output current value; The quotient of the output current value and the maximum output current value; the quotient is determined as the target duty cycle.
  • the embodiment of the present invention can quickly determine the target duty ratio by establishing a function relationship between the target output current value and the maximum output current value, which is convenient for implementation in an industrial field.
  • the bit determining module is configured to determine a control bit maximum value based on the number of bits of the PWM control bit; determine a product of the control bit maximum value and the target duty ratio, and take the product downward
  • the integer value is determined as the base value.
  • the embodiment of the present invention can conveniently determine the basic value according to the number of bits of the PWM control bit, and is applicable to various specific control environments.
  • the precision compensation data is the number of base values stored in the cache, and the remaining portion of the cache is padded with a base value plus one, and the number of base values in the cache is increased by one The sum of the number is equal to the maximum value of the cache bit determined based on the number of bits of the cache bit; or
  • the precision compensation data is a number of base values stored in the cache, and the remaining portion of the cache is filled with a base value, and the sum of the number of base values in the cache and the base value plus one is Equal to the maximum value of the cache bit determined based on the number of bits of the cache bit.
  • the embodiment of the present invention can determine the specific storage structure of the cache based on the number of base values, and can also determine the specific storage structure of the cache based on the number of base values plus one.
  • the cache storage structure has multiple implementation manners.
  • the dynamic adjustment module is configured to extract all the base values from the cache and sum them as the first value, extract all the base values from the cache and sum them together as the second value; a sum of a value and a second value, dividing the sum of the first value and the second value by the maximum value of the buffer bit to obtain a third value; determining the actual duty ratio by using the third value, and based on the actual occupation The air ratio generates a PWM signal.
  • the specific storage structure of the cache determines the actual duty ratio and generates a PWM signal, and the calculation process is simple, and the PWM signal generation speed is fast.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically false, one of the buffers is stored. The base value becomes the base value plus one, the dynamic adjustment flag is set to logically true, and the step value is subtracted from the dynamic compensation bit maximum.
  • the embodiment of the present invention adds one base value stored in the cache to the base value plus one, that is, increases the base value in the cache.
  • the number of ones is increased, and the number of additions is strictly limited to one, and the number of base values in the cache is reduced, wherein the number of reductions is strictly limited to one, thus finely compensating for loss accuracy.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is less than the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically true, a base stored in the buffer is stored. The value plus one becomes the base value, and the dynamic adjustment flag is set to logical false.
  • the embodiment of the present invention adds one base value stored in the cache to the base value, that is, reduces the base value in the cache.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logic true, the step value is increased.
  • the embodiment of the present invention re-adds the step value to constitute a new complete cycle.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is less than the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is a logical false, the step value is increased.
  • the embodiment of the present invention can re-add the step value to form a new complete cycle.
  • a HART device that includes:
  • the embodiment of the present invention also proposes a HART device that improves the control precision of the PWM signal, and the HART device can also reduce the number of bits and the buffer space of the PMW control bit.
  • a storage medium storing a computer program for performing the method of any of the above. It can be seen that the embodiment of the present invention also proposes a storage medium that improves the control precision of the PWM signal.
  • FIG. 1 is a flow chart of a method for dynamically adjusting a PWM signal according to an embodiment of the present invention
  • FIG. 2 is an exemplary structural diagram of a bit composition when the number of control precision bits is 16 according to an embodiment of the present invention
  • FIG. 3 is an exemplary flowchart of a dynamic compensation method based on the bit structure shown in FIG. 2 according to an embodiment of the present invention
  • FIG. 4 is a structural diagram of a dynamic adjustment device for a PWM signal according to an embodiment of the present invention.
  • FIG. 5 is a structural diagram of a HART device according to an embodiment of the present invention.
  • FIG. 7 is a simulation diagram of an output current according to an embodiment of the present invention.
  • the embodiment of the present invention not only the accuracy of the precision data lost due to the number of bits of the PWM control being less than the number of control precision bits is compensated by the buffer (which may be referred to as one-time compensation), but also the dynamic compensation bit pair is used due to the number of PWM control bits.
  • the lost precision data performs dynamic compensation again (which can be called quadratic compensation).
  • the embodiment of the invention can reduce the number of bits and the buffer space of the PMW control bit, thereby reducing the requirement on the CPU clock frequency and saving cost.
  • FIG. 1 is a flow chart of a method for dynamically adjusting a PWM signal according to an embodiment of the present invention.
  • the method includes:
  • Step 101 Determine a target duty ratio (DutyRatio) and a control precision bit number.
  • the duty cycle is the ratio of the time that the active level occupies within one cycle; the target duty cycle is the duty cycle that the desired PWM signal can reach.
  • the target duty ratio may be determined based on the target output current value and the maximum output current value.
  • the method includes: first determining a target output current value and a maximum output current value, and then calculating a quotient of the target output current value and the maximum output current value; determining the quotient as the target duty ratio.
  • control precision bits can be specifically implemented as 4 bits, 8 bits, 16 bits, 32 bits, 64 bits. Bit, and so on.
  • Step 102 Determine respective digits of the PWM control bit, the buffer bit, and the dynamic compensation bit, wherein the sum of the bits of the PWM control bit, the buffer bit, and the dynamic compensation bit is equal to the control precision bit number.
  • the number of control precision bits determined in step 101 is divided into three parts, which are the number of bits of the PWM control bit, the number of bits of the buffer bit, and the number of bits of the dynamic compensation bit.
  • the number of bits of the PWM control bit can be 6 bits, the number of bits of the buffer bit can be 5 bits, and the number of bits of the dynamic compensation bit can be 5 bits; or, the PWM control bit
  • the number of bits can be 8 bits, the number of bits of the buffer bit can be 4 bits, the number of bits of the dynamic compensation bit can be 4 bits, and so on.
  • the number of bits of the PWM control bits, buffer bits, and dynamic compensation bits can be flexibly allocated within the number of control precision bits based on the specific application requirements. As long as the sum of the number of bits of the assigned PWM control bit, buffer bit and dynamic compensation bit is still equal to the number of control precision bits, the control accuracy can still be guaranteed.
  • the number of bits of the PWM control bit can be reduced; when the CPU clock frequency is high, the number of bits of the PWM control bit can be increased.
  • the number of bits of the cache bit can be reduced; when the cache storage space is sufficient, the number of bits of the cache bit can be increased.
  • Step 103 Determine the base value based on the target duty ratio, store the base value in the PWM control bit, store the precision compensation data of the base value in the buffer bit, and store the dynamic compensation parameter in the dynamic compensation bit.
  • the PWM control bits are typically used to hold the base value determined by the target duty cycle.
  • the base value is an intermediate value determined by the number of bits of the PWM control bit and the target duty cycle, which is used to quickly calculate the actual duty cycle.
  • the target duty ratio of the remainder it is also convenient for the cache to store.
  • determining the base value based on the target duty ratio includes: determining a control bit maximum value based on the number of bits of the PWM control bit; determining a product of the control bit maximum value and the target duty ratio, and rounding down the product Determined as the base value.
  • the target output current value is 12.3456 mA
  • the PWM control bit is 5 bits, so the PWM control bit has a maximum value of 2 5 , that is, 32, and the product of the PWM control bit maximum value and the target duty ratio is 32 ⁇ 0.3858, and the product result is rounded down to obtain a value of 12 , to determine the base value is 12.
  • the number of PWM control bits is less than the number of control precision bits, which can reduce the PWM control period and thereby reduce low frequency noise.
  • the base value can usually only be close to the target duty cycle within the accuracy determined by the number of PWM control bits.
  • the precision compensation data of the underlying value is saved in the cache bit. Accuracy compensation data can be lost to the number of precision controlled by the number of PWM control bits According to the implementation of compensation.
  • the method includes: setting a cache whose storage space is equal to the maximum value of the cache bit, and storing a plurality of base values and a plurality of base values plus one in the cache. By adding the base value in the cache and adding one to the base value of the finest value of the base value, the finest adjustment of the duty cycle indirectly reflected by the base value can be achieved.
  • the cached storage space is determined by the size of the cache bits, and the precision compensation data represents the ratio between the base value in the cache and the base value plus one.
  • the precision compensation data can be implemented as the number of base values stored in the cache, or as the number of base values stored in the cache plus one.
  • the precision compensation data is the number of base values stored in the cache, and the remaining portion of the cache is filled with the base value plus one, and the number of base values in the cache is increased by one. And, equal to the maximum number of cache bits determined based on the number of bits in the cache bit. At this time, the number of base values stored in the cache is equal to the precision compensation data, and the remaining portion of the cache stores the base value plus one, that is, the number of base values plus one is the maximum value of the cache bit minus the precision compensation data.
  • the precision compensation data is a number of the base value stored in the cache, and the remaining part of the buffer is filled with the base value, and the number of base values in the cache is increased by one. And, equal to the maximum number of cache bits determined based on the number of bits in the cache bit. At this time, the number of base values added in the buffer plus one is equal to the precision compensation data, and the remaining portion of the buffer stores the base value, that is, the number of base values is the maximum value of the buffer bit minus the precision compensation data.
  • the sum of the number of bits of the PWM control bit and the number of bits of the buffer bit is still less than the number of control precision bits. Therefore, even if the buffer bit is used to compensate the precision data lost by the PWM control bit limit, the accuracy data will still be lost.
  • the embodiment of the present invention performs secondary dynamic compensation on the lost precision data by using the dynamic compensation parameter stored in the dynamic compensation bit, and the secondary dynamic compensation mode will be specifically described in the subsequent step 104.
  • Step 104 Generate a PWM signal by using the base value and the precision compensation data, and dynamically adjust the precision compensation data based on the dynamic compensation parameter to dynamically adjust the PWM signal.
  • generating the PWM signal using the base value and the precision compensation data comprises: extracting all the base values from the buffer and summing them as the first value, extracting all the base values from the buffer and summing them together as a a second value; calculating a sum of the first value and the second value, dividing the sum of the first value and the second value by the maximum value of the buffer bit to obtain a third value; determining the actual duty ratio by using the third value, and based on The actual duty cycle generates a PWM signal.
  • the PWM signal is a PWM signal generated after performing one compensation using the precision compensation data, and the PWM signal still loses part of the precision data after being compensated once.
  • the PWM generation circuit traverses the entire cache, wherein when a base value is encountered in the cache, a base value of a high level pulse is generated within a control period determined by a maximum value of the PWM control bit, and in the control The other time of the cycle is kept low; when the base value is increased by one in the buffer, the base value is added and a high level pulse is generated in the control period determined by the maximum value of the PWM control bit, and other ones in the control cycle Time is kept low. After the PWM generation circuit traverses the complete buffer, all the combination of level pulses generated constitutes a PWM signal.
  • the dynamic compensation parameter stored in the dynamic compensation bit is used to add one to the base value and the base value in the buffer.
  • the scale is finely and dynamically adjusted to perform dynamic compensation on the missing precision data.
  • the dynamic adjustment flag is set in advance before performing dynamic compensation.
  • the dynamic adjustment flag is used to identify whether the cache has been dynamically adjusted. When the dynamic adjustment flag is logically false, it indicates that the cache has not been dynamically adjusted; when the dynamic adjustment flag is logically true, it indicates that the cache has been dynamically adjusted. The initial value of the dynamic adjustment flag is logically false.
  • the dynamic compensation parameter includes a step value
  • dynamically adjusting the accuracy compensation data based on the dynamic compensation parameter includes:
  • the maximum value of the dynamic compensation bit is determined based on the number of bits of the dynamic compensation bit; when the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically false, one of the base values stored in the buffer is incremented by one, The dynamic adjustment flag is set to logic true and the step value is subtracted from the dynamic compensation bit maximum.
  • the base value stored in the cache is changed to the base value plus one, that is, the number of the base value plus one in the cache is increased (the number of increments is strictly limited to 1), and the cache is reduced.
  • the number of base values in (the number of reductions is strictly limited to 1), which finely compensates for the loss accuracy.
  • the dynamic compensation parameter includes a step value
  • dynamically adjusting the accuracy compensation data based on the dynamic compensation parameter includes:
  • the maximum value of the dynamic compensation bit is determined based on the number of bits of the dynamic compensation bit; when the step value is smaller than the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically true, adding a base value stored in the buffer to the base becomes Value, set the dynamic adjustment flag to logically false.
  • the base value stored in the cache is added to the base value, that is, the number of base values in the cache is increased by one (the number of reduction is strictly limited to 1), and the cache is increased.
  • the number of base values in (the number of increments is strictly limited to 1), thereby preventing errors caused by repeated compensation.
  • the dynamic compensation parameter includes a step value
  • dynamically adjusting the accuracy compensation data based on the dynamic compensation parameter includes: determining a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit; and when the step value is greater than or equal to the maximum value of the dynamic compensation bit When the preset dynamic adjustment flag is logically true, the step value is increased.
  • the dynamic compensation parameter includes a step value
  • dynamically adjusting the accuracy compensation data based on the dynamic compensation parameter includes: determining a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit; and when the step value is less than the maximum value of the dynamic compensation bit and When the preset dynamic adjustment flag is logically false, the step value is increased.
  • the method illustrated in Figure 1 can be implemented based on various hardware circuits or software flows.
  • a hardware circuit When a hardware circuit is employed, a specially designed permanent circuit, logic device, or programmable logic device can be utilized to perform the method illustrated in FIG.
  • a software flow When a software flow is employed, the method illustrated in Figure 1 can be performed in a variety of programming languages or assembly languages.
  • FIG. 2 is an exemplary structural diagram of bit composition when the number of control precision bits is 16 according to an embodiment of the present invention.
  • the number of control precision bits is 16 bits, wherein the PWM control bit is the first 6 bits, the buffer bit is the middle 5 bits, and the dynamic compensation bit is the last 5 bits.
  • the maximum output current value is 32 mA (mA); the target output current value is 12.3456 mA; the CPU clock frequency is 1.84320 MHz; The corner frequency of the filter is 18HZ.
  • the PWM control bit is 6 bits, so the PWM control bit has a maximum value of 2 6 , which is 64.
  • the product of the maximum value of the PWM control bit and the target duty ratio is 64 ⁇ 0.3858, and the product result is rounded down to obtain a value of 24 to determine the base value of 24.
  • the base value (24) is converted to a binary number and the result of the conversion is 011000, so the binary number (011000) is stored in the PWM control bit.
  • the cached bits are stored with the calculated precision compensation data such that the compensated actual duty cycle is as close as possible to the target duty cycle.
  • a binary number 10110 ie, 22
  • the step value is saved in the dynamic compensation bit.
  • the step value is used to control the cycle speed of the dynamic compensation process.
  • the step value is a preset value. When the desired cycle speed is faster, the step value can be increased; when the cycle speed is expected to be slow, the step value can be lowered.
  • a dynamic adjustment flag is set in advance to identify whether the cache has been dynamically adjusted. When the dynamic adjustment flag is logically false, it indicates that the cache has not been dynamically adjusted; when the dynamic adjustment flag is logically true, it indicates that the cache has been dynamically adjusted.
  • FIG. 3 is a flow chart of a dynamic compensation method based on the bit structure shown in FIG. 2, in accordance with an embodiment of the present invention.
  • the method includes:
  • Step 300 Set the initial value of the dynamic adjustment flag to logic false, obtain the base value from the PWM control bit, store the base value (ie, 24) in the cache according to the ratio of the number of storage determined by the precision of the PWM control bit.
  • the base value is incremented by one (ie, 25), and the step value is determined to be 4 based on the stored content of the dynamic compensation bit.
  • Step 301 Extract all base values and all base values from the cache and add one to generate a PWM signal.
  • all 22 base values plus one (ie 25) are extracted from the cache, and the 22 base values are summed to obtain a first value 550; all 10 base values are extracted from the cache ( That is, 24), then summing the 10 24 to obtain the second value 240; then dividing the sum of the first value (550) and the second value (240) by the maximum value of the buffer bit (32) to obtain the third value ( 24.6875), using the third value to determine the actual duty cycle after buffer compensation is 0.3857. Then, the PWM signal is generated by the actual duty ratio after the buffer compensation.
  • the PWM generation circuit traverses the entire cache, wherein when a base value is encountered in the buffer, a base value high level pulse is generated within a control period determined by a maximum value of the PWM control bit; When the base value is incremented by one in the buffer, a base value is added plus a high level pulse in the control period determined by the maximum value of the PWM control bit.
  • the PWM generation circuit traverses the entire buffer. When the base value (ie, 24) is encountered in the buffer, the PWM generation circuit generates 24 high-level pulses in 64 clock cycles, while the remaining 40 clock cycles remain low. When the base value is incremented by one (ie, 25), the PWM generation circuit generates 25 high-level pulses in 64 clock cycles, while the remaining 39 clock cycles remain low.
  • the PWM generation circuit will encounter 10 base values in the buffer and thus perform the following operations 10 times: 24 high-level pulses are generated in 64 clock cycles; the PWM generation circuit will encounter 22 base values in the buffer One is added, and thus 22 operations are performed as follows: 25 high-level pulses are generated in 64 clock cycles. After the PWM generation circuit traverses the complete buffer, all the combination of level pulses generated constitutes a PWM signal.
  • Step 302 The step value is incremented.
  • Step 303 Determine whether the step value is greater than or equal to the maximum value of the dynamic compensation bit. If it is greater, step 304 is performed, otherwise step 305 is performed.
  • Step 304 Determine whether the dynamic adjustment flag is logically true. If yes, go back to step 301, otherwise go to step 307.
  • Step 305 Determine whether the dynamic adjustment flag is logically true. If yes, execute step 306, otherwise return to step 301.
  • Step 306 Set the dynamic adjustment identifier to logical false, and add one base value stored in the cache to the base value, that is, reduce the number of base values plus one in the cache (the number of reduction is strictly limited to 1), and increase The number of base values in the cache (the number of additions is strictly limited to 1), and then returns to step 301.
  • the original PWM signal can be dynamically restored based on the buffer that has been adjusted to prevent the error caused by the repeated compensation.
  • Step 307 Set the dynamic adjustment identifier to logically true, and add a base value stored in the cache to the base value plus one, that is, increase the number of base values plus one in the cache (the number of additions is strictly limited to 1), and decrease The number of base values in the cache (the number of additions is strictly limited to 1), and then returns to step 301. After adjustment, the number of base values in the cache becomes 9, and the number of base values plus one becomes 23. Then, in the subsequent step 301, the PWM signal can be dynamically adjusted based on the buffer that has been adjusted to finely compensate for the loss accuracy.
  • the PWM generating circuit will encounter 9 basic values, and thus perform the following operations 9 times: 24 high-level pulses are generated in 64 clock cycles; the PWM generating circuit will encounter 23 The base values are incremented by one, and thus 23 operations are performed as follows: 25 high-level pulses are generated in 64 clock cycles.
  • the subsequent step 301 after the PWM generation circuit traverses the complete buffer, all the combination of level pulses generated constitutes the adjusted PWM signal.
  • the dynamic adjustment identifier may be not set to a logically true operation in step 307, but the dynamic adjustment identifier is set to a logically true operation between step 303 and step 303. . That is, the dynamic adjustment flag is set to a logically true operation, moving from step 307 to between step 303 and step 303, thereby avoiding possible loops.
  • an embodiment of the present invention further provides a dynamic adjustment device for a PWM signal.
  • FIG. 4 is a structural diagram of a dynamic adjustment device for a PWM signal according to an embodiment of the present invention.
  • the apparatus 400 includes:
  • a duty ratio and accuracy determining module 401 for determining a target duty ratio and a number of control precision bits
  • the bit number determining module 402 is configured to determine respective digits of the PWM control bit, the buffer bit, and the dynamic compensation bit, wherein a sum of the bits of the PWM control bit, the buffer bit, and the dynamic compensation bit is equal to the control precision bit number;
  • the bit determining module 403 is configured to determine a base value based on the target duty ratio, store the base value in the PWM control bit, store the precision compensation data of the base value in the buffer bit, and store the dynamic compensation parameter in the dynamic compensation bit;
  • the dynamic adjustment module 404 is configured to generate a PWM signal by using the base value and the precision compensation data, and dynamically adjust the precision compensation data based on the dynamic compensation parameter to dynamically adjust the PWM signal.
  • the duty cycle and progress determination module 401 is configured to determine a target output current value and a maximum output current value; calculate a quotient of the target output current value and the maximum output current value; determine the quotient as the target duty ratio.
  • the bit determining module 403 is configured to determine a control bit maximum value based on the number of bits of the PWM control bit; determine a product of the control bit maximum value and the target duty ratio, and round down the product The value is determined as the base value.
  • the precision compensation data is the number of base values stored in the cache, and the remaining portion of the cache is padded with the base value plus one; the number of base values in the cache is increased by one of the base values And, equal to the maximum value of the cache bit determined based on the number of bits of the cache bit.
  • the dynamic adjustment module 404 is configured to extract all the base values from the cache and sum them as the first value, extract all the base values from the cache and sum them together as the second value; a sum of the first value and the second value, dividing the sum of the first value and the second value by the maximum value of the buffer bit to obtain a third value; determining the actual duty ratio by using the third value, and generating the actual duty ratio based on the actual duty ratio PWM signal.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module 404 is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically false, the buffer is stored in the cache. A base value becomes the base value plus one, the dynamic adjustment flag is set to logically true, and the step value is subtracted from the dynamic compensation bit maximum.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module 404 is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is smaller than the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically true, one of the caches is stored. The base value plus one becomes the base value, and the dynamic adjustment flag is set to logical false.
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module 404 is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is greater than or equal to the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically true, the step value is increased. .
  • the dynamic compensation parameter includes a step value
  • the dynamic adjustment module 404 is configured to determine a maximum value of the dynamic compensation bit based on the number of bits of the dynamic compensation bit. When the step value is less than the maximum value of the dynamic compensation bit and the preset dynamic adjustment flag is logically false, the step value is increased.
  • HART devices are typically low-power devices, and the CPU clock frequency is typically low, making it difficult to provide a large number of PWM control bits.
  • the number of bits and the buffer space of the PMW control bit can be reduced under the premise of ensuring the control precision, thereby reducing the CPU clock frequency requirement and saving cost, especially for the HART device. .
  • FIG. 5 is a structural diagram of a HART device according to an embodiment of the present invention.
  • the device 500 includes:
  • a dynamic signal adjusting device 501 for generating a PWM signal
  • the current output module 502 is configured to output a current controlled by the PWM signal.
  • the PWM signal dynamic adjustment device 501 can have the same structure of the dynamic adjustment device 400 of the PWM signal as shown in FIG. 4.
  • FIG. 6 is a prior art output current simulation diagram using only buffer compensation
  • FIG. 7 is an output current simulation diagram in accordance with an embodiment of the present invention.
  • the number of bits in the PWM control bit is 9, and the number of bits in the buffer bit is 7.
  • the number of bits in the PWM control bit is 6, the number of bits in the buffer bit is 5, and the number of bits in the dynamic compensation bit. Is 5.
  • the vertical axis represents the output current
  • the horizontal axis represents the stored value of the buffer bit
  • the vertical axis represents the output current
  • the horizontal axis represents the stored value of the dynamic compensation bit.
  • the output current has the same limit value, which are -0.5 and +0.5, respectively.
  • the PWM control bit only needs 6 bits. Compared with the 9 bits required in the prior art, the number of PWM control bits is significantly reduced, and the requirement for the CPU clock frequency can be reduced.
  • the number of bits of the cache bit only needs 5 bits. Compared with the 7 bits required in the prior art, the number of cache bits is also significantly reduced, and the requirement for the cache space can also be reduced.
  • the hardware modules in the various embodiments may be implemented mechanically or electronically.
  • a hardware module can include specially designed permanent circuits or logic devices (such as dedicated processors such as FPGAs or ASICs) for performing specific operations.
  • the hardware modules may also include programmable logic devices or circuits (such as including general purpose processors or other programmable processors) that are temporarily configured by software for performing particular operations.
  • Hardware implementations can be made based on cost and time considerations, either by mechanical means, by dedicated permanent circuits, or by temporarily configured circuits (as configured by software).
  • the present invention also provides a machine readable storage medium storing instructions for causing a machine to perform a method as described herein.
  • a system or apparatus equipped with a storage medium on which software program code implementing the functions of any of the above-described embodiments is stored, and a computer (or CPU or MPU) of the system or apparatus may be stored Reading and executing the program code stored in the storage medium.
  • some or all of the actual operations may be performed by an operating system or the like operating on a computer based on instructions of the program code. It is also possible to write the program code read out from the storage medium into a memory set in an expansion board inserted into the computer or into a memory set in an expansion unit connected to the computer, and then install the program based on the instruction of the program code.
  • the expansion board or the CPU or the like on the expansion unit performs part and all of the actual operations to implement the functions of any of the above embodiments.
  • Storage medium embodiments for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), Tape, non-volatile memory card and ROM.
  • the program code can be downloaded from the server computer by the communication network.

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  • Analogue/Digital Conversion (AREA)

Abstract

La présente invention concerne un procédé et un appareil pour le réglage dynamique de signaux de modulation de largeur d'impulsion, consistant à: déterminer un rapport cyclique cible et un nombre de bits de précision de commande; déterminer un nombre de bits pour des bits de commande de modulation de largeur d'impulsion, des bits de cache et des bits de compensation dynamique, respectivement, la somme du nombre de bits des bits de commande de modulation de largeur d'impulsion, des bits de cache et des bits de compensation dynamique étant égale au nombre de bits de précision de commande; déterminer une valeur de base sur la base du cycle de service cible, stocker la valeur de base dans les bits de commande de modulation de largeur d'impulsion, stocker des données de compensation de précision de la valeur de base dans les bits de mémoire cache, et stocker un paramètre de compensation dynamique dans les bits de compensation dynamique; utiliser la valeur de base et les données de compensation de précision pour générer un signal de modulation de largeur d'impulsion, et ajuster dynamiquement les données de compensation de précision sur la base du paramètre de compensation dynamique de façon à ajuster dynamiquement le signal de modulation de largeur d'impulsion. La présente invention permet d'améliorer la précision de commande de signaux de modulation de largeur d'impulsion et de réduire l'espace et les coûts d'une mémoire cache.
PCT/CN2017/097693 2017-08-16 2017-08-16 Procédé et appareil de réglage dynamique de signaux de modulation de largeur d'impulsion Ceased WO2019033306A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1419742A (zh) * 2000-03-23 2003-05-21 马科尼通讯有限公司 脉宽调制信号的产生方法和设备以及由脉宽调制信号控制的光学衰减器
US20130038360A1 (en) * 2011-08-09 2013-02-14 Renesas Electronics Corporation Timing control device and control method thereof
CN103442482A (zh) * 2013-08-12 2013-12-11 深圳市天微电子有限公司 发光二极管照明脉冲宽度调制驱动电路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1419742A (zh) * 2000-03-23 2003-05-21 马科尼通讯有限公司 脉宽调制信号的产生方法和设备以及由脉宽调制信号控制的光学衰减器
US20130038360A1 (en) * 2011-08-09 2013-02-14 Renesas Electronics Corporation Timing control device and control method thereof
CN103442482A (zh) * 2013-08-12 2013-12-11 深圳市天微电子有限公司 发光二极管照明脉冲宽度调制驱动电路

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