WO2019007082A1 - Chip encapsulation method - Google Patents

Abstract

The invention relates to a chip encapsulation method, comprising: providing a substrate (10), a chip (30) being disposed on the substrate (10); forming an encapsulation layer (40) for covering the substrate (10) and the chip (30), wherein there is a gap (50) between an upper surface of the chip remote from the substrate (10) and the layer of encapsulation (40); and partially removing the encapsulation layer (40) to expose the upper surface of the chip (30).

Description

Chip packaging method

Cross-reference to related applications

The present application claims priority to Chinese Patent Application No. JP-A No. No. No. No. No. No. No. No. No. No.

Technical field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a chip packaging method.

Background technique

With the continuous development of integrated circuit technology, electronic products are increasingly developing in the direction of miniaturization, intelligence and high reliability. However, integrated circuit packaging directly affects the performance of integrated circuits, electronic modules, and even the entire machine. With the gradual shrinking of integrated circuit chips and increasing integration, there is an increasing demand for integrated circuit packages.

Summary of the invention

Embodiments of the present disclosure provide a chip packaging method. The chip packaging method includes: providing a substrate on which a chip is disposed; forming an encapsulation layer to cover the substrate and the chip, wherein a distance between a top surface of the chip remote from the substrate and the encapsulation layer Having a void; and partially removing the encapsulation layer to expose the top surface of the chip.

In an embodiment of the present disclosure, a heat shrink layer is formed on the top surface of the chip before forming the encapsulation layer, wherein the encapsulation layer covers the substrate and the heat shrink layer. After forming the encapsulation layer, the heat shrink layer is heated to form the void.

In an embodiment of the present disclosure, partially removing the encapsulation layer further includes removing the heat shrink layer.

In an embodiment of the present disclosure, the heat shrink layer is a double-sided tape.

In an embodiment of the present disclosure, the material of the heat shrink layer includes a heat shrink resin.

In an embodiment of the present disclosure, heating the heat shrink layer includes heating the heat shrink layer from a side of the encapsulation layer remote from the substrate.

In an embodiment of the present disclosure, the encapsulation layer is partially removed by dry etching and/or wet etching.

In an embodiment of the present disclosure, partially removing the encapsulation layer includes: dry etching the encapsulation layer to thin the encapsulation layer; and performing wet etching on the thinned encapsulation layer Etched to expose the chip.

In an embodiment of the present disclosure, the chip packaging method further includes: forming a wiring layer and solder balls on the wiring layer over the chip and the encapsulation layer; and stripping the chip from the substrate .

In an embodiment of the present disclosure, the substrate includes a first substrate and a second substrate on the first substrate, the chip being disposed on the second substrate, wherein the first substrate is subjected to The stress is greater than the second substrate.

In an embodiment of the present disclosure, the second substrate includes a plurality of grooves, and the chip is placed in the groove.

In an embodiment of the present disclosure, the substrate is a panel level substrate.

DRAWINGS

In order to more clearly illustrate the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. Other drawings may also be obtained from those of ordinary skill in the art in light of the inventive work.

1 is a schematic view of a chip after packaging;

2 is a flow chart of a chip packaging method provided by the present disclosure;

3 is a schematic diagram of a gap formed between a chip and an encapsulation layer after the chip is packaged according to the present disclosure;

4 is a schematic view after partially removing the encapsulation layer on the basis of FIG. 3;

FIG. 5 is a flowchart of a chip packaging method provided by the present disclosure;

Figure 6 is a schematic view showing the formation of a wiring layer and solder balls on the basis of Figure 4;

Figure 7 is a schematic view of the chip after peeling off the substrate from the substrate;

FIG. 8 is a flowchart of a chip packaging method provided by the present disclosure;

9 is a schematic view of forming a heat shrink layer on a chip according to the present disclosure;

Figure 10 is a schematic view of the chip after packaging on the basis of Figure 9;

Figure 11 is a schematic illustration of a two-layer substrate provided by the present disclosure;

Figure 12 is a schematic illustration of a portion of a substrate including a recess and a chip placed within the recess.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. It is apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all of them. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without departing from the inventive scope are the scope of the disclosure.

FIG. 1 is a schematic view of a chip after packaging. A method of packaging a chip includes: after the chip 30 is disposed on the substrate, the chip 30 is directly packaged to form the package layer 40; thereafter, the package layer 40 is partially removed to expose the chip 30. However, in the process of achieving the above, when the encapsulation layer 40 is partially removed, the chip 30 is easily damaged. Moreover, when the encapsulation layer is partially removed by the chemical etching method, it is difficult to control the etching, so that it is difficult to accurately control the etching time and precision.

Embodiments of the present disclosure provide a chip packaging method. 2 is a flow chart of a chip packaging method provided by the present disclosure. FIG. 3 is a schematic diagram of a gap between a chip and an encapsulation layer after encapsulation of the chip and provided by the present disclosure. 4 is a schematic view after partially removing the encapsulation layer on the basis of FIG.

Referring to S10 and S11 in FIG. 2 and FIG. 3, a substrate 10 is provided, wherein the substrate 10 is provided with a chip 30 which is fixed on the substrate 10 by an adhesive layer 20 (described later). The encapsulation layer 40 is formed to cover the substrate 10 and the chip 30 with a gap 50 between the top surface of the chip 30 remote from the substrate 10 and the encapsulation layer 40.

Those skilled in the art will appreciate that the chip 30 can be adhesively bonded to the substrate 10 by an adhesive layer 20. The adhesive layer 20 is adhesive on both sides, that is, the adhesive layer 20 can be bonded to the substrate 10 and can bond the fixed chip 30.

It will be appreciated that chip 30 is a qualified chip 30.

In an exemplary embodiment of the present disclosure, the chip 30 may be placed at a predetermined position on the surface of the substrate 10 using a die attacher.

Depending on the size of the substrate 10 and the size of the chip 30, the adhesive layer 20 may be provided to fix dozens, hundreds, or even more chips 30 at predetermined positions on the surface of the substrate 10.

Referring to S12 and FIG. 4 in FIG. 2, the encapsulation layer 40 is partially removed to expose the top surface of the chip 30.

In an exemplary embodiment of the present disclosure, the method of partially removing the encapsulation layer 40 may include a chemical etching method such as a dry method, a wet etching process, or the like, or a physical method such as flattening.

It should be noted that the top surface of the chip 30 remote from the substrate 10 is the front surface of the chip 30.

The embodiment of the present disclosure provides a chip packaging method. By leaving the chip 30 away from the top surface of the substrate 10 and the package layer 40, a gap 50 is formed, which is equivalent to forming a buffer interface between the package layer 40 and the chip 30. Any method of removing the encapsulation layer can reduce damage to the chip 30. In addition, when the chemical etching method is employed, the etching can be made easier by partially removing the encapsulation layer 40 to expose the chip 30 due to the presence of the voids 50, and the etching process is easily controlled, thereby making the remaining encapsulation layer 40 is more uniform.

FIG. 5 is a flowchart of a chip packaging method provided by the present disclosure. Fig. 6 is a view showing the formation of a wiring layer and a solder ball on the basis of Fig. 4. Figure 7 is a schematic view of the chip after it has been peeled off from the substrate on the basis of Figure 6.

Referring to S13 and FIG. 6 in FIG. 5, a wiring layer 60 and solder balls 70 on the wiring layer 60 are formed over the chip 30 and the encapsulation layer 40.

It will be appreciated that chip 30 includes a semiconductor device or integrated circuit that has been fabricated on a semiconductor substrate. For example, chip 30 can include a substrate comprising silicon or other semiconductor material, an insulating layer on the substrate, conductive features (including such as metal pads, plugs, vias, or wires) and contact pads over the conductive features. . After the fabrication of the chip 30 is completed, the chips 30 are separated from one another to perform the packaging process of the present disclosure.

Further, the wiring layer 60 is electrically connected to the contact pads on the chip 30. The wiring layer 60 extends beyond the edges of the chip 30 to form a fan-out structure, so that better connectivity and design flexibility can be achieved.

In an exemplary embodiment of the present disclosure, the material of the wiring layer 60 may include copper, a copper alloy, or the like. The wiring layer 60 may be formed in the dielectric layer.

In an exemplary embodiment of the present disclosure, the solder ball 70 is a metal material including a metal such as tin, lead, copper, silver, gold, rhodium, or an alloy thereof. The method of forming the solder balls 70 includes printing, ball implantation, laser sintering, electroplating, electroless plating, sputtering, and the like.

Referring to S14 and FIG. 7 in FIG. 5, the chip 30 is peeled off from the substrate 10. That is, the chip 30 is separated from the adhesive layer 20. The chip 30 should not be damaged during the separation. The adhesive layer 20 can be applied to the adhesive layer 20 by, for example, chemical, heating, light, or the like to separate the chip 30 from the adhesive layer 20.

A chip packaging method will be specifically described below.

FIG. 8 is a flowchart of a chip packaging method provided by the present disclosure. FIG. 9 is a schematic view of a heat shrink layer formed over a chip according to the present disclosure. FIG. 10 is a schematic view after the chip is packaged on the basis of FIG. 9. FIG.

Referring to S20 and FIG. 9 in FIG. 8, a substrate 10 is provided, wherein the substrate 10 is provided with a chip 30 which is fixed on the substrate 10 by an adhesive layer 20; and a top surface of the chip 30 remote from the substrate 10. A heat shrink layer 80 is formed thereon.

As an example, the heat shrink layer 80 can be a double sided tape. Double-sided tape has lower cost and better heat shrinkage.

As another example, the heat shrink layer 80 includes a heat shrink resin. The heat shrink resin is, for example, a material which may include acrylic. When used, a heat-shrinkable resin material having a lower cost and a better heat shrinkability can be selected.

Referring to S21 and FIG. 10 in FIG. 8, an encapsulation layer 40 is formed to cover the substrate 10 and the heat shrink layer 80.

Since the epoxy molding compound (Epoxy Molding Compound, EMC for short) has a good sealing property, it is easy to package the chip. Therefore, the material of the encapsulation layer 40 is preferably EMC.

As an example, EMC is prepared by mixing an epoxy resin as a matrix resin, a phenol resin as a curing agent, and some fillers (such as fillers, flame retardants, colorants, coupling agents, and the like). Then, under the action of heat and a curing agent, the epoxy group of the epoxy resin is opened and chemically reacted with the phenol resin to produce cross-linking curing, thereby making the mixture into a thermosetting plastic.

The method of forming the encapsulation layer may include: pressing the EMC into the cavity by transfer molding, and embedding the chip 30. The EMC is thermally cured to form the encapsulation layer 40.

Referring to S22 and FIG. 3 in FIG. 8, a heat shrink layer 80 (not shown) is heated to form a void 50 between the top surface of the chip 30 away from the substrate 10 and the encapsulation layer 40.

It should be noted that since the heat shrink layer 80 is located between the top surface of the chip 30 and the encapsulation layer 40, heating of the heat shrink layer 80 alone is not easily achieved in the process. Therefore, the structure including the substrate 10, the chip 30, and the encapsulation layer 40 can be heated. Further, in order to prevent the adhesive layer 20 from being separated from the chip 30 by the influence of heating, heating may be performed from the side of the encapsulating layer 40.

It should be noted that after heating the heat shrink layer 80, there should be a heated heat shrink layer 80 at the void 50, which is not shown in FIG.

Referring to S23 and FIG. 4 in FIG. 8, the encapsulation layer 40 is partially removed to expose the top surface of the chip 30.

In an exemplary embodiment of the present disclosure, the encapsulation layer 40 may be partially removed by dry etching and/or wet etching.

When the dry etching and wet etching processes are employed, the specific steps of partially removing the encapsulation layer 40 are: dry etching the encapsulation layer 40 to thin the encapsulation layer 40; and thinning the encapsulation layer 40 A wet etch is performed to expose the top surface of the chip 30 away from the substrate 10.

By combining dry etching and wet etching, on the one hand, relatively only wet etching can avoid excessive corrosion of the chip 30 caused by excessive etching property of the etching liquid, thereby further The damage to the chip 30 is reduced; on the other hand, the etching speed can be increased by using only dry etching.

Referring to S24 and S25 and FIG. 6 in FIG. 8, the heat shrink layer 80 is removed; and the wiring layer 60 and the solder balls 70 on the wiring layer 60 are formed over the chip 30 and the package layer 40.

Referring to S26 and FIG. 7 in FIG. 8, the chip 30 is peeled off from the substrate 10.

Embodiments of the present disclosure form a void between the top surface of the chip 30 away from the substrate 10 and the encapsulation layer 40 by forming a heat shrink layer 80 over the chip 30 and heating the heat shrink layer 80 to shrink after forming the encapsulation layer 40. 50, making the process easier to implement.

Figure 11 is a schematic illustration of a two layer substrate provided by the present disclosure. Figure 12 is a schematic illustration of a portion of a substrate including a recess and a chip placed within the recess.

Alternatively, as shown in FIG. 11, the substrate 10 includes a first substrate 101 and a second substrate 102 on the first substrate 101. The chip 30 is disposed on the second substrate 102. The first substrate 101 is subjected to a greater stress than the second substrate 102.

By employing a two-layer substrate, it is not limited to the size of the current silicon substrate, and thus a two-layer substrate of a larger size can be selected as the substrate of the package of the present disclosure. This improves packaging efficiency as well as output efficiency and enhances the overall substrate's resistance to bending, impact, and multilayer processes.

Further, as shown in Fig. 12, the second substrate 102 includes a plurality of grooves, and the chip 30 is placed in the grooves.

In an exemplary embodiment of the present disclosure, the thickness of the groove may be equal to the thickness of the second substrate 102. That is, the second substrate 102 is etched through when the grooves are formed. In this case, the groove corresponds to the through hole. Alternatively, the thickness of the groove is less than the thickness of the second substrate 102. That is, the second substrate 102 is not inscribed when the grooves are formed.

In an exemplary embodiment of the present disclosure, the size of the groove may be greater than or equal to the size of the chip 30. It is contemplated that there may be errors in placing the chip 30, preferably the size of the recess is larger than the size of the chip 30 to ensure that the chip 30 can be completely placed within the recess.

In one aspect, placing the chip 30 in the recess of the second substrate 102 can make the difference between the top surface of the chip 30 away from the first substrate 101 and the top surface of the second substrate 102 away from the top surface of the first substrate 101 The flatness can reduce the subsequent process difficulty and enhance the process uniformity. On the other hand, the convex portion of the second substrate 102 located between the grooves can reduce the amount of the molding material during subsequent packaging. Since the stress of the molding material is large, the stress acting on the second substrate 102 and the first substrate 101 can be reduced when the amount of the molding material is reduced.

In an exemplary embodiment of the present disclosure, the substrate 10 is a panel level substrate. That is, the size of the substrate 10 can be the same as the size of the substrate in the display field.

On the one hand, since the device base of the display field can correspond to a larger substrate (for example, a square substrate of 2 meters), the size of the substrate 10 of the embodiment of the present disclosure is made into the size of the panel-level substrate, so that the subsequent packaging process can be Displayed in the production line of the field. Thereby, the integration of the chip package and the panel display process is realized, thereby achieving higher output efficiency. On the other hand, Printed Circuit Board (PCB) devices with very low resolution (about 5um) are currently used for fan-out packaging. However, due to poor device accuracy, the PCB industry can only be used for low- to mid-end packages. . The embodiments of the present disclosure can achieve higher resolution (about 1 um) by using devices in the display field, and thus can correspond to the high-end market.

The above is only the specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the disclosure. It should be covered within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be determined by the scope of the claims.

Claims (12)

A chip packaging method comprising: Providing a substrate on which a chip is disposed; Forming an encapsulation layer to cover the substrate and the chip, wherein a gap between the top surface of the chip remote from the substrate and the encapsulation layer; The encapsulation layer is partially removed to expose the top surface of the chip. The chip packaging method according to claim 1, wherein a heat shrink layer is formed on the top surface of the chip before forming the package layer, wherein the package layer covers the substrate and the heat Shrink layer, After forming the encapsulation layer, the heat shrink layer is heated to form the void. The chip packaging method according to claim 2, wherein the partially removing the encapsulation layer further comprises: removing the heat shrink layer. The chip packaging method according to claim 2, wherein the heat shrink layer is a double-sided tape. The chip packaging method according to claim 2, wherein the material of the heat shrink layer comprises a heat shrink resin. The chip packaging method according to claim 2, wherein heating the heat shrink layer comprises heating the heat shrink layer from a side of the encapsulation layer remote from the substrate. The chip packaging method according to claim 1, wherein the encapsulation layer is partially removed by dry etching and/or wet etching. The chip packaging method according to claim 7, wherein Drying the encapsulation layer to thin the encapsulation layer; The thinned encapsulation layer is wet etched to expose the chip. The chip packaging method according to claim 1, further comprising: Forming a wiring layer over the chip and the encapsulation layer and solder balls on the wiring layer; The chip is peeled from the substrate. The chip packaging method according to claim 1, wherein the substrate comprises a first substrate and a second substrate on the first substrate, the chip being disposed on the second substrate, Wherein the first substrate is subjected to a greater stress than the second substrate. The chip packaging method according to claim 10, wherein the second substrate comprises a plurality of grooves, and the chip is placed in the groove. The chip packaging method according to any one of claims 1 to 11, wherein the substrate is a panel level substrate.

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