WO2019005001A1

WO2019005001A1 - Trench isolation profile engineering for iii-n device components

Info

Publication number: WO2019005001A1
Application number: PCT/US2017/039365
Authority: WO
Inventors: Marko Radosavljevic; Sansaptak DASGUPTA; Han Wui Then; Tristan A. TRONIC; Paul B. Fischer
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2017-06-27
Filing date: 2017-06-27
Publication date: 2019-01-03
Anticipated expiration: 2019-12-27

Abstract

Disclosed herein are device assemblies implementing trench isolation with modified profiles. An exemplary device assembly includes a III-N channel material and comprises a first region with a first III-N device component, a second region with a second III-N device component, and a trench therebetween. The trench has a first depth at a first area and a second depth at a second area, where the first area is closer to the first region than the second area, and the first depth is greater than the second depth. Providing different depths in a trench that isolates two adjacent III-N device regions, in particular making the trench deeper in areas of the trench which are closest to the respective III-N device regions and making it shallower in the middle, may reduce current leakage between adjacent III-N devices (i.e. improve isolation) while, at the same time, advantageously preserving relatively shallow trench profile.

Description

TRENCH ISOLATION PROFILE ENGINEERING FOR lll-N DEVICE COMPONENTS

Technical Field

[0001] This disclosure relates generally to the field of semiconductor devices, and more specifically, to lll-N transistor devices/arrangements with modified profiles of trenches used for providing electrical isolation between adjacent lll-N device components.

Background

[0002] Solid-state devices that can be used in high voltage and/or high frequency applications are of great importance in modern semiconductor technologies. For example, power management integrated circuits (PMIC) and radio frequency integrated circuits ( FIC) may be critical functional blocks in system on a chip (SoC) implementations. Such SoC implementations may be found in mobile computing platforms such as smartphones, tablets, laptops, netbooks, and the like. In such implementations, the PMIC and RFIC are important factors for power efficiency and form factor, and can be equally or even more important than logic and memory circuits.

[0003] Due, in part, to their large bandgap and high mobility, lll-N material based transistors, such as e.g. gallium nitride (GaN) based transistors, may be particularly advantageous for high voltage and/or high frequency applications. For example, because GaN has a larger band gap (-3.4 eV) than silicon (Si; ~1.1 eV), a GaN transistor should be able to withstand a larger electric field (resulting e.g. from applying a large voltage to the drain, Vdd) before suffering breakdown, compared to a Si transistor of similar dimensions. Furthermore, GaN transistors may advantageously employ a 2D electron gas (i.e. a group of electrons, an electron gas, free to move in two dimensions but tightly confined in the third dimension, e.g. a 2D sheet charge) as its transport channel, enabling high mobilities without using impurity dopants. For example, the 2D sheet charge may be formed at an abrupt hetero-interface formed by epitaxial deposition, on GaN, of a charge-inducing film of a material having larger spontaneous and piezoelectric polarization, compared to GaN (such a film is generally referred to as a "polarization layer"). Providing a polarization layer on a lll-N material such as GaN allows forming very high charge densities, e.g. densities of about 2-10¹³ charges per square centimeter (cm²), without impurity dopants, which, in turn, enables high mobilities, e.g. mobilities greater than about 1000 cm²/(V-s).

[0004] Despite the advantages, there are some challenges in manufacturing lll-N transistors (or, in general, lll-V device components) which hinder their large-scale implementation. One such challenge resides in providing adequate trench isolation in a manner that is sufficiently compatible with planarization techniques used in modern very-large-scale integration (VLSI) processing. As used in the art, "trench isolation" (also sometimes referred to as "shallow trench isolation (STI)" or "box isolation") generally refers to integrated circuit features or techniques which aim to prevent electric current leakage between adjacent semiconductor device components. The challenge of reducing current leakage between adjacent lll-V device components becomes especially pronounced when considered in context with some common applications of such components. For example, because such components are often targeted for high voltage applications, trench isolation schemes have to be able to withstand significantly higher voltages than voltages typically present in other applications (e.g. significantly higher voltages compared to typical silicon logic devices), which is not an easy task. Improvements in this respect may be desirable.

Brief Description of the Drawings

[0005] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0006] FIGS. 1A-1D are cross-sectional side views illustrating challenges in providing trench isolation for lll-V semiconductor devices.

[0007] FIG. 2 is a cross-sectional side view providing a schematic illustration of implementing trench isolation with modified profiles to reduce isolation leakage between adjacent lll-N device components, according to some embodiments of the present disclosure.

[0008] FIG. 3 provides a schematic illustration of an exemplary real-life structure with a trench having a modified profile, according to some embodiments of the present disclosure.

[0009] FIG. 4 is a flow diagram of an example method of manufacturing a lll-N semiconductor device assembly implementing trench isolation with modified profiles, in accordance with various embodiments of the present disclosure.

[0010] FIGS. 5A and 5B are top views of a wafer and dies that include one or more lll-N

semiconductor device assemblies implementing trench isolation with modified profiles in accordance with any of the embodiments disclosed herein.

[0011] FIG. 6 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more lll-N semiconductor device assemblies implementing trench isolation with modified profiles in accordance with any of the embodiments disclosed herein.

[0012] FIG. 7 is a cross-sectional side view of an IC device assembly that may include one or more lll-N semiconductor device assemblies implementing trench isolation with modified profiles in accordance with any of the embodiments disclosed herein.

[0013] FIG. 8 is a block diagram of an example computing device that may include one or more lll-N semiconductor device assemblies implementing trench isolation with modified profiles in accordance with any of the embodiments disclosed herein. Detailed Description

[0014] Disclosed herein are device assemblies implementing trench isolation with modified profiles aiming to provide improvements in electrical isolation of adjacent lll-N device components. As used herein, the term "lll-N device component" (or, simply, "lll-N device") refers to a device component, such as e.g. a transistor, which employs one or more of group III semiconductor material(s) and nitrogen, e.g. GaN, as active materials. While some embodiments described herein refer to lll-N transistors (i.e. transistors employing one or more lll-N materials as a channel material), these embodiments are equally applicable to any lll-N device components besides lll-N transistors, such as e.g. lll-N diodes, sensors, light-emitting diodes (LEDs), and lasers.

[0015] In one aspect of the present disclosure, an exemplary device assembly includes a substrate and a channel material provided over the substrate, the channel material including a lll-N semiconductor material and comprising a first region, a second region, and a trench between the first and the second regions. The first and second regions are regions in which, respectively, a first and a second lll-N device components are, or will be, provided. The trench has different depths at different areas - namely, the trench has a first depth at a first trench area and a second depth at a second trench area, where the first trench area is closer to the first region than the second trench area, and the first depth is greater than the second depth. As described in greater detail below, providing different depths in a trench that isolates two adjacent lll-N device regions, in particular making the trench deeper in areas of the trench which are closest to the respective lll-N device regions and making the trench shallower in the middle, may reduce current leakage between adjacent lll-N devices (i.e. improve isolation) while, at the same time, advantageously preserving relatively shallow trench profile. Having a relatively shallow trench profile enables having a relatively small device pitch (i.e. center to center distance between adjacent lll-N devices or between adjacent lll-N device regions) and makes subsequent processing, such as e.g. filling of the trench with a dielectric material and smoothing out the surface, easier. Since the first region and the second region are portions which are elevated with respect to the valley (i.e. the bottom) of the trench, these regions may be referred to herein as first and second "islands."

[0016] lll-N semiconductor device assemblies implementing trench isolation with modified profiles as described herein may be implemented in one or more components associated with an integrated circuit (IC) or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC, provided as an integral part of an IC, or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

[0017] For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0018] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which are shown, by way of illustration, embodiments that may be practiced. The accompanying drawings are not necessarily drawn to scale. For example, to clarify various layers, structures, and regions, the thickness of some layers may be enlarged. Furthermore, while drawings illustrating various structures/assemblies of exemplary devices may be drawn with precise right angles and straight lines, real world process limitations may prevent implementations of devices exactly as shown. Therefore, it is understood that such drawings revised to reflect example real world process limitations, in that the features may not have precise right angles and straight lines, are within the scope of the present disclosure. Drawings revised in this manner may be more representative of real world structure/assemblies as may be seen on images using various characterization tools, such as e.g. scanning electron microscopy (SEM) or transmission electron microscopy (TEM). In addition, the various structures/assemblies of the present drawings may further include possible processing defects, such as e.g. the rounding of corners, the drooping of the layers/lines, unintentional gaps and/or discontinuities, unintentionally uneven surfaces and volumes, etc., although these possible processing defects may not be specifically shown in the drawings. It is to be understood that other embodiments may be utilized and structural or logical changes to the drawings and descriptions may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0019] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment.

Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. [0020] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0021] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. Furthermore, stating in the present disclosure that any part (e.g. a layer, film, area, or plate) is in any way positioned on or over (e.g. positioned on/over, provided on/over, located on/over, disposed on/over, formed on/over, etc.) another part means that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located

therebetween. On the other hand, stating that any part is in contact with another part means that there is no intermediate part between the two parts.

[0022] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0023] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. In some examples, as used herein, a "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. In another example, the term "connected" means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term "coupled" means either a direct electrical or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. [0024] For purposes of illustrating lll-N semiconductor device assemblies implementing trench isolation with modified profiles as proposed herein, it is important to understand the phenomena that may come into play in a typical assembly having two or more lll-N devices provided on a single substrate. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications. For example, in the following, some descriptions are provided with reference to GaN transistors as examples of lll-N devices. However, descriptions provided herein are equally applicable to transistors employing group lll-N semiconductor channel materials other than GaN, and/or to lll-N devices other than transistors.

[0025] The performance of an assembly where a plurality of lll-N transistors are provided on a single substrate may depend on a number of factors. For example, one factor is the quality of the III- N semiconductor layer that serves as a channel material for the transistors and forms a basis in which the transistors are built. Typically, but not necessarily, such a lll-N channel material is provided over a substrate by epitaxial growth. Also typically, but not necessarily, first, a buffer layer is provided over the substrate, and then the lll-N channel material layer is grown over the buffer layer. A buffer layer is a layer of a semiconductor material that has a bandgap larger than that of the channel material, so that the buffer layer can serve to prevent current leakage from the future lll-N transistors to the substrate and to enable better epitaxy of the channel material (i.e. to improve epitaxial growth of the channel material in terms of e.g. bridge lattice constant, amount of defects, etc.). For example, GaN may be used as the channel material, while AIGaN may be used as the buffer layer.

[0026] FIG. 1A shows a structure 100A having a substrate 102, a buffer layer 104 provided over the substrate 102, and a lll-N channel material 106 provided over the buffer layer 104, where, as described above, the buffer layer 104 is optional and may be absent in certain implementations. The thicker is the channel layer 106 (where a thickness of the channel layer is measured in the vertical direction of the view shown in FIG. 1A), the better is the quality of the lll-N channel material in the layer and the better is lll-N device performance. For example, a thickness of above about 500 nanometers (nm), preferably above about 1000 nm, may be required for the channel material 106. However, having such a thick layer of the lll-N layer is not without challenges, as will be described with reference to FIGS. IB-ID.

[0027] As described above, in order to provide electrical isolation between neighboring devices, regions of the channel material housing different devices are separated by trenches, a technique known as "trench isolation." FIG. IB illustrates a structure 100B which is a result of the structure 100A undergoing a process in which trenches 108-1 and 108-2 are created. The trenches 108 are openings formed in the channel material 106 (i.e. regions where the channel material 106 is removed from the original layer shown in FIG. 1A), leaving islands, shown in FIG. IB as regions 110, in which lll-N devices can be formed. The trenches separate different islands from one another, thus providing some electrical separation between the devices of these islands. In particular, as shown in FIG. IB, the trench 108-1 separates the region 110-1 and the region 110-2, while the trench 108-2 separates the region 110-2 and the region 110-3, where each of the regions 110 is an "island" (i.e. a portion of the channel material 106 that is left standing over/above the valleys 112 of the trenches 108) in which a different lll-N device component will be provided.

[0028] As is known in the field of IC manufacturing, etching openings to provide electrical separation and later filling those openings with one or more dielectrics may be challenging. In particular, the higher is the aspect ratio of the openings (i.e. a ratio between the depth and the width of the openings), the more challenging it becomes to both etch the openings in a controlled manner and later fill the openings with a high quality dielectric without defects such as e.g. voids left unfilled. Ideally, it would be desirable to form trenches 108 which would extend through the entire thickness of the channel material 106, but that would mean that either the aspect ratio of the trenches increases significantly, or the width of the trenches must be increased in order to have trenches with aspect ratios which are possible to form and fill with a dielectric. FIG. IB illustrates a scenario in which the trenches 108 do not extend through the entire thickness of the channel material 106, but which allow having three separate device regions on a certain area of a substrate. A drawback with such an implementation is that current can leak from one device region to the other via the channel material left below the trenches 108, schematically illustrated in FIG. IB with resistor signs in areas 114-1 and 114-2 in the channel material 106 still remaining below, respectively, the trenches 108-1 and 108-2. The current can also leak from one device region 110 to another via the buffer layer 104 (or the substrate 102, in case the buffer layer 104 is not used), which is schematically illustrated in FIG. IB with resistor signs in areas 116-1 and 116-2 in the buffer layer 104 (or the substrate 102) below, respectively, the trenches 108-1 and 108-2. Showing in FIG. IB the resistor signs in the channel material being smaller than those in the buffer layer/substrate indicates that current leakage through the channel material is greater than that through the buffer layer/substrate, in accordance with the Ohms law stating that current is inversely proportional to resistance. FIG. IB also schematically illustrates that the current leakage is greater

[0029] In contrast to FIG. IB, FIG. 1C illustrates a scenario showing a structure lOOC which may also be formed by creating trenches 108 in the channel material 106 of the structure 100A, but where the trenches 108 do extend through the entire thickness of the channel material 106 (thus, the only difference between FIG. IB and FIG. 1C is the depth of the trenches 108). While the structure lOOC allows eliminating current leakage via areas 114 shown in FIG. IB, the trenches 108 in the structure lOOC have such a high aspect ratio that they may be not easy to form to begin with (in a controlled manner) and is even more difficult to later uniformly fill with a dielectric material, i.e. such trench isolation is not manufacturable.

[0030] FIG. ID illustrates a solution to the drawbacks of FIG. 1C. As is shown with a structure 100D of FIG. ID, the trenches 108 which extend through the entire thickness of the channel material 106 may be made to preserve the manufacturable aspect ratio as shown e.g. in FIG. IB by

correspondingly increasing their width (i.e. a dimension measured in the horizontal direction in the view of FIGS. IB-ID). However, increasing the width of the trenches results in a situation shown in Fig. ID, where the same area on the substrate as that shown in FIG. IB now allows to have only two device regions 110, instead of three as in FIG. IB. Thus, this approach does not allow scaling to large number of devices in a given area.

[0031] Embodiments of the present disclosure provide device assemblies implementing trench isolation with modified profiles which may allow, simultaneously, reducing current leakage between adjacent lll-N devices (i.e. improving isolation) while, at the same time, advantageously preserving relatively shallow trench profile. FIG. 2 is a cross-sectional side view providing a schematic illustration of a structure 200 implementing such trench isolation with a modified profile, according to some embodiments of the present disclosure.

[0032] The structure 200 shown in FIG. 2 includes a substrate 202, a buffer layer 204 provided over the substrate 202, and a lll-N channel material 206 provided over the buffer layer 204.

[0033] The substrate 202 may be any substrate on which lll-N devices as described herein may be implemented. In some embodiments, the substrate 202 may include a semiconductor, such as silicon. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-N or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.

[0034] In some embodiments, the substrate 202 may include an insulating layer, sometimes referred to as an "interlayer dielectric" material (ILD), such as an oxide isolation layer, e.g. to electrically isolate the semiconductor material of the substrate 202 from the channel material 206, and thereby mitigate the likelihood that a conductive pathway will form between e.g. a source and a drain regions of a given lll-N transistor, or between neighboring lll-N transistors, through the substrate 202. Examples of ILDs that may be included in/on a substrate 202 in some embodiments may include silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride. The buffer layer 204 may be viewed as an example of such an insulating layer. When used, the buffer layer 204 may be a layer of a semiconductor material that has a bandgap larger than that of the channel material, so that the buffer layer can serve to prevent current leakage from the future lll-N transistors to the substrate and to enable better epitaxy of the channel material (i.e. to improve epitaxial growth of the channel material in terms of e.g. bridge lattice constant, amount of defects, etc.). For example, AIGaN may be used as the buffer layer 204 when the channel material 206 is GaN. In various embodiments when the buffer layer 204 is used, a thickness of such a layer (i.e. a dimension measured in the vertical direction of the view shown in FIG. 2) may be between about 500 and 5000 nm, including all values and ranges therein.

[0035] In general, the channel material 206 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In particular, for exemplary N-type transistor embodiments, the channel material 206 may advantageously be a lll-N material having a high electron mobility, such as, but not limited to GaN, InGaAs, InP, InSb, and InAs. For some ln_xGai- xAs fin embodiments, In content (x) is between 0.6 and 0.9, and advantageously is at least 0.7 (e.g., lno.7Gao.3As). For some such embodiments, the channel material 206 may be a ternary lll-N alloy, such as e.g. InGaN.

[0036] In some embodiments, the channel material 206 may be formed of a highly crystalline semiconductor, e.g. of substantially a monocrystalline semiconductor. In some embodiments, the channel material 206 may be formed of a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., N, P, As, Sb). In some embodiments, the channel material 206 may be a binary, ternary, or quaternary lll-N compound semiconductor that is an alloy of two, three, or even four elements from groups III and V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth.

[0037] In some embodiments, the channel material 206 may be an intrinsic lll-N semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel material 206, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the channel material 206 may be relatively low, for example below 10¹⁵ cm^"3, and advantageously below 10¹³ cm^"3. [0038] FIG. 2 further illustrates exemplary trenches 208-1 and 208-2 formed within the channel material 206. While two trenches 208 are shown in FIG. 2, this is for illustrative purposes only and, in various embodiments, more or less than two trenches 208 may be implemented.

[0039] Similar to FIGS. IB-ID, the trenches 208 are openings formed in the channel material 206 (i.e. regions where the channel material 206 is removed from the original layer of the channel material 206 deposited over the substrate 202), leaving/creating islands, shown in FIG. 2 as regions 210, in which lll-N devices can be formed. In particular, as shown in FIG. 2, the trench 208-1 separates a first region 210-1 (where a first lll-N device, e.g. a first lll-N transistor, can be provided) from a second region 210-2 (where a second lll-N device, e.g. a second lll-N transistor, can be provided), while the trench 208-2 separates the second region 210-2 from a third region 210-3 (where a third lll-N device, e.g. a third lll-N transistor, can be provided).

[0040] In contrast to the implementations of FIGS. IB-ID, at least some (but preferably all) of the trenches 208 have modified profiles in that the depth of the trenches is deliberately made uneven - namely, the portions of the trenches which are closest to the nearest islands are made deeper than the portions of the trenches substantially in the middle. Further details are explained with reference to the first trench 208-1, but the structure 200 may have one or more of additional other trenches similar to those of the first trench 208-1.

[0041] As shown in FIG. 2, the trench 208-1 may include a first area 218 where the trench has a first depth Dl, and a second trench area 220 where the trench has a second depth D2, which is less than the depth Dl. As also shown in FIG. 2, the trench 208-1 may also include a third area 222 where the trench also has the first depth Dl. The first and third areas 218 and 222 may be viewed as areas where the trench 208-1 has recesses, thus extending the depth of the trench further down with respect to the bottom 212-1 of the trench 208-1 in the second trench area 220.

[0042] The first area 218 is closer to the first island 210-1 than the second area 220. In fact, as shown in FIG. 2, in some embodiments, the first area 218 may be directly adjacent (i.e. in contact with) the first island 210-1. Similarly, the third area 222 is closer to the second island 210-2 than the second area 220. In fact, as shown in FIG. 2, in some embodiments, the third area 222 may be directly adjacent (i.e. in contact with) the second island 210-2.

[0043] In some embodiments, the trench may extend throughout the entire thickness of the channel material in the areas 218 and/or 222, as shown in FIG. 2 with the trench 208-1 extending into the buffer layer 204 in those areas (if the buffer layer is not used, then the trench 208-1 may similarly extend into the substrate 202 or whichever layer is provided between the substrate 202 and the channel material 206). In such embodiments, there may not be any channel material left under the areas 218 and/or 222 of the trench 208-1, while there may still be some channel material left under the area 220 of the trench 208-1, as also shown in FIG. 2. For example, in some embodiments, a thickness of the channel material 206 in the island regions 210 may be at least about 500 nanometers, including all values and ranges therein, e.g. at least about 1000 nanometers, or e.g. about between 750 and 1250 nanometers. If, in such embodiments, depth D2 is less than about 350 nm, then some channel material will be left under the area 220 of the trench 208-1. On the other hand, depth Dl may be at least about 500 nm, which means that the trench 208 is deeper in the first area 218 and in the third area 222, compared to the middle area 220, and that it may extend all through the channel material and even further into the layer under the channel material 206. It should be noted that, in general, the trench 208 does not have to extend all the way through the channel material 206 in the first and/or third areas 218 and 222 as shown in FIG. 2, and that, in other embodiments, having some channel material remaining under the first and/or third areas 218 and 222 would still result in improved isolation while preserving relatively shallow trench profile, compared to conventional implementations as shown in FIGS. IB-ID.

[0044] In various embodiments, the width of the trench 208-1, labeled in FIG. 2 as W_tr, may be between about 30 and 150 nanometers, including all values and ranges therein, e.g. between about 35 and 100 nm, or between 45 and 80 nm.

[0045] In some embodiments, a distance between the first/third trench area 218/222 and the second trench area 220, labeled as W_r in FIG. 2, may be between about 2 and 30 nm, including all values and ranges therein, e.g. between about 5 and 20 nm, or between about 8 and 15 nm. T

[0046] The depth of the trench 208-1 may gradually decrease from the outer trench areas 218/222 which are deeper towards the substantially central trench area 220 which is more shallow, as is shown in FIG. 2 with the recesses of the first trench area 218 and the third trench area 222 having substantially triangular profiles. However, in other embodiments, the recesses of the first/third trench areas 218/222 may have different shapes as those shown in FIG. 2.

[0047] In some embodiments, angles cti and ct₂, labeled in FIG. 2, may be at most about 45 degrees. Thus, the distance W_r between the first trench area and the second trench area (or an analogous distance between the third trench area and the second trench area) may be substantially equal to or less than a difference between the first depth Dl and the second depth D2.

[0048] Embodiments of the present disclosure are based on recognition that providing recesses in the trench near the islands allows removing additional channel material and disrupting the current path between neighboring lll-N devices/device regions 210, while still maintaining relatively shallow trench profile and relatively low aspect ratio of the trenches, which aspect ratio is manufacturable. Considering that a depth D2 of the trench is e.g. 350 nm, while the width W_tr is e.g. 150 nm, the trench would have an aspect ratio of 350/150. [0049] In various embodiments, a fin pitch, labeled in FIG. 2 as FP, which is a distance between centers of adjacent islands (e.g. a distance between a center of the first region 210-1 and a center of the second region 210-2) may be between about 45 and 200 nanometers, including all values and ranges therein, e.g. between about 55 and 150 nm, or between about 60 and 120 nm.

[0050] In some embodiments, the channel material 206 may be a stack of materials in that it may also include a polarization layer as an upper-most layer of the channel material 206 (i.e. the material above the dotted line 224 shown in FIG. 2 near the surface of the channel material 206). As described above, a polarization layer is a charge-inducing film of a material having larger spontaneous and piezoelectric polarization than that of the bulk (i.e. the rest) of the channel material (i.e. the material below the dotted line 224 shown in FIG. 2), creating a hetero-interface with the bulk portion of the channel material and leading to formation of 2DEG at that interface. In various embodiments, such a polarization layer may include materials such as e.g. AIN, InAIN, or AIGaN, and may have a thickness between about 2 and 30 nm, including all values and ranges therein e.g. between about 5 and 15 nm.

[0051] Although not specifically shown in FIG. 2, the trenches 208 may subsequently be filled with a dielectric material. In some embodiments, such a dielectric material may be a low-k dielectric (i.e. a dielectric material that has a lower dielectric constant (k) than silicon dioxide). Examples of low-k materials that may be used may include, but are not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, spin-on organic polymeric dielectrics such as e.g.

polyimide, polynorbornenes, benzocyclobutene, and polytetrafluoroethylene (PTFE), or spin-on silicon based polymeric dielectric such as e.g. hydrogen silsesquioxane (HSQ) and

methylsilsesquioxane (MSQ)). Other examples of low-k materials that may be used to fill the trenches 208 include various porous dielectric materials, such as for example porous silicon dioxide or porous carbon-doped silicon dioxide, where large voids or pores are created in a dielectric in order to reduce the overall dielectric constant of the layer, since voids can have a dielectric constant of nearly 1.

[0052] In various embodiments, the dimensions of the trenches 208 and, in particular, those of the first and third areas 218 and 222 as described herein can take on any suitable values, and these elements may have any suitable shapes, as long as they can be supported by a manufacturing process used to form them. For example, considerations such as e.g. aspect ratio that is possible to achieve with a suitable manufacturing process may have influence on the exact first and second depths Dl and D2, the width of the trench W_tr, and the width W_r of the recesses in the first/third areas 218/222. In another example, considerations such as particular etching processes used for creating the trenches 208 and/or for creating the recesses in the first/third areas 218/222 may have influence on the exact profile of the trenches 208.

[0053] It should be noted that, while illustrations and descriptions provided herein refer to the trenches having recesses in both the area closest to one of the island regions (e.g. the first area 218) and the area closest to the other one of the island regions (e.g. the third area 222), i.e. on both sides of the trench, in other embodiments, such recesses may be implemented only on one side (e.g. only in the first area 218 or only in the third area 222, and the other one of these areas may have a depth substantially equal to the depth D2 in the middle trench portion 220). Similarly, while recesses in the first area 218 and the third area 222 are shown as substantially symmetric (e.g. with respect to a centerline of the trench 208), this is illustrated only because, with typical manufacturing techniques, this is often what is easier, or possible, to manufacture. In general, the recesses in the first area 218 and the third area 222 do not have to be symmetrical (e.g. these recesses may have different shapes and/or different depths other than the ones shown in FIG. 2), as long as their depths are higher than that in the middle trench portion 220, to create improved isolation with a relatively shallow trench profile as defined by the depth D2, as described herein.

[0054] Thus, e.g. with reference to FIG. 2, while the recesses in the trenches 208 are illustrated in FIG. 2 with going towards the middle portion 220 with straight tilted lines (forming angles cti and ct₂ with the corresponding islands), in other embodiments, the recess on each side of a trench may have other shapes and forms, and the recess on the source side of a given trench 208 may be different from the recess on the other side of that trench. In general, any number of recesses at the edges of a trench, with each recess having any suitable three-dimensional (3D) shape (i.e. not necessarily with a straight tilted line profile as shown in FIG. 2) are within the scope of the present disclosure.

[0055] Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g. optical microscopy, Transmission Electron Microscopy (TEM), or Scanning Electron Microscopy (SEM), and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using e.g. Physical Failure Analysis (PFA) would allow determination of the modified trench profiles as described herein.

[0056] FIG. 3 provides a schematic illustration of an exemplary real-life structure 300 with an opening 308 having a modified profile with recesses as described herein, according to some embodiments of the present disclosure. FIG. 3 represents a cross-section view similar to that shown in FIG. 2, in particular a view of the trench 308, except that only on trench is shown in FIG. 3.

Elements indicated in FIG. 3 with reference numerals 302, 304, 306, 308, and 310 are

similar/analogous to elements indicated with, respectively, reference numerals 202, 204, 206, 208, and 210, described above. Thus, in the interests of brevity, detailed discussions of these elements are not repeated here. FIG. 3 further illustrates a dielectric material 326 filling the trench 308, also as described above with reference to FIG. 2, although not specifically shown in FIG. 2.

[0057] As can be seen, FIG. 3 is drawn to reflect example real world process limitations, in that the features are not drawn with precise right angles and straight lines. Such a structure could be visible in e.g. an SEM image or a TEM image of a lll-N device assembly such as the lll-N device assembly 300. In such an image of a real structure, possible processing defects could also be visible, such as e.g. egregious surface roughness of the trench interfaces, particles in the film, and/or potential intermixing between various layers (i.e. non-discrete interfaces).

[0058] While FIG. 2 illustrates trenches 208 as openings having perfectly straight profiles, i.e. profiles where the openings have sidewalls extending perpendicularly from the surface, because such profiles are often desirable for trenches, they are not always achievable in real world manufacturing processes. Namely, a real world opening for a trench in accordance with various embodiments described herein, although designed to have a straight profile, may end up having a so-called "re-entrant" profile, where the width at the top of the opening is smaller than the width at the bottom of the opening, as is illustrated in FIG. 3. In other embodiments, some of the real world trenches in accordance with various embodiments described herein may have a so-called "non-reentrant" profile, where the width at the top of the opening is larger than the width at the bottom of the opening (not specifically shown in FIGS.). Oftentimes, as a result of a trench not having perfectly straight sidewalls, imperfections may form within the dielectric material 326 filling the trench. For example, typical for re-entrant profiles, a void may be formed in the center of the trench, where the growth of the dielectric material 326 pinches off at the top of a re-entrant profile opening, shown in FIG. 3 as a void 328, substantially triangular in form. In other implementations, the dielectric material 326 may form a seam substantially in the center of the trench, instead of a void (not shown in FIG. 3), which sometimes happens with non-re-entrant profile trenches.

[0059] FIG. 3 also illustrates that voids 330 may form at the bottom of the recesses in the trench 308, because it may be difficult to uniformly get dielectric material in such small features.

[0060] In various embodiments, isolation trenches with modified profiles as described herein may be included in lll-N semiconductor device assemblies where the lll-V device components provided in the islands separated by trenches are lll-N transistors of any suitable transistor structure. For example, such trenches may be used to isolate transistors having any planar architecture as known in the art, such as e.g. single-gate or double-gate transistors, as well as within transistors having a non-planar architectures such as e.g. tri-gate/FinFET or all-around gate transistors. FinFETs refer to transistors having a non-planar architecture where the channel material is shaped as a fin that extends away from a base. FinFETs are sometimes referred to as "tri-gate transistors," where the name "tri-gate" originates from the fact that, in use, such a transistor may form conducting channels on three "sides" of the fin. FinFETs potentially improve performance relative to single-gate transistors and double-gate transistors. All-around gate transistors refer to transistors where the channel material is shaped as a wire and the gate stack wraps around the wire. All-around gate transistors may form conducting channels on more than three "sides" of the wire, potentially improving performance relative to FinFETs.

[0061] The lll-N device assemblies illustrated in FIGS. 2-3 do not represent an exhaustive set of assemblies in which trench isolation with modified profiles as described herein may be

implemented, but merely provide examples of such structures/assemblies. Although particular arrangements of materials are discussed with reference to FIGS. 2-3, intermediate materials may be included in the transistor devices of these FIGS. Note that FIGS. 2-3 are intended to show relative arrangements of the components therein, and that lll-N device components of these FIGS, may include other components that are not specifically illustrated (e.g., various interfacial layers).

Additionally, although some elements of the lll-N device assembly are illustrated in FIG. 2 as being planar rectangles or formed of rectangular solids, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies.

[0062] The lll-N device assemblies implementing trench isolation with modified profiles as described herein may be manufactured using any suitable techniques. For example, FIG. 4 is a flow diagram of an example method 400 of manufacturing a lll-N semiconductor device assembly implementing trench isolation with modified profiles, in accordance with various embodiments of the present disclosure. Although the operations of the method 400 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture, substantially simultaneously, multiple trenches with modified profiles as described herein or/and multiple lll-N device assemblies implementing trench isolation with modified profiles as described herein. In another example, the operations may be performed in a different order to reflect the structure of a lll-N device assembly in which one or more trenches with modified profiles as described herein will be included.

[0063] At 402, one or more lll-N semiconductor materials for forming a channel material layer may be provided over a substrate. The one or more semiconductor materials provided at 402 may take the form of any of the embodiments of the channel material 206 disclosed herein and the substrate may take form of any of the embodiments of the substrate 202, for example (e.g., any of the embodiments discussed herein with reference to the structure 200/300 and other lll-N device assemblies with isolation trenches having modified profiles described herein). The channel material may be provided at 402 using any suitable deposition and patterning techniques known in the art, such as e.g. epitaxial growth/deposition. In this context, epitaxial growth refers to the deposition of a crystalline overlayer in the form of the desired lll-N semiconductor channel material on a crystalline underlayer such as e.g. the substrate 202 or the buffer layer 204. The buffer layer 204 described herein may also be provided as a part of the process 402, using any suitable deposition and patterning techniques known in the art. The epitaxial growth of 402 may be carried out using any known gaseous or liquid precursors for forming the desired channel material 202 and, optionally, the buffer layer 204.

[0064] At 404, the channel material provided at 402 is etched to form shallow trench openings for isolating regions with various lll-N device components from one another. As used herein, forming shallow trench openings means that trenches as known in the art (i.e. without recesses and without deliberate variations in the depth within each opening) are formed at 404, the trenches having a depth D2 shown in FIG. 2, using any of the etching processes as known in the art. For example, the etch performed at 404 may include performing an anisotropic etch, using etchants in a form of e.g. chemically active ionized gas (i.e. plasma) using e.g. bromine (Br) and chloride (CI) based chemistries. In some embodiments, during the etch at 404, the structure in which the trench openings are formed may be heated to elevated temperatures, e.g. to temperatures between about room temperature and 200 degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface

[0065] At 406, a second etching process is performed in that the edges of the shallow trenches formed at 404 are etched further to form recesses within the trenches which go as deep as to the depth Dl shown in FIG. 2. Performing the etch at 406 may include performing an ion channeling etch at the edges of the trenches formed at 404, which may e.g. be achieved by utilizing a hard mask material which can easily charge up, such as an insulating material, such as e.g. silicon oxide or silicon nitride, which, in turn, leads to steering ions in the plasma. Specifically negatively charge hard mask will focus positively charged ions toward trench sidewalls thus resulting in higher etch rate in the areas 218 and 222. As a result of performing the etch at 406, trenches with modified profiles as described herein are formed, where edges of the trenches extend deeper into the structure than the middle portions of the trenches. Such trenches provided at 406 may take the form of any of the embodiments of the trenches 208/308 disclosed herein (e.g., any of the embodiments discussed herein with reference to the structure 200/300 and other lll-N device assemblies with isolation trenches having modified profiles described herein).

[0066] At 408, lll-N device components, e.g. lll-N transistors, may be provided in the islands separated by the trenches, using any suitable processes as known in the art. While FIG. 4 illustrates the process 408 as being performed after formation of the trenches with the modified trench profiles, in other embodiments, the lll-N device components may be formed first within the layer of the channel material provided at 402, followed by the formation of the trenches with the modified trench profiles as described herein.

[0067] The lll-N device assemblies having one or more isolation trenches with modified profiles as disclosed herein may be included in any suitable electronic device. FIGS. 5A-8 illustrate various examples of apparatuses that may include one or more lll-N semiconductor device assemblies implementing trench isolation with modified profiles, as disclosed herein.

[0068] FIGS. 5A-5B are top views of a wafer 2000 and dies 2002 that may include one or more lll-N semiconductor device assemblies implementing trench isolation with modified profiles in accordance with any of the embodiments disclosed herein. The wafer 2000 may be composed of semiconductor material and may include one or more dies 2002 having IC structures formed on a surface of the wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more structures 200/300, or any other structures where lll-N device components are isolated using trenches with modified profiles as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more structures 200/300, or any other structures where lll-N device components are isolated using trenches with modified profiles as described herein), the wafer 2000 may undergo a singulation process in which each of the dies 2002 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, devices that include one or more lll-N semiconductor device assemblies implementing trench isolation with modified profiles as disclosed herein may take the form of the wafer 2000 (e.g., not singulated) or the form of the die 2002 (e.g., singulated). The die 2002 may include one or more transistors (e.g., one or more of the transistors 2140 of FIG. 6, discussed below, which may take the form of any of the transistors which may be separated by trenches with modified profiles as described herein) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer 2000 or the die 2002 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 2002. For example, a memory array formed by multiple memory devices may be formed on a same die 2002 as a processing device (e.g., the processing device 2302 of FIG. 8) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0069] FIG. 6 is a cross-sectional side view of an IC device 2100 that may include one or more lll-N semiconductor device assemblies implementing trench isolation with modified profiles in accordance with any of the embodiments disclosed herein. The IC device 2100 may be formed on a substrate 2102 (e.g., the wafer 2000 of FIG. 5A) and may be included in a die (e.g., the die 2002 of FIG. 5B). The substrate 2102 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. The substrate 2102 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In some embodiments, the semiconductor substrate 2102 may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group ll-VI, lll-V, or IV may also be used to form the substrate 2102. Although a few examples of materials from which the substrate 2102 may be formed are described here, any material that may serve as a foundation for an IC device 2100 may be used. The substrate 2102 may be part of a singulated die (e.g., the dies 2002 of FIG. 5B) or a wafer (e.g., the wafer 2000 of FIG. 5A).

[0070] The IC device 2100 may include one or more device layers 2104 disposed on the substrate 2102. The device layer 2104 may include features of one or more transistors 2140 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 2102. The device layer 2104 may include, for example, one or more source and/or drain (S/D) regions 2120, a gate 2122 to control current flow in the transistors 2140 between the S/D regions 2120, and one or more S/D contacts 2124 to route electrical signals to/from the S/D regions 2120. Although not specifically shown in FIG. 6, the transistors 2140 may be electrically isolated from one another using trenches with modified profiles as described herein with reference to the trenches 208/308 of the structures 200/300. The S/D regions 2120 may be formed within the substrate 2102 either adjacent to or at a distance from the gate 2122 of each transistor 2140, using any suitable processes known in the art, some of which are described above. The transistors 2140 may include additional features not depicted for the sake of clarity, such as additional device isolation regions, gate contacts, and the like. The transistors 2140 are not limited to the type and configuration depicted in FIG. 6 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or FinFETs, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors. [0071] Each transistor 2140 may include a gate 2122 formed of at least two layers, a gate dielectric layer and a gate electrode layer. Generally, the gate dielectric layer of a transistor 2140 may include one layer or a stack of layers, and the one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material. The high-k dielectric material of the transistor 2140 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used as the gate dielectric of the transistor 2140 include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the structure to improve its quality when a high-k material is used.

[0072] The gate electrode layer may include at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may include a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

[0073] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0074] In some embodiments, when viewed as a cross section of the transistor 2140 along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate (e.g., in a FinFET). In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may include a V-shaped structure (e.g., when the fin of a FinFET does not have a "flat" upper surface, but instead has a rounded peak).

[0075] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0076] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 2140 of the device layer 2104 through one or more interconnect layers disposed on the device layer 2104 (illustrated in FIG. 6 as interconnect layers 2106-2110). For example, electrically conductive features of the device layer 2104 (e.g., the gate 2122 and the S/D contacts 2124) may be electrically coupled with the interconnect structures 2128 of the interconnect layers 2106-2110. The one or more interconnect layers 2106-2110 may form an interlayer dielectric (ILD) stack 2119 of the IC device 2100.

[0077] The interconnect structures 2128 may be arranged within the interconnect layers 2106-2110 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 2128 depicted in FIG. 6). Although a particular number of interconnect layers 2106-2210 is depicted in FIG. 6, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0078] In some embodiments, the interconnect structures 2128 may include trench structures 2128a (sometimes referred to as "lines") and/or via structures 2128b (sometimes referred to as "holes") filled with an electrically conductive material such as a metal. The trench structures 2128a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 2102 upon which the device layer 2104 is formed. For example, the trench structures 2128a may route electrical signals in a direction in and out of the page from the perspective of FIG. 6. The via structures 2128b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 2102 upon which the device layer 2104 is formed. In some embodiments, the via structures 2128b may electrically couple trench structures 2128a of different interconnect layers 2106-2110 together. [0079] The interconnect layers 2106-2110 may include a dielectric material 2126 disposed between the interconnect structures 2128, as shown in FIG. 6. In some embodiments, the dielectric material 2126 disposed between the interconnect structures 2128 in different ones of the interconnect layers 2106-2110 may have different compositions; in other embodiments, the composition of the dielectric material 2126 between different interconnect layers 2106-2110 may be the same.

[0080] A first interconnect layer 2106 (referred to as Metal 1 or "Ml") may be formed directly on the device layer 2104. In some embodiments, the first interconnect layer 2106 may include trench structures 2128a and/or via structures 2128b, as shown. The trench structures 2128a of the first interconnect layer 2106 may be coupled with contacts (e.g., the S/D contacts 2124) of the device layer 2104.

[0081] A second interconnect layer 2108 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 2106. In some embodiments, the second interconnect layer 2108 may include via structures 2128b to couple the trench structures 2128a of the second interconnect layer 2108 with the trench structures 2128a of the first interconnect layer 2106. Although the trench structures 2128a and the via structures 2128b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 2108) for the sake of clarity, the trench structures 2128a and the via structures 2128b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

[0082] A third interconnect layer 2110 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 2108 according to similar techniques and configurations described in connection with the second interconnect layer 2108 or the first interconnect layer 2106.

[0083] The IC device 2100 may include a solder resist material 2134 (e.g., polyimide or similar material) and one or more bond pads 2136 formed on the interconnect layers 2106-2110. The bond pads 2136 may be electrically coupled with the interconnect structures 2128 and configured to route the electrical signals of the transistor(s) 2140 to other external devices. For example, solder bonds may be formed on the one or more bond pads 2136 to mechanically and/or electrically couple a chip including the IC device 2100 with another component (e.g., a circuit board). The IC device 2100 may have other alternative configurations to route the electrical signals from the interconnect layers 2106-2110 than depicted in other embodiments. For example, the bond pads 2136 may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

[0084] FIG. 7 is a cross-sectional side view of an IC device assembly 2200 that may include one or more lll-N semiconductor device assemblies implementing trench isolation with modified profiles in accordance with any of the embodiments disclosed herein. The IC device assembly 2200 includes a number of components disposed on a circuit board 2202 (which may be, e.g., a motherboard). The IC device assembly 2200 includes components disposed on a first face 2240 of the circuit board 2202 and an opposing second face 2242 of the circuit board 2202; generally, components may be disposed on one or both faces 2240 and 2242. In particular, any suitable ones of the components of the IC device assembly 2200 may include any of the lll-N semiconductor device assemblies implementing trench isolation with modified profiles in accordance with any of the embodiments disclosed herein or be electrically isolated from one another using trenches with modified profiles in accordance with any of the embodiments disclosed herein.

[0085] In some embodiments, the circuit board 2202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2202. In other embodiments, the circuit board 2202 may be a non-PCB substrate.

[0086] The IC device assembly 2200 illustrated in FIG. 7 includes a package-on-interposer structure 2236 coupled to the first face 2240 of the circuit board 2202 by coupling components 2216. The coupling components 2216 may electrically and mechanically couple the package-on-interposer structure 2236 to the circuit board 2202, and may include solder balls (as shown in FIG. 7), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0087] The package-on-interposer structure 2236 may include an IC package 2220 coupled to an interposer 2204 by coupling components 2218. The coupling components 2218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2216. Although a single IC package 2220 is shown in FIG. 7, multiple IC packages may be coupled to the interposer 2204; indeed, additional interposers may be coupled to the interposer 2204. The interposer 2204 may provide an intervening substrate used to bridge the circuit board 2202 and the IC package 2220. The IC package 2220 may be or include, for example, a die (the die 2002 of FIG. 5B), an IC device (e.g., the IC device 2100 of FIG. 6), or any other suitable component. Generally, the interposer 2204 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 2204 may couple the IC package 2220 (e.g., a die) to a ball grid array (BGA) of the coupling components 2216 for coupling to the circuit board 2202. In the embodiment illustrated in FIG. 7, the IC package 2220 and the circuit board 2202 are attached to opposing sides of the interposer 2204; in other embodiments, the IC package 2220 and the circuit board 2202 may be attached to a same side of the interposer 2204. In some embodiments, three or more components may be interconnected by way of the interposer 2204.

[0088] The interposer 2204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-N and group IV materials. The interposer 2204 may include metal interconnects 2208 and vias 2210, including but not limited to through-silicon vias (TSVs) 2206. The interposer 2204 may further include embedded devices 2214, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency ( F) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2204. The package-on-interposer structure 2236 may take the form of any of the package-on-interposer structures known in the art.

[0089] The IC device assembly 2200 may include an IC package 2224 coupled to the first face 2240 of the circuit board 2202 by coupling components 2222. The coupling components 2222 may take the form of any of the embodiments discussed above with reference to the coupling components 2216, and the IC package 2224 may take the form of any of the embodiments discussed above with reference to the IC package 2220.

[0090] The IC device assembly 2200 illustrated in FIG. 7 includes a package-on-package structure 2234 coupled to the second face 2242 of the circuit board 2202 by coupling components 2228. The package-on-package structure 2234 may include an IC package 2226 and an IC package 2232 coupled together by coupling components 2230 such that the IC package 2226 is disposed between the circuit board 2202 and the IC package 2232. The coupling components 2228 and 2230 may take the form of any of the embodiments of the coupling components 2216 discussed above, and the IC packages 2226 and 2232 may take the form of any of the embodiments of the IC package 2220 discussed above. The package-on-package structure 2234 may be configured in accordance with any of the package-on-package structures known in the art.

[0091] FIG. 8 is a block diagram of an example computing device 2300 that may include one or more lll-N semiconductor device assemblies implementing trench isolation with modified profiles in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device 2300 may include a die (e.g., the die 2002 (FIG. 5B)) having III- N device components, such as e.g. transistors, isolated using one or more trenches with modified profiles in accordance with any of the embodiments disclosed herein. Any one or more of the components of the computing device 2300 may include, or be included in, an IC device 2100 (FIG. 6). Any one or more of the components of the computing device 2300 may include, or be included in, an IC device assembly 2200 (FIG. 7).

[0092] A number of components are illustrated in FIG. 8 as included in the computing device 2300, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 2300 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

[0093] Additionally, in various embodiments, the computing device 2300 may not include one or more of the components illustrated in FIG. 8, but the computing device 2300 may include interface circuitry for coupling to the one or more components. For example, the computing device 2300 may not include a display device 2306, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2306 may be coupled. In another set of examples, the computing device 2300 may not include an audio input device 2318 or an audio output device 2308, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2318 or audio output device 2308 may be coupled.

[0094] The computing device 2300 may include a processing device 2302 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2300 may include a memory 2304, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 2304 may include memory that shares a die with the processing device 2302. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

[0095] In some embodiments, the computing device 2300 may include a communication chip 2312 (e.g., one or more communication chips). For example, the communication chip 2312 may be configured for managing wireless communications for the transfer of data to and from the computing device 2300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0096] The communication chip 2312 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for

Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2312 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2312 may operate in accordance with other wireless protocols in other embodiments. The computing device 2300 may include an antenna 2322 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0097] In some embodiments, the communication chip 2312 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2312 may include multiple communication chips. For instance, a first communication chip 2312 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2312 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2312 may be dedicated to wireless communications, and a second communication chip 2312 may be dedicated to wired communications.

[0098] The computing device 2300 may include battery/power circuitry 2314. The battery/power circuitry 2314 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2300 to an energy source separate from the computing device 2300 (e.g., AC line power).

[0099] The computing device 2300 may include a display device 2306 (or corresponding interface circuitry, as discussed above). The display device 2306 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0100] The computing device 2300 may include an audio output device 2308 (or corresponding interface circuitry, as discussed above). The audio output device 2308 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0101] The computing device 2300 may include an audio input device 2318 (or corresponding interface circuitry, as discussed above). The audio input device 2318 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (M IDI) output).

[0102] The computing device 2300 may include a global positioning system (GPS) device 2316 (or corresponding interface circuitry, as discussed above). The GPS device 2316 may be in

communication with a satellite-based system and may receive a location of the computing device 2300, as known in the art.

[0103] The computing device 2300 may include an other output device 2310 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0104] The computing device 2300 may include an other input device 2320 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2320 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0105] The computing device 2300 may have any desired form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2300 may be any other electronic device that processes data.

[0106] The following paragraphs provide various examples of the embodiments disclosed herein.

[0107] Example 1 provides a l l l-N semiconductor device assembly that includes a substrate and a channel material provided over the substrate. The channel material includes at least a ll l-N semiconductor material and has a first region including a first l ll-N device component, a second region including a second l ll-N device component, and a trench between the first region and the second region, the trench having a first depth (e.g. Dl shown in FIG. 2) at a first trench area and having a second depth (e.g. D2 shown in FIG. 2) at a second trench area, where the first trench area is closer to the first region than the second trench area, and the first depth is greater than the second depth. Thus, the first region and the second region are portions which are elevated with respect to the valley of the trench and are, therefore, referred to herein as first and second islands.

[0108] Example 2 provides the ll l-N semiconductor device assembly according to Example 1, where the trench has a third depth at a third trench area, where the third trench area is closer to the second region than the second trench area, and the third depth is greater than the second depth.

[0109] Example 3 provides the ll l-N semiconductor device assembly according to Example 2, where the third depth is substantially equal to the first depth.

[0110] Example 4 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where a thickness of the channel material in the first region or/and in the second region is at least about 500 nanometers, including all values and ranges therein, e.g. at least about 1000 nanometers, or e.g. about between 750 and 1250 nanometers.

[0111] Example 5 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where the second depth is less than about 350 nanometers.

[0112] Example 6 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where the first depth is at least about 500 nanometers.

[0113] Example 7 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, further including a buffer layer provided between the channel material and the substrate.

[0114] Example 8 provides the ll l-N semiconductor device assembly according to Example 7, where the buffer layer is a layer including aluminum, gallium, and nitrogen (e.g. a layer of AIGaN).

[0115] Example 9 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where the first depth is equal to or greater than a thickness of the channel material. Thus, at an area closest to the first region, the trench extends at least throughout the entire layer of the channel material and possibly even extends further into the buffer layer (or whichever layer is under the channel material), ensuring low isolation leakage between adjacent semiconductor device components.

[0116] Example 10 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where a portion of the channel material is present under the second trench area, and no channel material is present under the first trench area.

[0117] Example 11 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where a depth of the trench gradually decreases from the first depth at the first trench area to the second depth at the second trench area.

[0118] Example 12 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where the first trench area is an area of the trench that is directly adjacent to the first region.

[0119] Example 13 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where a distance between the first trench area and the second trench area (e.g. a distance between an edge of the first trench area, which edge is closest to the first region, and an edge of the second trench area, which edge is closest to the first region, e.g. W_r shown in FIG. 2) is between about 2 and 30 nanometers, including all values and ranges therein, e.g. between about 5 and 20 nm, or between about 8 and 15 nm.

[0120] Example 14 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where a distance between the first trench area and the second trench area (e.g. a distance between an edge of the first trench area, which edge is closest to the first region, and an edge of the second trench area, which edge is closest to the first region, e.g. W_r shown in FIG. 2) is substantially equal to or less than a difference between the first depth and the second depth.

[0121] Example 15 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where a width of the trench (e.g. W_tr shown in FIG. 2) is between about 30 and 150 nanometers, including all values and ranges therein, e.g. between about 35 and 100 nm, or between 45 and 80 nm.

[0122] Example 16 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where a distance between a center of the first region and a center of the second region (i.e. a fin pitch, e.g. FP shown in FIG. 2) is between about 45 and 200 nanometers, including all values and ranges therein, e.g. between about 55 and 150 nm, or between about 60 and 120 nm. [0123] Example 17 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, further including a dielectric material provided within the trench. In some embodiments, the dielectric material may include a low-k dielectric, such as e.g. Si02, SiOxNy, or a metal oxide (e.g. aluminum oxide or hafnium oxide).

[0124] Example 18 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where the channel material includes a stack of materials, the stack including a polarization layer over the l l l-N semiconductor material.

[0125] Example 19 provides the ll l-N semiconductor device assembly according to Example 18, where the polarization layer includes at least one of a material including aluminum and nitrogen (e.g. AI N), a material including indium, aluminum and nitrogen (e.g. InAI N), or a material including aluminum, gallium and nitrogen (e.g. AIGaN).

[0126] Example 20 provides the ll l-N semiconductor device assembly according to any one of the preceding Examples, where the first l ll-N device component is a first l ll-N transistor, and the second ll l-N device component is the second ll l-N transistor.

[0127] Example 21 provides a method of fabricating a l ll-N semiconductor device assembly, the method including providing a channel material over a substrate, the channel material including a group ll l-N semiconductor material; performing a first etch of the channel material to form an opening in the channel material between a first region of the channel material and a second region of the channel material, the opening having a first depth (e.g. D2 shown in FIG. 2); and performing a second etch the channel material at a first area of the opening to form a first recess in the opening, where the first area is adjacent to the first region, and the channel material within the first recess is removed to a second depth (e.g. Dl shown in FIG. 2).

[0128] Example 22 provides the method according to Example 21, where providing the channel material includes epitaxially growing the channel material over the substrate.

[0129] Example 23 provides the method according to Examples 21 or 22, where performing the first etch of the channel material includes performing an anisotropic etch, e.g. using reactive ion etching with gases such as CI2, BCI3. In addition, elevated temperature of the substrate may be used to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface.

[0130] Example 24 provides the method according to any one of Examples 21-23, where performing the second etch of the channel material includes performing an ion channeling etch. Ion channeling is achieved by utilizing a hard mask material which can easily charge up, such as an insulating material (Sio2, SiON) which in turn leads to steering ions in the plasma. Specifically negatively charge hard mask will focus positively charged ions toward trench sidewalls thus resulting in higher etch rate in that area. [0131] Example 25 provides the method according to any one of Examples 21-24, further including forming a first l ll-N device component within the first region; and forming a second l l l-N device component within the second region.

[0132] Example 26 provides the method according to Example 25, where the first l ll-N device component is a first l l l-N transistor, and the second ll l-N device component is the second ll l-N transistor.

[0133] Example 27 provides the method according to any one of Examples 21-26, where a thickness of the channel material in the first region or/and in the second region is at least about 500 nanometers.

[0134] Example 28 provides the method according to any one of Examples 21-27, where the first depth is less than about 350 nanometers.

[0135] Example 29 provides the method according to any one of Examples 21-28, where the second depth is at least about 500 nanometers.

[0136] Example 30 provides the method according to any one of Examples 21-29, further including providing a buffer layer between the channel material and the substrate.

[0137] Example 31 provides the method according to Example 30, where the second depth is equal to or greater than a thickness of the channel material.

[0138] Example 32 provides the method according to any one of Examples 21-31, where a width of the second etch is between about 2 and 30 nanometers.

[0139] Example 33 provides the method according to any one of Examples 21-32, where a width of the second etch is substantially equal to or less than a difference between the second depth and the first depth.

[0140] Example 34 provides the method according to any one of Examples 21-33, where a width of the opening (e.g. W_tr shown in FIG. 2) is between about 30 and 150 nanometers.

[0141] Example 35 provides the method according to any one of Examples 21-34, where a distance between a center of the first region and a center of the second region (i.e. a fin pitch, e.g. FP shown in FIG. 2) is between about 45 and 200 nanometers.

[0142] Example 36 provides the method according to any one of Examples 21-35, where further including depositing a dielectric material within the opening.

[0143] Example 37 provides the method according to any one of Examples 21-36, where the channel material includes a stack of materials, the stack including a polarization layer over the l ll-N semiconductor material.

[0144] Example 38 provides the method according to Example 37, where the polarization layer includes at least one of a material including aluminum and nitrogen (e.g. AI N), a material including indium, aluminum and nitrogen (e.g. InAIN), or a material including aluminum, gallium and nitrogen (e.g. AIGaN).

[0145] Example 39 provides a computing device that includes a carrier substrate, and an integrated circuit (IC) die coupled to the carrier substrate. The IC die includes a channel material including at least a layer of l ll-N semiconductor material and having a first region including a first ll l-N device component, a second region including a second l ll-N device component, and an opening, in the channel material, between the first region and the second region, where a first area of the opening includes a first recess and has a first depth (e.g. Dl shown in FIG. 2), and a second area of the opening has a second depth (e.g. D2 shown in FIG. 2) that is smaller than the first depth.

[0146] Example 40 provides the computing device according to Example 39, where the opening is a trench.

[0147] Example 41 provides the computing device according to Examples 39 or 40, where the first area is closer to the first region than the second area.

[0148] Example 42 provides the computing device according to any one of Examples 39-41, where the first area is adjacent to the first region.

[0149] Example 43 provides the computing device according to any one of Examples 39-42, where a thickness of the channel material in the first region or/and in the second region is at least about 500 nanometers.

[0150] Example 44 provides the computing device according to any one of Examples 39-43, where the second depth is less than about 350 nanometers.

[0151] Example 45 provides the computing device according to any one of Examples 39-44, where the first depth is at least about 500 nanometers.

[0152] Example 46 provides the computing device according to any one of Examples 39-45, where a distance between the first area and the second area (e.g. a distance between an edge of the first area, which edge is closest to the first region, and an edge of the second area, which edge is closest to the first region, e.g. W_r shown in FIG. 2) is between about 2 and 30 nanometers.

[0153] Example 47 provides the computing device according to any one of Examples 39-46, where a distance between the first area and the second area is substantially equal to or less than a difference between the first depth and the second depth.

[0154] Example 48 provides the computing device according to any one of Examples 39-47, where a width of the opening (e.g. W_tr shown in FIG. 2) is between about 30 and 150 nanometers.

[0155] Example 49 provides the computing device according to any one of Examples 39-48, where a distance between a center of the first region and a center of the second region (i.e. a fin pitch, e.g. FP shown in FIG. 2) is between about 45 and 200 nanometers. [0156] Example 50 provides the computing device according to any one of Examples 39-49, further including a dielectric material provided within the opening.

[0157] Example 51 provides the computing device according to any one of Examples 39-50, where the first l ll-N device component is a first l ll-N transistor, and the second l ll-N device component is the second ll l-N transistor.

[0158] Example 52 provides the computing device according to any one of Examples 39-51, where the computing device is a wearable or handheld computing device.

[0159] Example 53 provides the computing device according to any one of Examples 39-52, where the computing device further includes one or more communication chips and an antenna.

[0160] Example 54 provides the computing device according to any one of Examples 39-53, where the carrier substrate is a motherboard.

[0161] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0162] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

Claims:

1. A lll-N semiconductor device assembly, comprising:

a substrate; and

a channel material over the substrate, the channel material including at least a lll-N semiconductor material and comprising:

a first region comprising a first lll-N device component,

a second region comprising a second lll-N device component, and

a trench between the first region and the second region, the trench having a first depth at a first trench area and having a second depth at a second trench area, wherein the first trench area is closer to the first region than the second trench area, and the first depth is greater than the second depth.

2. The lll-N semiconductor device assembly according to claim 1, wherein the trench has a third depth at a third trench area, wherein the third trench area is closer to the second region than the second trench area, and the third depth is greater than the second depth.

3. The lll-N semiconductor device assembly according to claim 2, wherein the third depth is equal to the first depth.

4. The lll-N semiconductor device assembly according to claim 1, wherein a thickness of the channel material in the first region or/and in the second region is at least 500 nanometers.

5. The lll-N semiconductor device assembly according to claim 1, wherein the second depth is less than 350 nanometers.

6. The lll-N semiconductor device assembly according to claim 1, wherein the first depth is at least 500 nanometers.

7. The lll-N semiconductor device assembly according to claim 1, further comprising a buffer layer between the channel material and the substrate.

8. The lll-N semiconductor device assembly according to claim 7, wherein the buffer layer is a layer comprising aluminum, gallium, and nitrogen.

9. The lll-N semiconductor device assembly according to any one of claims 1-8,

wherein the first depth is equal to or greater than a thickness of the channel material.

10. The lll-N semiconductor device assembly according to any one of claims 1-8,

wherein a portion of the channel material is present under the second trench area, and no channel material is present under the first trench area.

11. The lll-N semiconductor device assembly according to any one of claims 1-8, wherein a depth of the trench gradually decreases from the first depth at the first trench area to the second depth at the second trench area.

12. The lll-N semiconductor device assembly according to any one of claims 1-8, wherein the first trench area is an area of the trench that is directly adjacent to the first region.

13. The lll-N semiconductor device assembly according to any one of claims 1-8, wherein a distance between the first trench area and the second trench area is between 2 and 30 nanometers.

14. The lll-N semiconductor device assembly according to any one of claims 1-8, wherein a distance between the first trench area and the second trench area is equal to or less than a difference between the first depth and the second depth.

15. The lll-N semiconductor device assembly according to any one of claims 1-8, wherein a width of the trench is between 30 and 150 nanometers.

16. The lll-N semiconductor device assembly according to any one of claims 1-8, wherein a distance between a center of the first region and a center of the second region is between 45 and 200 nanometers.

17. The lll-N semiconductor device assembly according to any one of claims 1-8, wherein the channel material includes a stack of materials, the stack including a polarization layer over the lll-N semiconductor material.

18. The lll-N semiconductor device assembly according to claim 17, wherein the polarization layer comprises at least one of a material comprising aluminum and nitrogen, a material comprising indium, aluminum and nitrogen, or a material comprising aluminum, gallium and nitrogen.

19. The lll-N semiconductor device assembly according to any one of claims 1-8, wherein the first III- N device component is a first lll-N transistor, and the second lll-N device component is the second lll-N transistor.

20. A method of fabricating a lll-N semiconductor device assembly, the method comprising:

providing a channel material over a substrate, the channel material comprising a group lll-N semiconductor material;

performing a first etch of the channel material to form an opening in the channel material between a first region of the channel material and a second region of the channel material, the opening having a first depth; and

performing a second etch the channel material at a first area of the opening to form a first recess in the opening,

wherein the first area is adjacent to the first region, and the channel material within the first recess is removed to a second depth.

21. The method according to claim 20, wherein:

providing the channel material comprises epitaxially growing the channel material over the substrate,

performing the first etch of the channel material comprises performing an anisotropic etch, and performing the second etch of the channel material comprises performing an ion channeling etch.

22. The method according to claims 20 or 21, further comprising:

forming a first lll-N device component within the first region; and

forming a second lll-N device component within the second region, wherein the first lll-N device component is a first lll-N transistor, and the second lll-N device component is the second lll-N transistor.

23. A computing device, comprising:

a carrier substrate; and an integrated circuit (IC) die coupled to the carrier substrate, wherein the IC die includes a channel material comprising at least a layer of lll-N semiconductor material and having:

a first region comprising a first lll-N device component,

a second region comprising a second lll-N device component, and

an opening, in the channel material, between the first region and the second region,

wherein:

a first area of the opening comprises a first recess and has a first depth, and

a second area of the opening has a second depth that is smaller than the first depth.

24. The computing device according to claim 23, wherein the opening is a trench.

25. The computing device according to claims 23 or 24, further comprising a dielectric material within the opening.