WO2019081996A1

WO2019081996A1 - Low temperature transistor processing

Info

Publication number: WO2019081996A1
Application number: PCT/IB2018/057221
Authority: WO
Inventors: Pradipta K. NAYAK; Fahad K. AL-SALEM; Ramzi Salem AL-MAGHATHUWI; Jesus Alfonso CARAVEO-FRESCAS; Abdulaziz H. AL-DUBAYAN
Original assignee: SABIC Global Technologies BV
Current assignee: SABIC Global Technologies BV
Priority date: 2017-10-26
Filing date: 2018-09-19
Publication date: 2019-05-02
Anticipated expiration: 2020-04-26

Abstract

A method for manufacturing high-performance oxide TFTs may include deposition and processing at temperature below 200 degrees Celsius, or below 160 degrees Celsius. These TFTs may be used in electronic devices built on rigid or flexible substrates. In some embodiments, the oxide TFTs may include an indium gallium zinc oxide (InGaZnO) portion formed at low processing temperatures (e.g., below 200 degrees Celsius).

Description

LOW TEMPERATURE TRANSISTOR PROCESSING

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

[0001] This application claims the benefit of priority of U. S. Provisional Patent Application No. 62/577,480 filed October 26, 2017, and U. S. Provisional Patent Application No. 62/662,141 filed April 24, 2018. The entire contents of each of the above-referenced disclosures are specifically incorporated herein by reference.

FIELD OF THE DISCLOSURE

[0002] The instant disclosure relates to semiconductor devices. Portions of this disclosure relate to low-temperature fabrication processes for semiconductor devices. BACKGROUND

[0003] Electronic devices with low power consumption are desirable for mobile devices to extend the life of the device' s battery. However, fast performance is also expected from mobile devices, along with long battery life. Electronic devices in the mobile devices are made of millions of transistors. The performance and efficiency of the transistors must increase to meet expectations of new electronic devices and enable new functionality. Oxide thin film transistors (TFTs) with a low-dielectric constant such as S1O2 and SiNx for gate insulators are normally operated using higher voltages. Characteristics of the transistors impact the performance of the electronic devices. For faster performance, the oxide TFTs should exhibit low subthreshold swing values (about 100 mV/decade), which is defined as the gate voltage required to increase the magnitude of current between drain and source electrode by ten times of its initial value in the subthreshold range of the transistor operation. High-k dielectric gate insulators have been used for low voltage operation of the TFTs. However, high-k dielectric when deposited at low processing temperatures does not exhibit desirable performance. Low- temperature-deposited gate insulators possess a large number of defects, which affect the quality of the interface between the insulator and semiconductor. In particular, oxide TFTs using hafnium oxide as the gate insulator, deposited by low-temperature sputtering show low performance and reliability. Conventional solutions for oxide TFTs thus use multi-component gate insulators, such as hafnium silicate, to reduce defects in the gate insulator and enhance TFT performance. SUMMARY

[0004] An oxide TFT manufactured without multi-component gate insulators while providing high performance and low power consumption is desirable for electronic devices used in or as sensors, mobile devices, and radio-frequency identification tags (RFID tags). Conventional solutions use high-temperature processes to form such devices or use multi- component gate insulators to form such devices. However, such devices have disadvantages including the high-temperature processing, the high-post-fabrication annealing temperature used to improve performance, the high energy consumption and expensive manufacturing processes used for high post-fabrication annealing, use of multiple semiconductors, use of dry etching that increases manufacturing cost, use of an etch stopper to prevent plasma damage during dry etching, low field-effect mobility and unstable performance, high subthreshold swing value not suitable for faster response time, and/or high-voltage range of operation. In addition to these disadvantages, high temperature processing prohibits manufacturing of oxide TFTs with desirable performance on flexible substrates or other non-silicon substrates. [0005] The present invention provides a solution to at least some of these disadvantages. The solution is premised on methods for manufacturing high-performance oxide TFTs that can include deposition and processing at temperature below 200 degrees Celsius, or below 160 degrees Celsius. These TFTs may be used in electronic devices built on rigid or flexible substrates. In some embodiments, the oxide TFTs may include an indium gallium zinc oxide (InGaZnO) portion formed at low processing temperatures (e.g., below 200 degrees Celsius).

[0006] In the contest of the current invention, 20 embodiments are described. Embodiment 1 is a method of manufacturing one or more thin film transistors (TFTs) on a substrate, the method comprising: forming a gate electrode comprising a metal oxide for the one or more thin film transistors (TFTs) without exceeding a temperature of 200 degrees C; forming a gate dielectric comprising hafnium oxide for the one or more thin film transistors (TFTs) without exceeding a temperature of 200 degrees C; forming a metal-oxide-based semiconductor channel region for the one or more thin film transistors (TFTs) without exceeding a temperature of 200 degrees C after forming the gate dielectric and without annealing the gate dielectric; and forming source and drain regions for the one or more thin film transistors (TFTs) without exceeding a temperature of 200 degrees C. Embodiment 2 is the method of embodiment 1, wherein the method comprises forming the gate electrode on the substrate, forming the gate dielectric on the gate electrode, and forming the semiconductor channel region on the gate dielectric to form a bottom-gate thin film transistor (TFT). Embodiment 3 is the method of embodiment 1, wherein the method comprises forming the semiconductor channel region on the substrate, forming the gate dielectric on the semiconductor channel region, and forming the gate electrode on the gate dielectric to form a top-gate thin film transistor (TFT). Embodiment

4 is the method of any of embodiments 1 to 3, wherein the step of forming the gate electrode comprises performing atomic layer deposition (ALD) to deposit at least one of aluminum- doped zinc oxide (AZO), Hf-ZnO, InZnO, ITO, SnCte, and ImCb as the gate electrode. Embodiment 5 is a method of manufacturing one or more thin film transistors (TFTs) on a substrate, the method comprising: depositing a gate electrode layer comprising a metal oxide electrode; patterning the gate electrode layer to form one or more gate electrodes for the one or more thin film transistors (TFTs); depositing a gate dielectric layer comprising hafnium oxide on the one or more gate electrodes; annealing the gate dielectric layer without exceeding a temperature of 200 degrees C; depositing a metal-oxide-based semiconductor layer on the gate dielectric layer; patterning the semiconductor layer to form one or more channel regions proximate to the one or more gate electrodes; forming vias (holes) through the gate dielectric layer to the one or more gate electrodes; and forming source and drain electrodes on the semiconductor layer proximate to the one or more gate electrodes to form the one or more thin film transistors (TFTs). Embodiment 6 is the method of embodiment 5, wherein the step of depositing the gate electrode layer comprises depositing at least one of aluminum-doped zinc oxide (AZO), Hf-ZnO, InZnO, SnCh, In2Cb, ITO, a metal oxide, and a metal without exceeding a temperature of 200 degrees C. Embodiment 7 is the method of any of embodiments 5 to 6, wherein the step of depositing the gate electrode layer comprises depositing aluminum-doped zinc oxide (AZO) by atomic layer deposition (ALD). Embodiment 8 is the method of any of embodiments 5 to 7, wherein the step of depositing the gate dielectric layer comprises depositing hafnium oxide without exceeding a temperature of 200 degrees C. Embodiment 9 is the method of any of embodiments 5 to 8, wherein the step of depositing the gate dielectric layer comprises depositing at least one of hafnium oxide and aluminum oxide by atomic layer deposition (ALD). Embodiment 10 is the method of any of embodiments 5 to 9, further comprising the step of annealing the gate dielectric layer without exceeding a temperature of 200 degrees C. Embodiment 11 is the method of any of embodiments 5 to 10, wherein the step of depositing a metal-oxide-based semiconductor layer comprises depositing indium gallium zinc oxide (IGZO) without exceeding a temperature of 200 degrees C. Embodiment 12 is the method of any of embodiments 5 to 11, further comprising depositing a protection layer on the one or more thin film transistors (TFTs). Embodiment 13 is the method of any of embodiments

5 to 12, further comprising annealing the one or more thin film transistors (TFTs) without exceeding a temperature of 200 degrees C. Embodiment 14 is the method of any of embodiments 5 to 13, wherein the step of forming source and drain electrodes comprises depositing a conductor comprising at least one of bi-layer of titanium and gold, Ti, Mo, Cr, Cu, Ni/Au, Ag, ITO, Al-ZnO, and InZnO. Embodiment 15 is the method of any of embodiments 5 to 14, wherein the substrate is a flexible substrate. Embodiment 16 is the method of any of embodiments 5 to 14, wherein the substrate comprises a rigid substrate, and wherein the method further comprises preparing the substrate by depositing an insulating base layer on the substrate. Embodiment 17 is the method of embodiment 16, wherein the insulating base layer comprises polyimide, and wherein the method further comprises depositing a barrier layer on the insulating base layer before depositing the gate electrode layer. Embodiment 18 is the method of embodiment 17, wherein the step of depositing the barrier layer comprises depositing an aluminum oxide by atomic layer deposition (ALD). Embodiment 19 is a thin film transistor made by the process of any one of embodiments 1 to 18. Embodiment 20 is an electronic device comprising a plurality of thin film transistors made by the process of any one of embodiments 1 to 18.

[0007] The terms "about" or "approximately" are defined as being close to as understood by one of ordinary skill in the art. In one non-limiting embodiment, the terms are defined to be within 10%, preferably within 5%, more preferably within 1%, and most preferably within 0.5%. [0008] The term "substantially" and its variations are defined to include ranges within 10%, within 5%, within 1%, or within 0.5%.

[0009] The terms "inhibiting" or "reducing" or "preventing" or "avoiding" or any variation of these terms, when used in the claims and/or the specification includes any measurable decrease or complete inhibition to achieve a desired result. [0010] The term "effective," as that term is used in the specification and/or claims, means adequate to accomplish a desired, expected, or intended result.

[0011] The use of the words "a" or "an" when used in conjunction with any of the terms "comprising," "including," "containing," or "having" in the claims, or the specification, may mean "one," but it is also consistent with the meaning of "one or more," "at least one," and "one or more than one."

[0012] The words "comprising" (and any form of comprising, such as "comprise" and "comprises"), "having" (and any form of having, such as "have" and "has"), "including" (and any form of including, such as "includes" and "include") or "containing" (and any form of containing, such as "contains" and "contain") are inclusive or open-ended and do not exclude additional, unrecited elements or method steps.

[0013] The methods of the present invention can "comprise," "consist essentially of," or "consist of particular ingredients, components, compositions, etc. disclosed throughout the specification. With respect to the transitional phrase "consisting essentially of," in one non- limiting aspect, a basic and novel characteristic of the methods of the present invention is the ability to manufacture one or more film transistors on a substrate at temperatures below 200 degrees C. [0014] The foregoing has outlined rather broadly certain features and technical advantages of embodiments of the present invention in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter that form the subject of the claims of the invention. It should be appreciated by those having ordinary skill in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same or similar purposes. It should also be realized by those having ordinary skill in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. Additional features will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures are provided for the purpose of illustration and description only and is not intended to limit the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For a more complete understanding of the disclosed system and methods, reference is now made to the following descriptions taken in conjunction with the accompanying drawings.

[0016] FIG. 1 is a flow chart illustrating a method of low-temperature oxide TFT manufacturing according to some embodiments of the disclosure.

[0017] FIG. 2 is a flow chart illustrating a method of low-temperature aluminum-doped zinc oxide (AZO)-based TFT manufacturing according to some embodiments of the disclosure. [0018] FIG. 3 is a cross-sectional illustrations of an oxide TFT according to some embodiments of the disclosure. [0019] FIGS. 4A-D are cross-sectional illustrations of oxide TFTs according different embodiments of the disclosure.

[0020] FIG. 5 is a graph illustrating transfer characteristics of InGaZnO TFTs without post-fabrication annealing according to some embodiments of the disclosure. [0021] FIG. 6 is a graph illustrating transfer characteristics of InGaZnO TFTs post- annealed at different temperatures according to some embodiments of the disclosure.

[0022] FIG. 7 is a graph illustrating evolution of positive gate bias stress of TFTs with InGaZnO semiconductor layer prepared at 3.2% Opp according to some embodiments of the disclosure. [0023] FIG. 8 is a graph illustrating evolution of positive gate bias stress of TFTs with InGaZnO semiconductor layer prepared at 3.6% Opp according to some embodiments of the disclosure.

[0024] FIG. 9 is a graph illustrating transfer characteristics of InGaZnO TFTs with different thickness of Hf02 gate insulator according to some embodiments of the disclosure. [0025] FIG. 10 is a graph illustrating transfer characteristics of an InGaZnO TFT with 27 nm H 02 showing break down behavior when operated at various gate voltages according to some embodiments of the disclosure.

[0026] FIG. 11 is a graph illustrating transfer characteristics of TFTs with InGaZnO prepared at different deposition pressure according to some embodiments of the disclosure. [0027] FIG. 12 is a graph illustrating transfer characteristics of InGaZnO TFTs with Hf0₂ deposited at different temperature according to some embodiments of the disclosure.

[0028] FIG. 13 is a graph illustrating transfer characteristics of InGaZnO TFTs with Hf0₂ gate dielectric post-annealed at different temperatures according to some embodiments of the disclosure. [0029] FIG. 14 is a graph illustrating transfer characteristics of TFTs with InGaZnO deposited at different temperatures according to some embodiments of the disclosure.

[0030] FIG. 15 is a graph illustrating transfer characteristics of TFTs with different thickness of the InGaZnO semiconductor layer according to some embodiments of the disclosure. [0031] FIG. 16 is a graph illustrating transfer characteristics of TFTs with InGaZnO TFTs with different gate dielectrics according to some embodiments of the disclosure.

[0032] FIG. 17 is a graph illustrating transfer characteristics of an InGaZnO TFT made on a polyimide (PI) substrate according to some embodiments of the disclosure. [0033] FIG. 18 is a graph illustrating transfer characteristics of a TFT using InGaZnO semiconductor layer with In:Ga:Zn composition of 1 : 1 : 1 according to some embodiments of the disclosure.

DETAILED DESCRIPTION

[0034] FIG. 1 is a flow chart illustrating a method of low-temperature oxide TFT manufacturing according to some embodiments of the disclosure. A method for manufacturing one or more TFTs on a substrate can include forming, at block 102, a gate electrode such as a metal oxide without exceeding a temperature of 200 degrees Celsius. The gate electrode may be formed on the substrate. The substrate may be processed prior to deposition of the gate electrode including, for example, cleaning and/or deposition of precursor materials or other layers prior to the gate layers. At block 104, a gate dielectric such as hafnium oxide is formed on the gate electrode without exceeding a temperature of 200 degrees Celsius. At block 106, a semiconductor channel such as a metal-oxide-based semiconductor is formed on the gate dielectric without exceeding a temperature of 200 degrees Celsius. In some embodiments, the semiconductor channel may be formed without an earlier annealing of the gate dielectric. At block 108, source and drain regions are formed on top of the semiconductor layer, around the gate electrode without exceeding a temperature of 200 degrees Celsius. Each of the manufacturing steps of blocks 102, 104, 106, and 108 are performed without exposing the substrate to temperatures exceeding 200 degrees Celsius. In some embodiments, the temperatures may be lower, such that the manufacturing steps are performed without exceeding 160 degrees Celsius.

[0035] The low temperature processing allows manufacturing of high-performance transistors on flexible substrates such as polymer-based substrates or thin substrates that can be damaged by high temperatures. For example, high performance thin film transistors can be manufactured at process temperatures as low as or not exceeding 160 degrees Celsius by using high-dielectric-constant hafnium oxide as gate dielectric, appropriate composition of indium gallium zinc oxide, and carefully controlling the process conditions of the indium gallium zinc oxide semiconductor layer. The indium gallium zinc oxide thin film transistors exhibit high field-effect mobility, high on-to-off drain current ratio, low subthreshold swing, and low threshold voltage values in low-voltage range of operation. Some example measurements of a transistor manufactured by a process according to embodiments of FIG. 1 are described below. The low temperature processing may also be performed on rigid substrates such as silicon or semiconductor compounds. In some embodiments using rigid substrates, an insulating layer may be deposited on the rigid substrate prior to forming the transistors.

[0036] One embodiment of the manufacturing method of FIG. 1 can be used to manufacture AZO-based TFTs. Aluminum-doped zinc oxide (AZO) is a metal-based oxide transparent conductor that can be used as a gate electrode for a transistor. FIG. 2 is a flow chart illustrating a method of low-temperature aluminum-doped zinc oxide (AZO)-based TFT manufacturing according to some embodiments of the disclosure. A method 200 begins at block 202 with preparing a glass substrate. Other layers may be deposited on the glass substrate prior to subsequent steps. At block 206, a gate electrode layer of AZO is deposited on the barrier layer, and then patterned to form gate electrodes at block 208. Other transparent conducting oxides such tin-doped indium oxide (ITO), gallium-doped zinc oxide (GZO), tin dioxide (Sn02), fluorine-doped tin oxide (FTO), tantalum nitride and any other conducting metals such as titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni) or a combination of these materials can also be used as the gate electrode. At block 210, a gate dielectric layer is deposited on the gate electrodes. The gate dielectric layer may be made of hafnium oxide deposited by atomic layer deposition (ALD) in the temperature range of 120 degrees Celsius to 200 degrees Celsius, such as 120, 140, 160, 180, or 200 degrees Celsius. The hafnium oxide layer can be deposited by ALD using water, hydrogen peroxide (H2O2), oxygen plasma, or ozone as the source of oxygen. The thickness of the Hf0₂ layer can be of 25 nm to 110 nm. The gate dielectric layer may be annealed at block 212. A post- deposition annealing of the Hf0₂ layer in air or oxygen ambient can be done in the temperature range of 80 - 180 degrees Celsius to reduce the defects in the surface and bulk of the Hf0₂ layer, which can improve the TFT performance. Then, at block 214, a semiconductor layer is deposited to be a channel region of a transistor corresponding to the gate electrodes. The semiconductor layer can be InGaZnO having a In:Ga:Zn ratio of 2: 1 : 1 (molar) or 1 : 1 : 1. In some embodiments, the semiconductor may be other compositions of InGaZnO or another oxide semiconductor having at least one of indium, zinc, and gallium as a component of the semiconductor layer. The semiconductor layer can be deposited by RF-sputtering, DC- sputtering, PECVD, ALD or another deposition techniques. Thickness of the InGaZnO-layer can be in the range of 5-50 nm.

[0037] After block 214, a layer may be deposited for source and drain electrodes. The source-drain electrodes can be a bilayer of titanium and gold, or another conducting material such as molybdenum (Mo), nickel (Ni) or transparent conducting oxides such tin-doped indium oxide (ITO), gallium-doped zinc oxide (GZO), tin dioxide (Sn0₂), fluorine-doped tin oxide (FTO), tantalum nitride or conducting metals such as titanium (Ti), Mo, Al, Cu, Cr or a combination of these materials. The conducting material, such as the bilayer, may be patterned to form individual source-drain electrodes. In some embodiments, gate via patterning step 216 may be performed after patterning of the semiconductor thin film after deposition of the semiconductor thin film at block 214. For example, to create access to the gate electrode through the gate dielectric, via holes can be formed by photolithography and dry etching.

[0038] In some embodiments, additional steps may be performed in the manufacturing process shown in method 200 or other manufacturing processes used to manufacture TFTs. For example, the thin film transistors may need an appropriate oxygen and water barrier material, such as to be protected from ambient effects that may affect the TFT performance. The protection layer material can be AI2O3, HfCh, silicon nitride, silicon dioxide, or any other organic materials such as SU-8, parylene, PVP and PVDF, which can protect the channel layer from the ambient effects. In some embodiments, post-annealing step 218 of the TFTs may be performed. After the whole fabrication process, the TFTs were annealed in the temperature range of 100 - 200 degrees Celsius for 2 hours in air ambient to get better performance and stability.

[0039] In some embodiments, a post-fabrication annealing in air environment is performed in the temperature range of 100 - 200 degrees Celsius using a conventional furnace to improve the device performance of InGaZnO TFTs. The TFTs can also be annealed under an oxygen- ambient environment. Photo-annealing/curing in air or oxygen ambient can also be performed for rapid thermal processing to improve the device performance.

[0040] In one embodiment, a HfC can be used as the gate dielectric for the fabricated TFTs. The gate can include Al dope ZnO and the HTO2 can be 25 nm to 60 nm. The following conditions can produce a INGaZO:TFT with maximum performance. Deposition temperature: 120-160 °C. Post-annealing of Hf0₂ before InGaZnO deposition: RT-120 °C in air. InGaZnO (2: 1 : 1) deposition conditions can include: a deposition pressure of < 2 mTorr; a deposition temperature of 20 to 80 °C; an oxygen partial pressure of from 2.8 to 3.2%; and IGZO thickness (t) of 15 nm < t <45 nm. The InGaZnO (1 : 1 : 1) deposition condition can include: deposition pressure of < 2 mTorr; a deposition temperature of 100 °C to 200 °C; an OPP of 2.8 to 3.2%; and IGZO thickness (t) of 15 nm < t < 45 nm. The post-fabrication annealing can include a temperature: 100 °C to 200 °C and ambient: air or 02-ambient.

[0041] In some embodiments, a flexible substrates for the TFTs may be polyimide (PI) substrates or other plastic substrates, such as polyethylene naphthalate (PEN), polyetherimide (PEI) or polyethylene terephthalate (PET) that can withstand the processing temperature can be used to fabricate the TFTs. The optional barrier layer described in some embodiments above can reduce or prevent the penetration of water and oxygen molecules from the substrate, such as a plastic substrate, to the layers of the TFT. An example barrier layer is ALD-deposited aluminum oxide (AI2O3), however other suitable barrier layers such as silicon oxide (S1O2), silicon nitride (SiNx), hafnium oxide, any other organic barrier layer, or a combination thereof, can be used. [0042] A cross-section of a transistor manufactured by an embodiment of the process of FIG. 2 is shown in FIG. 3. The transistor structure is a bottom-gate structure, named because the gate electrode is between the substrate and the gate dielectric insulator. FIG. 3 is a cross- sectional illustrations of an oxide TFT according to some embodiments of the disclosure. The cross-section 300 shows, starting from substrate 302, a gate electrode 304, a dielectric insulator 306, a semiconductor channel region 308, and source and drain electrodes 310A and 310B.

[0043] The manufacturing process examples of FIG. 1 and FIG. 2 describe formation of a bottom-gate structure shown in FIG. 3. However, the processes may be adapted to manufacture other TFT structures, including the staggered bottom-gate, coplanar bottom-gate, staggered top-gate, and coplanar top-gate TFT structures shown in FIGS. 4A-4D, respectively. FIGS. 4A-D are cross-sectional illustrations of oxide TFTs according different embodiments of the disclosure.

[0044] FIG. 5 is a graph illustrating transfer characteristics of InGaZnO TFTs without post- fabrication annealing according to some embodiments of the disclosure or manufactured in the non-limiting methods of the Examples. Graph 500 shows transfer characteristic curves of InGaZnO TFTs without annealing after fabrication prepared at oxygen partial pressures (Opp) of 2.4, 2.8, 3.2, 3.6, 4.0, and 4.8% during sputter deposition of the InGaZnO thin film in curves 502, 504, 506, 508, 510, and 512, respectively. Opp is defined as _ Oxygen flow (02)

p^{p ~} total flow (Ar+02)

[0045] The mobility of the TFTs was extracted in the saturation region of operation. The turn-on voltage (Von) is defined as the voltage from which the drain current (ID) rises rapidly in the logarithmic scale. The on-to-off current ratio is defined as the ratio (Wloff) of the lowest drain current in the off-state to the maximum drain current in the on-state of the TFT. The subthreshold swing (SS) value is defined as the gate voltage required to increase the drain current by ten times (decade) of its initial value. The hysteresis of the TFT was obtained by determining the voltage difference between the forward and backward sweep of the transfer curve at 10 pA drain current. In some embodiments, TFTs with desired performance can be obtained in the Opp range of 2.8 to 3.6%. Electrical parameters of the differently-manufactured TFTs shown in FIG. 5 are listed below in Table 1.

Table 1

[0046] FIG. 6 is a graph illustrating transfer characteristics of InGaZnO TFTs post- annealed at different temperatures according to some embodiments of the disclosure or manufactured in the non-limiting methods of the Examples. The InGaZnO TFTs can be post- annealed in air or oxygen environment in the temperature range of 100 - 200 degrees Celsius after completing the fabrication process of FIG. 1 or FIG. 2 to improve the device performance. Graph 600 shows transfer characteristic curves of the InGaZnO TFT and before and after such annealing at temperatures of 100, 120, 160, and 200 degrees Celsius in lines 602, 604, 606, and 608, respectively, compared with a TFT with no annealing in line 610. In some embodiments, TFTs with desired performance can be obtained with an annealing temperature range of 120 - 160 degrees Celsius. Electrical parameters of the differently-annealed TFTs of FIG. 6 are listed in Table 2. Table 2

[0047] FIG. 7 is a graph illustrating evolution of positive gate bias stress of TFTs with InGaZnO semiconductor layer prepared at 3.2% Opp according to some embodiments of the disclosure or manufactured in the non-limiting methods of the Examples. FIG. 8 is a graph illustrating evolution of positive gate bias stress of TFTs with InGaZnO semiconductor layer prepared at 3.6% Opp according to some embodiments of the disclosure or manufactured in the non-limiting methods of the Examples. FIG. 7 and FIG. 8 demonstrate the positive gate bias stress stability of TFTs with InGaZnO semiconductor layer prepared at 3.2% Opp and 3.6%) Opp, respectively. The gate bias stress measurements were performed by applying +5 V bias to the gate terminal of the TFT, while holding the drain and source terminals at 0 V. The positive gate bias stress was applied for times of 0, 100, 1000, 2000, and 3600 seconds and transfer curves of the TFTs manufactured at 3.2% Opp are shown in graph 700 as lines 702, 704, 706, 708, and 710, respectively, and transfer curves of TFTs manufactured at 3.6% Opp are shown in graph 800 as lines 802, 804, 806, 808, and 810, respectively. In some embodiments, desired characteristics can be obtained with InGaZnO semiconductor layer deposited at <3.6% Opp. For example, transfer characteristics of the TFT deposited at 3.6 % Opp show a significant threshold voltage shift of 0.8 V, whereas some films deposited at 3.2% Opp (and below) show a better stability with minimum (0.25 V) threshold voltage variation

[0048] FIG. 9 is a graph illustrating transfer characteristics of InGaZnO TFTs with different thickness of Hftte gate insulator according to some embodiments of the disclosure and/or as illustrated in a non-limiting manner in the Examples. FIG. 9 shows a graph 900 with curves 902, 904, and 906 for 27, 54, and 108 nm thicknesses, respectively. In some embodiments, a TFT with 27 nm of Hftte shows higher negative Von, reverse hysteresis and shows higher drain current in the off-state of the transistor. HfCh of thickness higher than 27 nm can be used to obtain TFTs with better Von and higher breakdown voltage. FIG. 10 is a graph illustrating transfer characteristics of an InGaZnO TFT with 27 nm HfCh showing break down behavior when operated at various gate voltages according to some embodiments of the disclosure. FIG. 10 illustrates that the InGaZnO TFT breaks down when the gate voltage increased to >14V.

[0049] FIG. 1 1 is a graph illustrating transfer characteristics of TFTs with InGaZnO prepared at different deposition pressure according to some embodiments of the disclosure and/or as illustrated in a non-limiting manner in the Examples. FIG. 11 shows the transfer characteristic curves of the InGaZnO TFTs prepared at pressures of 1.0, 1.4, 2.0, and 4.0 mTorr during the sputtering deposition of InGaZnO layer in lines 1102, 1104, 1106, and 1108, respectively. In some embodiments, desired characteristics for a TFT are obtained with sputtering pressure during the InGaZnO deposition lower than 2 mTorr to get better TFT performances. [0050] FIG. 12 is a graph illustrating transfer characteristics of InGaZnO TFTs with Hf02 deposited at different temperature according to some embodiments of the disclosure and/or as illustrated in a non-limiting manner in the Examples. FIG. 12 shows graph 1200 with transfer characteristic curves 1202, 1204, 1206, 1208, and 1210 of InGaZnO TFTs with Hf0₂ gate dielectric layer deposited at temperatures of 120, 140, 160, 180, and 200 degrees Celsius, respectively. In some embodiments, the deposition temperature of Hf0₂ gate dielectric layer can be higher than 120 degrees Celsius and lower than 180 degrees Celsius to get better TFT performance. The extracted electrical parameters of TFTs in FIG. 12 are listed in Table 3.

Table 3

[0051] FIG. 13 is a graph illustrating transfer characteristics of InGaZnO TFTs with Hf0₂ gate dielectric post-annealed at different temperatures according to some embodiments of the disclosure and/or as illustrated in a non-limiting manner in the Examples. FIG. 13 shows graph 1300 with transfer curves 1302, 1304, 1306, and 1308 of InGaZnO TFTs with Hf0₂ gate dielectric post annealed at temperatures of 120, 140, 160, and 200 degrees Celsius, respectively, before the deposition of InGZnO thin film on it and a non-annealed sample in curve 1310. In some embodiments, a temperature range of 120 to 160 degrees Celsius improves the hysteresis of the transfer curve. Further increases post-annealing temperature may degrade the TFT performance.

[0052] FIG. 14 is a graph illustrating transfer characteristics of TFTs with InGaZnO deposited at different temperatures according to some embodiments of the disclosure and/or as illustrated in a non-limiting manner in the Examples. FIG. 14 shows graph 1400 with transfer characteristic curves 1402, 1404, and 1406 of TFTs with InGaZnO active layers deposited at temperatures of 27, 80, and 120 degrees Celsius, respectively. In some embodiments, increasing the deposition temperature above 80 degrees Celsius shifts the transfer curve in the negative direction of the gate voltage, which may not be suitable for some applications as it would consume more power in the static state. Some embodiments of TFTs with InGaZnO deposited at 120 degrees Celsius show very high negative Von and reverse hysteresis with two humps.

[0053] FIG. 15 is a graph illustrating transfer characteristics of TFTs with different thickness of the InGaZnO semiconductor layer according to some embodiments of the disclosure and/or as illustrated in a non-limiting manner in the Examples. FIG. 15 shows graph 1500 with transfer characteristic curves 1502, 1504, 1506, 1508, and 1510 of TFTs with thickness of the InGaZnO semiconductor layer of 5, 10, 18, 22, and 43 nm, respectively. In some embodiments, desirable characteristics for TFT are achieved when the thickness of the InGaZnO semiconductor layer is above 10 nm. The electrical parameters of the TFTs shown in FIG. 15 are listed in Table 4.

Table 4

[0054] FIG. 16 is a graph illustrating transfer characteristics of TFTs with InGaZnO TFTs with different gate dielectrics according to some embodiments of the disclosure and/or as illustrated in a non-limiting manner in the Examples. FIG. 16 shows graph 1600 with transfer characteristic curves 1602, 1604, and 1606 of InGaZnO TFTs with gate dielectric layers of Hf02, AI2O3, and S1O2. In some embodiments, the performance of the InGaZnO TFT with H 02 gate dielectric layer is desirable compared to the TFTs with AI2O3 and S1O2 as gate dielectrics. The electrical parameters of the TFTs of FIG. 16 are listed in Table 5.

Table 5

[0055] FIG. 17 is a graph 1700 illustrating transfer characteristics of an InGaZnO TFT made on a polyimide (PI) substrate according to some embodiments of the disclosure and/or as illustrated in a non-limiting manner in the Examples. FIG. 17 illustrates that high performance InGaZnO TFTs can be made on flexible substrates using our novel process.

[0056] FIG. 18 is a graph illustrating transfer characteristics of a TFT using InGaZnO semiconductor layer with In:Ga:Zn composition of 1 : 1 : 1 according to some embodiments of the disclosure and/or as illustrated in a non-limiting manner in the Examples. FIG. 18 shows graph 1800 of transfer characteristic curves 1802 and 1804 of TFTs fabricated using a InGaZnO target having In:Ga:ZnO ratio of 1 : 1 : 1 (molar ratio in target) at room temperature and 150 degrees Celsius, respectively, with ALD deposited HfCh as the gate dielectric. In some embodiments, desirable characteristics may be obtained with InGaZnO layer deposited at 150 degrees Celsius. In some embodiments, desirable characteristics may be obtained with InGaZnO deposition temperature of 150 degrees Celsius for a molar ratio of 1 : 1 : 1. In some embodiments, desirable characteristics may be obtained at deposition temperatures from RT to 80 degrees Celsius for molar ratio of 2: 1 : 1.

[0057] Oxide TFTs may be manufactured using manufacturing processes described above to obtain high-performance TFTs for electronic devices. The manufacturing processes may be performed at temperatures of less than 200 degrees Celsius, or less than 160 degrees Celsius, including deposition of a low-temperature ALD-deposited hafnium oxide (FKC ) gate insulator. In some embodiments, a post-annealing of the gate insulator is performed to reduce defects in the gate insulator. The manufactured oxide TFTs may exhibit high performance, including high field-effect mobility (> 15 cm²/Vs), high On-to-off drain current ratio (>10⁸), subthreshold swing (approximately 100 mV/decade), and/or low negative turn-on voltage. The manufactured oxide TFTs may exhibit enhanced device stability without using a passivation layer by using one or more of a low-temperature ALD-deposited Hf02 layer, low pressure sputtering, and a combination ALD Hf02 with InGaZnO. The manufactured oxide TFTs may allow for low-voltage operation with low turn-on voltage for integrated circuits (ICs), for driving circuits for touch and force sensors, for pull-up transistors, for analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), for TFT-based memory devices, for RFID devices, for oscillators, and/or for power management circuits. In embodiments with AZO as a gate electrode, the oxide TFTs may provide control over turn-on voltage (Von) and low cost. In embodiments with wet etching of InGaZnO, the oxide TFTs may be manufacture faster, more cost effectively, such as without expensive dry-etching vacuum techniques, and/or by not using an etch-stopper layer in dry-etching processes.

EXAMPLES

[0058] The present invention will be described in greater detail by way of specific examples. The following examples are offered for illustrative purposes only, and are not intended to limit the invention in any manner. Those of skill in the art will readily recognize a variety of noncritical parameters which can be changed or modified to yield essentially the same results. Example 1

(InGaZnO Thin Film Transistor Fabrication)

[0059] Step 1: Substrate preparation. Two types of substrates, 1.1 mm thick glass substrates and Polyimide PI-2611 (~6 um) films deposited on a silicon wafer were used to build the TFT devices. The glass substrates were sonicated in acetone, isopropanol and deionized water separately and then lastly blown-dried by a high purity nitrogen (N₂) gas gun. The PI film was prepared by spin coating of commercially available (HD Microsystems) PI-2611 solution for 30 seconds at 3000 rpm. The spin coated PI films were soft baked for 90 seconds at 90 °C and 150 °C and then finally cured at 350 °C for 30 minutes in air. [0060] Step 2: Barrier layer deposition for PI substrate. To prevent the diffusion of oxygen or water molecules from the PI substrate to the devices, about 30 nm of aluminum oxide (AI2O3) thin film was deposited on top of the PI film prior to the device fabrication. The AI2O3 film was deposited at 160 °C by atomic layer deposition (ALD) using a Savannah S200 G2 (Ultratech / Cambridge NanoTech) ALD system. Trimethylaluminum (TMA) from Sigma Aldrich as source of aluminum and deionized water (DIW) as the source of oxygen and N2 (20 seem) gas was used as the process gas. The pulse time of both TMA and DIW precursor was fixed as 0.015 seconds.

[0061] Step 3: Gate electrode deposition. Aluminum doped zinc oxide (AZO) thin film of thickness of approximately 170 nm was used as the gate electrode. The AZO films were deposited on cleaned glass and PI films by ALD at 160 °C using diethylzinc (DEZ) and trimethylaluminum (TMA) from Sigma Aldrich as the source of Zn and Al and DIW as the source of oxygen. The ratio of DEZ sub-cycle (DIW/N2-purge/DEZ/ N2-purge) to TMA sub- cycle (DIW/ N2-purge /TMA/ N2-purge) was fixed as 20: 1 to get AZO film with low sheet resistance (approximately 100 Ω/square). The supper cycle [(DIW/N2-purge/DEZ/ N2-purge) + (DIW/ N2-purge /TMA/ N2-purge)] was repeated 45 times to get AZO films with thickness of approximately 170 nm. The pulse time ofDEZ, TMA and DIW precursor was fixed as 0.015 seconds and 20 seem of N2 gas was used as the process gas.

[0062] Step 4: Gate electrode pattering. The AZO film was patterned by standard photolithography and wet etching. A 1.4 μπι, AZ1512 positive photoresist (PR) was first spin coated on the substrate. The PR layer was then exposed with a broadband UV light source at a dose of 43 mJcm^"2 and then developed using AZ 726 MIF developer to get the desired features of the gate electrode. The unwanted areas of the AZO film were then etched for 30 seconds using diluted (1% v/v) hydrochloric acid. After etching the AZO film the PR layer was removed by cleaning with acetone, isopropanol and DTvV and finally dried using N2 gas.

[0063] Step 5: Gate dielectric layer deposition and post annealing. Hafnium oxide (HfCh) was used as the gate dielectric. The HfCh gate dielectric layer was deposited on top of the AZO gate electrodes by ALD technique using tetrakis(dimethylamido)hafnium(IV) from Sigma Aldrich as the source of Hf and ozone as the source of oxygen and 90 seem of N2 gas was used as the process gas. The pulse time of tetrakis(dimethylamido)hafnium(IV) and ozone was fixed as 0.2 second and 0.15 second, respectively. The growth temperature for the HTO2 film was varied from 120 °C to 200 °C. After the Hf0₂ deposition, the films were post annealed in the temperature range of 100 °C to 200 °C in air for 2 hours.

[0064] Step 6: InGaZnO semiconductor layer deposition. Indium gallium zinc oxide thin film was deposited on top of the Hf0₂ layer by radiofrequency sputtering (Angstrom Engineering) from a 2" InGaZnO (In:Ga:Zn=l : l : l and 2: 1 : 1) target (Super Conductor Materials Inc.) under the deposition conditions as listed in Table 6.

Table 6

Oxygen flow (02)

total flow (Ar+02)

[0065] Step 6: InGaZnO semiconductor patterning. The InGaZnO semiconductor film was patterned by standard photolithography and wet etching. A 1.4 μπι AZ 1512 positive photoresist (PR) was first spin coated on the substrate. The PR layer was then exposed with a broadband UV light source at a dose of mJcm^"2 and then developed using AZ 726 MIF developer to get the desired features of the gate electrode. The unwanted areas of the InGaZnO film was then etched for 60 seconds using diluted (4% v/v) hydrochloric acid. After etching the InGaZnO film the PR layer from the gate electrodes was removed by cleaning with acetone, isopropanol and DIW and finally dried using N₂ gas. [0066] Step 7: Gate via patterning. To create access to the gate electrode through HfCh gate dielectric, via holes were formed by standard photolithography and dry etching. A 1.4 μιη AZ 1512 positive photoresist (PR) was first spin coated on the substrate. The PR layer was then exposed with a broadband UV light source at a dose of 43 mJcm^"2 and then developed using AZ 726 MIF developer to get the desired features of the via-hole pattern. Then HfCh layer from the gate via pattern was etched by dry etching using CH₃ (20 seem) and Ar gas (4 sscm) plasma with an etching rate of approximately 55 nm/minute. After etching the Hf0₂ film the PR layer from the Hf0₂ film was removed by cleaning with acetone, isopropanol and DIW and finally dried using N₂ gas. [0067] Step 8: Source-drain contact deposition and patterning. A bi-layer of 10 nm titanium and 60 nm gold source and drain electrodes were patterned using conventional photolithography techniques and electron-beam evaporation deposition. A 1.4 um-thick AZ 1512 positive photoresist (PR) was first spin coated on the substrate. The PR layer was then exposed with a broadband UV light source at a dose of 43 mJcm^"2 and a photomask to transfer the desired features. The PR was then developed using AZ 726 MIF developer for 22 seconds. Titanium (15 nm) and gold (60 nm) electrodes were then deposited using thermal evaporation deposition. Lift-off using acetone was performed to remove the unwanted areas and cleaned in isopropanol and DIW to complete the patterning process.

[0068] Step 10: Post-annealing of TFTs. After the whole fabrication process, the TFTs were annealed in the temperature range of 100 °C to 200 °C for 2 hours in air ambient to produce the TFTs of the present invention.

[0069] The current and voltage characteristics of TFTs were measured using an Agilent B1500A semiconductor device parameter analyzer and Cascade Summit 1100 probe station under dark and ambient conditions. Transfer characteristic curves of the TFTs were obtained by sweeping the voltage applied to the gate electrode at a fixed voltage applied to the drain electrode while the source electrode was maintained as the common electrode (grounded). Other TFTs were manufactured and the characteristics and properties are shown in Tables 1-5 and FIGS. 5-18.

[0070] Although the present disclosure and certain representative advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. For example, the described order, steps, operations, and manufacturing processes are indicative of aspects of methods of the invention. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more steps, or portions thereof, of the illustrated method. As another example, the terms positive and negative voltages are only relative terms. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

A method of manufacturing one or more thin film transistors (TFTs) on a substrate, the method comprising:

forming a gate electrode comprising a metal oxide for the one or more TFTs without exceeding a temperature of 200 degrees C;

forming a gate dielectric comprising hafnium oxide for the one or more TFTs without exceeding a temperature of 200 degrees C;

forming a metal-oxide-based semiconductor channel region for the one or more

TFTs without exceeding a temperature of 200 degrees C after forming the gate dielectric and without annealing the gate dielectric; and

forming source and drain regions for the one or more TFTs without exceeding a temperature of 200 degrees C.

The method of claim 1, wherein the method comprises forming the gate electrode on the substrate, forming the gate dielectric on the gate electrode, and forming the semiconductor channel region on the gate dielectric to form a bottom-gate thin TFT.

The method of claim 1, wherein the method comprises forming the semiconductor channel region on the substrate, forming the gate dielectric on the semiconductor channel region, and forming the gate electrode on the gate dielectric to form a top-gate TFT.

The method of claim 1, wherein the step of forming the gate electrode comprises performing atomic layer deposition (ALD) to deposit at least one of aluminum-doped zinc oxide (AZO), hafnium zinc oxide (Hf-ZnO), indium zinc oxide (InZnO), indium titanium oxide (ITO), tin oxide (SnCh), and indium oxide (ImCb) as the gate electrode.

depositing a gate electrode layer comprising a metal oxide electrode;

patterning the gate electrode layer to form one or more gate electrodes for the one or more TFTs;

depositing a gate dielectric layer comprising hafnium oxide on the one or more gate electrodes;

annealing the gate dielectric layer without exceeding a temperature of 200 degrees C; depositing a metal-oxide-based semiconductor layer on the gate dielectric layer; patterning the semiconductor layer to form one or more channel regions proximate to the one or more gate electrodes;

forming vias through the gate dielectric layer to the one or more gate electrodes; and

forming source and drain electrodes on the semiconductor layer proximate to the one or more gate electrodes to form the one or more TFTs.

6. The method of claim 5, wherein the step of depositing the gate electrode layer comprises depositing at least one of aluminum-doped zinc oxide (AZO), hafnium zinc oxide (Hf-ZnO), indium zinc oxide (InZnO), tin oxide (SnCh), indium oxide (ImCb), indium titanium oxide (ITO), a metal oxide, and a metal without exceeding a temperature of 200 degrees C.

7. The method of claim 5, wherein the step of depositing the gate electrode layer comprises depositing AZO by atomic layer deposition (ALD).

8. The method of claim 5, wherein the step of depositing the gate dielectric layer comprises depositing hafnium oxide without exceeding a temperature of 200 degrees C.

9. The method of claim 5, wherein the step of depositing the gate dielectric layer comprises depositing at least one of hafnium oxide and aluminum oxide by ALD.

10. The method of claim 5, further comprising the step of annealing the gate dielectric layer without exceeding a temperature of 200 degrees C.

11. The method of claim 5, wherein the step of depositing a metal-oxide-based semiconductor layer comprises depositing indium gallium zinc oxide (IGZO) without exceeding a temperature of 200 degrees C.

12. The method of claim 5, further comprising depositing a protection layer on the one or more TFTs.

13. The method of claim 5, further comprising annealing the one or more TFTs without exceeding a temperature of 200 degrees C.

14. The method of claim 5, wherein the step of forming source and drain electrodes comprises depositing a conductor comprising at least one of bi-layer of titanium (Ti) and gold (Au), Ti, molybdenum (Mo), chromium (Cr), copper (Cu), nickel (Ni)/Au, silver (Ag), ITO, Al-ZnO, and InZnO.

15. The method of claim 5, wherein the substrate is a flexible substrate.

16. The method of claim 5, wherein the substrate comprises a rigid substrate, and wherein the method further comprises preparing the substrate by depositing an insulating base layer on the substrate.

17. The method of claim 16, wherein the insulating base layer comprises polyimide, and wherein the method further comprises depositing a barrier layer on the insulating base layer before depositing the gate electrode layer.

18. The method of claim 17, wherein the step of depositing the barrier layer comprises depositing an aluminum oxide by ALD.

19. A thin film transistor made by the process of claims 1 or 5.

20. An electronic device comprising a plurality of thin film transistors made by the process of claims 1 or 5.