WO2019078605A1 - Gate drive circuit and power switch control apparatus including same - Google Patents

Abstract

The present invention relates to a power switch control apparatus, and more particularly, to a power switch control apparatus including a PWM control unit for generating and outputting a plurality of control signals for controlling a soft switching operation of a power switch; And a gate driving circuit capable of driving the soft switching operation by adjusting a gate driving current according to a plurality of control signals input from the PWM control unit in a predetermined pattern when the power switch is turned on or off do.

Description

Gate drive circuit and power switch control device including the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driving circuit and a power switch control apparatus including the same, and more particularly, And a power switch control device including the same.

Generally, a power source is a semiconductor device that performs power conversion or control, and a rectifier diode, a power transistor, and a triac are widely used in various fields such as industry, information, communication, traffic, power, and home.

As a power source, there are a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and an electric power integrated circuit (IC), among which power switching is possible in particular, MOSFET switches are attracting attention.

In order to drive such a power MOSFET switch, it is necessary to turn on / turn off as fast as possible. To this end, a gate drive circuit for driving a power MOSFET switch at high speed is required, and several gate drive circuits have been conventionally proposed.

1 is a diagram showing an example of a power MOSFET gate drive circuit according to the related art. 1, a conventional MOSFET gate driving circuit 10 includes a first pre-driver 11, a P-type transistor 12, a first resistive element 13, a second pre-driver 14, N Type transistor 15 and a second resistance element 16. [

The MOSFET gate drive circuit 10 can drive the switching operation of the power switch 30 in accordance with the pulse width control signal output from the PWM control section 20. [ That is, the MOSFET gate driving circuit 10 turns on the P-type transistor 12 through the first pre-driver 11 and turns on the N-type transistor 15 through the second pre- Off of the power switch 30 to turn on the turn-on operation of the power switch 30.

The MOSFET gate driving circuit 10 also turns off the P-type transistor 12 through the first pre-driver 11 and turns off the N-type transistor 15 through the second pre- And turn on the power switch 30 to turn it on.

However, in the power switch using the conventional gate driving circuit, ripple phenomenon occurs at the time when the drain current I _D becomes a peak at the turn-on operation, and a turn-off operation A ripple phenomenon occurs at a point of time when the drain-source voltage V _DS becomes a peak. The switching noise, which is a ripple component caused by the Miller effect, causes the EMI (Electro Magnetic Interference) characteristic of the power switch to deteriorate.

On the other hand, when the power switch is driven by increasing the driving current, the switching loss can be reduced by improving the driving frequency or the switching time, but there is a disadvantage that the ripple component becomes larger due to the increased driving current. As described above, the power MOSFET gate drive circuit according to the related art maintains a trade-off relationship between switching loss and EMI characteristics.

In addition, since the driving current is fixed when designing the power MOSFET gate drive circuit, it is difficult to control it according to the application. In addition, there is a problem that an EMI problem occurs due to hard switching of the gate driving circuit when the power switch is turned on or off.

Therefore, in order to reduce the switching loss without deteriorating the EMI characteristics, a gate driving circuit is required which can be driven at an optimum point between the switching loss and the EMI characteristic by freely controlling the magnitude of the gate driving current. In addition, a gate drive circuit is needed to easily adjust the gate drive current depending on the application. In addition, a gate driver circuit capable of gradually adjusting the gate drive current to implement soft switching in a turn-on or turn-off operation is needed.

The present invention is directed to solving the above-mentioned problems and other problems. Another object of the present invention is to provide a power MOSFET gate driving circuit capable of gradually adjusting a gate driving current according to a plurality of control signals to which binary coding is applied, and a power switch control apparatus including the same.

Another object of the present invention is to provide a power MOSFET gate drive circuit capable of gradually adjusting the gate drive current to drive the soft switch operation of the power switch in the turn-on or turn-off operation of the power switch, and a power switch control device including the same .

According to an aspect of the present invention, there is provided a method of controlling a soft switching operation of a power switch, the method comprising: generating a plurality of control signals for controlling a soft switching operation of the power switch; And a gate driving circuit capable of driving the soft switching operation by adjusting a gate driving current according to a plurality of control signals input from the PWM control unit in a predetermined pattern when the power switch is turned on or off The power switch control apparatus comprising:

More preferably, the PWM control unit outputs a plurality of control signals based on the reference pulse width control signal received from the controller. In addition, the predetermined pattern is a pattern for gradually applying a gate driving current at a maximum value and decreasing it. The predetermined pattern is a pattern for gradually increasing the gate driving current to a maximum value.

More preferably, the PWM control unit outputs a plurality of control signals capable of operating each of the plurality of driving circuits, and the gate driving circuit controls the plurality of driving circuits individually based on the plurality of control signals And outputting the output current at a maximum value, and then gradually reducing the output current. The PWM control unit outputs a plurality of control signals capable of operating each of the plurality of driving circuits, and the gate driving circuit controls the plurality of driving circuits individually based on the plurality of control signals, And gradually increases to a maximum value.

More preferably, the gate drive circuit includes a plurality of drive circuits for generating at least one of a gate source current and a gate sink current. The gate driving circuit outputs a total of 2 ⁿ gate driving currents through binary coding of a plurality of control signals, and n corresponds to the number of the plurality of control signals. Each of the plurality of driver circuits includes P-type and N-type transistors having different transistor sizes so that binary coding is possible. Each of the plurality of driver circuits may include a P-type transistor and an N-type transistor having the same transistor size.

Effects of the power MOSFET gate driving circuit and the power switch control device including the power MOSFET gate driving circuit according to the embodiments of the present invention will be described as follows.

According to at least one of the embodiments of the present invention, the gate drive current is stepwise (or gradually) adjusted by using a plurality of control signals to which binary coding is applied, thereby increasing the gate drive current when a large amount of current is required for high- In order to improve the EMI characteristic, there is an advantage that the gate driving current can be reduced.

According to at least one of the embodiments of the present invention, when the power switch is turned on or off, the gate drive current is stepwise (or gradually) adjusted to drive the soft switching operation to effectively improve the EMI characteristics of the power switch There is an advantage that it can be.

However, the effects that can be achieved by the power MOSFET gate driving circuit and the power switch control device including the same according to the embodiments of the present invention are not limited to those mentioned above, It will be understood by those skilled in the art that the present invention can be understood by those skilled in the art.

1 is a diagram showing an example of a power MOSFET gate drive circuit according to the prior art;

2 is a diagram illustrating a configuration of a power switch system according to an embodiment of the present invention;

Fig. 3 is a diagram showing one configuration of the first drive circuit shown in Fig. 2;

Fig. 4 is a diagram showing one configuration of the second drive circuit shown in Fig. 2;

Fig. 5 is a diagram showing one configuration of the third drive circuit shown in Fig. 2;

6A is a diagram illustrating a detailed configuration of a power switch system according to an embodiment of the present invention;

FIG. 6B is a view for explaining a change in gate drive current according to binary coding of control signals; FIG.

7 is a diagram showing a configuration of a power switch system according to another embodiment of the present invention;

8 to 10 are diagrams referred to explain a soft switching driving method according to the first embodiment of the present invention;

11 to 13 are referred to for describing a soft switching driving method according to a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals are used to designate identical or similar elements, and redundant description thereof will be omitted. The suffix " module " and " part " for the components used in the following description are given or mixed in consideration of ease of specification, and do not have their own meaning or role.

In the following description of the embodiments of the present invention, a detailed description of related arts will be omitted when it is determined that the gist of the embodiments disclosed herein may be blurred. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. , ≪ / RTI > equivalents, and alternatives.

The present invention proposes a power MOSFET gate driving circuit capable of gradually adjusting a gate driving current according to a plurality of control signals to which binary coding is applied, and a power switch control apparatus including the same. In addition, the present invention proposes a power MOSFET gate driving circuit and a power switch control device including the power MOSFET switch for gradually switching the gate driving current to perform soft switching when the power switch is turned on or off.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings.

2 is a diagram showing a configuration of a power switch system according to an embodiment of the present invention. Figs. 3 to 5 are diagrams showing the detailed configurations of the first to third drive circuits shown in Fig. 2. Fig.

2 through 5, the power switch system 200 according to an embodiment of the present invention may include a power switch 210 and a power switch control device. Here, the power switch control apparatus may include a PWM control unit 220 and a gate drive circuit 230. 2 are not required to implement the power switch system 200, the power switch system described herein may have more or less components than those listed above .

The power switch 210 may include a power MOSFET composed of a gate G, a drain D and a source S as a kind of power device. The power MOSFET 210 has high speed and strong characteristics for high voltage and high current driving.

When an N-type transistor (NMOS) is used as the power switch 210, a gate voltage V _G having a high level is turned on and a gate voltage V c having a low level (V _G ). ≪ / RTI > Conversely, when the P-type transistor (NMOS) is used as the power switch 210, the gate is turned on by the gate voltage V _G having a low level, And is turned off by the gate voltage V _G.

The PWM control unit 220 may generate and output a plurality of control signals for controlling the soft switching operation of the power switch 210 based on the reference pulse width control signal received from the controller (not shown). In the present embodiment, the PWM control unit 220 generates and outputs a total of six control signals.

The reference pulse width control signal output from the controller adjusts the amount of current by adjusting the turn-on time of the power switch according to the pulse width. The logic level of the control signals output from the PWM control unit 220 is generally equal to the output level of the controller. The PWM control unit 220 may receive a pulse width control signal of a low voltage (for example, 3V to 5V) equal to the output level of the controller or may receive a high voltage (for example, ) Pulse width control signal.

When the PWM control unit 220 outputs low voltage signals (for example, a control signal of 3V), the gate drive circuit 230 outputs the low voltage signals to the high voltage signals (for example, , 20 V or more).

The PWM control unit 220 can adjust the gate driving current of the power switch 210 to eight levels by using three control signals to which binary coding is applied. At this time, the PWM control unit 220 may adjust the gate driving current stepwise (or gradually) according to the operation state of the power switch 210. [

The gate drive circuit 230 may generate the drive voltage V _G and the drive current I _G for driving the soft switching operation of the power switch 210. For example, the gate driving circuit 230 increases the driving voltage V _G when the control signal input from the PWM control unit 220 is at the high level, and increases the control signal input from the PWM control unit 220 to the low level , The driving voltage V _G can be reduced.

The gate drive circuit 230 may be configured to have a different size according to the values of the three control signals V _P1 , V _P2 , and V _P3 input from the PWM control unit 220 during the turn- (= 2 ³ ) gate drive currents (I _G ) having the gate drive currents I _G having I (= 2 ³ ). The gate drive circuit 230 may be turned on and off according to the values of the three control signals V _N1 , V _N2 , and V _N3 input from the PWM control unit 220 during the power- It is possible to output 8 (= 2 ³ ) gate drive currents I _G having different sizes.

To this end, the gate driving circuit 230 may include a first driving circuit 231, a second driving circuit 232, and a third driving circuit 233.

The first driving circuit 231 has a function of generating a first source current I _G, source 1 for driving the power switch 210 in accordance with the first control signal V _P1 output from the PWM control unit 220 Can be performed. The first driving circuit 231 generates a first sink current I _{G and} sink 1 for driving the power switch 210 in accordance with the second control signal V _N1 output from the PWM control unit 220 Can be performed.

3, the first driving circuit 231 includes a first pre-driver 310, a P-type transistor 320, a first resistive element 330, a second pre-driver 340 ), An N-type transistor 350, and a second resistive element 360.

The first pre-driver 310 may perform a function of driving the P-type transistor 320 according to the first control signal V _P1 output from the PWM control unit 220. Meanwhile, in another embodiment, the first pre-driver 310 may be configured to perform the function of the level shifter described above in addition to the function of driving the P-type transistor 320.

The P-type transistor 320 is connected between the first pre-driver 310 and the power switch 210 and includes a first source current I _G for driving the turn- _{, source1} ). At this time, the P-type transistor 320 may be a BJT element, and more preferably a P-type MOSFET element. A first resistor element 330 may be coupled to a drain terminal of the P-type MOSFET device 320.

The second pre-driver 340 may perform the function of driving the N-type transistor 350 according to the second control signal V _N1 output from the PWM controller 220. Meanwhile, in another embodiment, the second pre-driver 340 may be configured to perform the function of the level shifter described above in addition to the function of driving the N-type transistor 350.

The N-type transistor 350 is connected between the second pre-driver 340 and the power switch 210 and includes a first sink current I _G for driving a turn off operation of the power switch 210, _{, sink1} ). At this time, the N-type transistor 350 may be a BJT element, and more preferably an N-type MOSFET element. A second resistor element 360 may be connected to a drain terminal of the N-type MOSFET element 350.

The second driving circuit 232 has a function of generating a second source current I _G, source 2 for driving the power switch 210 in accordance with the third control signal V _P2 output from the PWM control unit 220 Can be performed. The second driving circuit 232 generates a second sink current I _{G and} sink 2 for driving the power switch 210 in accordance with the fourth control signal V _N2 output from the PWM control unit 220 Can be performed.

4, the second driver circuit 232 includes a third pre-driver 410, a P-type transistor 420, a third resistive element 430, a fourth pre-driver 440 ), An N-type transistor 450, and a fourth resistance element 460.

The third pre-driver 410 may perform a function of driving the P-type transistor 420 according to the third control signal V _P2 output from the PWM control unit 220. Meanwhile, in another embodiment, the third pre-driver 410 may be configured to perform the function of the level shifter described above in addition to the function of driving the P-type transistor 420. The third pre-driver 410 may be the same as the first pre-driver 310 of the first driving circuit 231 or may vary the driving current magnitude of the pre-driver.

The P-type transistor 420 is connected between the third pre-driver 410 and the power switch 210 and includes a second source current I _G for driving the turn- _{, source2} ). The Width / Length ratio of the P-type transistor 420 can be made double the P-type transistor 320 of the first driving circuit 231 so that the second source current is twice the first source current. At this time, the P-type transistor 420 may be a BJT element, and more preferably, a P-type MOSFET element. A third resistance element 430 may be connected to a drain terminal of the P-type MOSFET device 420.

The fourth pre-driver 440 may perform the function of driving the N-type transistor 450 according to the fourth control signal V _N2 output from the PWM controller 220. Meanwhile, in another embodiment, the fourth pre-driver 440 may be configured to perform the function of the level shifter described above in addition to the function of driving the N-type transistor 450. The fourth pre-driver 440 may be the same as the second pre-driver 340 of the first driving circuit 231 or may vary the driving current magnitude of the pre-driver.

The N-type transistor 450 is connected between the fourth pre-driver 440 and the power switch 210 and includes a second sink current I _G for driving a turn-off operation of the power switch 210, _{, sink2} ). The Width / Length ratio of the N-type transistor 450 can be made double the N-type transistor 350 of the first driving circuit 231 so that the second sink current is twice the first sink current. At this time, the N-type transistor 450 may be a BJT element, and more preferably an N-type MOSFET element. A fourth resistor 460 may be coupled to a drain terminal of the N-type MOSFET device 450.

The third driving circuit 233 has a function of generating a third source current I _{G and} source 3 for driving the power switch 210 in accordance with the fifth control signal V _P3 output from the PWM control unit 220 Can be performed. The third driving circuit 233 generates a third sink current I _{G and} sink 3 for driving the power switch 210 according to the sixth control signal V _N3 output from the PWM control unit 220 Can be performed.

5, the third driver circuit 233 includes a fifth pre-driver 510, a P-type transistor 520, a fifth resistor 530, a sixth pre-driver 540, an N-type A transistor 550, and a sixth resistive element 560.

The fifth pre-driver 510 may perform a function of driving the P-type transistor 520 according to the fifth control signal V _P3 output from the PWM control unit 220. Meanwhile, in another embodiment, the fifth pre-driver 510 may be configured to perform the function of the level shifter described above in addition to the function of driving the P-type transistor 520. [ The fifth pre-driver 510 may be the same as the first and third pre-drivers 310 and 410, or may vary the driving current magnitude of the pre-driver.

The P-type transistor 520 is connected between the fifth pre-driver 510 and the power switch 210 and includes a third source current I _G for driving the turn- _{, source3} ). The Width / Length ratio of the P-type transistor 520 may be four times that of the P-type transistor 320 of the first driving circuit 231 so that the third source current may be four times the first source current. At this time, the P-type transistor 520 may be a BJT element, and more preferably a P-type MOSFET element. A fifth resistance element 530 may be connected to the drain terminal of the P-type MOSFET element 520.

The sixth pre-driver 540 may perform the function of driving the N-type transistor 550 according to the sixth control signal V _N3 output from the PWM controller 220. Meanwhile, in another embodiment, the sixth pre-driver 540 may be configured to perform the function of the level shifter described above in addition to the function of driving the N-type transistor 550. The sixth pre-driver 540 may be the same as the second and fourth pre-drivers 340 and 440 or may vary the driving current magnitude of the pre-driver.

The N-type transistor 550 is connected between the sixth pre-driver 540 and the power switch 210 and includes a third sink current I _G for driving a turn-off operation of the power switch 210, _{, &lt}; _{/ RTI &} gt _{; sink3} ). The Width / Length ratio of the N-type transistor 550 can be made to be four times that of the N-type transistor 350 of the first driving circuit 231 so that the third sink current is four times the first sink current. At this time, the N-type transistor 550 may be a BJT element, and more preferably an N-type MOSFET element. A second resistance element 560 may be connected to a drain terminal of the N-type MOSFET element 550.

FIG. 6A is a diagram illustrating a detailed configuration of a power switch system according to an embodiment of the present invention, and FIG. 6B is a view for explaining a change in a gate driving current according to binary coding of control signals.

6A and 6B, during the turn-on operation of the power switch 210, the gate driving circuit 230 outputs the first control signal V _P1 , which is input from the PWM control unit 220, 1 driver circuit 231 to generate the first source current I _G, source 1.

The gate driving circuit 230 may generate the second source current I _{G and} source 2 by operating the second driving circuit 232 according to the third control signal V _P2 input from the PWM control unit 220 .

The gate driving circuit 230 may generate the third source current I _{G and} source 3 by operating the third driving circuit 233 according to the fifth control signal V _P3 input from the PWM control unit 220 .

As described above, the first source current I _G, source 1 generated in the first driving circuit 231, the second source current I _G, source 2 generated in the second driving circuit 232, the third driving circuit 233 The third source current I _G, source 3 generated in the power switch 210 flows in the direction of increasing the gate voltage of the power switch 210 by charging the input capacitance of the power switch 210. At this time, the second source current (I _{G, source2)} size can be two times the first source current (I _{G, source1)} size, the third size of the source current (I _{G, source3)} a first source current ( I _{G, source 1} ).

The power switch control apparatus controls the power switch (not _shown ) through the binary coding of the first control signal V _P1 , the third control signal V _P2 and the fifth control signal V _P3 during the turn- 210) can be controlled in a total of eight steps.

6B, the power switch control apparatus controls the power switch 210 according to the operation state of the power switch 210 such that 0, the first source current I _G, source 1, the second source current I _G, source 2, 1, the source current + the second source current, and the third source current (I _{G, source3),} the first source current + the third source current, the second source current + the third source current, the first source current + the second source current + The third source current can be adjusted stepwise (or gradually).

During the turn off operation of the power switch 210, the gate driving circuit 230 _drives the first driving circuit 231 in accordance with the second control signal V _N1 input from the PWM control unit 220 To generate the first sink current I _G, sink 1.

The gate driving circuit 230 may generate the second sink current I _{G and sink2} by operating the second driving circuit 232 according to the fourth control signal V _N2 input from the PWM control unit 220 .

The gate drive circuit 230 may generate the third sink current I _{G and} sink 3 by operating the third drive circuit 233 according to the sixth control signal V _N3 input from the PWM control unit 220 .

As described above, the first sink current I _G, sink 1 generated in the first driving circuit 231, the second sink current I _G, sink 2 generated in the second driving circuit 232, the third driving current I _R, The third sink current I _G, sink 3 generated in the power switch 210 is discharged in the direction of reducing the gate voltage of the power switch 210 by discharging the input capacitance of the power switch 210. At this time, the second amount of sink current size are first sink current (I _{G, sink1)} can be two times the size of the third sink current (I _{G, sink3)} of (I _{G, sink2)} a first sink current ( I _{G, sink 1} ).

The power switch control apparatus controls the power switch (not shown) through the binary coding of the second control signal V _N1 , the fourth control signal V _N2 and the sixth control signal V _{N3 in the} turn off operation 210) can be controlled in a total of eight steps.

6B, the power switch control apparatus controls the power switch 210 such that 0, the first sink current I _G, sink 1, the second sink current I _G, 1 sink current + second sink current, third sink current I _G, sink 3, first sink current + third sink current, second sink current + third sink current, first sink current + second sink current + The third sink current can be adjusted stepwise (or gradually).

As such, the power switch control device adjusts the gate driving current stepwise (or gradually) according to the operation state of the power switch 210, thereby increasing the gate driving current when a large amount of current is required for high-speed driving, The gate drive current can be reduced.

In the present embodiment, the power switch control device controls the gate driving current step by step according to the operation state of the power switch 210. However, the present invention is not limited thereto, It will be apparent to those skilled in the art that the driving current may be randomly adjusted.

7 is a diagram showing a configuration of a power switch system according to another embodiment of the present invention.

Referring to FIG. 7, a power switch system 700 according to another embodiment of the present invention may include a power switch 710 and a power switch control apparatus. Here, the power switch device may include a PWM control unit 720 and a gate drive circuit 730. The power switch 710 shown in FIG. 7 is the same as or similar to the power switch 210 shown in FIG. 2, so a detailed description thereof will be omitted.

The PWM control unit 720 can generate and output a plurality of control signals for controlling the soft switching operation of the power switch 710. In the present embodiment, the PWM control unit 720 generates and outputs 2m control signals.

The PWM control unit 720 can adjust the gate driving current of the power switch 710 to a total of ^2m steps using m control signals to which binary coding is applied. At this time, the PWM control unit 720 can adjust the gate driving current stepwise (or gradually) according to the operation state of the power switch 710. [

The gate drive circuit 730 can generate the drive voltage V _G and the drive current I _G for driving the soft switching operation of the power switch 710. [ For example, the gate driving circuit 730 may control the signal can be when the high level, and increasing the gate drive voltage (V _G) and the control signal is reduced to a gate drive voltage (V _G) when the low-level .

The gate driving circuit 730 may output 2 ^m gate driving currents I _G having different sizes according to the values of the m control signals input from the PWM control unit 720. To this end, the gate drive circuit 730 may include m drive circuits 730_1 to 730_m.

The first driving circuit 730_1 is connected to a first source current (V1) for driving the power switch 710 in accordance with the first control signal V _P1 and the second control signal V _N1 output from the PWM control unit 720, I _G, source 1) and the first sink current I _G, sink 1.

The second driving circuit 730_2 generates a second source current (for driving the power switch 710) according to the third control signal V _P2 and the fourth control signal V _N2 output from the PWM control unit 720, I _G, source 2) and a second sink current (I _G, sink 2).

The m-th driving circuit 730_m includes an m-th driving circuit 730_m for driving the power switch 710 in accordance with the second m-1 control signal V _Pm and the second m control signal V _Nm output from the PWM control unit 720, The current I _{G, the source m} , and the m th sink current I _{G, sink m} .

The sizes of the P-type and N-type transistors of the second driving circuit 730_2 may be twice the sizes of the P-type and N-type transistors of the first driving circuit 730_1. The P-type and N-type transistor sizes of the m-th driving circuit 730_m may be 2 ^m-1 times the P-type and N-type transistor sizes of the first driving circuit 730_1.

Due to the transistor size ratio of the first and second driving circuits 730_1 and 730_2, the magnitude of the second driving current I _{G, source2} , I _{G, and sink2} generated in the second driving circuit _{730_2} , (I _G, source 1, I _{G, sink} 1) generated by the first driving current generator 730_1.

Also, the magnitude of the m-th driving current I _{G, source m} , I _{G, and sink m} generated in the m-th driving circuit 730_m due to the transistor size ratio of the first and the m-th driving circuits 730_1 and 730_m May be 2 ^m-1 times the magnitude of the first driving current I _G, source 1, I _{G, sink} 1 generated in the first driving circuit 730 _{_} ¹ .

The power switch control apparatus controls the gate drive current (Vp) of the power switch 710 through the binary coding of the first control signal (V _P1 ) to the second m-1 control signal (V _Pm ) during the turn- Source current) can be adjusted to a total of 2 ^m steps.

On the other hand, during the turn-off operation, the power switch control apparatus controls the gate drive current (V _N1 ) of the power switch 710 through the binary coding of the second control signal V _N1 to the second m control signal V _Nm That is, the sink current) can be adjusted to a total of 2 ^m steps.

As described above, the power switch control device adjusts the gate drive current stepwise (or gradually) according to the operation state of the power switch 710, thereby reducing the switching loss without increasing the switching noise of the power MOSFET .

In this embodiment, the sizes of the P-type transistors and the N-type transistors constituting the plurality of driver circuits are different from each other, but the present invention is not limited thereto, and the P-type and N-type transistors It will be obvious to those skilled in the art that the sizes of the electrodes may be made equal to each other.

Hereinafter, various embodiments for driving the soft switching operation of the power switches 210 and 710 using the gate driving circuit 230 and 730 according to the present invention will be described in detail.

8 to 10 are views referred to explain a soft switching driving method according to the first embodiment of the present invention.

8 to 10, the PWM control unit 220 includes a plurality of control signals V _P1 , V _P2 , V _P3 , V _N1 , V _N2 , and V V for controlling the soft switching operation of the power switch 210 _N3 can be generated and output. At this time, the PWM controller 220 generates a plurality of control signals V _P1 , V _P2 , V _P3 , V _N1 , V _N2 , and V V3 based on the reference pulse width control signal V _{PWM_C} received from the controller _N3 ).

The PWM control unit 220 outputs a second control signal V _N1 , a fourth control signal V _N2 , and a third control signal V _N2 having a waveform in an off state at the turn-on operation of the power switch 210, 6 control signal V _N3 . For example, the PWM control unit 220 generates the second control signal V _N1 having the low level waveform, the fourth control signal V _N2 , and the fourth control signal V _N2 based on the on timing of the reference pulse width control signal V _{PWM_C} . And the sixth control signal V _N3 .

The PWM control unit 220 generates a first control signal for generating the first source current I _G, source 1 through the first driving circuit 231 during the turn on operation of the power switch 210 the third source via a V _P1) and the second driving circuit (third control signal (V _P2) and (233 to the third driver circuit for generating a second source current (I _{G, source2)} through 232)) And output a fifth control signal V _P3 for generating the current I _{G, source} 3.

More specifically, the PWM control unit 220 determines the time difference between the ON timing of the reference pulse width control signal V _{PWM_C} and the OFF state control signals V _N1 , V _N2 , and V _N3 , the first control signal (V _P1) having the form of a waveform shown in (a) of Fig. 9 has a time), it is possible to output a third control signal (V _P2) and the fifth control signal (V _P3).

The PWM control unit 220 controls the first control signal V _P1 in the off state, the third control signal V _P2 and the fifth control signal V _{P2 in the} turn off operation of the power switch 210, (V _P3 ). For example, the PWM control unit 220 generates the first control signal V _P1 having the waveform of the high-level form, the third control signal V _P2 (V _P2 ) based on the off timing of the reference pulse width control signal V _{PWM_C} , And a fifth control signal V _P3 .

The PWM control unit 220 generates a second control signal for generating the first sink current I _{G and} sink 1 through the first driving circuit 231 during the turn off operation of the power switch 210 V _N1 via the third driving circuit 233 and a fourth control signal V _N2 for generating the second sink current I _{G and} sink 2 through the second driving circuit 232, And output a sixth control signal V _N3 for generating the current I _{G, sink3} .

More specifically, the PWM control unit 220 determines a time difference (dead) between the off timing of the reference pulse width control signal V _{PWM_C} and the off state control signals V _P1 , V _P2 , and V _P3 (V _N1 ), the fourth control signal (V _N2 ), and the sixth control signal (V _N3 ) having a waveform shown in FIG. 9 (b).

The gate driving circuit 230 performs a soft switching operation of the power switch 210 according to a plurality of control signals V _P1 , V _P2 , V _P3 , V _N1 , V _N2 , and V _N3 output from the PWM control unit 220 Can be driven.

The gate driving circuit 230 may control the first to the fourth control signals in accordance with the control signals V _P1, V _{P2, and} V _P3 input from the PWM control unit 220 during the turn- a third drive circuit to operate the P-type transistors (320, 420, 520) of (231, 232, 233) generates the first to the third source current _{(I G, source1, I G} , source2, I G, source3) can do. At this time, the gate driving circuit 230 completely turns on the P-type transistors 320, 420, 520 of the first to third driving circuits 231, 232, 233, It is possible to drive the soft switching operation.

9 (a), the gate drive circuit 230 generates gate source current I _{G, source} (I _{G, source} ) using control signals V _P1, V _{P2, and} V _P3 to which binary coding is applied _, (7I ₀ -> 6I ₀ -> 5I ₀ -> 4I ₀ -> 3I ₀ -> 2I ₀ -> I ₀ ). This allows the gate drive circuit 230 to generate the gate source current I _G as shown in Figure 10 and to drive the soft switching operation of the power switch 210 based on the gate source current can do.

The gate driving circuit 230 may control the first to the third control signals _{VN1, VN2, and VN3} according to the control signals _{VN1, VN2, and VN3} input from the PWM control unit 220 during the turn- a third drive circuit to operate the N-type transistors (350, 450, 550) of (231, 232, 233) generates the first to third sink current _{(I G, sink1, I G} , sink2, I G, sink3) can do. At this time, the gate driving circuit 230 completely turns on the N-type transistors 350, 450 and 550 of the first to third driving circuits 231, 232 and 233 and turns them off stepwise It is possible to drive the soft switching operation.

9 (b), the gate driving circuit 230 generates the gate-sink current I _{G, sink} (i) using the binary-coded control signals V _N1, V _{N2, and} V _{N3 ,} (7I ₀ -> 6I ₀ -> 5I ₀ -> 4I ₀ -> 3I ₀ -> 2I ₀ -> I ₀ ) after the application of the gate current is maximized. This allows the gate drive circuit 230 to generate a gate sink current I _{G, sink} as shown in FIG. 10 and to drive the soft switching operation of the power switch 210 based on the gate sink current can do.

As described above, in the gate driving circuit according to the preferred embodiment of the present invention, when the power switch is turned on or off, the gate driving current is stepped down to drive the soft switching operation, thereby effectively improving the EMI characteristic of the power switch .

11 to 13 are diagrams for explaining the soft switching driving method according to the second embodiment of the present invention.

11 to 13, the PWM control unit 220 includes a plurality of control signals V _P1 , V _P2 , V _P3 , V _N1 , V _N2 , and V V for controlling the soft switching operation of the power switch 210 _N3 can be generated and output.

The PWM control unit 220 controls the PWM control unit 220 to turn off the power switch 210 based on the on timing of the reference pulse width control signal V _{PWM_C during} the turn- 2 control signal V _N1 , a fourth control signal V _N2 , and a sixth control signal V _N3 .

The PWM control unit 220 generates a first control signal for generating the first source current I _G, source 1 through the first driving circuit 231 during the turn on operation of the power switch 210 the third source via a V _P1) and the second driving circuit (third control signal (V _P2) and (233 to the third driver circuit for generating a second source current (I _{G, source2)} through 232)) And output a fifth control signal V _P3 for generating the current I _{G, source} 3.

More specifically, the PWM control unit 220 determines the time difference between the ON timing of the reference pulse width control signal V _{PWM_C} and the OFF state control signals V _N1 , V _N2 , and V _N3 , (V _P2 ), the third control signal (V _P2 ), and the fifth control signal (V _P3 ) having a waveform of the type shown in FIG. 12 (a).

The PWM control unit 220 generates a first control signal in an off state based on the off timing of the reference pulse width control signal V _{PWM_C} during the turn off operation of the power switch 210, (V _P1 ), a third control signal (V _P2 ), and a fifth control signal (V _P3 ).

The PWM control unit 220 generates a second control signal for generating the first sink current I _{G and} sink 1 through the first driving circuit 231 during the turn off operation of the power switch 210 V _N1 via the third driving circuit 233 and a fourth control signal V _N2 for generating the second sink current I _{G and} sink 2 through the second driving circuit 232, And output a sixth control signal V _N3 for generating the current I _{G, sink3} .

More specifically, the PWM control unit 220 determines a time difference (dead) between the off timing of the reference pulse width control signal V _{PWM_C} and the off state control signals V _P1 , V _P2 , and V _P3 the second control signal V _N1 , the fourth control signal V _N2 , and the sixth control signal V _N3 having the waveforms shown in FIG. 12 (b).

The gate driving circuit 230 performs a soft switching operation of the power switch 210 according to a plurality of control signals V _P1 , V _P2 , V _P3 , V _N1 , V _N2 , and V _N3 output from the PWM control unit 220 Can be driven.

The gate driving circuit 230 may control the first to the fourth control signals in accordance with the control signals V _P1, V _{P2, and} V _P3 input from the PWM control unit 220 during the turn- a third drive circuit to operate the P-type transistors (320, 420, 520) of (231, 232, 233) generates the first to the third source current _{(I G, source1, I G} , source2, I G, source3) can do. At this time, the gate drive circuit 230 can drive a soft switching operation for stepping on the P-type transistors 320, 420, 520 of the first to third drive circuits 231, 232, 233 have.

12 (a), the gate drive circuit 230 generates gate source current I _{G, source} (I _{G, source} ) using control signals V _P1, V _{P2, and} V _P3 to which binary coding is applied _, (I ₀ -> 2I ₀ -> 3I ₀ -> 4I ₀ -> 5I ₀ -> 6I ₀ -> 7I ₀ -> 7I ₀ -> 7I ₀ ) to the maximum. This allows the gate drive circuit 230 to generate the gate source current I _G as shown in Figure 13 and to drive the soft switching operation of the power switch 210 based on the gate source current can do.

The gate driving circuit 230 may control the first to the third control signals _{VN1, VN2, and VN3} according to the control signals _{VN1, VN2, and VN3} input from the PWM control unit 220 during the turn- a third drive circuit to operate the N-type transistors (350, 450, 550) of (231, 232, 233) generates the first to third sink current _{(I G, sink1, I G} , sink2, I G, sink3) can do. At this time, the gate driving circuit 230 can drive a soft switching operation for gradually turning on the N-type transistors 350, 450 and 550 of the first to third driving circuits 231, 232 and 233 have.

12 (b), the gate driving circuit 230 generates a gate-sink current I _{G, sink} (i) using the binary-coded control signals V _N1, V _{N2, and} V _{N3 ,} (I ₀ -> 2I ₀ -> 3I ₀ -> 4I ₀ -> 5I ₀ -> 6I ₀ -> 7I ₀ -> 7I ₀ -> 7I ₀ ) to the maximum. This allows the gate drive circuit 230 to generate a gate sink current I _{G, sink} as shown in FIG. 13 and to drive the soft switching operation of the power switch 210 based on the gate sink current can do.

As described above, in the gate driving circuit according to the preferred embodiment of the present invention, when the power switch is turned on or off, the gate driving current is stepped up to drive the soft switching operation to effectively improve the EMI characteristic of the power switch .

On the other hand, in various embodiments of the present invention, in the turn-on or turn-off operation of the power switch, the gate drive current is stepped down to drive the soft switching operation or the gate drive current is stepped up to drive the soft switching operation However, the present invention is not limited thereto. Thus, it will be apparent to those skilled in the art that the gate drive current may be stepped up and then the gate drive current may be stepped down to drive a soft switching operation. It will also be apparent to those skilled in the art that the gate drive current can be stepped up and then the gate drive current can be instantaneously decreased to drive the soft switching operation.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Of the right.

Claims (10)

A PWM controller for generating and outputting a plurality of control signals for controlling a soft switching operation of the power switch; And And a gate driving circuit capable of driving the soft switching operation by adjusting a gate driving current in a predetermined pattern according to a plurality of control signals input from the PWM control unit when the power switch is turned on or off, Power switch control device. The method according to claim 1, Wherein the PWM control unit outputs the plurality of control signals based on a reference pulse width control signal received from the controller. The method according to claim 1, Wherein the gate drive circuit includes a plurality of drive circuits for generating at least one of a gate source current and a gate sink current. The method of claim 3, Wherein each of the plurality of driver circuits includes P-type and N-type transistors having different transistor sizes so as to enable binary coding. The method of claim 3, Wherein each of the plurality of driver circuits includes P-type and N-type transistors having the same transistor size. The method according to claim 1, Wherein the gate driving circuit outputs a total of ²ⁿ gate driving currents through binary coding of the plurality of control signals, And the n corresponds to the number of the plurality of control signals. The method according to claim 1, Wherein the PWM control unit outputs a plurality of control signals capable of operating the plurality of driving circuits, Wherein the gate driving circuit controls the plurality of driving circuits individually based on the plurality of control signals to output an output current at a maximum value and then gradually reduces the output current. The method according to claim 1, Wherein the PWM control unit outputs a plurality of control signals capable of operating the plurality of driving circuits, Wherein the gate driving circuit controls the plurality of driving circuits individually based on the plurality of control signals to gradually increase the output current to a maximum value. The method according to claim 1, Wherein the predetermined pattern is a pattern for applying the gate driving current to a maximum value and gradually decreasing the gate driving current. The method according to claim 1, Wherein the predetermined pattern is a pattern for gradually increasing the gate drive current to a maximum value.

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