WO2019048828A1

WO2019048828A1 - Voltage regulator

Info

Publication number: WO2019048828A1
Application number: PCT/GB2018/052456
Authority: WO
Inventors: Lukasz FARIAN
Original assignee: Nordic Semiconductor ASA
Current assignee: Nordic Semiconductor ASA
Priority date: 2017-09-06
Filing date: 2018-08-30
Publication date: 2019-03-14
Anticipated expiration: 2020-03-06
Also published as: GB201714328D0

Abstract

A low-dropout voltage regulator (2) is arranged to receive an input voltage (V_DD) and produce an output voltage (V_0UT)- A pass field-effect-transistor (M_PASS) has a first terminal connected to the input voltage and a second terminal arranged to produce the output voltage. An error amplifier (4) is arranged to produce an error signal (V_SF) proportional to a difference between a feedback voltage (V_FB) and a reference voltage (V_REF)- The error signal (V_SF) is applied to the gate terminal of a source follower transistor (M_NA). The drain terminal of the source follower transistor (M_NA) is connected to the input voltage (V_DD), and its source terminal is connected to the gate terminal of the pass field-effect-transistor (M_PASS)- An adaptive biasing circuit portion (6) is arranged to measure the error signal (V_SF) and produce a bias current (l_M1, I _ADAPTIVE) which depends on said error signal (V_SF), and to supply the bias current (l_M1, I_ADAPTIVE) to the source follower transistor (M_NA).

Description

VOLTAGE REGULATOR

The present invention relates to voltage regulators, particularly low-dropout voltage regulators.

Low-dropout (or LDO) voltage regulators are linear DC voltage regulators that are capable of operating with very low input-output differential voltages. Such regulators are usually chosen because they have a low minimum operating voltage, high power efficiency and low heat dissipation.

A conventional LDO voltage regulator typically includes an error amplifier and a pass field-effect-transistor or "pass-FET". The error amplifier compares the output voltage (or a voltage derived therefrom) being generated by the LDO to a reference voltage and alters the conductance of the pass-FET in order to drive the output voltage to the desired value. LDO voltage regulators may also include a native source follower (sometimes referred to in the art as a common-drain amplifier) located between the error amplifier and the pass-FET, wherein this native source follower is arranged to reduce the impedance at the gate of the pass-FET. Such a native source follower also acts to push the pole at the gate of the pass-FET to higher frequencies. Such a source follower improves the frequency response and driving capabilities of the LDO voltage regulator. Those skilled in the art will appreciate that the term "native" as used herein when referring to a transistor (e.g. a transistor arranged as a source follower) should be understood to mean a metal- oxide-semiconductor field-effect-transistor (MOSFET) that is neither enhancement type nor depletion type and that typically exhibits a near-zero threshold voltage.

However, the Applicant has appreciated that, due to process and temperature variations, the threshold voltage of the native source follower can vary across a range of negative and positive values. This variation in the threshold voltage of the native source follower limits the output voltage swing at the gate of the pass-FET and decreases the maximum current that can be delivered by the LDO voltage regulator. This poses a problem as LDO voltage regulators should ideally be able to operate and be stable for supply voltages close to the regulated voltage and provide low drop-out voltages (e.g. less than 30 mV). As a result, large pass-FETs are required in order to obtain sufficiently low drop-out voltages and it becomes critical to be able to maximise the conductance of the pass-FET (e.g. by pulling the gate terminal of a p-channel MOSFET or "pMOSFET" based pass-FET down to ground) in order to maximise the current produced by the LDO voltage regulator.

When viewed from a first aspect, the present invention provides a low-dropout voltage regulator arranged to receive an input voltage at an input thereof and produce an output voltage at an output thereof, the low-dropout voltage regulator comprising:

a pass field-effect-transistor having a first terminal connected to the input voltage and a second terminal arranged to produce the output voltage;

an error amplifier circuit portion arranged to produce, at an output thereof, an error signal proportional to a difference between a feedback voltage and a reference voltage, said feedback voltage being derived from the output voltage; a source follower transistor having a gate terminal connected to the output of the error amplifier such that the error signal is applied to said gate terminal of the source follower transistor, a drain terminal thereof connected to the input voltage, and a source terminal thereof connected to a gate terminal of the pass field-effect- transistor; and

an adaptive biasing circuit portion arranged to measure the error signal and produce a bias current which depends on said error signal, and to supply the bias current to the source follower transistor.

Thus it will be appreciated by those skilled in the art that embodiments of the present invention provide an improved LDO voltage regulator that may operate close to the supply voltage and that provides an increased maximum current output compared to conventional LDO voltage regulators. This is achieved by having the adaptive biasing circuit portion provide a bias current to the source follower transistor which controls the conductance of the pass field-effect-transistor (the "pass-FET"). By providing the source follower with this bias current, its ability to drive the conductance of the pass-FET to the desired level is greatly improved as the voltage applied to the gate terminal of the pass-FET can be driven close to the full supply voltage range. Viewed in another way, an LDO voltage regulator in accordance with embodiments of the present invention advantageously allows the use of lower supply voltage ranges than conventional LDO voltage regulators, e.g. in one example allowing a reduction in the supply voltage from 1.2 V to 1.0 V, though it will of course be appreciated that the particular value of the supply voltage will depend on the process and types of transistors used. The bias current produced by the adaptive biasing circuit portion is effectively a scaled replica of a load current produced by the LDO voltage regulator, i.e. the current produced at its output and that is provided to a connected load. As the load current increases, the bias current also increases and the source follower is able to produce voltages at the gate of the pass-FET that provide a greater output voltage swing than is typically possible using conventional LDO voltage regulator designs, increasing the maximum current that can be delivered by the LDO voltage regulator. Conversely, when there is no load (or the load current is very low), the source follower can almost completely disable the pass-FET in order to limit leakage.

The pass-FET could comprise an nMOSFET. However, in a preferred set of embodiments, the pass field-effect-transistor comprises a p-channel metal-oxide- semiconductor field-effect-transistor. Similarly, while the pass-FET could be a depletion mode transistor, it is preferably an enhancement mode transistor. In such embodiments in which the pass-FET comprises an enhancement type p-channel metal-oxide-semiconductor field-effect-transistor, the source follower may drive the gate of the pass-FET very low and, when the load current is sufficiently high, the gate terminal may be "pulled down" as close to ground as possible in order to maximise the conductance of the pass-FET. However, when the load current is very low or zero, the source follower may pull up the gate of the pass-FET as close to the supply voltage as possible in order to restrict leakage as much as possible. In the alternative, where the pass field-effect-transistor comprises an enhancement type n-channel metal-oxide-semiconductor field-effect-transistor, the source follower may drive the gate of the pass-FET as close to the supply voltage as possible under high loads and as close to ground as possible under low loads.

In preferred embodiments, the source follower transistor comprises a native field- effect-transistor. As explained above and understood by those skilled in the art, the term "native" as used herein when referring to a transistor (e.g. a transistor arranged as a source follower) should be understood to mean a metal-oxide- semiconductor field-effect-transistor (MOSFET) that is neither enhancement type nor depletion type and that typically exhibits a near-zero threshold voltage - typically much less than 1 V, e.g. less than 100 mV. In some embodiments, the adaptive biasing circuit portion comprises a sense field- effect-transistor and a diode-connected field-effect-transistor arranged such that: the gate terminal of the sense field-effect-transistor is connected to the output of the error amplifier; and

the drain terminal of the sense field-effect-transistor is connected to the drain and gate terminals of the diode-connected field-effect-transistor.

Preferably, the sense field-effect-transistor comprises a p-channel metal-oxide- semiconductor field-effect-transistor. In some embodiments, the source terminal of the sense field-effect-transistor is connected to the input voltage.

The diode-connected field-effect-transistor preferably comprises an n-channel metal-oxide-semiconductor field-effect-transistor. In some embodiments, the source terminal of the diode-connected field-effect-transistor is connected to ground.

In a set of embodiments, the adaptive biasing circuit portion comprises a bias transistor having a drain terminal thereof connected to the source terminal of the source follower transistor and to the gate terminal of the pass field-effect-transistor, wherein a gate terminal of said bias transistor is connected to the drain and gate terminals of the diode-connected transistor.

While the drain and gate terminals of the diode-connected transistor could be directly connected to the gate terminal of the bias transistor, in a set of

embodiments, the drain and gate terminals of the diode-connected transistor are connected to the gate terminal of the bias transistor via a low-pass filter. The provision of a low pass filter between the diode-connected transistor and the bias- transistor reduces the impact of high frequency fluctuations on the conductance of the bias FET, and thus on the voltage at the gate of the pass-FET. While the bias transistor could be turned on at all times, in a set of embodiments the bias transistor is arranged such that it is turned off if a load current at the output of the low-dropout voltage regulator is below a predetermined threshold. This advantageously reduces the power consumption of the LDO voltage regulator when the bias transistor is not needed (i.e. at relatively low load currents).

An embodiment of the present invention will now be described with reference to the accompanying drawings, in which:

Fig. 1 is a circuit diagram of an LDO voltage regulator in accordance with an embodiment of the present invention;

Fig. 2 is a graph showing waveforms typical of the LDO voltage regulator of Fig. 1 in response to a step in the load current; and

Fig. 3 is a graph showing the output voltage and the voltage at the gate of the pass-FET of the LDO voltage regulator of Fig. 1 as a function of load current.

Fig. 1 is a circuit diagram of a low-dropout (LDO) voltage regulator 2 in accordance with an embodiment of the present invention. The LDO voltage regulator 2 is arranged to convert an input voltage V_DD to an output voltage V₀UT, wherein the output voltage V₀UT is regulated, i.e. the output voltage V₀UT is maintained at a constant voltage level. The LDO voltage regulator 2 comprises: an error amplifier 4; an adaptive biasing circuit portion 6; a source follower native n-channel metal- oxide-semiconductor field-effect-transistor (native nMOSFET) M_NA, and a pass field- effect-transistor or "pass-FET" M_PASs- The pass-FET M_PAss is a p-channel metal-oxide-semiconductor field-effect- transistor and is arranged in series with a potential divider constructed from two fixed resistors R₂. The source terminal of the pass-FET M_PAss is connected to the input voltage V_DD and the drain terminal of the pass-FET M_PASs is connected to one terminal of one of the fixed resistors F^ at an output node 8 from which the output voltage V₀UT is taken. The resistor F^ has its other terminal connected to ground via the other fixed resistor R₂. A load capacitance C_L is connected in parallel with the resistors R₂ such that it is connected to the output node 8.

The error amplifier 4 comprises a differential amplifier (e.g. an operational amplifier or "op-amp") and is arranged such that its inverting input is connected to a reference voltage V_REF and its non-inverting input is connected to a node 10 between the two fixed resistors R₂ which supplies a feedback voltage V_FB proportional to the output voltage V₀UT- The value of V_FB depends on the ratio of istors R₂ and the value output voltage VQUT

The error amplifier 4 produces at its output a voltage V_SF which is applied to the gate terminal of the source follower native nMOSFET M_NA. The drain terminal of the source follower nMOSFET M_NA is connected to the input voltage V_DD while the source terminal of the source follower native nMOSFET M_NA is connected to the gate terminal of the pass-FET M_PASs-

The adaptive biasing circuit portion 6 comprises: a sense pMOSFET M_SENSE; a diode-connected native nMOSFET M_D; a low-pass filter constructed from a resistor RI_P and a capacitor C_LP; and a bias transistor Mi . The sense pMOSFET M_SENSE is arranged such that its gate terminal is connected to the output of the error amplifier 4 (i.e. the voltage V_SF is applied to the gate terminal of the sense pMOSFET MSENSE), its source terminal is connected to the input voltage V_DD, and its drain terminal is connected to the drain and gate terminals of the diode-connected nMOSFET M_D. The source terminal of the diode-connected nMOSFET M_D is connected to ground.

The drain and gate terminals of the diode-connected nMOSFET M_D and the drain terminal of the sense pMOSFET M_SENSE are connected to one side of the low pass filter resistor R_Lp, the other side of which is connected to one plate of the filter capacitor C_LP and to the gate terminal of the bias transistor while the other plate of the filter capacitor C_LP is connected to ground. The drain terminal of the bias transistor is connected to the source terminal of the source follower native nMOSFET M_NA and to the gate terminal of the pass-FET M_PASs-

A small constant bias current I BIAS is connected in parallel to the biasing transistor M1 and is arranged to ensure that the native nMOSFET M_NA is properly biased even when there is no load current, preventing the gate terminal of the pass-FET M_PAss from floating. The LDO voltage regulator 2 is arranged to compare the feedback voltage V_FB to the reference voltage V_REF and, based on the difference between these, vary the conductance of the source follower native nMOSFET M_NA which, in turn, varies the conductance of the pass-FET M_PASs- The bias current UDAPTIVE that flow through the native nMOSFET M_NA (and, by extension, the biasing transistor M 1) will, in general, be a scaled replica of the load current l_L produced by the LDO voltage regulator 2, and affects the effective gate-source voltage (i.e. V_SF - V_GATE) of the native source follower M_NA. This bias current UDAPTIVE is equal to the sum of the small constant bias current I BIAS and the current IMI that flows through the biasing transistor M 1.

Fig. 2 is a graph showing waveforms typical of the LDO voltage regulator 2 of Fig. 1 in response to a step in the load current l_L. When the LDO voltage regulator 2 is only driving a small load current l_L, no current flows through the sense pMOSFET MSENSE which results in the impedance of M_SENSE being very high while the impedance of the diode-connected nMOSFET M_D is relatively low, which pulls V_Lp very close to ground. As a result, the biasing transistor M 1 is turned off and only a small current (e.g. 10 nA) flows through the native source follower M_NA. The voltage V_GATE at the gate terminal of the pass-FET M_PASs is approximately equal to the voltage V_SF applied to the gate terminal of the native source follower M_NA.

If the load current l_L is increased (e.g. it is stepped or ramped up), there will be a difference between the feedback voltage V_FB and the reference voltage V_REF which are input to the error amplifier 4. The output of the error amplifier 4 thus decreases, which will decrease the voltage V_SF applied to the gate terminal of the sense pMOSFET MSENSE- AS a result, the voltage V_Lp produced by the low-pass filter (i.e. the resistor R_Lp and capacitor C_LP), applied to the gate of the biasing transistor M 1 , is increased. This increase in V_Lp increases the bias current l_Mi through the biasing transistor M 1 and the current UDAPTIVE flowing through the native transistor MNA, thus decreasing the gate voltage V_GATE applied to the gate terminal of the pass-FET

M_PAss, such that it is pulled close to ground. As the pass-FET M_PASs is an enhancement type pMOSFET, this increases the conductance of the pass-FET M_PAss, increasing V₀UT- This increase in the output voltage V₀UT results in an increase in the feedback voltage V_FB- As the feedback voltage V_FB approaches the reference voltage V_REF, V_SF reduces which causes a reduction in the voltage V_Lp produced by the low-pass filter. This reduction in V_Lp reduces the bias current l_Mi through the biasing transistor M1 , and thus increases the current _DAPTIVE flowing through the native transistor M_NA- This effectively increases V_GATE, which reduces the conductance of the pass-FET M_PASs This dynamic process maintains V_0UT at (or at least close to) the desired output

Fig. 3 is a graph showing the output voltage V_0UT and the voltage V_GATE at the gate of the pass-FET of the LDO voltage regulator 2 of Fig. 1 as a function of load current l_L compared to an output voltage V_0UT* and the voltage V_GATE* at the gate of a pass-FET typical of a conventional LDO voltage regulator without adaptive biasing. As can be seen from the graph, the adaptive biasing circuit portion 6 within the LDO voltage regulator 2 described above is able to pull the voltage V_GATE applied to the gate terminal of the pass-FET M_PAss down to ground (i.e. 0 V), i.e. it is pulled lower than the corresponding voltage V_GATE* for the conventional LDO voltage regulator for a given load current l_L. This results in the pass-FET M_PAss within the LDO voltage regulator 2 having a higher conductance for a given load current IL than the conventional pass-FET which results in a higher output voltage V_OUT being produced by the LDO voltage regulator 2 compared to the output voltage V_OUT* produced by the conventional LDO voltage regulator.

Thus it will be appreciated by those skilled in the art that embodiments of the present invention provide an improved LDO voltage regulator that can provide a greater maximum current than conventional LDO voltage regulators. Those skilled in the art will appreciate that an LDO voltage regulator in accordance with embodiments of the present invention may also be more stable than conventional LDO voltage regulators and may employ a pass-FET that is physically smaller than would typically be permissible with conventional designs. It will be appreciated by those skilled in the art that the embodiment described above is merely exemplary and is not limiting on the scope of the invention.

Claims

1. A low-dropout voltage regulator arranged to receive an input voltage at an input thereof and produce an output voltage at an output thereof, the low-dropout voltage regulator comprising:

an adaptive biasing circuit portion arranged to measure the error signal and produce a bias current which depends on said error signal, and to supply the bias current to the source follower transistor;

wherein the adaptive biasing circuit portion comprises a sense field-effect- transistor and a diode-connected field-effect-transistor arranged such that:

the gate terminal of the sense field-effect-transistor is connected to the output of the error amplifier; and

the drain terminal of the sense field-effect-transistor is connected to the drain and gate terminals of the diode-connected field-effect-transistor;

wherein the adaptive biasing circuit portion further comprises a bias transistor having a drain terminal thereof connected to the source terminal of the source follower transistor and to the gate terminal of the pass field-effect-transistor, wherein a gate terminal of said bias transistor is connected to the drain and gate terminals of the diode-connected transistor via a low-pass filter.

2. The low-dropout voltage regulator as claimed in claim 1 , wherein the pass field-effect-transistor comprises a p-channel metal-oxide-semiconductor field-effect- transistor.

3. The low-dropout voltage regulator as claimed in claim 1 or 2, wherein the pass field-effect-transistor is an enhancement mode transistor.

4. The low-dropout voltage regulator as claimed in any preceding claim, wherein the source follower transistor comprises a native field-effect-transistor.

5. The low-dropout voltage regulator as claimed in any of claims 1 to 4, wherein the sense field-effect-transistor comprises a p-channel metal-oxide- semiconductor field-effect-transistor.

6. The low-dropout voltage regulator as claimed in any preceding claim, wherein the source terminal of the sense field-effect-transistor is connected to the input voltage.

7. The low-dropout voltage regulator as claimed in any preceding claim, wherein the diode-connected field-effect-transistor comprises an n-channel metal- oxide-semiconductor field-effect-transistor.

8. The low-dropout voltage regulator as claimed in any preceding claim, wherein the bias transistor is arranged such that it is turned off if a load current at the output of the low-dropout voltage regulator is below a predetermined threshold.