WO2019042250A1 - Memory structure and forming method thereof - Google Patents

Abstract

The present invention relates to a memory structure and a forming method thereof. The memory structure comprises a first base. The first base comprises: a substrate layer and a storage layer, wherein the substrate layer has a first surface and a second surface disposed opposite to each other. The storage layer is located on the first surface of the substrate layer. The substrate layer has a doped quantum well provided therein, and a connecting portion region is provided on at least part of the first surface of the substrate layer. An insulating layer is formed in the connecting portion region, and the insulating layer has a top surface and a bottom surface disposed opposite to each other, wherein the top surface faces a side of the first surface of the substrate layer, and the bottom surface faces a side of the second surface of the substrate layer. The storage layer comprises a connecting portion, and one end of the connecting portion is in contact with the insulating layer. The memory structure further comprises: an insulating structure passing through the substrate layer, located on the edge of the doped quantum well and surrounding the doped quantum well. The insulating structure is configured to insulate the doped quantum well from the substrate layer at the outside of the insulating structure. The memory structure prevents leakage between the quantum doped well and the substrate layer, thereby improving performance.

Description

Memory structure and method of forming same Technical field

The present invention relates to the field of semiconductor technologies, and in particular, to a memory structure and a method of forming the same.

Background technique

In recent years, the development of flash memory has been particularly rapid. The main feature of flash memory is that it can store stored information for a long time without power supply, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc., so it can be used in many fields such as microcomputer and automation control. Has been widely used. In order to further increase the bit density of the flash memory and reduce the bit cost, the three-dimensional flash memory (3D NAND) technology has been rapidly developed.

In a 3D NAND flash memory structure, including a memory array structure and a CMOS circuit structure located above the memory array structure, the memory array structure and the CMOS circuit structure are usually formed on two different wafers respectively, and then by bonding, The CMOS circuit wafer is bonded to the storage column structure to connect the CMOS circuit and the memory array circuit; then the back side of the wafer on which the memory array structure is located is thinned, and the entire circuit is taken out through the contact portion through the back surface. During the backside thinning process, the thickness of the substrate remaining under the deep doped well or deep doped well in the wafer is too small, which may cause serious leakage between the deep doped well and the substrate.

In the prior art, leakage current is generally reduced by tightly controlling the depth of the doped well and leaving a sufficient substrate thickness under the deep doped well. However, the prior art method for preventing leakage current requires strict control of the process, resulting in a small effective window of the process, and process variations may result in bulk scrapping of the wafer. Moreover, due to the connection of the circuit, it is necessary to open the silicon on the back surface to form a through-contact portion, and increasing the thickness remaining under the doped well may cause an increase in the aspect ratio of the through-contact portion, which increases the difficulty of the process. Further, an increase in the thickness of the substrate remaining under the doped well causes an increase in the parasitic capacitance of the pad of the output circuit, which affects the performance of the product.

Summary of the invention

The technical problem to be solved by the present invention is to provide a memory structure and a method of forming the same, which avoids leakage between the doped well and the substrate.

The technical solution of the present invention provides a memory structure, comprising: a first substrate comprising: a substrate layer and a memory layer, the substrate layer having opposite first and second surfaces, the memory layer being located at the substrate layer On the first surface, the substrate layer has a doped well therein, and the first surface of the substrate layer is provided with a connection portion at least in part; an insulating layer is formed in the connection portion, and the insulating layer has a relative a top surface and a bottom surface, wherein the top surface is a side facing a first surface of the substrate layer, the bottom surface being a side facing a second surface of the substrate layer; the storage layer including a connection portion One end of the connecting portion is in contact with the insulating layer; an isolation structure penetrating the substrate layer and located at an edge of the doped well surrounding the doped well for isolating the doped well The substrate layer on the periphery of the isolation structure.

Optionally, at least one side wall of the isolation structure is connected to the doped well.

Optionally, a first contact portion is formed in the storage layer for connecting to the first type doped well, and the first contact portion is located on a first type doped well surface surrounded by the isolation structure. .

Optionally, the isolation structure includes an isolation trench penetrating the substrate layer and an isolation material filling the isolation trench.

Optionally, the first substrate further includes a dielectric layer on the second surface of the substrate layer, and the isolation structure further penetrates the dielectric layer.

Optionally, the method further includes: a second contact portion penetrating the dielectric layer and the substrate layer, the second contact portion includes a metal connection structure and an insulating sidewall spacer on a sidewall surface of the metal connection structure, the second The contact portion is electrically connected to the connection portion.

Optionally, an opening is formed on the second surface of the substrate layer, the opening exposing at least a portion of the surface of the insulating layer; the dielectric layer covering at least a sidewall of the opening and an opening of the opening a surface of the insulating layer; further comprising: a second contact portion penetrating the dielectric layer and the substrate layer, the second contact portion comprising a first metal connection structure and a second metal connection structure, the first metal connection structure and The connecting portion is electrically connected, the second metal connecting structure is located in the opening, and the first metal connecting structure is electrically connected to the second metal connecting structure.

Optionally, the doped well bottom is located in the substrate layer and has a spacing from the second surface of the substrate layer.

Optionally, the second surface of the substrate layer exposes a bottom surface of the doped well.

Optionally, the doped well comprises a doped well of a first type and a doped well of a second type located within the doped well of the first type.

Optionally, a bottom surface of the insulating layer is located inside the substrate layer, a top surface of the insulating layer is flush with a first surface of the substrate layer, and a top surface of the insulating layer is higher than a bottom surface of the substrate layer The first surface, the bottom surface of the insulating layer is in horizontal contact with the first surface of the substrate layer, and the top surface of the insulating layer is higher than the first surface of the substrate layer.

Optionally, the storage layer comprises a three-dimensional memory, the three-dimensional memory comprising a three-dimensional memory device layer and a first metal layer sequentially away from the first surface of the substrate layer, the connection portion being located in the three-dimensional memory device layer, the connection One end of the portion is in contact with the insulating layer, and the other end of the connecting portion is in contact with the first metal layer.

Optionally, one end of the connecting portion is located in an inner portion of the insulating layer, or one end of the connecting portion is in contact with a top surface of the insulating layer, or one end of the connecting portion passes through the insulating layer and It is in contact with the bottom surface of the insulating layer.

Optionally, the method further includes: a second substrate, wherein the second substrate is formed with a peripheral circuit; the second substrate is located at a surface of the storage layer, wherein the storage layer is formed with a storage unit and the storage unit is connected The memory circuit structure forms an electrical connection between a peripheral circuit within the second substrate and a memory circuit structure within the memory layer.

In order to solve the above problems, the technical solution of the present invention further provides a method for forming a memory structure, comprising: providing a first substrate, including a substrate layer and a storage layer, the substrate layer having opposite first and second surfaces, a doped well is disposed in the substrate layer, the first surface of the substrate layer is provided with a connection portion at least part of the region; an insulating layer is formed in the connection portion region, and the insulating layer has oppositely disposed top and bottom surfaces Wherein the top surface is a side facing the first surface of the substrate layer, the bottom surface being a side facing the second surface of the substrate layer; at least the insulating layer is included in the substrate layer Forming a memory layer on the first surface, the memory layer including a connection portion, one end of the connection portion is in contact with the insulating layer; forming an isolation structure penetrating the substrate layer, the isolation structure being located at the edge of the doped well Surrounding the doped well arrangement for isolating the doped well from the substrate layer on the periphery of the isolation structure.

Optionally, at least one side wall of the isolation structure is connected to the doped well.

Optionally, a first contact portion is formed in the storage layer for connecting to the first type doped well, and the first contact portion is located on a first type doped well surface surrounded by the isolation structure. .

Optionally, the step of forming an isolation structure penetrating the substrate layer further comprises: forming an isolation trench penetrating through the substrate layer, the isolation trench being located at an edge of the doped well, disposed around the doped well; An isolation material filling the isolation trench is formed.

Optionally, the method further includes: forming a dielectric layer on the second surface of the substrate layer, wherein the isolation structure further penetrates the dielectric layer.

Optionally, the method for forming the second contact portion and the isolation structure comprises: etching the dielectric layer to the substrate layer, forming a first opening and a second opening in the dielectric layer, the second opening Corresponding to the position of the connecting portion; simultaneously etching the substrate layer along the first opening and the second opening to form isolation trenches and contact holes respectively penetrating the substrate layer, the contact holes and corresponding The connecting portion is in communication; forming an insulating material layer filling the isolation trench, the first opening, and covering the contact hole and the inner surface of the second opening; removing the insulating material layer at the bottom of the contact hole; forming a full fill And contacting the metal material layer of the contact hole and the second opening, and planarizing the metal material layer with the dielectric layer as a stop layer, and forming a metal connection structure in the contact hole.

Optionally, the method further includes: performing a hole treatment on the second surface of the substrate layer to expose at least a portion of the surface of the insulating layer; forming a dielectric layer on the second surface of the substrate layer, the dielectric layer covering at least the a sidewall of the opening and a surface of the insulating layer exposed in the opening; etching the dielectric layer and the insulating layer, and forming a contact hole at a position corresponding to the connecting portion at a second surface of the substrate layer, the contact The hole is in communication with the corresponding connecting portion; a first metal connecting structure is formed in the contact hole, and a second metal connecting structure is formed in the opening, the first metal connecting structure and the second metal connecting structure are electrically Connected, and the first metal connection structure is electrically connected to the connection portion.

Optionally, the doped well bottom is located in the substrate layer, and has a spacing between the second surface of the substrate layer, or the second surface of the substrate layer exposes the bottom of the doped well surface.

Optionally, the doped well comprises a doped well of a first type and a doped well of a second type located within the doped well of the first type.

Optionally, a bottom surface of the insulating layer is located inside the substrate layer, a top surface of the insulating layer is flush with a first surface of the substrate layer, and a top surface of the insulating layer is higher than a bottom surface of the substrate layer The first surface, the bottom surface of the insulating layer is in horizontal contact with the first surface of the substrate layer, and the top surface of the insulating layer is higher than the first surface of the substrate layer.

Optionally, the storage layer comprises a three-dimensional memory, the three-dimensional memory comprising a three-dimensional memory device layer and a first metal layer sequentially away from the first surface of the substrate layer, the connection portion being located in the three-dimensional memory device layer, the connection One end of the portion is in contact with the insulating layer, and the other end of the connecting portion is in contact with the first metal layer.

Optionally, one end of the connecting portion is located in an inner portion of the insulating layer, or one end of the connecting portion is in contact with a top surface of the insulating layer, or one end of the contact portion passes through the insulating layer and It is in contact with the bottom surface of the insulating layer.

Optionally, the surface of the storage layer further has a second substrate, a peripheral circuit is formed in the second substrate; the second substrate is located on a surface of the storage layer, and a storage unit and a connection body are formed in the storage layer The memory circuit structure of the memory cell, the peripheral circuit in the second substrate and the memory circuit structure in the memory layer form an electrical connection.

An isolation structure is formed in the substrate layer of the memory structure of the present invention as a physical isolation structure between the doped well and the surrounding substrate, so that leakage current between the doped well and the substrate layer on the periphery of the isolation structure can be avoided, thereby improving Memory performance. The bottom of the doped well need not have a thicker substrate, so that the overall thickness of the substrate layer is lower, so that the parasitic capacitance between the pad or other electrical connection structure formed on the dielectric layer and the device layer can be reduced, thereby Improve the performance of the memory structure. An insulating layer is disposed between the substrate layer and the storage layer, and a connection portion for metal interconnection is disposed in contact with the dielectric layer, and a back surface lead can be realized through a thick device layer in forming the lead connection structure. Reduced production costs and improved product yield.

The method of forming a memory structure of the present invention forms an isolation structure between the doped well and the surrounding substrate while forming a contact portion connected to the memory layer through the substrate layer, without adding an additional process step, without increasing Under the premise of process cost, the leakage problem between the doped well and the surrounding substrate can be avoided, which is beneficial to improve the performance of the memory structure.

DRAWINGS

1 to FIG. 6 are schematic structural diagrams showing a process of forming a memory structure according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a memory structure according to an embodiment of the present invention; FIG.

8 to FIG. 10 are schematic structural diagrams showing a process of forming a memory structure according to an embodiment of the present invention;

11 to FIG. 15 are schematic structural diagrams showing a process of forming a memory structure according to an embodiment of the present invention.

Detailed ways

The specific embodiments of the memory structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

Please refer to FIG. 1 to FIG. 6 , which are structural diagrams showing a process of forming a memory structure according to an embodiment of the present invention.

Referring to FIG. 1, a first substrate 100 is provided, including: a substrate layer 101 having a first surface 11 and a second surface 12, and a memory layer 102, the memory layer 102 being located at the substrate layer 101. On the first surface 11, the substrate layer 101 has a doped well therein.

In FIG. 1, the first substrate 100 is in an inverted state, at which time, the first surface 11 of the substrate layer 101 is the lower surface of the substrate layer 101, and the second surface 12 is the upper surface of the substrate layer 101. The storage layer 102 covers the first surface 11 of the substrate layer 101, and in the inverted state, the corresponding storage layer 102 is also located below the substrate layer 101. In the specific embodiment of the present invention, the relative positional descriptions of the upper, lower, top, and bottom portions are all in a state of being opposite to the first substrate 100.

The substrate layer 101 is a semiconductor material layer, and may be a single crystal silicon wafer, a semiconductor epitaxial layer including a single crystal silicon wafer and a wafer surface, or a silicon-on-insulator substrate. In this embodiment, the substrate layer 101 includes a single crystal silicon wafer and a single crystal silicon epitaxial layer on the surface of the single crystal silicon substrate, and the surface of the single crystal silicon epitaxial layer is a first surface 11 The other side surface of the single crystal silicon wafer is the second surface 12.

The doped well is formed by ion doping the first surface 11 of the substrate layer 101. According to the direction of ion doping, near the first surface 11 is the top of the doped well, near the second surface 12 To do the bottom of the well. The top surface of the doped well is coplanar with the first surface 11 of the substrate layer 101. In a specific embodiment, the doped well includes a first type doped well 111 and a second type doped well 112 located within the first type doped well 111. In a specific embodiment, the first type doped well 111 is an N-type doped well and the second type doped well 112 is a P-type doped well. Further, the second type doped well 112 is a P-type doped well, and the first type doped well 111 includes an N-type doped well on both sides of the P-type doped well and is located at the An N-type doped well and an N-type deep doped well under the P-type doped well.

A plurality of doped wells may be formed in the substrate layer 101 with a certain spacing between adjacent doped wells. The substrate layer 101 may be formed by thinning the back surface of the wafer on which the doped well is formed, and the distance between the bottom of the doped well and the second surface 12 of the substrate layer 101 may be adjusted according to the degree of thinning. .

In this embodiment, the second surface 12 of the substrate layer 101 exposes the bottom surface of the first type doped well 111, and is thinned to expose the thinned surface of the wafer during the thinning process. The first type is doped with a well 111.

In another embodiment, the first type doped well 111 is located in the substrate layer 101, and a bottom surface of the first type doped well 111 and the second surface 12 of the substrate layer 101 have a spacing. A substrate having a certain thickness between the bottom of the first type doped well 111 and the second surface 12 of the substrate layer 101.

The memory layer 102 includes an insulating layer and a memory cell formed in the insulating layer and a memory cell connected to the memory cell. In a specific embodiment, a 3D NAND memory cell is formed in the memory layer 102, and the memory cells are all formed on a top surface of the second type doped well 112. The memory layer 102 further includes a through array contact portion 121 penetrating the memory cell and an interconnect layer 122 connecting the array contact portion 121. In Fig. 1, only one through array contact 121 and a portion of interconnect layer 122 are shown, just to show. In an actual memory structure, a plurality of the through array contact portions 121 may be formed in each memory cell.

In this embodiment, the first substrate 100 further includes a dielectric layer 103 on the second surface 12 of the substrate layer 101. The dielectric layer 103 serves as a passivation layer covering the second surface 12 of the substrate layer 101 for protecting the second surface 12 of the substrate layer 101. The material of the dielectric layer 103 may be an insulating dielectric material such as TEOS, silicon nitride, silicon oxynitride, or silicon oxide. The dielectric layer 103 may be a single layer structure or a multi-layer stacked structure. The dielectric layer 103 may be formed by various deposition processes such as a chemical vapor deposition process, a spin coating process, an atomic layer deposition process, and the like.

The other side surface of the storage layer 102 opposite to the substrate layer 101 is further connected to a second substrate 200. The second substrate 200 is formed with a peripheral circuit. The second substrate 200 is located at the storage. The surface of the layer 102 forms an electrical connection between a peripheral circuit within the second substrate 200 and a memory circuit within the memory layer 102. Specifically, the second substrate 200 exposes a surface of the connection portion of the peripheral circuit toward the surface of the storage layer 102, and the surface of the storage layer 102 exposes the surface of the connection portion of the storage circuit, and the two are bonded to form Electrical connection.

Referring to FIG. 2, the dielectric layer 103 is etched to the second surface 12 of the substrate layer 101, and a first opening 131 and a second opening 132 are formed in the dielectric layer 103.

Specifically, the method for forming the first opening 131 and the second opening 132 includes: forming a photoresist layer on the surface of the dielectric layer 103, and performing exposure and development on the photoresist layer by using a photomask to form a pattern a photoresist layer; the dielectric layer 103 is etched by using the patterned photoresist layer as a mask layer to form the first opening 131 and the second opening 132. The first opening 131 is used to define the position and size of a subsequent isolation structure to be formed, and the second opening 132 is used to define the position and size of a contact portion to be formed through the substrate layer 101 to be subsequently formed. Forming a patterned photoresist layer on the dielectric layer 103 by using the same mask, and etching the dielectric layer 103 while forming the second opening 132 and the first opening 131 without additional process steps for the isolation structure .

The first opening 131 is in the shape of an annular groove; the second opening 132 is in the shape of a hole, and the cross section may be circular, rectangular or polygonal.

Referring to FIG. 3, the substrate layer 101 is simultaneously etched along the first opening 131 and the second opening 132 to form isolation trenches 113 and contact holes 114 penetrating the substrate layer 101, respectively.

The bottom of the contact hole 114 exposes an electrical connection structure in the storage layer 102, and subsequently forms a second contact portion through the substrate layer 101 in the contact hole 114, and is connected to the electrical connection structure in the storage layer 102. . In this embodiment, only one contact hole 114 is shown, the contact hole 114 passes through the doped well, and the bottom exposes the through array contact portion 121 in the memory layer 102. In other embodiments, a plurality of contact holes 114 may be formed, and a portion of the contact holes 114 may be located at the periphery of the doped well to expose an electrical connection structure external to the memory cell.

At least one side wall of the isolation trench 113 is connected to the doped well. The isolation trench 113 is located at the edge of the doped well and is disposed around the doped well. In this embodiment, the isolation trenches 113 are located in the first type doped well 111, and the sidewalls on both sides of the isolation trench 113 expose the first type doped well 111. In another embodiment, the isolation trench 113 exposes the first type doped well 111 only on one side sidewall and the substrate layer 101 on the other side sidewall.

In another embodiment, the isolation trench 113 and the edge of the first type doped well 111 may further have a spacing between the first type doped well 111 and the subsequent isolation trench. There is a partial thickness of silicon between the isolation structures formed within 113. Although a portion of the substrate structure is formed between the isolation structure formed in the isolation trench 113 and the first type doped well 111, the substrate layer 101 on the periphery of the isolation trench 113 is grounded during operation. Therefore, a portion of the substrate layer 101 between the isolation structure and the first type doped well 111 does not form a conductive path, and thus does not cause leakage.

The width of the isolation trench 113 is smaller than the width of the contact hole 114. In one embodiment of the present invention, the width of the isolation trench 113 is less than half of the aperture width of the contact hole 114 and greater than 20 nm, and the contact hole 114 has a maximum aperture width of 1500 nm.

Referring to FIG. 4, a layer of insulating material 400 filling the isolation trench 113, the first opening 131, and the inner wall surface covering the contact hole 114 and the second opening 132 is formed.

The material of the insulating material layer 400 may be an insulating dielectric material such as silicon oxide, silicon oxynitride or silicon nitride. The insulating material layer 400 may be formed using a chemical vapor deposition process, an atomic layer deposition process, a plasma enhanced chemical vapor deposition process, or the like. Since the width of the isolation trench 113 is smaller than the diameter of the contact hole 114, when the insulating material layer 400 fills the isolation trench 113 and the first opening 131, the insulating material layer 400 covers only the contact. The inner wall surface of the hole 114 and the second opening 132.

The insulating material layer 400 also covers the surface of the dielectric layer 103.

Referring to FIG. 5, the insulating material layer 400 at the bottom of the contact hole 114 is removed to form an insulating spacer 402 covering the sidewalls of the contact hole 114 and the second opening 132, and is filled in the isolation trench 113 and the first The insulating material layer in the opening 131 serves as the isolation structure 401.

The insulating material layer 400 at the bottom of the contact hole 114 is removed by an anisotropic etching process. The insulating material layer 400 on the surface of the dielectric layer 103 is also removed while removing the insulating material layer 400 at the bottom of the contact hole 114. In other embodiments, after the insulating material layer 400 located at the bottom of the contact hole 114 is removed, a portion of the thickness of the insulating material layer 400 remains on the surface of the dielectric layer 103.

At least one sidewall of the isolation structure 401 is coupled to the doped well. In this embodiment, the isolation structure 401 is completely located in the first type doped well 111 near the edge of the first type doped well 111. Therefore, both sidewalls of the isolation structure 401 are Connected to the first type doped well 111, a majority of the first type doped well 111 and the second type doped well 112 are surrounded by the isolation structure 401, and the doped well region surrounded by the isolation structure 401 is Physical isolation between the surrounding substrate layers 101 is achieved by the isolation structure 401.

In another embodiment, one side sidewall of the isolation structure 401 is connected to the first type doped well 111, and the other side is connected to the substrate layer 101 at the periphery of the first type doped well 111.

In another embodiment, the isolation structure 401 and the edge of the first type doped well 111 may further have a spacing therebetween, and between the first type doped well 111 and the isolation structure 401. A substrate material having a partial thickness. The isolation structure 401 is used to achieve isolation between a region surrounded by the isolation structure 401 and a substrate material on the periphery of the isolation structure 401.

Since the substrate layer 101 is grounded when the memory is in an operating state, the isolation structure 401 serves as a physical isolation structure, and leakage current between the first doped well 111 and the substrate layer 101 on the periphery of the isolation structure 401 can be avoided. Improve the performance of the memory.

Although the first type doped well 111 is in direct contact with the surrounding substrate layer 101 to form a depletion layer, leakage can be reduced, but the depletion layer needs to have sufficient thickness to completely avoid leakage. In this case, an undoped substrate having a large thickness is required around the periphery of the doped well 111 of the first type, and therefore, the thickness of the substrate layer is required to be large. In the embodiment of the present invention, since the first type doped well 111 is physically isolated from the peripheral substrate layer 101 through the isolation structure 401, it is not necessary to isolate through the depletion layer. Accordingly, the second surface 12 of the substrate layer 101 can be thinned to expose the bottom surface of the first type doped well 111. In other embodiments, the bottom surface of the first type doped well 111 and the second surface 12 further have a partial thickness of the substrate material, and the bottom surface of the first type doped well 111 The distance from the second surface 12 is small, for example, may be less than 1 μm, so the thickness of the substrate layer 101 is low.

In this embodiment, the isolation structure 401 is formed during the formation of the insulating spacers 402 without adding additional process steps.

A first contact portion 123 connecting the first type doping well 111 may be formed in the storage layer 102, and the first contact portion 123 is located in the first type doped well 111 surrounded by the isolation structure 401. The top surface.

Referring to FIG. 6 , a metal material layer filling the contact hole 114 and the second opening 132 is formed, and the dielectric layer 102 is planarized as a stop layer, and is formed in the contact hole 114 and the second opening 132 . Metal column 403. The insulating spacer 402 and the metal post 403 constitute a second contact portion.

The material of the metal material layer may be a metal material such as W, Cu, Al, or Au. The metal material layer may be formed using a physical vapor deposition process, such as a sputtering process.

The metal material layer is planarized to remove the metal material layer on the surface of the dielectric layer 103 to form a metal pillar 403, and the metal pillar 403 is connected to the through array contact portion 121 in the memory layer 102, The connection of the storage circuits within the storage layer 102.

Subsequently, a pad or other electrical connection structure connected to the metal post 403 is formed on the surface of the dielectric layer 103. In this embodiment, the isolation structure 401 is formed in the substrate layer 101 as a physical isolation structure between the doped well and the surrounding substrate. Therefore, the doped well bottom does not need to have a thick substrate, so that the doped well bottom does not need to have a thick substrate. The substrate layer 101 has a low overall thickness, so that the parasitic capacitance between the pad or other electrical connection structure formed on the dielectric layer 103 and the device layer 102 can be reduced, so that the performance of the memory structure can be improved.

In another embodiment, before the forming the dielectric layer 103, the substrate layer 101 may be etched to form an isolation trench, and the isolation trench is filled with a spacer material as an isolation structure; A dielectric layer 103 is formed on the second surface 12 of the substrate layer 101, and the dielectric layer 103 and the substrate layer 101 are etched to form a contact hole penetrating the dielectric layer 103 and the substrate layer 101, and formed on the inner wall surface of the contact hole. An insulating sidewall 402 and a metal post 403 filled with the contact hole.

A specific embodiment of the present invention also provides a memory structure formed by the above method.

Please refer to FIG. 6 , which is a schematic structural diagram of a storage structure according to an embodiment of the present invention.

The memory structure includes a first substrate 100 including a substrate layer 101 and a memory layer 102 having opposing first and second surfaces 11 and 12, the memory layer 102 Located on the first surface 11 of the substrate layer 101, the substrate layer 101 has a doped well therein; an isolation structure 401 penetrating the substrate layer 101 and located at the edge of the doped well for isolating the doping The well is surrounded by the surrounding substrate layer 101.

The substrate layer 101 is a semiconductor material layer, and may be a single crystal silicon wafer, a semiconductor epitaxial layer including a single crystal silicon wafer and a wafer surface, or a silicon-on-insulator substrate. In this embodiment, the substrate layer 101 includes a single crystal silicon wafer and a single crystal silicon epitaxial layer on the surface of the single crystal silicon substrate, and the surface of the single crystal silicon epitaxial layer is a first surface 11 The other side surface of the single crystal silicon wafer is the second surface 12.

In FIG. 1, the first substrate 100 is in an inverted state, at which time, the first surface 11 of the substrate layer 101 is the lower surface of the substrate layer 101, and the second surface 12 is the upper surface of the substrate layer 101. The storage layer 102 covers the first surface 11 of the substrate layer 101, and in the inverted state, the corresponding storage layer 102 is also located below the substrate layer 101.

The doped well is formed by ion doping the first surface 11 of the substrate layer 101. According to the direction of ion doping, near the first surface 11 is the top of the doped well, near the second surface 12 To do the bottom of the well. A top surface of the doped well is coplanar with the first surface 11 of the substrate layer 101. In a specific embodiment, the doped well includes a first type doped well 111 and a second type doped well 112 located within the first type doped well 111. In a specific embodiment, the first type doped well 111 is an N-type doped well and the second type doped well 112 is a P-type doped well. Further, the second type doped well 112 is a P-type doped well, and the first type doped well 111 includes an N-type doped well on both sides of the P-type doped well and is located at the An N-type doped well and an N-type deep doped well under the P-type doped well.

A plurality of doped wells may be formed in the substrate layer 101 with a certain spacing between adjacent doped wells. The substrate layer 101 may be formed by thinning the back surface of the wafer on which the doped well is formed, and the distance between the bottom of the doped well and the second surface of the substrate layer 101 may be adjusted according to the degree of thinning.

In this embodiment, the second surface 12 of the substrate layer 101 exposes the bottom surface of the doped well 111 of the first type. During the thinning of the back side of the wafer, it is thinned to expose the doped well 111 of the first type.

In another embodiment, the first type doped well 111 is located in the substrate layer 101, and a bottom surface of the first type doped well 111 and the second surface 12 of the substrate layer 101 have a spacing. A substrate material having a certain thickness between the bottom of the first type doped well 111 and the second surface 12 of the substrate layer 101.

The memory layer 102 includes an insulating layer and a memory cell formed in the insulating layer and a memory cell connected to the memory cell. In a specific embodiment, a 3D NAND memory cell is formed in the memory layer 102, and the memory cells are all formed on a surface of the second type doped well 112. The memory layer 102 further includes a through array contact portion 121 extending through the memory cell and an interconnect layer 122 extending through the array contact portion 121. In Fig. 1, only one through array contact portion 121 and a portion of interconnect layer 122 are shown as illustrations. In an actual memory structure, a plurality of the through array contact portions 121 may be formed in each memory cell.

In this embodiment, the first substrate 100 further includes a dielectric layer 103 on the second surface 12 of the substrate layer 101. The dielectric layer 103 acts as a passivation layer on the second surface 12 of the substrate layer 101 for protecting the second surface 12 of the substrate layer 101. The material of the dielectric layer 103 may be an insulating dielectric material such as TEOS, silicon nitride, silicon oxynitride, or silicon oxide. The dielectric layer 103 may be a single layer structure or a multi-layer stacked structure. The dielectric layer 103 may be formed by various deposition processes such as a chemical vapor deposition process, a spin coating process, an atomic layer deposition process, and the like.

The isolation structure 401 includes an isolation trench penetrating the substrate layer 101 and an isolation material filling the isolation trench. In this embodiment, the isolation structure 401 also penetrates the dielectric layer 103. In another embodiment, the isolation structure 401 may also be located only within the substrate layer 101.

At least one side wall of the isolation structure 401 is connected to the doped well. In this embodiment, the isolation structure 401 is completely located in the first type doped well 111 near the edge of the first type doped well 111. Therefore, both sidewalls of the isolation structure 401 are Connected to the first type doped well 111, a majority of the first type doped well 111 and the second type doped well 112 are surrounded by the isolation structure 401, and the doped well region surrounded by the isolation structure 401 is Physical isolation between the surrounding substrate layers 101 is achieved by the isolation structure 401.

In another embodiment, one side sidewall of the isolation structure 401 is connected to the first type doped well 111 and the other side is connected to the substrate layer 101 at the periphery of the first type doped well 111.

In another embodiment, the isolation structure 401 and the edge of the first type doped well 111 may further have a spacing therebetween, and between the first type doped well 111 and the isolation structure 401. A substrate material having a partial thickness. The isolation structure 401 is used to achieve isolation between a region surrounded by the isolation structure 401 and a substrate material on the periphery of the isolation structure 401.

Since the substrate layer 101 is grounded when the memory is in an operating state, the isolation structure 401 serves as a physical isolation structure, and leakage current between the first doped well 111 and the substrate layer 101 on the periphery of the isolation structure 401 can be avoided. Improve the performance of the memory. Since the first type doped well 111 is physically isolated from the peripheral substrate layer 101 through the isolation structure 401, it is no longer necessary to isolate through the depletion layer. Accordingly, the second surface 12 of the substrate layer 101 can be thinned to expose the bottom surface of the first type doped well 111. In other embodiments, the bottom surface of the first type doped well 111 and the second surface 12 further have a partial thickness of the substrate material, and the bottom surface of the first type doped well 111 The distance from the second surface 12 is small, for example, may be less than 1 μm, so the thickness of the substrate layer 101 is low.

A first contact portion 123 is formed in the memory layer 102 for connecting to the first type doped well 111, and the first contact 123 portion is located in a first type doped well surrounded by the isolation structure 401. The top surface of the 111.

The memory structure further includes a second contact portion penetrating the dielectric layer 103 and the substrate layer 101, the second contact portion including a metal pillar 403 and an insulating sidewall spacer 402 on a sidewall surface of the metal pillar 403. The material of the metal pillar 403 may be a metal material such as W, Cu, Al, or Au. The metal post 403 is connected to the through array contact portion 121 to achieve connection with a memory circuit in the memory layer 102.

Since the isolation structure 401 and the second contact portion penetrate the dielectric layer 103 and the substrate layer 101, the isolation trench and the contact hole can be simultaneously formed by etching the dielectric layer 103 and the substrate layer 101, and then forming the Simultaneously with insulating the spacers 402, an isolation structure 401 filling the isolation trenches is formed without adding additional process steps.

The surface of the dielectric layer 103 may also have pads or other electrical connection structures connected to the metal posts 403. In this embodiment, the isolation structure 401 is formed in the substrate layer 101 as a physical isolation structure between the doped well and the surrounding substrate. Therefore, the doped well bottom does not need to have a thick substrate, so that the doped well bottom does not need to have a thick substrate. The substrate layer 101 has a low overall thickness, so that the parasitic capacitance between the pad or other electrical connection structure formed on the dielectric layer 103 and the device layer 102 can be reduced, so that the performance of the memory structure can be improved.

The surface of the storage layer 102 further has a second substrate 200, and a peripheral circuit is formed in the second substrate 200; the second substrate 200 is located on the surface of the storage layer 102, and peripheral circuits in the second substrate 200 are Electrical connections are formed between the memory circuits within the memory layer 102. Specifically, the second substrate 200 exposes a surface of the connection portion of the peripheral circuit toward the surface of the storage layer 102, and the surface of the storage layer 102 exposes the surface of the connection portion of the storage circuit, and the two are bonded to form Electrical connection.

Please refer to FIG. 7 , which is a schematic structural diagram of a storage structure according to another embodiment of the present invention.

In this embodiment, the memory structure includes: a first substrate 700, the first substrate 700 includes a substrate layer 701 and a memory layer 702, the substrate layer 701 having opposite first and second surfaces, The storage layer 702 is located on a first surface of the substrate layer 701, the substrate layer 701 has a doped well therein; an isolation structure 710 extends through the substrate layer 701 and is located at the edge of the doped well for isolation The doped well is surrounded by a surrounding substrate layer 701. In FIG. 7, the first substrate 700 is in an upright state.

A plurality of doped wells are formed in the substrate layer 701, and the doped wells include a first type doped well 711 and a second type doped well 712 located in the first type doped well 711. The doped well surface is coplanar with the first surface of the substrate layer 701. The bottom of the doped well has a substrate layer 701 of a certain thickness.

The memory layer 702 includes an insulating layer and a memory cell formed in the insulating layer and a memory cell connected to the memory cell. A 3D NAND memory cell is formed in the memory layer 702, and the memory cells are all formed on a surface of the second type doped well 712.

A through array contact portion 721 penetrating the memory cell is further formed in the memory layer 702, the through array contact portion 721 is connected to the second type doped well 712; and the memory layer 702 is further formed therein A contact portion 722 is connected to the first type doped well 711; a substrate contact portion 723 is also formed in the memory layer 702 for connection to the substrate layer 701. A circuit connection portion 724 is also formed in the storage layer 702 for extracting the storage circuit in the storage layer 702.

The first substrate 700 further includes a dielectric layer 703 on the second surface of the substrate layer 701. The dielectric layer 703 serves as a passivation layer on the second surface of the substrate layer 701 for protecting the second surface of the substrate layer 701.

The isolation structure 710 penetrates through the dielectric layer 703 and the substrate layer 701. One side of the isolation structure 710 is connected to the first type doped well 711 to surround the first type doped well 711 and the second type doped well 712, and is isolated from the substrate layer 701 on the periphery of the isolation structure 710. . A first contact portion 722 connecting the first type doped well 711 is located on a surface of the first type doped well 111 surrounded by the isolation structure 401.

The memory structure further includes a second contact portion penetrating the dielectric layer 703 and the substrate layer 701, the second contact portion including a metal post 731 and an insulating sidewall 732 on a sidewall surface of the metal post 731. The metal post 731 is coupled to the circuit connection 724 within the memory layer 702 for connection to a memory circuit within the memory layer 702. In other embodiments, the memory structure further includes a second contact portion connected to the through array contact portion 721, the first contact portion 722, and the substrate contact portion 723.

The surface of the storage layer 702 further has a second substrate 800, and a peripheral circuit is formed in the second substrate 800; the second substrate 800 is located on the surface of the storage layer 702, and peripheral circuits in the second substrate 800 are Electrical connections are formed between the memory circuits within the memory layer 702. Specifically, the second substrate 800 exposes the surface of the connection portion of the peripheral circuit toward the surface of the storage layer 702, and the surface of the storage layer 702 exposes the surface of the connection portion of the storage circuit, and the two are bonded to form Electrical connection.

Please refer to FIG. 8 to FIG. 10 , which are schematic diagrams showing a process of forming a memory structure according to another embodiment of the present invention.

Referring to FIG. 8, a first substrate is provided, including a substrate layer 11, the substrate layer 11 having opposite first and second surfaces, the substrate layer 11 having a doped well therein; and the substrate layer 11 A surface portion 12 is provided at least in part on a surface; an insulating layer 13 is formed in the connecting portion region 12, and the insulating layer 13 is an oxide insulating layer 13 or a nitride insulating layer 13 in the connecting portion region 12. The process of forming the insulating layer 13 includes one of lithography, etching, deposition, filling, and grinding, or any combination thereof, the insulating layer 13 having oppositely disposed top and bottom surfaces, wherein the top surface is toward the first surface of the substrate layer One side of the bottom surface is a side facing the second surface of the substrate layer.

In this embodiment, in the step of forming the insulating layer 13, first, a shallow trench is formed in the connection portion region 12 of the first surface of the substrate layer 11 by a lithography and etching process, and then deposition and The filling process forms the insulating layer 13 in the shallow trench, and the insulating layer 13 may be subsequently polished by a polishing process to planarize it. After the above process steps, the bottom surface of the insulating layer 13 is formed inside the substrate layer 11, and the top surface of the insulating layer 13 is flush with the first surface of the substrate layer 11. Preferably, the insulating layer 13 has a thickness of about 1 micron.

The specific process step of forming the insulating layer is: first, forming a hard mask layer on the first surface of the substrate layer, sequentially etching the hard mask layer and the substrate layer to form a trench, and the hard mask layer is, for example, A silicon nitride layer formed by a chemical vapor deposition process or a silicon oxide layer formed by a High Density Plasma Chemical Vapor Deposition (HDPCVD) process. The hard mask layer and the substrate layer are etched to form trenches using any of the prior art techniques well known to those skilled in the art.

Then, an insulating layer is deposited in the trench and on the hard mask layer, the insulating layer filling the trench; the insulating layer material such as silicon oxide, silicon nitride, silicon oxynitride, etc., is filled with the dielectric material The process is, for example, a High Density Plasma Chemical Vapor Deposition (HDPCVD) method.

Then, the insulating layer on the hard mask layer is removed; the process of removing the insulating layer on the hard mask layer is performed, for example, by a chemical mechanical polishing (CMP) method, after the CMP, the surface of the hard mask layer is deposited. The insulating layer is completely removed, so that the upper surface of the hard mask layer is completely exposed.

Then, the rapid thermal oxidation treatment is performed, and the ambient temperature of rapid thermal oxidation is 400-800 degrees Celsius. This step can eliminate the damage of the atomic structure caused by the corners of the groove in the foregoing process, and avoid the ditch in the subsequent process. Slot corner damage. Preferably, the trench is at an ambient temperature of 500-700 degrees Celsius. In one embodiment of the invention, the ambient temperature at which the trench is placed is linearly heated to between 400 and 800 degrees Celsius in 60 seconds to 140 seconds.

In the specific implementation, the ambient temperature of the trench can be, for example, 450 degrees Celsius, 480 degrees Celsius, 550 degrees Celsius, 600 degrees Celsius, 660 degrees Celsius, 640 degrees Celsius, 750 degrees Celsius, and the like. The time for linear heating of the ambient temperature is, for example, 70 seconds, 75 seconds, 80 seconds, 95 seconds, 103 seconds, 115 seconds, 125 seconds, 130 seconds.

In the rapid thermal oxidation process, the method further includes the step of introducing an oxygen-containing gas into the environment in which the trench is located, wherein the oxygen-containing gas, such as oxygen (O ₂ ), ozone (O ₃ ), etc., has an oxidizing ability. gas.

In the rapid thermal oxidation process, the insulating layer in the trench is in a high temperature oxygen environment, the oxygen molecule concentration in the high temperature environment is large and the molecular activity is high, and the edge of the insulating layer in the trench is The original molecular structure is relatively loose, so the free silicon ions generated in the CMP process will be fully oxidized in this process, and the oxides formed after oxidation and the original oxide molecules in the insulating layer in the trench are at a high temperature. Recombining underneath to form a stable molecular bond, so that the oxide structure at the corners of the insulating layer in the trench becomes stable and dense from the original looseness, so that the corner damage of the insulating layer in the trench can Effective repair is obtained, which is also commonly referred to as high temperature quenching.

Finally, the hard mask layer is removed. The process of removing the hard mask layer is, for example, wet etching (Wet Etch), and the chemical etching reagent used varies depending on the material of the hard mask layer, and is a technique known to those skilled in the art.

In another embodiment, the insulating layer 13 has oppositely disposed bottom surfaces and a top surface that is away from the first metal layer 18 with respect to the top surface. In the step of forming the insulating layer 13, first, a shallow trench is formed in the contact hole region 12 of the first surface of the substrate layer 11 by a lithography and etching process, and a shallow trench is formed by a deposition and filling process. The insulating layer 13 is formed in the middle, and the insulating layer 13 may be subsequently polished by a polishing process to be planarized. After the above process steps, the bottom surface of the insulating layer 13 is formed inside the substrate layer 11, and the top surface of the insulating layer 13 is higher than the first surface of the substrate layer 11. Preferably, the insulating layer 13 has a thickness of about 1 micron.

In another embodiment, the insulating layer 13 has oppositely disposed bottom surfaces and a top surface that is away from the first metal layer 18 with respect to the top surface. In the step of forming the insulating layer 13, first, the insulating layer 13 is formed on the surface of the contact hole region 12 of the first surface of the substrate layer 11 by a deposition process, and the insulating layer 13 may be further polished by a grinding process. Flatten it. After the above process steps, the bottom surface of the insulating layer 13 is formed in horizontal contact with the first surface of the substrate layer 11, and the top surface of the insulating layer 13 is higher than the first surface of the substrate layer 11. Preferably, the insulating layer 13 has a thickness of about 1 micron.

The doped well within the substrate layer 11 includes a first type doped well 1101 and a second type doped well 1102 located within the first type doped well 1101. The junction region 12 is located within the second type doped well 1102. In other embodiments, the connecting portion region 12 may also be located at other locations.

A storage layer 14 is formed on a region of the first surface of the substrate layer 11 including at least the insulating layer 13. The storage layer 14 includes a connecting portion 15 having one end in contact with the insulating layer 13, and the connecting portion 15 is connected. a metal material filled in the hole, the metal material being one of copper, aluminum, tin or tungsten or any combination thereof;

The memory layer 14 includes a three-dimensional memory including a three-dimensional memory device layer 141 and a first metal layer 18 sequentially spaced away from the first surface of the substrate layer 11, the connection portion 15 being located within the three-dimensional memory device layer 141, the connection portion One end of the contact portion 15 is in contact with the insulating layer 13, and the other end of the connecting portion 15 is in contact with the first metal layer 18. One end of the connecting portion 15 is located in the interior of the insulating layer 13. Alternatively, one end of the connecting portion 15 is in contact with the top surface of the insulating layer 13, or one end of the connecting portion 15 is passed through the insulating layer 13 and is in contact with the bottom surface of the insulating layer 13.

The side of the memory layer 14 of the substrate layer 11 including the memory layer 14 is bonded to the second substrate 16, and the second surface of the substrate layer 11 is thinned; the second surface of the substrate layer after thinning An upper dielectric layer 19 is deposited, which is made of an oxide or a nitride or an oxynitride.

Referring to FIG. 9, the dielectric layer 19 and the substrate layer 11 are etched, and a contact hole 21 is formed at a position corresponding to the connection portion 15 at a first surface of the substrate layer 11, and a doping around the doped well edge is formed. The well is provided with an isolation trench; and an insulating material is filled in the isolation trench to form the isolation structure 191, and an insulating spacer 23 is formed on the sidewall surface of the contact hole 21. The contact hole 21 is in communication with the corresponding connecting portion 15. Specifically, the method for forming the contact hole 21 and the isolation structure 191 includes: etching the dielectric layer 19 to the substrate layer 11, and forming a first opening and a second opening in the dielectric layer 19, Two openings corresponding to the position of the connecting portion 15; the substrate layer 11 is simultaneously etched along the first opening and the second opening, respectively forming isolation trenches and contact holes 21 penetrating the substrate layer, a contact hole 21 communicating with the corresponding connecting portion 15; forming a layer of insulating material filling the isolation trench, the first opening, and covering the contact hole 21 and the inner surface of the second opening; removing the bottom of the contact hole The layer of insulating material forms an insulating spacer 23 .

Referring to FIG. 10, a metal material layer filling the contact hole 21 and the second opening is formed, and the metal material layer is planarized with the dielectric layer 19 as a stop layer, and formed in the contact hole 21 a metal connection structure 22; a lead metal layer is deposited on the second surface of the substrate layer 11, and the lead structure 17 is defined by photolithography of the lead metal layer, the lead structure 17 and the metal connection structure 22 in the contact hole 21 Electrically connected, the material of the lead metal layer is one of copper, silver, aluminum, tin or tungsten or any combination thereof. After forming the lead structure 17, a second protective layer is deposited on the second surface of the substrate layer 11, and the second protective layer is formed into the second protective layer structure 20 by a lithography and etching process. The material of the second protective layer is an oxide or a nitride or an oxynitride.

Please refer to FIG. 11 to FIG. 15 , which are schematic diagrams showing a process of forming a memory structure according to another embodiment of the present invention. In this embodiment, portions that are different from the above embodiments will be described, and the same portions will not be described again.

Referring to FIG. 11, the second surface of the substrate layer 11 after the thinning is subjected to an opening treatment to expose at least a part of the surface of the insulating layer 13.

Referring to FIG. 12, a dielectric layer 19 is formed on the second surface of the substrate layer 11, covering at least a sidewall of the opening and a surface of the insulating layer 13 exposed in the opening. The dielectric layer 19 is made of oxide or nitrogen. One of the compounds or oxynitrides or any combination thereof.

Referring to FIG. 13, the etched dielectric layer 19 and the insulating layer 13 form a contact hole 21 at a position corresponding to the connecting portion 15 at a second surface of the substrate layer 11. The process of forming the contact hole 21 includes lithography and etching. The contact hole 21 is in communication with the corresponding connection portion 15. While the contact hole 21 is formed, the dielectric layer 19 and the substrate layer 11 are etched, an isolation trench is formed at the edge of the doped well, and an insulating material is filled in the isolation trench to form the isolation structure 191.

Referring to FIG. 14 , a first metal connection structure 2101 is formed in the through hole 21, and a second metal connection structure 2102 is formed in the opening, and the first metal connection structure 2101 is electrically connected to the second metal connection structure 2102. And the first metal connection structure 2101 is electrically connected to the connection portion 15, the first metal connection structure is formed in the through hole, and the process of forming the second metal connection structure in the opening includes metal filling and chemical mechanical polishing; The material of the first metal connection structure 2101 and the second metal connection structure 2102 is one of copper, aluminum, tin or tungsten or any combination thereof.

Referring to FIG. 15, a lead metal layer is deposited on the second surface of the substrate layer 11, and the lead structure 24 is defined by the lithography and etching process for the lead metal layer. The lead structure 24 and the second metal connection structure 2102 Electrically connecting, the material of the lead metal layer is one of copper, silver, aluminum, tin or tungsten or any combination thereof; after forming the lead structure 24, a protective layer 20 is deposited on the second surface of the substrate layer 11 and passed The lithography and etching processes form the structure of the protective layer 20. The material of the protective layer 20 is an oxide or a nitride or an oxynitride.

The above description is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. These improvements and retouchings should also be considered. It is the scope of protection of the present invention.

Claims (20)

A memory structure, comprising: a first substrate comprising: a substrate layer having opposite first and second surfaces, the memory layer being on a first surface of the substrate layer, the substrate layer having a doping a well, at least a portion of the first surface of the substrate layer is provided with a connection region; An insulating layer is formed in the connecting portion region, the insulating layer has oppositely disposed top and bottom surfaces, wherein the top surface is a side facing the first surface of the substrate layer, and the bottom surface is toward the One side of the second surface of the substrate layer; The storage layer includes a connecting portion, one end of the connecting portion is in contact with the insulating layer; An isolation structure penetrating the substrate layer and located at an edge of the doped well surrounding the doped well for isolating the doped well from a substrate layer on a periphery of the isolation structure. The memory structure of claim 1 wherein at least one side sidewall of said isolation structure is coupled to said doped well. The memory structure according to claim 1, wherein a first contact portion is formed in said memory layer for connection to said first type doped well, said first contact portion being located in said isolation The first type of doped well surface surrounded by the structure. The memory structure of claim 1 wherein said isolation structure comprises an isolation trench extending through said substrate layer and an isolation material filling said isolation trench. The memory structure of claim 1 wherein said first substrate further comprises a dielectric layer on a second surface of said substrate layer, said isolation structure also extending through said dielectric layer. The memory structure according to claim 5, further comprising: a second contact portion penetrating the dielectric layer and the substrate layer, the second contact portion including a metal connection structure and a sidewall of the metal connection structure The insulating sidewall of the surface, the second contact portion is electrically connected to the connecting portion. The memory structure according to claim 5, wherein the second surface of the substrate layer is formed with an opening, the opening exposing at least a portion of a surface of the insulating layer; the dielectric layer covering at least the a sidewall of the opening and a surface of the insulating layer exposed in the opening; further comprising: a second contact portion penetrating the dielectric layer and the substrate layer, the second contact portion including the first metal connection structure and the second metal connection The first metal connection structure is electrically connected to the connection portion, the second metal connection structure is located in the opening, and the first metal connection structure is electrically connected to the second metal connection structure. The memory structure of claim 1 wherein said doped well bottom is located within said substrate layer with a spacing from said second surface of said substrate layer. The memory structure of claim 1 wherein the second surface of the substrate layer exposes a bottom surface of the doped well. The memory structure of claim 1 wherein said doped well comprises a first type of doped well and a second type of doped well located within said first type of doped well. The memory structure according to claim 1, wherein a bottom surface of the insulating layer is located inside the substrate layer, a top surface of the insulating layer is flush with a first surface of the substrate layer, and the insulating layer The top surface is higher than the first surface of the substrate layer, and the bottom surface of the insulating layer is in horizontal contact with the first surface of the substrate layer, and a top surface of the insulating layer is higher than a first surface of the substrate layer. The memory structure of claim 1 wherein said memory layer comprises a three dimensional memory comprising a three dimensional memory device layer and a first metal layer sequentially spaced away from a first surface of said substrate layer, said connection portion being located In the three-dimensional memory device layer, one end of the connection portion is in contact with the insulating layer, and the other end of the connection portion is in contact with the first metal layer. The memory structure according to claim 1, wherein one end of the connecting portion is located in an interior of the insulating layer, or one end of the connecting portion is in contact with a top surface of the insulating layer, or the connection One end of the portion passes through the insulating layer and is in contact with the bottom surface of the insulating layer. The memory structure according to claim 1, further comprising: a second substrate, wherein the second substrate is formed with a peripheral circuit; the second substrate is located on a surface of the storage layer, and the storage layer is formed There is a memory cell and a memory circuit structure connecting the memory cells, and a peripheral circuit in the second substrate forms an electrical connection with a memory circuit structure in the memory layer. A method for forming a memory structure, comprising: Providing a first substrate comprising a substrate layer having a first surface and a second surface, and a second surface having a doped well therein, the first surface of the substrate layer being disposed at least in part There is a connection area; Forming an insulating layer in the connecting portion region, the insulating layer having oppositely disposed top and bottom surfaces, wherein the top surface is a side facing a first surface of the substrate layer, the bottom surface being oriented toward the One side of the second surface of the substrate layer; Forming a memory layer on the first surface of the substrate layer including the insulating layer, the memory layer including a connection portion, one end of the connection portion being in contact with the insulating layer; An isolation structure is formed through the substrate layer, the isolation structure being located at an edge of the doped well surrounding the doped well for isolating the doped well from a substrate layer on a periphery of the isolation structure. The method of forming a memory structure according to claim 15, wherein at least one side wall of the isolation structure is connected to the doped well. The method of forming a memory structure according to claim 15, wherein a first contact portion is formed in the memory layer for connecting to the first type doped well, and the first contact portion is located The first type of doped well surface surrounded by the isolation structure. The method of forming a memory structure according to claim 15, wherein the step of forming an isolation structure penetrating the substrate layer further comprises: forming an isolation trench penetrating the substrate layer, the isolation trench being located Doping a well edge, surrounding the doped well; forming an isolation material that fills the isolation trench. The method of forming a memory structure according to claim 15, further comprising: forming a dielectric layer on the second surface of the substrate layer, the isolation structure also extending through the dielectric layer. The method of forming a memory structure according to claim 15, further comprising: performing a hole opening treatment on the second surface of the substrate layer to expose at least a portion of the surface of the insulating layer; Forming a dielectric layer covering at least a sidewall of the opening and a surface of the insulating layer exposed in the opening; etching the dielectric layer and the insulating layer at a second surface of the substrate layer a contact hole is formed at a position corresponding to the connecting portion, the contact hole is in communication with a corresponding connecting portion; a first metal connecting structure is formed in the contact hole, and a second metal connecting structure is formed in the opening, A metal connection structure is electrically connected to the second metal connection structure, and the first metal connection structure is electrically connected to the connection portion.

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