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WO2018215309A1 - Composant semi-conducteur et procédé de fabrication d'un composant semi-conducteur - Google Patents

Composant semi-conducteur et procédé de fabrication d'un composant semi-conducteur Download PDF

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Publication number
WO2018215309A1
WO2018215309A1 PCT/EP2018/062989 EP2018062989W WO2018215309A1 WO 2018215309 A1 WO2018215309 A1 WO 2018215309A1 EP 2018062989 W EP2018062989 W EP 2018062989W WO 2018215309 A1 WO2018215309 A1 WO 2018215309A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor
deformation
main surface
carrier layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2018/062989
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German (de)
English (en)
Inventor
Isabel OTTO
Anna Kasprzak-Zablocka
Christian LEIRER
Berthold Hahn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Priority to US16/615,835 priority Critical patent/US11430917B2/en
Publication of WO2018215309A1 publication Critical patent/WO2018215309A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/8506—Containers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • H10H20/8312—Electrodes characterised by their shape extending at least partially through the bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/032—Manufacture or treatment of electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN

Definitions

  • the invention relates to a semiconductor component and to a method for producing a semiconductor component.
  • this includes
  • semiconductor device a semiconductor body having a first semiconductor layer and a second semiconductor layer. Furthermore, the semiconductor body has a first main area and a second area opposite the first main area
  • semiconductor layer is formed.
  • first major surface and the second major surface define the first major surface and the second major surface
  • the semiconductor body in a vertical direction. Furthermore, the semiconductor body preferably has at least one side surface which connects the first main surface to the second main surface. The number of side surfaces is determined by the geometry of the semiconductor body.
  • the semiconductor body has a plurality of side surfaces. This is the case, for example, if the
  • Semiconductor chip is cuboid and correspondingly has four side surfaces.
  • the at least one side surface is preferably arranged largely transversely to the first and second main surfaces. "Cross" means that one
  • Normal vector of the first and / or second major surface extends.
  • the lateral directions are arranged in a plane whose normal vector is arranged parallel to the vertical direction.
  • the direction in which the second semiconductor layer follows the first semiconductor layer denotes the vertical direction.
  • the at least one side surface may be a surface composed of at least two partial surfaces.
  • the partial surfaces may be planar surfaces, wherein in particular the surface normals of two adjoining partial surfaces extend transversely, ie not parallel, to one another.
  • the first semiconductor layer may have a first conductivity and the second semiconductor layer may have a second conductivity.
  • the first conductivity may be a first conductivity and the second semiconductor layer may have a second conductivity.
  • the semiconductor body may comprise further semiconductor layers between the first and second semiconductor layer.
  • Semiconductor body preferably an active zone, which is suitable for radiation generation or for radiation detection.
  • the active zone is a p-n transition zone.
  • the active zone may be formed as a layer or as a layer sequence of several layers.
  • the active zone emits during operation of the
  • Semiconductor device electromagnetic radiation such as in the visible, ultraviolet or infrared spectral range.
  • the active zone is in particular between the first semiconductor layer and the second
  • the layers of the semiconductor body are preferably based on nitride compound semiconductors materials.
  • "Based on nitride compound semiconductors” in the present context means that at least one layer of the semiconductor body comprises a nitride III / V compound semiconductor material, preferably Al n Ga m i nn m - n , where 0 ⁇ n ⁇ 1, 0 ⁇ m ⁇ 1 and n + m ⁇ 1. This material does not necessarily have to be mathematically exact
  • composition according to the above formula may contain one or more dopants as well as additional
  • the above formula contains only the essential constituents of the crystal lattice (Al, Ga, In, N), even if these may be partially replaced by small amounts of other substances.
  • the semiconductor component may have an electrically conductive carrier layer.
  • the carrier layer has a comparatively low electrical resistance.
  • the support layer is due to their nature, such as their thickness and / or their material, a stability-giving component of the
  • the second major surface is at least
  • the carrier layer partially covered by the carrier layer. It is possible that the carrier layer largely
  • Main surface preferably at least 50%, in particular at least 80%, preferably at least 90% of the
  • Carrier layer is covered.
  • the carrier layer thus has in particular only a few places where
  • the semiconductor component may have an electrically conductive deformation layer.
  • the deformation layer has a comparatively low electrical resistance.
  • the electrically conductive deformation layer has a comparatively low electrical resistance.
  • Deformation layer equal or greater elasticity than the electrically conductive support layer.
  • the "elasticity" refers to the elastic properties of the material used for the various layers Stiffness of the deformation layer of the stiffness of the support layer.
  • the rigidity of the material refers to the elastic properties of the material used for the various layers Stiffness of the deformation layer of the stiffness of the support layer.
  • the stiffness of a layer depends not only on the elastic properties of the material used, but also decisively on the geometry of the layer.
  • the second main surface of the electrically conductive deformation layer at least partially
  • Main surface at 70%, in particular at least 80%
  • Deformation layer can be formed largely uninterrupted. So the deformation layer has
  • Deformation layer is structured so that the
  • Deformation layer is preferably less than 70%, but in particular greater than 30%.
  • Structuring of the deformation layer in particular, the rigidity of the deformation layer can be reduced.
  • the deformation layer is a coherent layer. This means that all areas of the deformation layer
  • Lead semiconductor device to be intercepted.
  • the carrier layer more compliant deformation layer thus compensates for the rigidity of the carrier layer. According to at least one embodiment, the
  • Deformation layer disposed on a semiconductor body side facing away from the carrier layer.
  • the deformation layer is applied directly to the carrier layer. Between the carrier layer and the deformation layer, therefore, preferably no further layer is arranged. in the
  • Area of the carrier layer occurring tensions can thus by the arranged in the immediate vicinity
  • Deforming layer are advantageously degraded.
  • the carrier layer conforms to the
  • Deformation layer covered This means in particular that mutually facing boundary surfaces of the carrier and
  • Deformation layer are identical in terms of their geometric shape.
  • a thickness of the deformation layer may be half or less than half the thickness of the support layer.
  • the thickness of the strain layer is between about 200 nm and about 5 ⁇ m, with deviations from the stated values up to 10% being tolerable.
  • the thickness of the support layer between 2 ym inclusive and including 100 ym, in particular between 5 ym and 30 ym, preferably between 5 ym and 15 ym, deviations from the stated values up to 10% being tolerable.
  • the thickness is a maximum
  • Extension of the respective layer in a direction which is arranged perpendicular to a main extension plane of the respective layer.
  • the deformation layer is predominantly a layer of uniform thickness, wherein the thickness may vary within the usual manufacturing tolerances.
  • the deformation layer reinforces in particular the
  • Carrier layer and can be used in combination with this
  • the carrier layer and the deformation layer are formed of different materials.
  • the deformation layer has a higher elasticity than the carrier layer.
  • the carrier layer and the deformation layer may be formed of the same material, wherein the electrically conductive deformation layer has an equal elasticity as the electrically conductive carrier layer. If the deformation and support layer formed of the same material, so is preferably a material with
  • the deformation layer is a metallic layer.
  • a "metallic layer” is to be understood as meaning a layer which is formed from a metal or a metal compound and is distinguished by at least one of the following properties: high electrical conductivity, which is associated with increasing temperature decreases, high thermal conductivity, ductility (ductility), metallic luster
  • the carrier layer is preferably a metallic layer.
  • Suitable materials for the deformation layer are
  • the deformation layer can contain at least one of these materials or consist of one of these materials.
  • the carrier layer come as materials, for example, Au, Zn, Al, Sn, Ni and Cu or
  • the carrier layer may therefore contain at least one of these materials or consist of one of these materials.
  • the deformation layer can be a galvanic, sputtered or vapor-deposited layer.
  • the deformation layer can be a galvanic, sputtered or vapor-deposited layer.
  • the carrier layer is in particular a
  • Galvanic layer which is electrodeposited on a arranged on the semiconductor body seed layer.
  • the starting layer of one of the materials Au, Ti, Cu, Al, Ag, Sn, Rh, Ni or Pt contain or consist of one of these materials.
  • Carrier layer from the second major surface to at least one side surface of the semiconductor body.
  • the carrier layer may extend up to at least one side surface of the first semiconductor layer. It can be
  • Deformation layer in lateral directions up to an edge of the carrier layer.
  • the deformation layer can project beyond the semiconductor body in lateral directions.
  • At least one side surface of the semiconductor component is formed in regions by side surfaces of the carrier layer and the deformation layer.
  • Semiconductor device partially formed by side surfaces of the carrier layer and the deformation layer.
  • Semiconductor component is thus limited laterally by side surfaces of both layers at least partially. According to at least one embodiment of the
  • the semiconductor body has at least one recess which extends from the second main surface in the direction of the first main surface and which terminates in the first semiconductor layer.
  • the recess is
  • the semiconductor body may have a plurality of such recesses.
  • the carrier layer is arranged in the at least one recess. This is used advantageously for electrical contacting of the first
  • connection contact for electrical contacting of the second semiconductor layer.
  • the first connection contact be electrically connected to the carrier layer.
  • Connection layer be electrically conductively connected, which is electrically conductively connected to the second semiconductor layer.
  • Deforming layer at least one recess in which the second terminal contact is arranged.
  • the recess extends from one of the support layer facing away from the boundary surface of the deformation layer through the deformation layer through to one of
  • Deformation layer That is, the deformation layer is completely penetrated by the recess. Furthermore, the recess can continue into the carrier layer and penetrate it completely.
  • the deformation layer is preferably arranged between the semiconductor body and the base body.
  • the first and second terminal contacts are embedded in the base body.
  • the first and the second terminal contact extend in particular from the side of the semiconductor body through the main body to a surface of the semiconductor body facing away from
  • the main body may be formed, for example, by a casting process.
  • the base body is made of a castable plastic, such as a polymer such as resin, epoxy or silicone.
  • a castable plastic such as a polymer such as resin, epoxy or silicone.
  • a casting process is generally understood to mean a process by means of which a molding composition is preferably configured under pressure in accordance with a predetermined shape and, if necessary, cured.
  • the term includes
  • a method for producing a semiconductor component has the following steps:
  • Main surface opposite the second main surface wherein the first main surface is formed by a surface of the first semiconductor layer and the second main surface is formed by a surface of the second semiconductor layer,
  • Main surface connects to the second major surface
  • the above-mentioned process steps are carried out in the order given.
  • the above-mentioned process steps are carried out in the order given.
  • the deformation layer on a side facing away from the semiconductor body of the carrier layer applied thereto.
  • the deformation layer is applied directly to the carrier layer.
  • the deformation layer can be applied to the carrier layer by means of a coating method, preferably by means of a galvanic coating method.
  • a coating method preferably by means of a galvanic coating method.
  • Deformation layer is sputtered or vapor-deposited on the carrier layer.
  • the carrier layer can be applied by means of a coating method, preferably by means of a galvanic coating method, to one on the
  • the starting layer may be, for example, a sputtered or vapor-deposited layer.
  • connection contacts are applied to the semiconductor body by means of a coating method, preferably by means of a galvanic coating method.
  • a further starting layer which is in particular sputtered or vapor-deposited, serve as a seed layer for the connection contacts.
  • the first and second semiconductor layers can be layered successively on a single layer by means of an epitaxy process
  • Growth substrate are produced. Suitable materials for the growth substrate are, for example, sapphire, SiC and / or GaN.
  • the growth substrate can be at least partially removed after the production of the semiconductor body, so that the first main area or a surface of the first semiconductor layer is at least partially exposed.
  • a laser lift-off method is possible for the detachment of the growth substrate on which the first and second semiconductor layers are arranged. In this case, pressure waves or mechanical stresses in the semiconductor body can arise, which can be advantageously reduced by the deformability of the deformation layer.
  • a wafer composite For producing a plurality of semiconductor components, a wafer composite can be provided which has a
  • a semiconductor layer sequence comprising a first and a second semiconductor layer, a plurality of first
  • Terminal contacts a plurality of second
  • the wafer composite may include a plurality of isolation trenches along which the wafer composite is separable into a plurality of semiconductor devices. A complete penetration of the semiconductor layer sequence by the
  • Separation trenches is not necessary. Rather, the Separating trenches through the second semiconductor layer and the active layer through into the first semiconductor layer
  • the separation trenches extend in the vertical direction through the entire wafer composite, so that even by the formation of the separation trenches separate
  • semiconductor body or semiconductor devices arise. This variant is particularly advantageous if the semiconductor bodies are to be covered on the side surfaces with a material, for example with a reflective material.
  • a basic body composite is molded onto the wafer composite.
  • Basic body composite is a suitable material applied to the wafer composite such that the separation trenches and intermediate areas between the terminal contacts are at least partially or completely filled. In a subsequent process step, the wafer composite and the basic body composite along the separation trenches in a
  • a plurality of semiconductor devices such isolated that the semiconductor devices each have a semiconductor body, a carrier layer, a deformation layer and a
  • Semiconductor devices particularly suitable. In connection with The features described in the semiconductor device can therefore also be used for the method and vice versa.
  • Figure 1A is a schematic plan view and Figure 1B is a schematic cross-sectional view of a method step or a semiconductor device in a
  • Figure 2A is a schematic plan view and Figure 2B is a further schematic cross-sectional view of
  • Figure 3 is a schematic cross-sectional view of a
  • FIG. 4 shows a comparative example of a semiconductor component i in a schematic cross-sectional view
  • FIG. 5 shows a FIB (so-called “focused ion beam”) absorption of a semiconductor component according to an exemplary embodiment
  • FIG. 6 shows a FIB (so-called “focused ion beam”) absorption of a semiconductor component according to a comparative example.
  • FIGS. 1A and 1B illustrate an intermediate stage of a method for producing a semiconductor component 1 and an intermediate stage of a semiconductor component 1 described herein.
  • FIG. 1A shows the unfinished semiconductor component 1 in plan view of a second main surface 2B of the semiconductor body 2.
  • FIG. 1B shows a cross section of the unfinished semiconductor component 1 along the line ⁇ ⁇ shown in FIG. 1A.
  • the unfinished semiconductor device 1 comprises a
  • Semiconductor body 2 having a first semiconductor layer 3, a second semiconductor layer 4 and a growth substrate 3A, on which the first and second semiconductor layers 3, 4 are arranged. Furthermore, the semiconductor body 2 has a first main surface 2A and a second main surface 2B opposite the first main surface 2A, wherein the first main surface 2A extends through a surface of the first
  • Semiconductor layer 3 and the second main surface 2B is formed by a surface of the second semiconductor layer 4.
  • the semiconductor body 2 has several
  • first main surface 2A and the second main surface 2B define the semiconductor body 2 in the final semiconductor device (see Fig. 3) in a vertical direction V, while the
  • Side surfaces 2C, 2D limit the semiconductor body 2 in lateral directions L.
  • the lateral directions L run transversely, in particular perpendicularly, to the vertical direction V.
  • the side surfaces 2C, 2D can each be composed of a plurality of partial surfaces, the individual partial surfaces in particular each are planar surfaces and preferably the surface normals of two adjoining partial surfaces transversely, that is not parallel to each other.
  • Semiconductor layer 4 the semiconductor body 2 on an active zone 5, which is preferably for generating radiation
  • the active zone 5 is a p-n transition zone.
  • the active zone 5 may be formed as a layer or as a layer sequence of several layers.
  • the first semiconductor layer 3 may have a first conductivity and the second semiconductor layer 4 may have a second conductivity.
  • the first conductivity may have a first conductivity and the second semiconductor layer 4 may have a second conductivity.
  • the first conductivity may have a first conductivity and the second semiconductor layer 4 may have a second conductivity.
  • the layers of the semiconductor body 2 are preferably based on nitride compound semiconductors materials.
  • the semiconductor device 1 comprises an electrically conductive carrier layer 7, which has the second main surface 2B and the
  • the semiconductor component 1 comprises a
  • the electrically conductive deformation layer 8 which on a the Semiconductor body 2 facing away from the carrier layer 7 is arranged.
  • the electrically conductive deformation layer 8 covers the second main surface 2B at least in regions. Furthermore, the electrically conductive deformation layer 8 covers a boundary surface 7A of the carrier layer 7 facing it.
  • the carrier layer 7 is in particular conformed by the
  • Deformation layer 8 covered. This means in particular that mutually facing boundary surfaces 7A, 8B of
  • Carrier and deformation layer 7, 8 are identical in terms of their geometric shape.
  • the deformation layer 8 is preferably directly on the carrier layer 7
  • the deformation layer 8 is formed at most half as thick as the carrier layer 7.
  • the thickness Dl of the deformation layer 8 is between about 200 nm and about 5 ym, with deviations from the stated values up to 10 % are tolerable.
  • the thickness D2 of the carrier layer 7 may be between 2 ym inclusive and 100 ym inclusive, in particular between 5 ym and 30 ym, preferably between 5 ym and 15 ym, wherein
  • Deviations from the specified values up to 10% are tolerable.
  • the thickness D2 of the carrier layer 8 is determined perpendicular to a main extension plane, that is, parallel to the vertical direction V.
  • the deformation layer 8 can reinforce the carrier layer 7 and in combination with this for stabilizing the semiconductor device 1
  • the deformation layer 8 is formed predominantly with a uniform thickness Dl, wherein the thickness Dl may vary within conventional manufacturing tolerances.
  • the deformation layer 8 is formed largely uninterrupted, so that the second main surface 2B to at least 70%, in particular at least 80%, preferably to
  • the deformation layer 8 thus has in particular only a few places where interruptions, that is
  • the carrier layer 7 extends from the second
  • the deformation layer 8 extends in lateral directions L up to an edge of the carrier layer 7. In this case, the deformation layer 8 extends in lateral
  • the carrier layer 7 and the deformation layer 8 are identical to The carrier layer 7 and the deformation layer 8.
  • the deformation layer 8 advantageously has a higher
  • Materials for the strain layer 8 are, for example, Au, In, and Cu.
  • the deformation layer 8 may contain at least one of these materials or one of these materials.
  • carrier layer 7 materials, for example, Au, Zn, Al, Sn, Ni and Cu or
  • the carrier layer 7 can thus contain at least one of these materials or consist of one of these materials.
  • the deformation layer 8 may be a galvanic, sputtered or evaporated layer.
  • the carrier layer 7 is in particular a galvanic layer which is galvanically deposited on a start layer 6 arranged on the semiconductor body 2.
  • the semiconductor device 1 may comprise further layers.
  • connection layer 14 may be provided which directly adjoins the second semiconductor layer 4.
  • the connection layer 14 is formed of an electrically conductive and highly reflective material.
  • the connection layer 14 is an electrically conductive mirror layer.
  • the connection layer 14 may contain or consist of Ag. It is, however
  • connection layer 14 is formed of a transparent conductive oxide ("TCO") such as zinc oxide. Further, adjacent to the terminal layer 14 may be a TCO (TCO)
  • Current spreading layer 15 may be arranged.
  • Stromausweitungs slaughter 15 may as a layer stack
  • the current spreading layer 15 may include metals such as Pt, Au, Cu, Al, Ag, Sn, Rh, and Ti.
  • the passivation layer 16 can be the
  • the deformation layer 8 has a plurality of recesses 17, in each of which a second connection contact can be arranged.
  • the recesses 17 each extend from a boundary surface 8A of the deformation layer 8 facing away from the carrier layer 7 through the deformation layer 8 to one of the carrier layer 7
  • FIG. 2B shows the above-described intermediate stage of a method or of a semiconductor component 1 in another view, FIG. 2B showing a cross section along the line BB ⁇ shown in FIG. 2A.
  • the semiconductor body 2 has a recess 18 which extends from the second main surface 2B in the direction of the first
  • Main surface 2A extends and that in the first
  • Semiconductor layer 3 ends.
  • the recess 18 is completely surrounded by the semiconductor body 2 in lateral directions.
  • the semiconductor body 2 has a plurality of such recesses 18.
  • the carrier layer 7 is arranged. This is used advantageously for electrical contacting of the first
  • a contact element 19 may be arranged in the recess 18 in direct contact therewith.
  • the arranged in the recess 18 carrier layer 7 is by a laterally surrounding insulation of the electrically isolated adjacent layers.
  • the passivation layer 16 extends into the
  • Recess 18 ensures an electrical insulation of the carrier layer 7 with respect to the adjacent layers.
  • Carrier layer 7 facing away from boundary surface 8A of
  • Deforming layer 8 is formed, wherein the
  • Insulation layer 12 preferably extends into the recess 17.
  • connection contacts 10, 11 are formed.
  • connection contacts 10, 11 are used.
  • a base body 13 is formed, in which the connection contacts 10, 11 are embedded.
  • the base body 13 advantageously represents a further stability-imparting component.
  • the growth substrate 3A can be at least partially removed, so that the first main surface 2A or a
  • the occurring pressure waves or mechanical loads can by the elastic, yielding
  • Deformation layer 8 are advantageously degraded.
  • FIG. 3 shows a finished semiconductor component 1 in a cross-sectional view along that shown in FIG. 1A Line ⁇ ⁇ .
  • the semiconductor component 1 is in particular an optoelectronic semiconductor component.
  • Semiconductor component 1 is preferably provided for the emission of radiation.
  • the active zone 5 in the operation of the semiconductor device 1 electromagnetic radiation, such as in the visible, ultraviolet or infrared
  • Main surface 2A coupled out of the semiconductor device 1.
  • the semiconductor device 1 has a first one
  • Terminal contact 10 for electrically contacting the first semiconductor layer 3 and a second terminal contact 11 for electrically contacting the second semiconductor layer 4.
  • the first terminal 10 is connected to the
  • the second terminal contact 11 is disposed in the recess 17 and extends in the vertical direction V through the
  • the second terminal contact 11 is in electrical contact with the terminal layer 14.
  • the second connection contact 11 is electrically insulated from the deformation layer 8 and the carrier layer 7 by the insulation layer 12 arranged in the recess 18.
  • the insulating layer 12 may be formed of an electrically insulating material such as silicon oxide and / or silicon nitride.
  • the semiconductor component 1 has an integrally formed main body 13, which is arranged on the semiconductor body 2. In the vertical direction V are between the
  • connection contacts 10, 11 extend starting from the Semiconductor body 2 through the base body 13 through to a surface 13A of the base body 13, which is arranged on a side facing away from the second main surface 2B of the base body 13.
  • the connection contacts 10, 11 are from
  • Main body 13 in lateral directions L fully enclosed.
  • FIG. 4 shows a comparative example of FIG
  • FIG. 5 shows a section from the cross section of a semiconductor component as shown in FIG. 3 in a FIB recording device. Between the insulating layer 12 and the
  • Carrier layer 7 is a deformation layer 8 is arranged, the formation of defects such as cracks and
  • FIG. 6 shows a section from the cross section of a comparative example of a, as shown in FIG.
  • the semiconductor device 1 can in the insulation layer 12 detect defects 20, which can be prevented with the deformation layer 8.

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Abstract

L'invention concerne un composant semi-conducteur (1) comprenant : un corps semi-conducteur (2) présentant une première couche semi-conductrice (3) et une deuxième couche semi-conductrice (4), une première surface principale (2A) et une deuxième surface principale (2B) opposée à la première, la première surface principale (2A) étant formée par une surface de la première couche semi-conductrice (3) et la deuxième surface principale (2B) par une surface de la deuxième couche semi-conductrice (4), au moins une surface latérale (2C, 2D) qui relie la première surface principale (2A) et la deuxième surface principale (2B) ; une couche de support (7) conductrice électriquement qui recouvre au moins par endroits la deuxième surface principale (2B) ; ainsi qu'une couche de déformation (8) conductrice électriquement qui recouvre au moins par endroits la deuxième surface principale (2B), cette couche de déformation (8) conductrice électriquement présentant une élasticité identique ou supérieure à celle de la couche de support (7) conductrice électriquement. L'invention concerne en outre un procédé de fabrication d'un tel composant semi-conducteur (1).
PCT/EP2018/062989 2017-05-23 2018-05-17 Composant semi-conducteur et procédé de fabrication d'un composant semi-conducteur Ceased WO2018215309A1 (fr)

Priority Applications (1)

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US16/615,835 US11430917B2 (en) 2017-05-23 2018-05-17 Semiconductor component comprising a deformation layer and method for producing a semiconductor component comprising a deformation layer

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DE102017111278.2A DE102017111278A1 (de) 2017-05-23 2017-05-23 Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements
DE102017111278.2 2017-05-23

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DE102021118706A1 (de) 2021-07-20 2023-01-26 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektronischer halbleiterchip und herstellungsverfahren
DE102021123996A1 (de) * 2021-09-16 2023-03-16 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektornisches halbleiterbauelement und verfahren zur herstellung eines optoelektronischen halbleiterbauelements

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WO2015140159A1 (fr) * 2014-03-20 2015-09-24 Osram Opto Semiconductors Gmbh Composant optoélectronique et procédé de fabrication de composants semi-conducteurs optoélectroniques
DE102015100578A1 (de) * 2015-01-15 2016-07-21 Osram Opto Semiconductors Gmbh Bauelement und Verfahren zur Herstellung eines Bauelements

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DE102015111492B4 (de) 2015-07-15 2023-02-23 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Bauelemente und Verfahren zur Herstellung von Bauelementen
DE102015114583A1 (de) 2015-09-01 2017-03-02 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip
JP6604786B2 (ja) * 2015-09-11 2019-11-13 三星電子株式会社 半導体発光装置およびその製造方法
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WO2015140159A1 (fr) * 2014-03-20 2015-09-24 Osram Opto Semiconductors Gmbh Composant optoélectronique et procédé de fabrication de composants semi-conducteurs optoélectroniques
DE102015100578A1 (de) * 2015-01-15 2016-07-21 Osram Opto Semiconductors Gmbh Bauelement und Verfahren zur Herstellung eines Bauelements

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US11430917B2 (en) 2022-08-30
US20200168767A1 (en) 2020-05-28

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