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WO2018214210A1 - 一种阵列基板及其制作方法 - Google Patents

一种阵列基板及其制作方法 Download PDF

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Publication number
WO2018214210A1
WO2018214210A1 PCT/CN2017/089617 CN2017089617W WO2018214210A1 WO 2018214210 A1 WO2018214210 A1 WO 2018214210A1 CN 2017089617 W CN2017089617 W CN 2017089617W WO 2018214210 A1 WO2018214210 A1 WO 2018214210A1
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WIPO (PCT)
Prior art keywords
metal layer
layer
array substrate
insulating layer
substrate according
Prior art date
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Ceased
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PCT/CN2017/089617
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English (en)
French (fr)
Inventor
雍玮娜
徐向阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/572,494 priority Critical patent/US20180342539A1/en
Publication of WO2018214210A1 publication Critical patent/WO2018214210A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • TFT-LCD Thin Film Transistor Liquid Crystal
  • GOA Gate driver On Array, array substrate row drive technology, that is, the gate drive circuit is directly fabricated on the array substrate.
  • each via has ITO at the uppermost layer, and is used to connect the signal lines on different layers to form a box. After that, it will be in direct contact with the frame glue.
  • the frame material used on the market after being applied to the panel, may cause corrosion of ITO in the GOA circuit area under the frame rubber due to the problem of water absorption or adhesion during the high temperature and high humidity test stage, and finally the panel appears.
  • a failure mode such as an abnormality is displayed, which affects the production yield and performance of the panel.
  • An object of the present invention is to provide an array substrate and a manufacturing method thereof, which can avoid corrosion of ITO in a GOA circuit region on an array substrate, and improve production yield and performance of the panel.
  • the present invention provides an array substrate including a display region and a non-display region, the non-display region including a GOA region, wherein the GOA region sequentially forms a first metal layer, an insulating layer, a second metal layer, and a protective layer from bottom to top. ;among them,
  • the second metal layer is connected to the first metal layer through a via, and the protective layer covers the second metal layer for protecting the circuit of the GOA region from corrosion;
  • the first metal layer is a gate metal layer
  • the insulating layer is a gate insulating layer
  • the second metal layer is a source and drain metal layer
  • the protective layer is a passivation layer
  • the second metal layer extends to the via and is connected to the first metal layer.
  • an active layer is further formed between the insulating layer and the second metal layer.
  • the via holes penetrate the insulating layer.
  • the protective layer has a thickness of 1-2 ⁇ m.
  • the present invention also provides an array substrate comprising a display area and a non-display area, the non-display area comprising a GOA area, the GOA area forming a first metal layer, an insulating layer, a second metal layer and a protective layer in order from bottom to top ;among them,
  • the second metal layer is connected to the first metal layer through a via, and the protective layer covers the second metal layer for protecting the circuit of the GOA region from corrosion.
  • the first metal layer is a gate metal layer
  • the insulating layer is a gate insulating layer
  • the second metal layer is a source/drain metal layer
  • the protective layer is passivated Floor.
  • an active layer is further formed between the insulating layer and the second metal layer.
  • the via holes penetrate the insulating layer.
  • the second metal layer extends to the via and is connected to the first metal layer.
  • the protective layer has a thickness of 1-2 ⁇ m.
  • a method for fabricating an array substrate which includes:
  • a protective layer is formed on the second metal layer, the protective layer covering the second metal layer for protecting the circuit of the GOA region from corrosion.
  • an active layer is further formed between the insulating layer and the second metal layer.
  • the first metal layer is a gate metal layer
  • the insulating layer is a gate insulating layer
  • the second metal layer is a source drain metal layer
  • the protection The layer is a passivation layer.
  • the second metal layer extends to the via and is connected to the first metal layer.
  • the second metal layer is directly connected to the first metal layer through the via hole, and a protective layer is formed on the second metal layer, thereby avoiding direct contact between the metal and the sealant, thereby making the array
  • the circuit of the GOA area on the substrate is protected from corrosion, improving the production yield and performance of the panel.
  • FIG. 1 is a schematic structural diagram of an array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a film layer of a GOA region of an array substrate according to a preferred embodiment of the present invention
  • FIG. 3 is a schematic flow chart of a method for fabricating an array substrate according to a preferred embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of an array substrate according to a preferred embodiment of the present invention.
  • the array substrate of the preferred embodiment includes a display area 101 and a non-display area (not shown), and the non-display area includes a GOA area 102.
  • the data area 1012 and the scan line 1011 are disposed on the display area 101.
  • the GOA area 102 is disposed on both sides of the display area 101.
  • the GOA area 101 is integrated with a GOA circuit.
  • the GOA circuit includes a plurality of GOA units 1021 for A scan signal is output, which is output to the display area 101 of the array substrate for driving the turning on or off of the pixels in the display area 101.
  • the sealant when the display panel is fabricated, the sealant is usually pasted on the array substrate. With the development of the narrow bezel and the high-resolution panel, the sealant is inevitably pasted on the GOA region 102.
  • the present invention changes the array substrate.
  • the film structure of the upper GOA region 102 avoids the direct contact of the sealant with the metal wire for transmitting signals, so that the circuit of the GOA region on the array substrate is protected from corrosion, and the production yield and performance of the panel are improved.
  • FIG. 2 is a schematic structural diagram of a film layer of a GOA region of an array substrate according to a preferred embodiment of the present invention.
  • a first metal layer 201, an insulating layer 202, a second metal layer 203, and a protective layer 204 are sequentially formed on the GOA region from bottom to top; wherein, the second The metal layer 203 is connected to the first metal layer 201 through a via 205 (the area indicated by the dotted line in the figure is the area where the via is located), and the protective layer 204 covers the second metal layer 203 for protecting the GOA area.
  • the circuit is protected from corrosion.
  • an active layer 206 is further formed between the insulating layer 202 and the second metal layer 203, and the via 205 penetrates through the insulating layer 202.
  • the first metal layer 201 is formed on a substrate 200
  • the substrate 200 may be a glass substrate, wherein the glass substrate is uniform in material, has high transparency and low reflectivity, and has good thermal stability, thereby It can maintain stable properties after multiple high temperature processes.
  • the preferred embodiment does not limit the substrate 200.
  • the process personnel can select the substrate 200 according to specific needs.
  • the first metal layer 201 may be a metal compound conductive layer formed of a plurality of layers of metal.
  • the first metal layer 201 is usually formed by a vapor deposition technique, and then various signal lines are formed through an etching process or the like.
  • the insulating layer 202 covers the first metal layer 201, and the insulating layer 202 may be a layer which may be formed of an oxide, a nitride or an oxynitride. Of course, in order to further improve the quality of the film layer, the insulating layer 202 may also be two layers.
  • the active layer 206 is formed over the insulating layer 202 and is an amorphous silicon layer or a polysilicon layer.
  • the second metal layer 203 is formed over the active layer 206, which is typically formed by a vapor deposition technique, and then forms various signal lines through an etching process or the like. It should be noted that, in the GOA area of the array substrate, in order to reduce the resistance, it is often necessary to set the signal lines for transmitting the same signal on different film layers, so that the signal lines for transmitting the same signal through the via holes are required. connect them.
  • the second metal layer 203 extends to the via 205 and is connected to the first metal layer 201 to connect signal lines for transmitting the same signal and located on different film layers.
  • the protective layer 204 is formed over the second metal layer 203. It should be noted that, after the protective layer 204 is formed, it will directly contact the sealant. Since the protective layer 204 does not participate in any signal transmission in the array substrate, the circuit on the GOA region of the array substrate can be protected from corrosion. Further, the protective layer 204 has a thickness of 1-2 micrometers.
  • the first metal layer 201 is a gate metal layer
  • the insulating layer 202 is a gate insulating layer
  • the second metal layer 203 is a source and drain metal layer
  • the protective layer 204 is blunt. Layer.
  • the second metal layer is directly connected to the first metal layer through the via hole, and a protective layer is formed on the second metal layer, thereby avoiding direct contact between the metal and the sealant, thereby making the array substrate.
  • the circuit of the GOA area is protected from corrosion, improving the production yield and performance of the panel.
  • FIG. 3 is a schematic flow chart of a method for fabricating an array substrate according to a preferred embodiment of the present invention. As shown in FIG. 3, the method includes the following steps:
  • Step S301 sequentially forming a first metal layer and an insulating layer on the GOA region of the substrate;
  • Step S302 forming a via hole in the insulating layer, the bottom of the via hole being the first metal layer;
  • Step S303 forming a second metal layer on the insulating layer, the second metal layer being connected to the first metal layer through the via hole;
  • Step S304 forming a protective layer on the second metal layer, the protective layer covering the second metal layer for protecting the circuit of the GOA region from corrosion.
  • an active layer is further formed between the insulating layer and the second metal layer.
  • the first metal layer is formed on a substrate
  • the substrate may be a glass substrate, wherein the glass substrate is uniform in material, has high transparency and low reflectivity, and has good thermal stability, so that The properties remain stable after the sub-high temperature process.
  • the preferred embodiment does not limit the substrate.
  • the first metal layer may be a metal compound conductive layer formed of a plurality of layers of metal.
  • the first metal layer is usually formed by a vapor deposition technique, and then various signal lines are formed through an etching process or the like.
  • the insulating layer is overlying the first metal layer, which may be a layer that may be formed of an oxide, a nitride or an oxynitride.
  • the insulating layer may also be two layers.
  • the active layer is formed over the insulating layer and is an amorphous silicon layer or a polysilicon layer.
  • the second metal layer is formed over the active layer, which is usually formed by a vapor deposition technique, and then forms various signal lines through an etching process or the like. It should be noted that, in the GOA area of the array substrate, in order to reduce the resistance, it is often necessary to set the signal lines for transmitting the same signal on different film layers, so that the signal lines for transmitting the same signal through the via holes are required. connect them.
  • the second metal layer extends to the via and is connected to the first metal layer to connect the signal lines for transmitting the same signal and on different film layers.
  • the protective layer is formed over the second metal layer. It should be noted that, after the protective layer is formed, it will directly contact the sealant. Since the protective layer does not participate in any signal transmission in the array substrate, the circuit on the GOA region of the array substrate can be protected from corrosion. Further, the protective layer has a thickness of 1-2 microns.
  • the first metal layer is a gate metal layer
  • the insulating layer is a gate insulating layer
  • the second metal layer is a source/drain metal layer
  • the protective layer is passivated. Floor.
  • the second metal layer is directly connected to the first metal layer through the via hole, and a protective layer is formed on the second metal layer, thereby avoiding direct contact between the metal and the sealant, thereby making the array
  • the circuit of the GOA area on the substrate is protected from corrosion, improving the production yield and performance of the panel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板及其制作方法，阵列基板包括显示区域（101）和非显示区域，非显示区域包括GOA区域（102），GOA区域（102）从下至上依次形成第一金属层（201）、绝缘层（202）、第二金属层（203）和保护层（204）；其中，第二金属层（203）通过过孔（205）与第一金属层（201）连接，保护层（204）覆盖第二金属层（203），用于保护GOA区域的电路免受腐蚀。

Description

一种阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法。
 背景技术
薄膜晶体管显示器（Thin Film Transistor Liquid Crystal Display，TFT-LCD）的发展趋势势必为超窄边框、超低成本。为了实现这样的目的，已经有越来越多的面板厂引入了GOA (Gate driver On Array，阵列基板行驱动)技术，即直接将闸极驱动电路制作在阵列基板上。
但随着窄边框和高分辨率面板的发展，GOA区电路设计占用显示区两侧的面积越来越多，导致框胶可占用的面积不断缩减，最终不可避免的占到GOA区电路上。而GOA区电路由于信号的传递，会设计大量的过孔，对于面板下侧阵列基板而言，每一处过孔均有ITO处在最上层，用于连接不同层上的信号线，成盒后就会与框胶直接接触。而目前市面上的框胶材料，应用于面板后，在经过高温高湿的测试阶段，均会因吸水性或粘着性问题，导致框胶下GOA电路区的ITO出现腐蚀现象，最终造成面板出现显示异常等失效模式，影响面板的生产良率和使用性能。
故，有必要提供一种阵列基板及其制作方法，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种阵列基板及其制作方法，可以避免阵列基板上的GOA电路区的ITO出现腐蚀现象，提高面板的生产良率和使用性能。
 技术解决方案
本发明提供一种阵列基板，包括显示区域和非显示区域，所述非显示区域包括GOA区域，其中所述GOA区域从下至上依次形成第一金属层、绝缘层、第二金属层和保护层；其中，
所述第二金属层通过过孔与所述第一金属层连接，所述保护层覆盖所述第二金属层，用于保护所述GOA区域的电路免受腐蚀；
所述第一金属层为栅极金属层，所述绝缘层为栅极绝缘层，所述第二金属层为源漏极金属层，所述保护层为钝化层；
所述第二金属层延伸至所述过孔，并与所述第一金属层连接。
在本发明的阵列基板中，在所述绝缘层和所述第二金属层之间还形成有源层。
在本发明的阵列基板中，所述过孔贯穿所述绝缘层。
在本发明的阵列基板中，所述保护层的厚度为1-2微米。
本发明还提供一种阵列基板，包括显示区域和非显示区域，所述非显示区域包括GOA区域，所述GOA区域从下至上依次形成第一金属层、绝缘层、第二金属层和保护层；其中，
所述第二金属层通过过孔与所述第一金属层连接，所述保护层覆盖所述第二金属层，用于保护所述GOA区域的电路免受腐蚀。
在本发明的阵列基板中，所述第一金属层为栅极金属层，所述绝缘层为栅极绝缘层，所述第二金属层为源漏极金属层，所述保护层为钝化层。
在本发明的阵列基板中，在所述绝缘层和所述第二金属层之间还形成有源层。
在本发明的阵列基板中，所述过孔贯穿所述绝缘层。
在本发明的阵列基板中，所述第二金属层延伸至所述过孔，并与所述第一金属层连接。
在本发明的阵列基板中，所述保护层的厚度为1-2微米。
依据本发明的上述目的，还提供一种阵列基板的制作方法，其包括：
在基板的GOA区域上依次形成第一金属层、绝缘层；
在所述绝缘层形成过孔，所述过孔的底部为所述第一金属层；
在所述绝缘层上形成第二金属层，所述第二金属层通过所述过孔与所述第一金属层连接；以及
在所述第二金属层上形成保护层，所述保护层覆盖所述第二金属层，用于保护所述GOA区域的电路免受腐蚀。
在本发明的阵列基板的制作方法中，在所述绝缘层与所述第二金属层之间还形成有源层。
在本发明的阵列基板的制作方法中，所述第一金属层为栅极金属层，所述绝缘层为栅极绝缘层，所述第二金属层为源漏极极金属层，所述保护层为钝化层。
在本发明的阵列基板的制作方法中，所述第二金属层延伸至所述过孔，并与所述第一金属层连接。
 有益效果
本发明的阵列基板及其制作方法，第二金属层通过过孔与第一金属层直接连接，并在该第二金属层上形成保护层，避免了金属与框胶的直接接触，从而使得阵列基板上的GOA区域的电路免受腐蚀，提高面板的生产良率和使用性能。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图1为本发明优选实施例提供的阵列基板的结构示意图；
图2为本发明优选实施例提供的阵列基板的GOA区域的膜层结构示意图；
图3为本发明优选实施例提供的阵列基板的制作方法的流程示意图。
 本发明的最佳实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参阅图1，图1为本发明优选实施例提供的阵列基板的结构示意图。如图1所示，本优选实施例的阵列基板，包括显示区域101和非显示区域（图中未标示），该非显示区域包括GOA区域102。其中，显示区域101上交叉设置有数据线1012和扫描线1011；GOA区域102设置在显示区域101两侧，该GOA区域101上集成有GOA电路，该GOA电路包括多个GOA单元1021，用于输出扫描信号，该扫描信号输出至阵列基板的显示区域101，用于驱动显示区域101中像素的开启或关闭。
特别地，在制作显示面板时，通常会在阵列基板上粘贴框胶，随着窄边框和高分辨率面板的发展，框胶不可避免的会粘贴在GOA区域102上，本发明通过改变阵列基板上GOA区域102的膜层结构，从而避免了框胶与用于传递信号的金属线的直接接触，使得阵列基板上的GOA区域的电路免受腐蚀，提高面板的生产良率和使用性能。
下面对阵列基板的GOA区域的膜层结构进行详细的描述。参阅图2，图2为本发明优选实施例提供的阵列基板的GOA区域的膜层结构示意图。如图2所示，本优选实施例提供的阵列基板，在GOA区域上，从下至上依次形成第一金属层201、绝缘层202、第二金属层203和保护层204；其中，该第二金属层203通过过孔205（图中虚线框标示的区域即是过孔所在的区域）与该第一金属层201连接，该保护层204覆盖第二金属层203，用于保护该GOA区域的电路免受腐蚀。
进一步的，在该绝缘层202和该第二金属层203之间还形成有源层206，该过孔205贯穿绝缘层202。
具体而言，该第一金属层201形成在一基板200上，该基板200可以是玻璃基板，其中，该玻璃基板材质均匀，具有高透明度和低反射率，并且有好的热稳定性，从而能在多次高温工艺之后保持性质稳定。本优选实施例不对基板200进行限制，在制作阵列基板时，工艺人员可以根据具体需要选择基板200。
其中，第一金属层201可以是多层金属形成的金属化合物导电层。该第一金属层201通常通过气相沉积技术形成，然后经过蚀刻工艺等形成各种信号线。
绝缘层202覆盖在第一金属层201之上，该绝缘层202可以为一层，其可由氧化物、氮化物或者氮氧化合物形成。当然，为了进一步提高膜层的质量，绝缘层202还可以是两层。
有源层206形成在绝缘层202之上，为非晶硅层或多晶硅层。
第二金属层203形成在有源层206之上，该第二金属层203通常通过气相沉积技术形成，然后经过蚀刻工艺等形成各种信号线。需要说明的是，在阵列基板的GOA区域上，为了减小电阻，常常需要将用于传递同一信号的信号线设置在不同膜层上，故需要通过过孔将用于传递同一信号的信号线连接起来。
具体地，第二金属层203延伸至该过孔205，并与第一金属层201连接，从而将用于传递同一信号且位于不同膜层上信号线连接起来。
该保护层204形成在第二金属层203之上。需要说明的是，该保护层204形成后将直接与框胶接触，由于保护层204在阵列基板中不参与任何信号的传递，可以保护阵列基板的GOA区域上的电路免受腐蚀。进一步的，该保护层204的厚度为1-2微米。
本优选实施例中的阵列基板，该第一金属层201为栅极金属层，该绝缘层202为栅极绝缘层，该第二金属层203为源漏极金属层，该保护层204为钝化层。
本优选实施例的阵列基板，第二金属层通过过孔与第一金属层直接连接，并在该第二金属层上形成保护层，避免了金属与框胶的直接接触，从而使得阵列基板上的GOA区域的电路免受腐蚀，提高面板的生产良率和使用性能。
本发明还提供一种阵列基板的制作方法，参阅图3，图3为本发明优选实施例提供的阵列基板的制作方法的流程示意图。如图3所示，该方法包括以下步骤：
步骤S301，在基板的GOA区域上依次形成第一金属层、绝缘层；
步骤S302，在所述绝缘层中形成过孔，所述过孔的底部为所述第一金属层；
步骤S303，在所述绝缘层上形成第二金属层，所述第二金属层通过所述过孔与所述第一金属层连接；以及，
步骤S304，在所述第二金属层上形成保护层，所述保护层覆盖所述第二金属层，用于保护所述GOA区域的电路免受腐蚀。
进一步的，在该绝缘层与该第二金属层之间还形成有源层。
具体而言，该第一金属层形成在一基板上，该基板可以是玻璃基板，其中，该玻璃基板材质均匀，具有高透明度和低反射率，并且有好的热稳定性，从而能在多次高温工艺之后保持性质稳定。本优选实施例不对基板进行限制，在制作阵列基板时，工艺人员可以根据具体需要选择基板。
其中，第一金属层可以是多层金属形成的金属化合物导电层。该第一金属层通常通过气相沉积技术形成，然后经过蚀刻工艺等形成各种信号线。
绝缘层覆盖在第一金属层之上，该绝缘层可以为一层，其可由氧化物、氮化物或者氮氧化合物形成。当然，为了进一步提高膜层的质量，绝缘层还可以是两层。
有源层形成在绝缘层之上，为非晶硅层或多晶硅层。
第二金属层形成在有源层之上，该第二金属层通常通过气相沉积技术形成，然后经过蚀刻工艺等形成各种信号线。需要说明的是，在阵列基板的GOA区域上，为了减小电阻，常常需要将用于传递同一信号的信号线设置在不同膜层上，故需要通过过孔将用于传递同一信号的信号线连接起来。
具体地，第二金属层延伸至该过孔，并与第一金属层连接，从而将用于传递同一信号且位于不同膜层上信号线连接起来。
该保护层形成在第二金属层之上。需要说明的是，该保护层形成后将直接与框胶接触，由于保护层在阵列基板中不参与任何信号的传递，可以保护阵列基板的GOA区域上的电路免受腐蚀。进一步的，该保护层的厚度为1-2微米。
本优选实施例中的阵列基板的制作方法，该第一金属层为栅极金属层，该绝缘层为栅极绝缘层，该第二金属层为源漏极金属层，该保护层为钝化层。
本发明的阵列基板及其制作方法，第二金属层通过过孔与第一金属层直接连接，并在该第二金属层上形成保护层，避免了金属与框胶的直接接触，从而使得阵列基板上的GOA区域的电路免受腐蚀，提高面板的生产良率和使用性能。
综上，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，包括显示区域和非显示区域，所述非显示区域包括GOA区域，其中所述GOA区域从下至上依次形成第一金属层、绝缘层、第二金属层和保护层；其中，
    所述第二金属层通过过孔与所述第一金属层连接，所述保护层覆盖所述第二金属层，用于保护所述GOA区域的电路免受腐蚀；
    所述第一金属层为栅极金属层，所述绝缘层为栅极绝缘层，所述第二金属层为源漏极金属层，所述保护层为钝化层；
    所述第二金属层延伸至所述过孔，并与所述第一金属层连接。
  2. 根据权利要求1所述的阵列基板，其中在所述绝缘层和所述第二金属层之间还形成有源层。
  3. 根据权利要求1所述的阵列基板，其中所述过孔贯穿所述绝缘层。
  4. 根据权利要求1所述的阵列基板，其中所述保护层的厚度为1-2微米。
  5. 一种阵列基板，包括显示区域和非显示区域，所述非显示区域包括GOA区域，其中所述GOA区域从下至上依次形成第一金属层、绝缘层、第二金属层和保护层；其中，
    所述第二金属层通过过孔与所述第一金属层连接，所述保护层覆盖所述第二金属层，用于保护所述GOA区域的电路免受腐蚀。
  6. 根据权利要求5所述的阵列基板，其中所述第一金属层为栅极金属层，所述绝缘层为栅极绝缘层，所述第二金属层为源漏极金属层，所述保护层为钝化层。
  7. 根据权利要求5所述的阵列基板，其中在所述绝缘层和所述第二金属层之间还形成有源层。
  8. 根据权利要求6所述的阵列基板，其中在所述绝缘层和所述第二金属层之间还形成有源层。
  9. 根据权利要求7所述的阵列基板，其中所述过孔贯穿所述绝缘层。
  10. 根据权利要求8所述的阵列基板，其中所述过孔贯穿所述绝缘层。
  11. 根据权利要求5所述的阵列基板，其中所述第二金属层延伸至所述过孔，并与所述第一金属层连接。
  12. 根据权利要求6所述的阵列基板，其中所述第二金属层延伸至所述过孔，并与所述第一金属层连接。
  13. 根据权利要5所述的阵列基板，其中所述保护层的厚度为1-2微米。
  14. 根据权利要6所述的阵列基板，其中所述保护层的厚度为1-2微米。
  15. 一种阵列基板的制作方法，其包括：
    在基板的GOA区域上依次形成第一金属层、绝缘层；
    在所述绝缘层形成过孔，所述过孔的底部为所述第一金属层；
    在所述绝缘层上形成第二金属层，所述第二金属层通过所述过孔与所述第一金属层连接；以及
    在所述第二金属层上形成保护层，所述保护层覆盖所述第二金属层，用于保护所述GOA区域的电路免受腐蚀。
  16. 根据权利要求15所述的阵列基板的制作方法，其中在所述绝缘层与所述第二金属层之间还形成有源层。
  17. 根据权利要求15所述的阵列基板的制作方法，其中所述第一金属层为栅极金属层，所述绝缘层为栅极绝缘层，所述第二金属层为源漏极极金属层，所述保护层为钝化层。
  18. 根据权利要求15所述的阵列基板的制作方法，其中所述第二金属层延伸至所述过孔，并与所述第一金属层连接。
  19. 根据权利要求16所述的阵列基板的制作方法，其中所述第二金属层延伸至所述过孔，并与所述第一金属层连接。
  20. 根据权利要求17所述的阵列基板的制作方法，其中所述第二金属层延伸至所述过孔，并与所述第一金属层连接。
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Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
CN107783342A (zh) * 2017-10-30 2018-03-09 深圳市华星光电技术有限公司 液晶显示面板及其制备方法
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102033371A (zh) * 2009-09-24 2011-04-27 北京京东方光电科技有限公司 阵列基板及其制造方法
CN103413811A (zh) * 2013-07-23 2013-11-27 北京京东方光电科技有限公司 阵列基板及其制造方法、显示装置
CN104658981A (zh) * 2015-03-17 2015-05-27 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN105280649A (zh) * 2015-09-17 2016-01-27 深圳市华星光电技术有限公司 阵列基板、显示装置及阵列基板的制备方法
CN105702685A (zh) * 2016-03-01 2016-06-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN106057824A (zh) * 2016-08-03 2016-10-26 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI328788B (en) * 2008-03-11 2010-08-11 Au Optronics Corp Gate driver-on-array and method of making the same
CN103018991B (zh) * 2012-12-24 2015-01-28 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
CN104576523A (zh) * 2013-10-16 2015-04-29 北京京东方光电科技有限公司 一种阵列基板及其制作方法和显示装置
CN103676382B (zh) * 2013-12-26 2017-03-08 京东方科技集团股份有限公司 阵列基板及显示装置
CN104199216A (zh) * 2014-08-25 2014-12-10 京东方科技集团股份有限公司 液晶显示面板及其封装方法、显示装置
CN105097834B (zh) * 2015-07-06 2017-10-17 合肥京东方光电科技有限公司 一种阵列基板及其制造方法、显示装置
CN106646982B (zh) * 2017-03-21 2019-09-17 京东方科技集团股份有限公司 显示面板及其制造方法和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102033371A (zh) * 2009-09-24 2011-04-27 北京京东方光电科技有限公司 阵列基板及其制造方法
CN103413811A (zh) * 2013-07-23 2013-11-27 北京京东方光电科技有限公司 阵列基板及其制造方法、显示装置
CN104658981A (zh) * 2015-03-17 2015-05-27 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN105280649A (zh) * 2015-09-17 2016-01-27 深圳市华星光电技术有限公司 阵列基板、显示装置及阵列基板的制备方法
CN105702685A (zh) * 2016-03-01 2016-06-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN106057824A (zh) * 2016-08-03 2016-10-26 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

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