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WO2018135914A1 - Dispositif de cellule dram et son procédé de fabrication - Google Patents

Dispositif de cellule dram et son procédé de fabrication Download PDF

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Publication number
WO2018135914A1
WO2018135914A1 PCT/KR2018/000946 KR2018000946W WO2018135914A1 WO 2018135914 A1 WO2018135914 A1 WO 2018135914A1 KR 2018000946 W KR2018000946 W KR 2018000946W WO 2018135914 A1 WO2018135914 A1 WO 2018135914A1
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WIPO (PCT)
Prior art keywords
gate
insulating layer
region
main body
storage body
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Ceased
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PCT/KR2018/000946
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English (en)
Korean (ko)
Inventor
강인만
윤영준
서재화
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Industry Academic Cooperation Foundation of KNU
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Industry Academic Cooperation Foundation of KNU
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Priority claimed from KR1020170041029A external-priority patent/KR101899793B1/ko
Application filed by Industry Academic Cooperation Foundation of KNU filed Critical Industry Academic Cooperation Foundation of KNU
Publication of WO2018135914A1 publication Critical patent/WO2018135914A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs

Definitions

  • the present invention relates to a DRAM cell device and a method of manufacturing the same, and a DRAM cell device and a method of manufacturing the same implemented with a transistor.
  • DRAM is composed of a cell device that records one bit of information by using one transistor and one capacitor (1T / 1C), and has a high integration due to a difficulty in minimizing a transistor as well as a transistor during the miniaturization process. There was a limit to.
  • the 1T DRAM cells have the advantage of easy miniaturization, fast operation speed, and easy integration into CMOS processes, thereby reducing production costs.
  • the most traditional programming method is to apply a voltage to the gate to allow current to flow through a MOSFET (Metal Oxide Silicon Field Effect Transistor), and then apply a high voltage to the drain through impact ionization. Creating holes and storing them in the body.
  • MOSFET Metal Oxide Silicon Field Effect Transistor
  • BJT Bipolar Junction Transistor
  • GIDL Gate Induced Drain Leakage
  • the MOSFET-based ionization collision programming method or the BJT operation-based programming method may consume less power during the program operation than the read operation, but the GIDL current magnitude is relatively small, so that the programming is faster. There is a problem that a high gate voltage is required.
  • the present invention provides a DRAM cell device using a tunneling field effect transistor and a method of manufacturing the same.
  • the substrate is formed with an insulating layer; A first gate surrounded by the insulating layer; A first gate insulating film formed on the first gate; A main body positioned above the first gate insulating layer; Source and drain formed on both sides of the main body, respectively; A second gate insulating film formed on the main body; A second gate formed on the second gate insulating film; And a hole storage body formed between the main body and the first gate insulating layer and storing holes from the main body by tunneling.
  • the source and drain are an N-type impurity doping layer (N + region), the main body is a P-type impurity doping layer (P-region), and the hole storage body is a P-type impurity doping layer doped at a higher concentration than the main body. It may be (P + region).
  • the first gate When the second gate is grounded or floated, the first gate is applied with a second predetermined positive voltage, and the drain is applied with a predetermined third positive voltage smaller than the second positive voltage.
  • a hole of the hole storage body is moved to the main body to reduce the hole of the hole storage body to perform an erasing (writing '0') operation.
  • a read operation may be performed by sensing a current flowing between the sources.
  • the main body may be stacked vertically on top of the hole storage body.
  • the main body, the hole storage body and the first gate may be located concentrically, and the hole storage body may have a width equal to or greater than that of the main body.
  • the source and drain may be coplanar with the main body, and may be vertically stacked on the hole storage body together with the main body, and the first gate may have a width equal to or smaller than that of the hole storage body.
  • the insulating layer may have a pattern for applying a voltage to the first gate.
  • the source and drain are P-type impurity doping layers (P + region), the main body is an N-type impurity doping layer (N-region), and the hole storage body is an N-type impurity doping layer doped at a higher concentration than the main body. (N + region).
  • the DRAM cell device formed substrate; A first gate surrounded by the insulating layer; A first gate insulating film formed on the first gate; An active layer disposed on the insulating layer and doped with the same conductivity type; A second gate insulating film formed on the active layer; A second gate formed on the second gate insulating film; And a hole storage body formed between the active layer and the first gate insulating layer and storing holes from the active layer by tunneling.
  • the active layer may be an N-type impurity doped layer (N + region), and the hole storage body may be a P-type impurity doped layer (P + region).
  • the active layer may be a P-type impurity doped layer (P + region), and the hole storage body may be an N-type impurity doped layer (N + region).
  • the active layer may form a single impurity region in which impurities of the same type are injected at a total concentration, and may be electrically connected to sources and drains formed at both sides of the second gate.
  • a method of manufacturing a DRAM cell device includes depositing a first insulating layer on a substrate; Patterning and etching a first gate region in the first insulating layer; Forming a first gate and a first gate insulating layer in the first gate region; Patterning and etching a hole storage body region on the first gate insulating layer; Growing a silicon thin film in the hole storage body region and doping impurities; Growing a silicon thin film on top of the hole storage body region and doping impurities of a source, a drain and a main body; Forming a second gate insulating layer on the main body; And depositing a second gate on the second gate insulating layer, and depositing the source and drain contact metals.
  • the method may further include depositing a second insulating layer on an upper surface of the first gate insulating layer and the first insulating layer before patterning and etching the hole storage body region.
  • the doping of the source and drain is formed of an N-type impurity doping layer (N + region), the doping of the main body is formed of a P-type impurity doping layer (P-region), and the doping of the hole storage body region is performed in the main It may be formed of a P-type highly doped layer (P + region) doped at a higher concentration than the body.
  • the DRAM cell device manufacturing method the step of depositing a first insulating layer on the substrate; Patterning and etching a first gate region in the first insulating layer; Forming a first gate and a first gate insulating layer in the first gate region; Patterning and etching a hole storage body region on the first gate insulating layer; Forming an active layer doped with an impurity of the same type on the hole storage body region; Forming a second gate insulating layer on the active layer; And depositing a second gate on the second gate insulating layer, and depositing a source and a drain contact metal.
  • the active layer may be implanted with the same concentration of impurities of the same type as a whole, and may be electrically connected to the source and drain contact metals to be unbonded.
  • a DRAM cell device using one transistor without a capacitor may be provided.
  • low-power, low-voltage and high-speed operation are possible during programming by using the band-band tunneling phenomenon of charges (holes and electrons), and the retention time is increased because the leakage of holes due to the energy barrier in the hold operation is blocked. Can be.
  • an upper portion of the hole storage body of the DRAM cell device may be integrated into a general silicon-based Complementary Metal-Oxide Semiconductor (CMOS) process for forming a metal oxide silicon field effect transistor (MOSFET). Since it can be reduced, it has an advantageous effect than the conventional DRAM cell device in terms of cost competitiveness and process technology compatibility.
  • CMOS Complementary Metal-Oxide Semiconductor
  • MOSFET metal oxide silicon field effect transistor
  • FIG. 1 is a cross-sectional view illustrating a DRAM cell device according to a first embodiment of the present invention.
  • FIG. 2 is a layered cross-sectional view illustrating a fabrication process of a DRAM cell device according to a first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view illustrating a band-to-band tunneling operation principle of a DRAM cell device according to the first embodiment of the present invention illustrated in FIG. 1.
  • FIG. 4 is a diagram illustrating an energy band in a program operation of a DRAM cell device according to the first embodiment of the present invention illustrated in FIG. 3.
  • FIG. 5 is a diagram illustrating an energy band in a hold operation of the DRAM cell device according to the first embodiment of the present invention illustrated in FIG. 3.
  • FIG. 6 and 7 are diagrams illustrating an energy band in a read operation of the DRAM cell device according to the first embodiment of the present invention illustrated in FIG. 3.
  • FIG. 8 is a diagram illustrating an energy band in an erase operation of the DRAM cell device according to the first embodiment of the present invention illustrated in FIG. 3.
  • FIG. 9 is a graph showing the amount of drain current versus time of operations of the DRAM cell device according to the first embodiment of the present invention.
  • FIG. 10 is a graph illustrating changes in threshold voltages in a program, erase, and read operation of a DRAM cell device according to the first embodiment of the present invention shown in FIG. 3.
  • FIG. 11 is a graph illustrating a change in current margin according to a hold time after programming of a DRAM cell device according to the first exemplary embodiment of FIG. 3.
  • FIG. 12 is a layered cross-sectional view of a DRAM cell device according to a second embodiment of the present invention.
  • FIG. 13 is a layered cross-sectional view of a DRAM cell device according to a third embodiment of the present invention.
  • FIG. 14 is a flowchart illustrating a method of manufacturing a DRAM cell device according to the first to third embodiments of the present invention.
  • FIG. 15 is a cross-sectional view illustrating a DRAM cell device according to a fourth embodiment of the present invention.
  • FIG. 16 is a layered cross-sectional view illustrating a fabrication process of a DRAM cell device according to a fourth embodiment of the present invention.
  • FIG. 17 is a cross-sectional view illustrating a band-to-band tunneling principle of a DRAM cell device in accordance with a fourth embodiment of the present invention illustrated in FIG. 15.
  • FIG. 18 is a diagram illustrating an energy band in a program operation of a DRAM cell device according to the fourth embodiment of the present invention illustrated in FIG. 17.
  • FIG. 19 is a diagram illustrating an energy band in a hold operation of a DRAM cell device according to a fourth exemplary embodiment of the present invention illustrated in FIG. 17.
  • 20 and 21 are diagrams illustrating an energy band in a read operation of the DRAM cell device according to the fourth embodiment of the present invention illustrated in FIG. 17.
  • FIG. 22 is a diagram illustrating an energy band in an erase operation of a DRAM cell device according to a fourth exemplary embodiment of the present invention illustrated in FIG. 17.
  • FIG. 23 is a graph showing the amount of drain current versus time of operations of the DRAM cell device according to the fourth embodiment of the present invention.
  • FIG. 24 is a graph illustrating changes in threshold voltages during program, erase, and read operations of the DRAM cell device of FIG. 17 according to the fourth embodiment of the present invention.
  • FIG. 25 is a graph illustrating a change in current margin according to a hold time after programming of a DRAM cell device according to the first exemplary embodiment of FIG. 17.
  • 26 is a flowchart illustrating a method of manufacturing a DRAM cell device according to a fourth embodiment of the present invention.
  • ordinal numbers such as “first”, “second”, and the like may be used to distinguish between components. These ordinal numbers are used to distinguish the same or similar components from each other, and the meaning of the terms should not be construed as limited by the use of these ordinal numbers. For example, the components combined with these ordinal numbers should not be limited in order of use or arrangement by the number. If necessary, the ordinal numbers may be used interchangeably.
  • a part when a part is connected to another part, this includes not only a direct connection but also an indirect connection through another medium.
  • the meaning that a part includes a certain component means that it may further include other components, without excluding other components, unless specifically stated otherwise.
  • FIG. 1 is a cross-sectional view illustrating a DRAM cell device according to a first embodiment of the present invention
  • FIG. 2 is a layered cross-sectional view illustrating a fabrication process of a DRAM device according to a first embodiment of the present invention.
  • the terms “deposition” and “growth” are used in the same sense as forming a semiconductor material layer, and the layer or thin film formed through various embodiments of the present invention is organometallic vapor deposition (metal-).
  • organometallic vapor deposition MOCVD
  • MBE molecular beam epitaxy
  • PECVD, APCVD, LPCVD, UHCVD, PVD, electron beam method PECVD, APCVD, LPCVD, UHCVD, PVD, electron beam method, It may be deposited and formed by various methods such as resistance heating.
  • the flow rate of the gas injected therein can be determined according to the volume of the MOCVD reaction chamber, and the thin film grown according to the type of gas, the pressure inside the reaction chamber, and the temperature conditions
  • the thickness, surface roughness, doped concentration of the dopant and the like may vary.
  • the higher the temperature the better the crystallinity of the thin film can be obtained, which should be limited in consideration of the physical properties of the reaction gas, the temperature at which the reaction occurs.
  • ALD Atomic layer deposition
  • the thin film growth can be controlled on an atomic basis.
  • a DRAM cell device 100 may include a first gate 30 surrounded by a substrate 10 on which a first insulating layer 20 is formed and a first insulating layer 20. ), The hole storage body 40 formed on the first gate 30, the main body 45 formed on the hole storage body 40, the sources 42 formed on both sides of the main body 45, and The drain 48 and the second gate 60 formed on the main body 45 are included.
  • a first gate insulating layer 35 is formed between the first gate 30 and the hole storage body 40, and the second gate 60 is formed.
  • the second gate insulating layer 65 may be formed between the main body 45 and the main body 45.
  • a second insulating layer 25 may be formed on upper surfaces of the first gate insulating layer 35 and the first insulating layer 20.
  • a first insulating layer 20 is formed on a substrate 10 to a predetermined thickness.
  • the substrate 10 may be formed of any one of silicon, silicon germanium, strained silicon, tensile silicon germanium, silicon carbide, or a group III-V compound.
  • the first insulating layer 20 may include an oxide.
  • the first insulating layer 20 may be a silicon oxide film (SiO 2) or a high dielectric film (a dielectric film having a high dielectric constant (high-k)).
  • patterning and etching of the first gate region 31 may be performed on the upper surface of the first insulating layer 20.
  • the pattern may be a pattern in which a plurality of metal thin films are spaced from 1 to 2 micrometers and their widths are several hundred nanometers each. An etching process is performed in a region where the metal thin film is not formed and the first insulating layer 20 is exposed.
  • the pattern may be formed by sequentially applying a photoresist and an etching process. Specifically, a photoresist is applied on the upper portion of the metal thin film, and the photoresist is exposed to a pattern form through a mask to denature the exposed photoresist and then developed. After development, the portion where the photoresist has been removed may be wet or dry etched to form a final thin film pattern.
  • the first gate region 31 may be formed at the center of the first insulating layer 20.
  • the first gate 30 may be formed by depositing polycrystalline silicon in the first gate region 31, but is not limited thereto, and may include polycrystalline SiGe, polycrystalline Ge, amorphous silicon, amorphous SiGe, or silicide with various metals, Various metal oxides, binary metals such as TaN, TiN, WN and the like can also be used.
  • the first gate 30 may be an n-type polysilicon doped with an n-type dopant or a p-type polysilicon thin film doped with a p-type dopant.
  • the first gate 30 may be formed in the center of the first insulating layer 20 and may be surrounded by the first insulating layer 20.
  • the first gate 30 tunnels holes from the main body 45 to the hole storage body 40 or from the hole storage body 40 to the main body 45 through a current flow between the second gates 60 to be described later. Can be.
  • the top surface of the first gate 30 may be planarized through chemical mechanical polishing.
  • a pattern for applying a voltage to the first gate 30 may be formed in the first insulating layer 20.
  • a first gate insulating layer 35 may be deposited on the top surface of the first gate 30.
  • the first gate insulating layer 35 may be formed of SiO 2, which is an oxide film formed by oxidizing the first gate 30 made of a polysilicon thin film.
  • the first gate insulating layer 35 is configured to insulate the first gate 30 and the hole storage body 40 disposed thereon, and may be located between the first gate 40 and the hole storage body 40. .
  • a second insulating layer 25 may be deposited on the first gate insulating layer 35 and the first insulating layer 20.
  • the second insulating layer 25 may be formed of the same material as the above-described first insulating layer 20 to have a predetermined thickness.
  • the hole storage body region 41 is patterned and etched.
  • the silicon thin film may be grown in the hole storage body region 41 and doped with impurities to form the hole storage body 40.
  • the hole storage body 40 may be positioned concentrically with the first gate 30 and may be stacked on the first gate 30 so as to be perpendicular to the first gate insulating layer 35.
  • the hole-storage bodies (40) are P-type impurity high concentration doping layer may be a (P + regions, for example, doping concentration is 5 ⁇ 10 18 cm 3).
  • the hole storage body 40 may have the same width as the main body 45.
  • the upper surface of the hole storage body 40 may be planarized to have a thickness corresponding to the neighboring second insulating layer 25 through chemical mechanical polishing.
  • the silicon thin film 50 is grown to a predetermined thickness on the upper surface of the second insulating layer 25 and the hole storage body 40.
  • the dopants are doped to form a main body and a source 42 and a drain 48 on both sides of the main body 45 in the silicon thin film 50.
  • the source 42 and drain 48 is N-type impurity highly doped layer (N + regions, such as the doping concentration is 5 ⁇ 10 18 cm - 3) may be a main body (45) is P-type impurity low concentration doping may be -: (3 1 ⁇ 10 15 cm P- type region, for example, doping density) layer. That is, the hole storage body 40 may be a P-type impurity doping layer (P + region) doped at a higher concentration than the main body 45. In this case, the source 42 and the drain 48 are coplanar with the main body 45, and only the main body 45 except the source 42 and the drain 48 is the upper portion of the hole storage body 40. It may be formed to be stacked perpendicular to the.
  • the main body 45, the source 42, the drain 48 and the hole storage body 40 are each region according to the storage means (hole or electron) of the hole storage body 40 All may be formed in the opposite type.
  • the source 42 and the drain 48 may have a P-type impurity high concentration doping layer (P + type region)
  • the main body 45 may have an N-type impurity low concentration doping layer (N-type region)
  • the hole storage body 40 silver may be formed of an N-type impurity high concentration doping layer (N + type region), respectively.
  • a second gate insulating layer 65 is deposited on the upper surface of the main body 45.
  • a second gate 60 is formed on the top surface of the second gate insulating layer 65, and respective contact metals 43 and 49 are deposited on the top surface of the source 42 and the drain 48.
  • first gate 30, the hole storage body 40, the main body 45, and the second gate 60 may be formed to be concentric.
  • the contact metal 43 (or source metal) of the source 42 may electrically connect the external element and the source 42.
  • the source metal 43 may be made of a metal such as titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au) to form an ohmic contact with the source 42.
  • the ohmic contact is a non-rectified or ohmic contact, and the I-V curve follows the general Ohm's law.
  • the drain 48 is disposed at a predetermined distance from the source 42 via the main body 45, and operates as a passage to allow the carrier supplied from the source 42 to go to an external device to generate a drain current.
  • drain 48 may be doped with an N-type dopant to lower the resistance.
  • the N-type dopant may be Si, Ge, Sn, Se, Te, or the like.
  • the contact metal 49 (or drain metal) of the drain 48 may electrically connect the external element and the drain 48.
  • the drain metal 49 may be formed of metals such as titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au) for ohmic contact with the drain 48. .
  • a passivation oxide film deposition and a post process may be performed.
  • the second gate insulating layer 65 and the second gate 60 may be formed to correspond to the first gate insulating layer 35 and the first gate 30 described above.
  • the first and second gate insulating layers 35 and 65 and the first and second insulating layers 20 and 25 may be formed of an oxide film formed by thermally oxidizing a silicon surface or may be formed by depositing an oxide film.
  • FIG. 3 is a cross-sectional view illustrating a band-to-band tunneling operation principle of a DRAM cell device according to the first embodiment of the present invention illustrated in FIG. 1, and FIG. 4 is a DRAM cell according to the first embodiment of the present invention illustrated in FIG. 3. It is a figure which shows the energy band in the program operation of an element.
  • FIG. 3 illustrates the first gate, the first gate insulating layer, and the hole based on the stacking order of the DRAM cell device according to the first embodiment of the present invention illustrated in FIG. 1 to explain the band-band tunneling operation.
  • Sectional drawing which shows a storage body, a main body / source / drain, a 2nd gate insulating film, and a 2nd gate. 4 is a graph showing energy band diagrams in Y-Y 'and X-X' cross-sections shown in FIG.
  • a program '1' operation of the DRAM cell device 100 may include a first preset in the second gate 60 and the drain 48.
  • a positive voltage is applied and a first negative voltage is applied to the first gate 30
  • the hole of the main body 45 is moved to the hole storage body 40 by the tunneling phenomenon, and thus the hole storage body This can be done by increasing the hole of 40.
  • the programming operation reduces the hole concentration of the P-type main body 45 due to the inter-band tunneling phenomenon (oppositely, the electron concentration of the P-type main body 45 is increased), and XX 'is shown.
  • a phenomenon occurs in which an energy barrier is reduced in the main body 45 (channel region) between the drain 48 and the source 42.
  • the threshold voltage is greatly lowered, and the drain current, which is the current between the drain 48 and the source 42, rises high. Since the program operation is performed based on the band-band tunneling phenomenon, low power, low voltage, and high speed operation are possible. This is because charge transfer through the band-band tunneling effect is generally possible for high-speed movement in a relatively low voltage range compared to drift or diffusion movement.
  • FIG. 5 is a diagram illustrating an energy band in a hold operation of the DRAM cell device according to the first embodiment of the present invention illustrated in FIG. 3.
  • FIG. 5A is an energy band diagram in the hold '1' operation in the YY 'cross-section shown in FIG. 3
  • FIG. 5B is an energy band diagram in the hold' 0 'operation in the YY' cross-section shown in FIG. .
  • the second gate 60 and the drain 48 are grounded or floated, and a first negative voltage is applied to the first gate 30.
  • a second negative voltage preset than the voltage is applied, the hole moved to the hole storage body 40 may be maintained.
  • the hold operation is an operation for maintaining a charge state before confining or removing holes in the hole storage body 40 to perform a read operation to determine a retention time characteristic of the DRAM cell. Therefore, the hold operation is divided into a hold '1' and a hold '0' operation according to programming or erase states, respectively.
  • the first gate 30 applies -0.4 V and the rest is performed.
  • the second gate 60 and the drain 48 perform an operation in a grounded or floating state.
  • holes stored in the hole storage body 40 may be stored and maintained without moving to the main body 45 by the energy band barrier.
  • holes moveable from the main body 45 to the hole storage body 40 by a depletion layer generated between the hole storage body 40 and the main body 45. Can prevent the inflow of
  • the leakage and inflow of holes trapped in the hole storage body 40 may be blocked by blocking the band barrier and the depletion layer. Therefore, the retention time can be increased in the state where the drain current does not flow.
  • FIG. 6A is an energy band diagram in the lead '1' operation in the Y-Y 'cross-section shown in FIG. 3
  • FIG. 7B is an energy band diagram in the lead' 0 'operation in the X-X' cross section shown in FIG.
  • the second gate 60 and the drain 48 are applied with a fourth positive voltage smaller than the third positive voltage.
  • the first gate 30 may be read by sensing a current flowing between the drain 48 and the source 42 according to the increase and decrease of the holes stored in the hole storage body 40.
  • the read operation may be referred to as an operation for reading whether holes are stored in the hole storage body 40.
  • a voltage of 0.2V is applied to the second gate 60 and the first gate 30 is grounded or floated, and then a voltage of 0.2V is applied to the drain 48 and the drain 48 and By sensing the drain current flowing between the sources 43, the storage state of the holes can be read.
  • a read operation according to an embodiment of the present invention may be divided into read '1' and read '0' according to whether or not holes are stored in the charge storage body 40.
  • the hole concentration is lowered.
  • the energy band of the main body 40 is lowered and the drain current increases with the decrease of the threshold voltage.
  • an additional hole storage body may be added in addition to the potential variation caused by the second gate 60.
  • FIG. 8 is a diagram illustrating an energy band in an erase operation of the DRAM cell device according to the first embodiment of the present invention illustrated in FIG. 3. Specifically, FIG. 8 is an energy band diagram in erase (write '0') of the Y-Y 'cross-section shown in FIG.
  • the writing '0' of the DRAM cell device 100 has a second gate grounded or floated, and the first gate 30
  • the set second positive voltage is applied and the drain 48 is applied with a predetermined third positive voltage smaller than the second positive voltage
  • holes in the hole storage body 40 move to the main body 45. Can be performed by reducing the holes of the hole storage body 40.
  • the erase operation is for discharging holes stored in the hole storage body 40 to the main body 45
  • a voltage of 1 V is applied to the first gate 30 and a voltage of 0.5 V is applied to the drain 48. Is applied, and the second gate 60 makes a grounded or floating state.
  • Table 1 below is a table illustrating voltages applied to the first gate 30, the second gate 40, and the drain 48 in the above-described operations of the program, erase, read, and hold, respectively.
  • FIG. 9 is a graph showing the amount of drain current versus time of operations of the DRAM cell device according to the first embodiment of the present invention.
  • FIG. 9A is a graph in which the program operation, the hold operation, the read operation, and the erase operation of the DRAM cell device according to an embodiment of the present invention measure drain current values for 20 nm at a temperature of 300 K.
  • FIG. 9b is a graph measuring the drain current value by increasing only the hold operation time to 100 nm under the same conditions as in FIG. 9a.
  • FIG. 10 is a graph illustrating changes in threshold voltages in a program, erase, and read operation of a DRAM cell device according to the first exemplary embodiment of the present invention shown in FIG. 3, and FIG. 11 is a graph of the present invention shown in FIG. A graph showing a change in current margin according to a hold time after programming of a DRAM cell device according to the first embodiment.
  • the DRAM cell device 100 may perform a program operation, a hold operation, a read operation, and an erase operation.
  • the drain current reduction amount is 50% based on the current margin extracted through simulation, the retention time of 850ms is excellent.
  • the value is about 13 times higher than the 64ms retention time currently suggested by the International Semiconductor Technology (ITRS) roadmap.
  • the hole concentration is lowered, and the energy band of the main body is lowered, thereby increasing the drain current.
  • the hold time is arbitrarily set to a condition of 100 ms, and the magnitude of the drain current for each operation mode is checked.
  • the result can be confirmed to have high reliability even when the hold time is increased. That is, by blocking the band barrier and the depletion layer, the outflow and inflow of the holes trapped in the hole storage body can be blocked as much as possible, so that the retention time can be increased in the state where the drain current does not flow.
  • FIG. 12 is a layered cross-sectional view of a DRAM cell device according to a second embodiment of the present invention
  • FIG. 13 is a layered cross-sectional view of a DRAM cell device according to a third embodiment of the present invention.
  • the following description will focus on the manufacturing process and differences of the DRAM cell device 100 according to the first embodiment of the present invention described above with reference to FIGS. 1 through 11, and the descriptions omitted will be replaced with the above description. Can be.
  • the hole storage body 40a of the DRAM cell device 200 may be formed of a substrate 10 and a first insulating layer on which the first insulating layer 20 is formed. 20, the hole storage body 40a formed on the first gate 30, the hole storage body 40a formed on the first gate 30, the main body 45 and the main body 45 formed on the hole storage body 40a. A source 42 and a drain 48 formed on both sides, and a second gate 60 formed on the main body 45.
  • a first gate insulating layer 35 is formed between the first gate 30 and the hole storage body 40a
  • a second gate insulating layer 65 is formed between the second gate 60 and the main body 45. Can be formed.
  • the main body 45 may be stacked vertically on top of the hole storage body 40a.
  • the main body 45, the hole storage body 40a, and the first gate 30 may be concentric with each other, and the hole storage body 40a may have a larger width than the main body 45.
  • the source 42, the drain 48, and the main body 45 may all be stacked vertically on top of the hole storage body 40a, and the width of the hole storage body 40a may be the source 42, the drain. 48 and the main body 45 may be equal to the sum of the widths.
  • the first gate 30 may have a smaller width than the hole storage body 40a and may have the same width as the main body 45 and the second gate 60.
  • the first gate 31b of the DRAM cell device 300 according to the third exemplary embodiment of the present invention may be formed to have the same width as the hole storage body 41a.
  • the various embodiments of the present invention described above are examples showing that the widths of the first gates 30 and 30b and the hole storage bodies 40 and 40a may be changed. That is, the DRAM cell devices 100, 200, and 300 of the present invention may be satisfied only when the hole storage bodies 40 and 40a and the first gates 30 and 31b are formed under the main body 45. Their relationship is not limited to this.
  • the mask used in the port lithography process may be integrated and used, thereby reducing the production cost thereof.
  • the first gates 30 and 30b may have a width larger than that of the main body 45 and smaller than the hole storage bodies 40 and 40a, and the hole storage bodies 40 and 40a may be the main body (not shown). It is also possible to form an area smaller than both ends of the source 42 and the drain 48 respectively positioned on both sides of the 45.
  • the DRAM cell devices 100, 200, and 300 described in the embodiments of the present invention may deposit only the first insulating layers 20 and 20b by omitting deposition of the second insulating layers 25, 25a and 25b. Thereafter, the first gates 30 and 30b, the first gate insulating layer 35, and the hole storage bodies 40 and 40a may be sequentially formed. In addition, when the second insulating layers 25, 25a and 25b are formed, the deposition process of the first gate insulating layer 35 may be omitted. In addition, the width of each region may vary if the first gate can generate vertical tunneling between the hole storage body and the main body.
  • FIG. 14 is a flowchart illustrating a method of manufacturing a DRAM cell device according to the first to third embodiments of the present invention.
  • a dummy silicon oxide is deposited on a silicon substrate (S100), and a first gate is formed by using a patterning and polysilicon deposition process (S200).
  • an additional dummy silicon oxide film and a first gate insulating film are deposited (S300), and a hole storage body is formed through a silicon thin film growth process and an impurity doping (S400).
  • the first gate may be formed to have a width equal to or smaller than that of the hole storage body.
  • the silicon thin film is further grown, and impurities are doped in the source, main body, and drain regions (S500).
  • the hole storage body may be formed to have the same or larger width as the main body.
  • a second gate is formed on the main body to form a second gate, and a DRAM cell device may be provided by depositing a source and a drain contact metal (S600).
  • a series of processes after forming the hole storage body in the manufacturing process of the DRAM cell device of the present invention through the process of manufacturing a conventional silicon MOSFET (Metal Oxide Silicon Field Effect transistor) final DRAM cell device Can be prepared.
  • This process can be integrated into existing Complementary Metal-Oxide Semiconductor (CMOS) processes to reduce production costs.
  • CMOS Complementary Metal-Oxide Semiconductor
  • a separate group III-V compound semiconductor material may be added to the present invention in the form of a single junction, a homojunction, or a heterojunction. You can also apply.
  • the DRAM cell device using the N-channel MOSFET structure may be implemented through a symmetrical structure.
  • the basic principle and operation of the DRAM cell device having the symmetrical structure may be the same as described above, but the current characteristics and the voltage application characteristics may be different.
  • Various embodiments of the present invention may provide a DRAM cell device using one transistor without a capacitor.
  • the DRAM cell device of the present invention may perform a programming operation to distinguish '1' from '0' by using a band-to-band tunneling phenomenon of holes generated from the P-type main body to the lower P + type hole storage body. This tunneling phenomenon enables low power, low voltage, and high speed operation during programming, and additionally, retention time can be increased because the leakage of holes due to the energy barrier in the hold operation is blocked.
  • the upper portion of the hole storage body of the DRAM cell device can be integrated into a general silicon-based CMOS process forming a MOSFET, so that the advantages of price competitiveness and process technology compatibility Advantages over conventional DRAM cell devices.
  • FIG. 15 is a cross-sectional view illustrating a DRAM cell device according to a fourth embodiment of the present invention
  • FIG. 16 is a layered cross-sectional view illustrating a fabrication process of a DRAM cell device according to a fourth embodiment of the present invention.
  • the charge storage region described below may be referred to as a region including a hole storage body and a first gate, and a junctionless field-effect transistor (JLFET) region is formed on the charge storage region.
  • JLFET junctionless field-effect transistor
  • This may mean a region including a source, a drain, a main body, and a second gate.
  • no junction may mean that there is no pn junction due to the formation of a source, a drain, and a main body having different conductivity types in a field effect transistor structure (MOSFET).
  • MOSFET field effect transistor structure
  • the DRAM cell device 400 may include a first gate 30 surrounded by a substrate 10 on which the first insulating layer 20 is formed and the first insulating layer 20. ), A hole storage body 40 formed on the first gate 30, a main body 450 formed on the hole storage body 40, a source 420 formed on both sides of the main body 450, and The drain 480 and the second gate 60 formed on the main body 450 are included.
  • a first gate insulating layer 35 is formed between the first gate 30 and the hole storage body 40, and the second gate 60 is formed.
  • the second gate insulating layer 65 may be formed between the main body 45 and the main body 45.
  • a second insulating layer 25 may be formed on upper surfaces of the first gate insulating layer 35 and the first insulating layer 20.
  • the first insulating layer 20 is formed on the substrate 10 to have a predetermined thickness.
  • the substrate 10 may be formed of any one of silicon, silicon germanium, strained silicon, tensile silicon germanium, silicon carbide, or a group III-V compound.
  • the first insulating layer 20 may include an oxide.
  • the first insulating layer 20 may be a silicon oxide film (SiO 2) or a high dielectric film (a dielectric film having a high dielectric constant (high-k)).
  • patterning and etching of the first gate region 31 may be performed on the upper surface of the first insulating layer 20.
  • the pattern may be a pattern in which a plurality of metal thin films are spaced from 1 to 2 micrometers and their widths are several hundred nanometers each. An etching process is performed in a region where the metal thin film is not formed and the first insulating layer 20 is exposed.
  • the pattern may be formed by sequentially applying a photoresist and an etching process. Specifically, a photoresist is applied on the upper portion of the metal thin film, and the photoresist is exposed to a pattern form through a mask to denature the exposed photoresist and then developed. After development, the portion where the photoresist has been removed may be wet or dry etched to form a final thin film pattern.
  • the first gate region 31 may be formed at the center of the first insulating layer 20.
  • the first gate 30 may be formed by depositing polycrystalline silicon in the first gate region 31, but is not limited thereto, and may include polycrystalline SiGe, polycrystalline Ge, amorphous silicon, amorphous SiGe, or silicide with various metals, Various metal oxides, binary metals such as TaN, TiN, WN and the like can also be used.
  • the first gate 30 may be an n-type polysilicon doped with an n-type dopant or a p-type polysilicon thin film doped with a p-type dopant.
  • the first gate 30 may be formed in the center of the first insulating layer 20 and may be surrounded by the first insulating layer 20.
  • the first gate 30 tunnels holes from the main body 45 to the hole storage body 40 or from the hole storage body 40 to the main body 45 through a current flow between the second gates 60 to be described later. Can be.
  • the top surface of the first gate 30 may be planarized through chemical mechanical polishing.
  • a pattern for applying a voltage to the first gate 30 may be formed in the first insulating layer 20.
  • a first gate insulating layer 35 may be deposited on the top surface of the first gate 30.
  • the first gate insulating layer 35 may be formed of SiO 2, which is an oxide film formed by oxidizing the first gate 30 made of a polysilicon thin film.
  • the first gate insulating layer 35 is configured to insulate the first gate 30 and the hole storage body 40 disposed thereon, and may be located between the first gate 40 and the hole storage body 40. .
  • a second insulating layer 25 may be deposited on the first gate insulating layer 35 and the first insulating layer 20.
  • the second insulating layer 25 may be formed of the same material as the above-described first insulating layer 20 to have a predetermined thickness.
  • the hole storage body region 41 is patterned and etched.
  • the silicon thin film may be grown in the hole storage body region 41 and doped with impurities to form the hole storage body 40.
  • the hole storage body 40 may be positioned concentrically with the first gate 30 and may be stacked on the first gate 30 so as to be perpendicular to the first gate insulating layer 35.
  • the hole-storage bodies (40) are P-type impurity high concentration doping layer may be a (P + regions, for example, doping concentration is 5 ⁇ 10 18 cm 3).
  • the upper surface of the hole storage body 40 may be planarized to have a thickness corresponding to the neighboring second insulating layer 25 through chemical mechanical polishing.
  • an active layer 410 doped with impurities of the same type is formed on the top surface of the second insulating layer 25 and the hole storage body 40.
  • the active layer 410 is N-type impurity highly doped layer (N + type region, for example, the doping concentration: 5 ⁇ 10 18 cm - 3 ) may be a hole storage body is P-type impurity highly doped layer (P + type Regions, for example, doping concentration: 5 ⁇ 10 18 cm ⁇ 3 ).
  • N-type impurities may be arsenic (As), phosphorus (P), bismuth (Bi), antimony (Sb), or the like, and may be used alone or in combination of two or more.
  • each region may be formed in the opposite type.
  • the active layer 410 may be formed of a P-type impurity high concentration doping layer (P + type region), and the hole storage body may be an N-type impurity high concentration doping layer (N + type region).
  • the P-type impurities may be aluminum (Al), boron (B), indium (In), gallium (Ga), or the like, and these may be used alone or in combination of two or more thereof.
  • the active layer 410 may be implanted with the same concentration of impurities of the same type as a whole. Impurity implantation may be optimized by varying ionization energy so that the active layer 410 may be uniformly implanted with impurities having substantially the same polarity from bottom to top.
  • a rapid annealing process at a temperature of 900 to 1100 degrees may be additionally performed so that impurities injected into the active layer 410 may be uniformly spread in the active layer.
  • the second gate insulating layer 65 is deposited on the upper surface of the main body 45.
  • a second gate 60 is formed on the top surface of the second gate insulating layer 65, and respective contact metals 43 and 49 are deposited on the top surface of the source 42 and the drain 48.
  • the contact metal 43 (or source metal) of the source 42 may electrically connect the external element and the source 42.
  • the source metal 43 may be made of a metal such as titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au) to form an ohmic contact with the source 42.
  • the ohmic contact is a non-rectified or ohmic contact, and the I-V curve follows the general Ohm's law.
  • a passivation oxide film deposition and a post process may be performed.
  • the second gate insulating layer 65 and the second gate 60 may be formed to correspond to the first gate insulating layer 35 and the first gate 30 described above.
  • the first and second gate insulating layers 35 and 65 and the first and second insulating layers 20 and 25 may be formed of an oxide film formed by thermally oxidizing a silicon surface or may be formed by depositing an oxide film.
  • the DRAM cell device includes a charge storage region including a hole storage body and a first gate, and a source, a drain, a main body, and a second gate formed on the static storage region. It may include a junctionless field effect transistor (JLFET) region.
  • JLFET junctionless field effect transistor
  • FIG. 17 is a cross-sectional view illustrating a band-to-band tunneling principle of a DRAM cell device in accordance with a fourth embodiment of the present invention illustrated in FIG. 15, and FIG. 18 is a DRAM cell according to a fourth embodiment of the present disclosure illustrated in FIG. 17.
  • FIG. 19 is a diagram illustrating an energy band in a program operation of the device, and FIG. 19 is a diagram illustrating an energy band in the hold operation of the DRAM cell device according to the fourth embodiment of the present invention illustrated in FIG. 17.
  • 20 and 21 are views illustrating energy bands in a read operation of the DRAM cell device according to the fourth embodiment of the present invention illustrated in FIG. 17, and FIG. 22 is a fourth embodiment of the present invention illustrated in FIG. 17. Shows an energy band in an erase operation of a DRAM cell device according to the present invention.
  • Table 2 below is a table illustrating a voltage application of the DRAM device according to the fourth embodiment of the present invention.
  • the operation of the DRAM cell device according to the voltage application example of Table 2 will be described with reference to FIGS. 17 to 25.
  • FIGS. 17, 18A, and 18B correspond to FIGS. 3, 4A, and 4B, descriptions thereof will be omitted.
  • 18C is a diagram illustrating the principle of interband tunneling operation. Referring to FIG. 18C, it can be seen that the depletion layer 490 is reduced and the main body 450 is increased through FIGS. 18A and 18B.
  • FIG. 22A is an energy band diagram in erase (write '0') of the Y-Y 'cross-section shown in FIG. 17, and FIG. 22B is a diagram showing the principle of interband tunneling operation.
  • the erase operation of the DRAM cell device is for discharging holes stored in the P + type hole storage body to the N + type body region, a positive voltage (eg, 1.5 V) and a small amount of voltage (e.g., 1 V) is applied to the drain and the second gate is grounded or floated.
  • a positive voltage eg, 1.5 V
  • a small amount of voltage e.g., 1 V
  • the energy band of the P + type hole storage region is lowered and the energy band of the N + type body region is increased by applying a voltage, an energy barrier that limits the movement of holes previously formed is reduced. Accordingly, the holes stored in the P + type hole storage region are discharged to the N + type body region by the drift phenomenon. The holes moved to the N + type body region are then moved to the source due to the characteristics of the JLFET where the source, drain, and main body have the same impurity doping concentration. On the contrary, electrons present in the source are introduced into the main body by the drain current. do.
  • This phenomenon which can be seen in FIG. 22B, may cause a high increase in the electron concentration of the N + type main body 450. Accordingly, the depletion layer 490 may be reduced to increase the main body channel.
  • FIG. 23A is a graph in which the program operation, the hold operation, the read operation, and the erase operation of the DRAM cell device according to the fourth embodiment of the present invention measure drain current values for 10 nm time at a temperature of 300 K
  • FIG. 23A is a graph measuring the drain current value by increasing only the hold operation time to 100 nm under the same conditions as in FIG. 23A.
  • FIG. 24 is a graph illustrating changes in threshold voltages in a program, erase, and read operation of a DRAM cell device according to a fourth exemplary embodiment of the present invention shown in FIG. 17.
  • FIG. 25 is a graph of the present invention shown in FIG. A graph showing a change in current margin according to a hold time after programming of a DRAM cell device according to a fourth embodiment.
  • the read operation may be divided into read '1' and read '0' according to whether or not holes are stored in the charge storage region. For example, in the case where holes are stored in the charge storage region ('1', in the case of a programmed 1T-DRAM cell), the hole concentration of the N + type body region is lowered by the holes stored in the P + type hole storage region. In this state, the energy band of the N + type body region is lowered, and the drain current increases with the decrease of the threshold voltage.
  • drain current which is a current between the drain region and the source region. current
  • 26 is a flowchart illustrating a method of manufacturing a DRAM cell device according to a fourth embodiment of the present invention.
  • a dummy silicon oxide is deposited on a silicon substrate (S1000), and a first gate is formed by using a patterning and polysilicon deposition process (S2000).
  • the first gate may be formed to have a width equal to or smaller than that of the hole storage body.
  • an active layer of a silicon thin film doped with the same conductivity type without forming a separate source and drain regions is formed (S5000).
  • a second gate is formed on the main body to form a second gate, and a DRAM cell device may be provided by depositing a source and a drain contact metal (S6000).
  • the source, the main body, and the drain are all made of the same doping concentration, current flows to the main body. Therefore, the bulk current flowing into the body bulk region rather than the channel current formed at the gate bottom of the conventional MOSFET is a key part of the transistor operation.

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Abstract

L'invention concerne un dispositif de cellule DRAM et son procédé de fabrication. Le dispositif de cellule DRAM selon l'invention comprend : un substrat ayant une couche d'isolation; une première grille entourée par la couche d'isolation; un premier film d'isolation de grille formé sur la première grille; un corps principal situé sur une partie supérieure du premier film d'isolation de grille; une source et un drain respectivement formés sur les deux côtés du corps principal; un second film d'isolation de grille formé sur le corps principal; une seconde grille formée sur le second film d'isolation de grille; et un corps de stockage de trous formé entre le corps principal et le premier film d'isolation de grille et stockant des trous par tunnelisation à partir du corps principal.
PCT/KR2018/000946 2017-01-23 2018-01-22 Dispositif de cellule dram et son procédé de fabrication Ceased WO2018135914A1 (fr)

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