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WO2018129932A1 - 移位寄存器单元电路及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元电路及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2018129932A1
WO2018129932A1 PCT/CN2017/099871 CN2017099871W WO2018129932A1 WO 2018129932 A1 WO2018129932 A1 WO 2018129932A1 CN 2017099871 W CN2017099871 W CN 2017099871W WO 2018129932 A1 WO2018129932 A1 WO 2018129932A1
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WIPO (PCT)
Prior art keywords
potential
node
terminal
transistor
circuit
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PCT/CN2017/099871
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English (en)
French (fr)
Inventor
樊君
李伟
李付强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US15/756,975 priority Critical patent/US10706767B2/en
Publication of WO2018129932A1 publication Critical patent/WO2018129932A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to generation of a gate drive signal, and more particularly to a shift register unit circuit, a driving method for the shift register unit circuit, a gate driving circuit, and a display device.
  • a shift register including a plurality of cascaded shift register unit circuits can operate as a gate drive circuit of the display panel.
  • high temperature conditions eg, 70-85 ° C
  • the leakage current of certain transistors in the shift register cell circuit may increase significantly, for example, relative to an increase of 2 to 3 orders of magnitude at room temperature. This can result in a large change in the potential of some internal nodes, and thus a deterioration in the output gate drive signal.
  • the display panel has poor high temperature reliability.
  • a shift register unit circuit comprising: an input circuit configured to supply an effective potential from a first scan level terminal to a first node in response to an input pulse from an input being active, And supplying an inactive potential from the second scan level terminal to the first node in response to the reset pulse from the reset terminal being active; the output circuit being configured to be from the first clock in response to the second node being at the active potential a first clock signal of the terminal is supplied to the output terminal, and a potential of the second node is changed from the effective potential to further away from the potential of the output terminal to jump to the effective potential An invalid potential; and a potential control circuit configured to limit a change in a potential of the first node caused by the transition of the potential of the output terminal from an inactive potential to an active potential.
  • the potential control circuit is configured to cause the first node to be non-conducting with the second node in response to a change in potential of the second node exceeding a threshold.
  • the potential control circuit includes a first control transistor having a gate coupled to the potential control terminal, a first electrode coupled to the first node, and a connection To the second electrode of the second node.
  • the first control transistor is configured to be turned on in response to a control signal from the potential control terminal being active, and turned off in response to the change in potential of the second node exceeding the threshold.
  • the first node is directly connected to the second node
  • the potential control circuit includes a second capacitor coupled to the second node and a first one for supplying the reactive potential Between the reference levels.
  • the potential control circuit is further configured to supply an effective potential from the second reference level terminal to the second scan level terminal in response to the output being at the active potential.
  • the potential control circuit further includes a second control transistor having a gate connected to the output, a first electrode connected to the second reference level terminal, and a second to Scan the second electrode at the level end.
  • the input circuit includes: a first transistor having a gate connected to the input, a first electrode connected to the first node, and a first connected to the first scan level end a second electrode; and a second transistor having a gate connected to the reset terminal, a first electrode connected to the second scan level terminal, and a second electrode connected to the first node.
  • the output circuit includes: a third transistor having a gate connected to the second node, a first electrode connected to the output, and a second electrode connected to the first clock terminal And a first capacitor connected between the second node and the output.
  • the output circuit is further configured to supply the inactive potential from the first reference level terminal to the output terminal in response to the third node being at the active potential.
  • the output circuit further includes a fourth transistor having a gate connected to the third node, a first electrode connected to the first reference level terminal, and a connection to the output terminal Second electrode.
  • the shift register unit circuit further includes a node control circuit configured to set the third node at the inactive potential in response to the second node being at the active potential, And setting the third node at the effective potential in response to the second node being at the inactive potential.
  • the node control circuit includes: a sixth transistor having a connection a gate connected to the second node, a first electrode connected to the first reference level terminal, and a second electrode connected to the third node; a seventh transistor having a connection to supply for a gate of a second clock end of the second clock signal of the opposite phase of the first clock signal, a first electrode connected to the third node, and a second electrode connected to the second clock terminal; and a third capacitor Connected between the third node and the first reference level terminal.
  • the node control circuit is further configured to set the second node at the inactive potential in response to the third node being at the active potential.
  • the node control circuit further includes a fifth transistor having a gate connected to the third node, a first electrode connected to the second node, and connected to the first reference The second electrode at the level end.
  • a method of driving a shift register unit circuit as described above includes supplying an effective potential from the first scan level terminal to the first node in response to an input pulse from the input being active; responsive to the second node being at the active potential a first clock signal from the first clock terminal is supplied to the output terminal; causing a potential of the second node to be from the effective potential in response to the output terminal transitioning from the inactive potential to being at the active potential Changing to further away from the inactive potential; limiting a change in potential of the first node caused by the transition of the potential of the output from an inactive potential to an active potential; and in response to a reset pulse from the reset terminal
  • the effective potential from the second scan level terminal is supplied to the first node.
  • a gate driving circuit including a plurality of cascaded shift register unit circuits as described above is provided.
  • a display device comprising the gate drive circuit as described above.
  • 1 is a circuit diagram of a portion of a typical shift register unit circuit
  • FIG. 2 is a block diagram of a shift register unit circuit in accordance with an embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of an example circuit of the shift register unit circuit shown in FIG. 2;
  • FIG. 4 is an example timing diagram for an example circuit as shown in FIG. 3;
  • Figure 5 is a circuit diagram of another example circuit of the shift register unit circuit shown in Figure 2;
  • FIG. 6 is an example timing diagram for an example circuit as shown in FIG. 5;
  • FIGS. 7A and 7B are block diagrams of gate drive circuits in different scan modes, in accordance with an embodiment of the present disclosure.
  • FIG. 8 is a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • FIG. 1 is a circuit diagram of a portion of a typical shift register unit circuit. How the performance of the shift register unit circuit is affected by high temperature conditions will be described below with reference to FIG.
  • the circuit portion includes a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor C1.
  • a high level voltage from the first scan level terminal CN is supplied to the pull-up node PU through the first transistor T1, and the third transistor T3 is turned on.
  • the turned-on third transistor T3 transmits a clock signal from the clock terminal CLK to the output terminal OUT such that the potential of the output terminal OUT changes as the clock signal changes.
  • the potential of the output terminal OUT transitions from a low level to a high level, the potential at the pull-up node PU is further raised due to the bootstrap effect of the capacitor C1.
  • Vgs the gate-source voltage
  • Vds the drain-source voltage
  • the shift register unit circuit 200 includes an input circuit 210, an output circuit 220, a potential control circuit 230, and a node control circuit 240.
  • the input circuit 210 is configured to supply an effective potential from the first scan level terminal CN to the first node N1 in response to the input pulse from the input terminal IN being active.
  • the input circuit 210 is also configured to supply an inactive potential from the second scan level terminal CNB to the first node N1 in response to the reset pulse from the reset terminal RST being active.
  • the output circuit 220 is configured to supply a first clock signal from the first clock terminal CLK to the output terminal OUT in response to the second node N2 being at an active potential.
  • the output circuit 220 is also configured to cause the potential of the second node N2 to be changed from the effective potential to further away from the inactive potential in response to the potential of the output terminal OUT transitioning from the inactive potential to the active potential.
  • the potential control circuit 230 is configured to limit a change in the potential of the first node N1 caused by the jump of the potential of the output terminal OUT from the inactive potential to the effective potential. As will be discussed later, this can suppress leakage current flowing from the first node N1 in the circuit, and thus improve the performance of the shift register unit circuit 200 under high temperature conditions.
  • the node control circuit 240 as indicated by the dashed box is less closely related to the inventive concept of the present disclosure and will be described later.
  • the term "effective potential” as used herein refers to the potential at which the circuit component (eg, transistor) involved is enabled.
  • the term “invalid potential” refers to the potential at which the circuit components involved are disabled.
  • the effective potential is high and the inactive potential is low.
  • the effective potential is low and the inactive potential is high.
  • FIG. 3 is a circuit diagram of an example circuit 200A of shift register unit circuit 200 as shown in FIG. 2. An example configuration of the shift register unit circuit 200 will be described below with reference to FIG.
  • the input circuit 210 includes a first transistor T1 and a second transistor T2.
  • the first transistor T1 has a gate connected to the input terminal IN, a first electrode connected to the first node N1, and a second electrode connected to the first scan level terminal CN.
  • the second transistor T2 has a gate connected to the reset terminal RST, a first electrode connected to the second scan level terminal CNB, and a second electrode connected to the first node N1.
  • the output circuit 220 includes a third transistor T3 and a first capacitor C1.
  • the third transistor T3 has a gate connected to the second node N2, a first electrode connected to the output terminal OUT, and a second electrode connected to the first clock terminal CLK.
  • the first capacitor C1 is connected between the second node N2 and the output terminal OUT.
  • the output circuit 220 is further configured to supply an inactive potential from the first reference level terminal VGL to the output terminal OUT in response to the third node N3 being at an active potential.
  • the output circuit 220 further includes a fourth transistor T4 having a gate connected to the third node N3, a first electrode connected to the first reference level terminal VGL, and being connected to the output terminal OUT.
  • the second electrode is a fourth transistor T4 having a gate connected to the third node N3, a first electrode connected to the first reference level terminal VGL, and being connected to the output terminal OUT.
  • the potential control circuit 230 is configured to cause the first node N1 and the second node N2 to bring out of conduction in response to the change in the potential of the second node N2 exceeding a threshold.
  • the potential control circuit 230 includes a first control transistor TK1 having a gate connected to the potential control terminal PCN, a first electrode connected to the first node N1, and a second electrode connected to the second node N2.
  • the first control transistor TK1 is configured to be turned on in response to the control signal from the potential control terminal PCN being active.
  • the first control transistor TK1 is also configured to be turned off in response to the change in the potential of the second node N2 exceeding the threshold.
  • the node control circuit 240 is configured to set the third node N3 to be in an inactive potential in response to the second node N2 being at an active potential, and to be inactive in response to the second node N2
  • the third node N3 is set to be at an effective potential.
  • the node control circuit 240 includes a sixth transistor T6, a seventh transistor T7, and a third capacitor C3.
  • the sixth transistor T6 has a gate connected to the second node N2, a first electrode connected to the first reference level terminal VGL, and a second electrode connected to the third node N3.
  • the seventh transistor T7 has a gate connected to a second clock terminal CLKB for supplying a second clock signal having an opposite phase to the first clock signal, a first electrode connected to the third node N3, and a second clock connected thereto The second electrode of terminal CLKB.
  • the third capacitor C3 is connected between the third node N3 and the first reference level terminal VGL.
  • node control circuit 240 is further configured to set second node N2 to an inactive potential in response to third node N3 being at an active potential.
  • the node control circuit 240 further includes a fifth transistor T5 having a gate connected to the third node N3, a first electrode connected to the second node N2, and being connected to the first reference The second electrode of the flat end VGL.
  • FIG. 4 is an example timing diagram for an example circuit 200A as shown in FIG. The operation of the example circuit 200A of FIG. 3 is described below with reference to FIG. Hereinafter, a high level is indicated by 1 and a low level is indicated by 0. It is also assumed that the first scan level terminal CN supplies a high level voltage, and the second scan level terminal CNB and the first reference level terminal VGL supply a low level voltage.
  • the sixth transistor T6 and the seventh transistor T7 are designed such that the equivalent resistance of the sixth transistor T6 is much smaller than the equivalent resistance of the seventh transistor T7.
  • the third node N3 is set to be at an inactive potential. Since the first node N1 is at the effective potential, the third transistor T3 is turned on, and the invalid clock signal from the first clock terminal CLK is transmitted to the output terminal OUT.
  • Vds is reduced by approximately one time, greatly reducing the leakage current flowing through the second transistor T2. Therefore, the potential of the second node N2 is less affected by the leakage current, so that the output terminal OUT can output a normal pulse signal.
  • the third node N3 is set to the effective potential, and the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the turned-on fourth transistor T4 transmits a low level voltage from the first reference level terminal VGL to the output terminal OUT, so that the output terminal OUT outputs an inactive level signal.
  • the first capacitor C1 keeps the first node PU at an inactive potential
  • the third capacitor C3 keeps the third node N3 at an effective potential. Since the third node N3 is at an effective potential, the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the turned-on fifth transistor T5 transmits a low level voltage from the first reference level terminal VGL to the first node N1, ensuring that the first node N1 is at an inactive potential.
  • the turned-on fourth transistor T4 transmits a low level voltage from the first reference level terminal VGL to the output terminal OUT, ensuring that the output terminal OUT outputs an inactive level signal.
  • FIG. 5 is a circuit diagram of another example circuit 200B of shift register unit circuit 200 as shown in FIG. 2.
  • Input circuit 210, output circuit 220, and node control circuit 240 The configuration is the same as those described above with respect to FIG. 3 and will not be repeated here.
  • the first node N1 is directly connected to the second node N2 without the first control transistor TK1 being connected therebetween.
  • the potential control circuit 240 includes a second capacitor C2 connected between the second node N2 and the first reference level terminal VGL for supplying an ineffective potential.
  • the second capacitor C2 is operable to maintain the potential of the first node N1 stable when the potential of the second node N2 jumps due to the bootstrap effect of the first capacitor C1. This is because the second capacitor C2 is connected in series with the first capacitor C1, and thus the voltage jump across the first capacitor C1 can be shared.
  • the variation of the potential of the first node N1 is limited such that the drain-source voltage Vds of the second transistor T2 is reduced compared to the second capacitor C2 otherwise, thereby reducing the leakage flowing through the second transistor T2.
  • the current and in turn, contributes to the stabilization of the potential of the first node N1. This can improve the reliability of the example circuit 200B under high temperature conditions.
  • the potential control circuit 240 can also be configured to supply an effective potential from the second reference level terminal VGH to the second scan level terminal CNB in response to the output terminal OUT being at an active potential.
  • the potential control circuit 240 further includes a second control transistor TK2 having a gate connected to the output terminal OUT, a first electrode connected to the second reference level terminal VGH, and connected to the second Scanning the second electrode CNB at the level end.
  • FIG. 6 is an example timing diagram for an example circuit as shown in FIG. 5.
  • the operation of the example circuit 200B of FIG. 5 is described below with reference to FIG.
  • a high level is indicated by 1
  • a low level is indicated by 0.
  • the first scan level terminal CN and the second reference level terminal VGH supply a high level voltage
  • the second scan level terminal CNB and the first reference level terminal VGL supply a low level voltage.
  • the potential of the second node N2 (equivalently, the first node N1) is further pulled high. Due to the presence of the second capacitor C2, the rise in the potential of the first node N1 is limited, thereby reducing the leakage current flowing through the second transistor T2.
  • the first capacitor C1 keeps the first node PU at an inactive potential
  • the third capacitor C3 keeps the third node N3 at an effective potential. Since the third node N3 is at an effective potential, the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the turned-on fifth transistor T5 transmits a low level voltage from the first reference level terminal VGL to the first node N1, ensuring that the first node N1 is at an inactive potential.
  • the turned-on fourth transistor T4 transmits a low level voltage from the first reference level terminal VGL to the output terminal OUT, ensuring that the output terminal OUT outputs an inactive level signal.
  • the gate driving circuits 700A, 700B each include n The cascaded shift register unit circuits, each of which may be the shift register unit circuit 200 as described above.
  • the n shift register unit circuits are respectively connected to n gate lines G[1], G[2], G[3], ..., G[n-1], and G[n] to supply gates thereto.
  • Pole drive signal. n may be an integer greater than or equal to two.
  • each of the shift register unit circuits is connected to the output terminal OUT of the adjacent previous shift register unit circuit, and except for the nth shift register
  • the reset terminal RST of each of the shift register unit circuits is connected to the output terminal OUT of the adjacent next shift register unit circuit.
  • the input terminal IN of the first shift register unit circuit receives the start signal STV as the input pulse.
  • the reset terminal RST of the nth shift register unit circuit receives the start signal STV as the input pulse.
  • the input terminal IN and the reset terminal RST of the shift register unit circuit are used interchangeably, and the first scan level terminal CN and the second scan level terminal CNB are used interchangeably.
  • the first scan level terminal CN supplies the active level voltage
  • the second scan level terminal CNB supplies the inactive level voltage
  • the input terminal IN and the reset terminal RST are normally used.
  • the reverse scan mode the first scan level terminal CN supplies an inactive level voltage
  • the second scan level terminal CNB supplies an active level voltage.
  • the input terminal IN serves as a "reset terminal”
  • the reset terminal RST serves as an "input terminal".
  • FIG. 8 is a block diagram of a display device 800 in accordance with an embodiment of the present disclosure.
  • the display device 800 includes a display panel 810, a timing controller 820, a gate driving circuit 830, and a data driving circuit 840.
  • Gate drive circuit 830 can be gate drive circuit 700A or 700B as described above with respect to Figures 7A and 7B.
  • the display panel 810 is connected to the plurality of gate lines GL and the plurality of data lines DL.
  • the display panel 810 displays an image having a plurality of gradations based on the output image data RGBD'.
  • the gate line GL may extend in the first direction D1
  • the data line DL may extend in the second direction D2 crossing (eg, substantially perpendicular) to the first direction D1.
  • the display panel 810 may include a plurality of pixels (not shown) arranged in a matrix form. Each of the pixels may be electrically connected to a corresponding one of the gate lines GL and one corresponding one of the data lines DL.
  • the display panel 810 can be a liquid crystal display panel, an organic light emitting diode (OLED) display panel, or other suitable type of display panel.
  • OLED organic light emitting diode
  • the timing controller 820 controls the operations of the display panel 810, the gate drive circuit 830, and the data drive circuit 840.
  • the timing controller 820 receives input image data RGBD and an input control signal CONT from an external device (eg, a host).
  • the input image data RGBD may include a plurality of input pixel data for a plurality of pixels. Each of the input pixel data may include red gradation data R, green gradation data G, and blue gradation data B for a corresponding one of the plurality of pixels.
  • the input control signal CONT may include a main clock signal, a data enable signal, a vertical sync signal, a horizontal sync signal, and the like.
  • the timing controller 720 generates output image data RGBD', a first control signal CONT1, and a second control signal CONT2 based on the input image data RGBD and the input control signal CONT.
  • the gate drive circuit 830 receives the first control signal CONT1 from the timing controller 820.
  • the gate driving circuit 830 generates a plurality of gate signals for driving the gate lines GL based on the first control signal CONT1.
  • the gate driving circuit 830 can sequentially apply a plurality of gate signals to the gate lines GL.
  • the data driving circuit 840 receives the second control signal CONT2 and the output image data RGBD' from the timing controller 820.
  • the data driving circuit 840 generates a plurality of data voltages (e.g., analog data voltages) based on the second control signal CONT2 and the output image data RGBD' (e.g., digital image data).
  • the data driving circuit 840 can apply a plurality of data voltages to the data lines DL.
  • gate drive circuit 830 and/or data drive circuit 840 may be disposed (eg, directly mounted) on display panel 810, or may be by, for example, a Tape Carrier Package (TCP). Connected to display panel 810. In some embodiments, gate drive circuit 830 and/or data drive circuit 840 can be integrated in display panel 810.
  • TCP Tape Carrier Package
  • Examples of display device 800 include, but are not limited to, cell phones, tablets, televisions, displays, notebook computers, digital photo frames, navigators.
  • each transistor is illustrated and described as an n-type transistor, a p-type transistor is possible.
  • the gate-on voltage has a low level
  • the gate-off voltage has a high level.
  • each transistor can be, for example, a thin film transistor that is typically fabricated such that their first and second electrodes are used interchangeably. Other embodiments are also contemplated.

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  • Shift Register Type Memory (AREA)

Abstract

一种移位寄存器单元电路(200,200A,200B)，包括：输入电路(210)，被配置成响应于来自输入端(IN)的输入脉冲有效而将有效电位供应到第一节点(N1)，并且响应于来自复位端(RST)的复位脉冲有效而将无效电位供应到第一节点(N1)；输出电路(220)，被配置成响应于第二节点(N2)处于有效电位而将第一时钟信号供应到输出端(OUT)，并且响应于输出端(OUT)的电位从无效电位跳变到有效电位而引起第二节点(N2)的电位从有效电位被改变为进一步远离无效电位；以及电位控制电路(230)，被配置成限制由输出端(OUT)的电位从无效电位到有效电位的跳变引起的第一节点(N1)的电位的变化。

Description

移位寄存器单元电路及其驱动方法、栅极驱动电路和显示装置 技术领域
本公开涉及栅极驱动信号的生成，尤其涉及一种移位寄存器单元电路、用于该移位寄存器单元电路的驱动方法、栅极驱动电路和显示装置。
背景技术
包括多个级联的移位寄存器单元电路的移位寄存器可以作为显示面板的栅极驱动电路操作。在高温条件(例如，70～85℃)下，移位寄存器单元电路中的某些晶体管的漏电流可能显著增大，例如相对于在室温条件下2～3个数量级的升高。这可以导致一些内部节点的电位的大幅变化，并且因此导致输出的栅极驱动信号的恶化。由此，显示面板具有差的高温信赖性。
发明内容
提供一种可以解决上述问题中的一个或多个的移位寄存器单元电路将是有利的。
根据本公开的一个方面，提供了一种移位寄存器单元电路，包括：输入电路，被配置成响应于来自输入端的输入脉冲有效而将来自第一扫描电平端的有效电位供应到第一节点，并且响应于来自复位端的复位脉冲有效而将来自第二扫描电平端的无效电位供应到所述第一节点；输出电路，被配置成响应于第二节点处于所述有效电位而将来自第一时钟端的第一时钟信号供应到输出端，并且响应于所述输出端的电位从所述无效电位跳变到所述有效电位而引起所述第二节点的电位从所述有效电位被改变为进一步远离所述无效电位；以及电位控制电路，被配置成限制由所述输出端的电位从无效电位到有效电位的所述跳变引起的所述第一节点的电位的变化。
在一些实施例中，所述电位控制电路被配置成响应于所述第二节点的电位的变化超过一阈值而使所述第一节点与所述第二节点不导通。
在一些实施例中，所述电位控制电路包括第一控制晶体管，其具有连接到电位控制端的栅极、连接到第一节点的第一电极、以及连接 到第二节点的第二电极。所述第一控制晶体管被配置成响应于来自所述电位控制端的控制信号有效而被开启，并且响应于所述第二节点的电位的所述变化超过所述阈值而被关断。
在一些实施例中，所述第一节点直接连接到所述第二节点，并且所述电位控制电路包括第二电容器，其连接在所述第二节点与用于供应所述无效电位的第一参考电平端之间。
在一些实施例中，所述电位控制电路还被配置成响应于所述输出端处于所述有效电位而将来自第二参考电平端的有效电位供应到所述第二扫描电平端。
在一些实施例中，所述电位控制电路还包括第二控制晶体管，其具有连接到所述输出端的栅极、连接到所述第二参考电平端的第一电极、以及连接到所述第二扫描电平端的第二电极。
在一些实施例中，所述输入电路包括：第一晶体管，具有连接到所述输入端的栅极、连接到所述第一节点的第一电极、以及连接到所述第一扫描电平端的第二电极；和第二晶体管，具有连接到所述复位端的栅极、连接到所述第二扫描电平端的第一电极、以及连接到所述第一节点的第二电极。
在一些实施例中，所述输出电路包括：第三晶体管，具有连接到所述第二节点的栅极、连接到所述输出端的第一电极、以及连接到所述第一时钟端的第二电极；和第一电容器，连接在所述第二节点与所述输出端之间。
在一些实施例中，所述输出电路还被配置成响应于第三节点处于所述有效电位而将来自第一参考电平端的所述无效电位供应到所述输出端。
在一些实施例中，所述输出电路还包括第四晶体管，其具有连接到所述第三节点的栅极、连接到所述第一参考电平端的第一电极、以及连接到所述输出端的第二电极。
在一些实施例中，所述移位寄存器单元电路还包括节点控制电路，其被配置成响应于所述第二节点处于所述有效电位而将所述第三节点设定处于所述无效电位，并且响应于所述第二节点处于所述无效电位而将所述第三节点设定处于所述有效电位。
在一些实施例中，所述节点控制电路包括：第六晶体管，具有连 接到所述第二节点的栅极、连接到所述第一参考电平端的第一电极、以及连接到所述第三节点的第二电极；第七晶体管，具有连接到用于供应具有与所述第一时钟信号相反相位的第二时钟信号的第二时钟端的栅极、连接到所述第三节点的第一电极、以及连接到所述第二时钟端的第二电极；和第三电容器，连接在所述第三节点与所述第一参考电平端之间。
在一些实施例中，所述节点控制电路还被配置成响应于所述第三节点处于所述有效电位而将所述第二节点设定处于所述无效电位。
在一些实施例中，所述节点控制电路还包括第五晶体管，其具有连接到所述第三节点的栅极、连接到所述第二节点的第一电极、以及连接到所述第一参考电平端的第二电极。
根据本公开的另一方面，提供了一种驱动如上所述的移位寄存器单元电路的方法。所述方法包括：响应于来自所述输入端的输入脉冲有效而将来自所述第一扫描电平端的有效电位供应到所述第一节点；响应于所述第二节点处于所述有效电位而将来自所述第一时钟端的第一时钟信号供应到输出端；响应于所述输出端从处于所述无效电位跳变到处于所述有效电位而引起所述第二节点的电位从所述有效电位被改变为进一步远离所述无效电位；限制由所述输出端的电位从无效电位到有效电位的所述跳变引起的所述第一节点的电位的变化；以及响应于来自所述复位端的复位脉冲有效而将来自所述第二扫描电平端的无效电位供应到所述第一节点。
根据本公开的又另一方面，提供了一种栅极驱动电路，包括多个级联的如上所述的移位寄存器单元电路。
根据本公开的再另一方面，提供了一种显示装置，包括如上所述的栅极驱动电路。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1是一种典型的移位寄存器单元电路中的一部分的电路图；
图2是根据本公开实施例的移位寄存器单元电路的框图；
图3是如图2所示的移位寄存器单元电路的示例电路的电路图；
图4是用于如图3所示的示例电路的示例时序图；
图5是如图2所示的移位寄存器单元电路的另一示例电路的电路图；
图6是用于如图5所示的示例电路的示例时序图；
图7A和7B是根据本公开实施例的栅极驱动电路在不同扫描模式下的框图；并且
图8是根据本公开实施例的显示装置的框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件和/或部分，但是这些元件、部件和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件或部分与另一个元件、部件或部分相区分。因此，下面讨论的第一元件、部件或部分可以被称为第二元件、部件或部分而不偏离本公开的教导。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件被称为“连接到另一个元件”或“耦合到另一个元件”时，其可以直接连接到另一个元件或直接耦合到另一个元件，或者可以存在中间元件。相反，当元件被称为“直接连接到另一个元件”或“直接耦合到另一个元件”时，没有中间元件存在。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
图1是一种典型的移位寄存器单元电路中的一部分的电路图。下面参考图1说明移位寄存器单元电路的性能如何受到高温条件的影响。
如图1所示，该电路部分包括第一晶体管T1、第二晶体管T2、第三晶体管T3以及电容器C1。当输入端IN被施加高电平电压时，来自第一扫描电平端CN的高电平电压通过第一晶体管T1供应到上拉节点PU，并且第三晶体管T3被开启。开启的第三晶体管T3将来自时钟端CLK的时钟信号传送到输出端OUT，使得输出端OUT的电位随着时钟信号变化而变化。当输出端OUT的电位从低电平跳变(transition)至高电平时，上拉节点PU处的电位由于电容器C1的自举效应而进一步升高。此时，对于第二晶体管T2可以有典型的工作状况：Vgs＝0V和Vds＝28V，其中Vgs为栅-源电压，并且Vds为漏-源电压。在这种情况下，存在从上拉节点PU通过第二晶体管T2流到第二扫描电平端CNB的漏电流，进而导致上拉节点PU处的电位下降。这可以引起输出端OUT输出的脉冲信号的恶化，例如下降沿变得不陡峭。特别地，在高温条件(例如，70～85℃)下，由于晶体管的特性变化，第二晶体管T2的漏电流比起室温条件下可以升高2～3个数量级。这可以引起输出端OUT输出的脉冲信号的相当明显的恶化。
图2是根据本公开实施例的移位寄存器单元电路200的框图。参考图2，移位寄存器单元电路200包括输入电路210、输出电路220、电位控制电路230和节点控制电路240。
输入电路210被配置成响应于来自输入端IN的输入脉冲有效而将来自第一扫描电平端CN的有效电位供应到第一节点N1。输入电路210还被配置成响应于来自复位端RST的复位脉冲有效而将来自第二扫描电平端CNB的无效电位供应到第一节点N1。
输出电路220被配置成响应于第二节点N2处于有效电位而将来自第一时钟端CLK的第一时钟信号供应到输出端OUT。输出电路220还被配置成响应于输出端OUT的电位从无效电位跳变到有效电位而引起第二节点N2的电位从有效电位被改变为进一步远离无效电位。
电位控制电路230被配置成限制由输出端OUT的电位从无效电位到有效电位的所述跳变引起的第一节点N1的电位的变化。如后面将讨论的，这可以抑制电路中的从第一节点N1流出的漏电流，并且因此改善移位寄存器单元电路200在高温条件下的性能。
如虚线框指示的节点控制电路240与本公开的发明构思不太密切，并且将稍后进行描述。
如本文使用的术语“有效电位”是指所涉及的电路元件(例如，晶体管)被启用所处的电位。相反，术语“无效电位”是指所涉及的电路元件被禁用所处的电位。对于n型晶体管而言，有效电位是高电位，并且无效电位是低电位。对于p型晶体管而言，有效电位是低电位，并且无效电位是高电位。
图3是如图2所示的移位寄存器单元电路200的示例电路200A的电路图。下面参考图3描述移位寄存器单元电路200的示例配置。
输入电路210包括第一晶体管T1和第二晶体管T2。第一晶体管T1具有连接到输入端IN的栅极、连接到第一节点N1的第一电极、以及连接到第一扫描电平端CN的第二电极。第二晶体管T2具有连接到复位端RST的栅极、连接到第二扫描电平端CNB的第一电极、以及连接到第一节点N1的第二电极。
输出电路220包括第三晶体管T3和第一电容器C1。第三晶体管T3具有连接到第二节点N2的栅极、连接到输出端OUT的第一电极、以及连接到第一时钟端CLK的第二电极。第一电容器C1连接在第二节点N2与输出端OUT之间。在该示例中，输出电路220还被配置成响应于第三节点N3处于有效电位而将来自第一参考电平端VGL的无效电位供应到输出端OUT。具体地，如图3所示，输出电路220还包括第四晶体管T4，其具有连接到第三节点N3的栅极、连接到第一参考电平端VGL的第一电极、以及连接到输出端OUT的第二电极。
在该示例中，电位控制电路230被配置成响应于第二节点N2的电位的变化超过一阈值而使第一节点N1与第二节点N2不导通(bring out of conduction)。具体地，电位控制电路230包括第一控制晶体管TK1，其具有连接到电位控制端PCN的栅极、连接到第一节点N1的第一电极、以及连接到第二节点N2的第二电极。第一控制晶体管TK1被配置成响应于来自电位控制端PCN的控制信号有效而被开启。第一控制晶体管TK1还被配置成响应于第二节点N2的电位的所述变化超过所述阈值而被关断。
节点控制电路240被配置成响应于第二节点N2处于有效电位而将第三节点N3设定处于无效电位，并且响应于第二节点N2处于无效电 位而将第三节点N3设定处于有效电位。具体地，在图3的示例中，节点控制电路240包括第六晶体管T6、第七晶体管T7和第三电容器C3。第六晶体管T6具有连接到第二节点N2的栅极、连接到第一参考电平端VGL的第一电极、以及连接到第三节点N3的第二电极。第七晶体管T7具有连接到用于供应具有与第一时钟信号相反相位的第二时钟信号的第二时钟端CLKB的栅极、连接到第三节点N3的第一电极、以及连接到第二时钟端CLKB的第二电极。第三电容器C3连接在第三节点N3与第一参考电平端VGL之间。
在一些实施例中，节点控制电路240还被配置成响应于第三节点N3处于有效电位而将第二节点N2设定处于无效电位。具体地，如图3所示，节点控制电路240还包括第五晶体管T5，其具有连接到第三节点N3的栅极、连接到第二节点N2的第一电极、以及连接到第一参考电平端VGL的第二电极。
图4是用于如图3所示的示例电路200A的示例时序图。下面参考图4描述图3的示例电路200A的操作。在下文中，以1表示高电平，并且以0表示低电平。还假定：第一扫描电平端CN供应高电平电压，并且第二扫描电平端CNB和第一参考电平端VGL供应低电平电压。
在阶段P1，PCN＝1，IN＝1，CLKB＝1，CLK＝0，RST＝0。由于IN＝1，所以第一晶体管T1导通，并且将来自第一扫描电平端CN的高电平电压传送到第一节点N1，使得第一节点N1被设定处于有效电位。由于PCT＝1，第一控制晶体管TK1导通，并且将第一节点N1的有效电位传送到第二节点N2，使得第六晶体管T6导通。由于CLKB＝1，所以第七晶体管T7导通。导通的第六晶体管T6和第七晶体管T7具有电阻分压效应。第六晶体管T6和第七晶体管T7被设计使得第六晶体管T6的等效电阻远小于第七晶体管T7的等效电阻。这样，第三节点N3被设定处于无效电位。由于第一节点N1处于有效电位，第三晶体管T3导通，并且将来自第一时钟端CLK的无效时钟信号传送到输出端OUT。
在阶段P2，PCN＝1，IN＝0，CLKB＝0，CLK＝1，RST＝0。由于PCN＝1，第一控制晶体管TK1保持开启。由于IN＝0且CLKB＝0，所以第一晶体管T1和第七晶体管T7关断。第一电容器C1保持第二节点N2处于有效电位，使得第三晶体管T3和第六晶体管T6导通。导通的第六晶体管T6将来自第一参考电平端VGL的低电平电压传送到第三节点N3， 使得第三节点N3保持处于无效电位。导通的第三晶体管T3将来自第一时钟端CLK的有效时钟信号传送到输出端OUT，使得输出端OUT输出有效电平信号。由于第一电容器C1的自举效应，第二节点N2的电位被进一步拉高。由于第一控制晶体管TK1导通，第一节点N1的电位随着第二节点N2的电位的升高而升高。当第一节点N1的电位升高到等于第一控制晶体管TK1的栅极电压时，第一控制晶体管TK1被关断，使得第一节点N1和第二节点N2不导通。因此，第一节点N1的电位的升高受到限制。在这种情况下，对于第二晶体管T2，可以有典型的工作状况：Vgs＝0V，Vds＝14.7V。与上面讨论的图1的配置相比，Vds降低约一倍，大大减小了流过第二晶体管T2的漏电流。因此，第二节点N2的电位较小地受到漏电流的影响，从而使得输出端OUT能够输出正常的脉冲信号。
在阶段P3，PCN＝1，IN＝0，CLKB＝1，CLK＝0，RST＝1。由于RST＝1，所以第二晶体管T2导通，并且将来自第二扫描电平端CNB的低电平电压传送到第一节点N1，使得第一节点N1被设定处于无效电位。由于PCN＝1，所以第一控制晶体管TK1被开启，并且将第一节点N1的无效电位传送到第二节点N2，使得第三晶体管T3和第六晶体管T6被关断。由于CLKB＝1，所以第七晶体管T7导通，使得来自第二时钟端CLKB的有效时钟信号被传送到第三节点N3，并且对第三电容器C3充电。因此，第三节点N3被设定处于有效电位，并且第四晶体管T4和第五晶体管T5导通。导通的第四晶体管T4将来自第一参考电平端VGL的低电平电压传送到输出端OUT，使得输出端OUT输出无效电平信号。
此后，第一电容器C1保持第一节点PU处于无效电位，并且第三电容器C3保持第三节点N3处于有效电位。由于第三节点N3处于有效电位，第四晶体管T4和第五晶体管T5导通。导通的第五晶体管T5将来自第一参考电平端VGL的低电平电压传送到第一节点N1，确保第一节点N1处于无效电位。导通的第四晶体管T4将来自第一参考电平端VGL的低电平电压传送到输出端OUT，确保输出端OUT输出无效电平信号。
图5是如图2所示的移位寄存器单元电路200的另一示例电路200B的电路图。输入电路210、输出电路220和节点控制电路240的 配置与上面关于图3描述的那些相同，并且在此不再重复。
在示例电路200B中，第一节点N1直接连接到第二节点N2，而没有第一控制晶体管TK1连接在其间。替代地，电位控制电路240包括第二电容器C2，其连接在第二节点N2与用于供应无效电位的第一参考电平端VGL之间。第二电容器C2可操作来在第二节点N2的电位由于第一电容器C1的自举效应而跳变时维持第一节点N1的电位稳定。这是因为第二电容C2与第一电容器C1串联连接，并且因此可以分担跨第一电容器C1的电压跳变。以这种方式，第一节点N1的电位的变化被限制，使得第二晶体管T2的漏-源电压Vds比起否则没有第二电容器C2被减小，从而减小流过第二晶体管T2的漏电流，并且反过来有利于第一节点N1的电位的稳定。这可以提高示例电路200B在高温条件下的可靠性。
在一些实施例中，电位控制电路240还可以被配置成响应于输出端OUT处于有效电位而将来自第二参考电平端VGH的有效电位供应到第二扫描电平端CNB。具体地，如图5所示，电位控制电路240还包括第二控制晶体管TK2，其具有连接到输出端OUT的栅极、连接到第二参考电平端VGH的第一电极、以及连接到第二扫描电平端的第二电极CNB。借助于这样的配置，当第二节点N2(等价地，第一节点N1和第二晶体管T2的第二电极)的电位由于第一电容器C1的自举效应升高时，第二晶体管T2的第一电极的电位也同步地升高。这减小了第二晶体管T2的漏-源电压Vds，并且因此减小了流过第二晶体管T2的漏电流。这进一步有利于第一节点N1的电位的稳定。
图6是用于如图5所示的示例电路的示例时序图。下面参考图6描述图5的示例电路200B的操作。在下文中，以1表示高电平，并且以0表示低电平。还假定：第一扫描电平端CN和第二参考电平端VGH供应高电平电压，并且第二扫描电平端CNB和第一参考电平端VGL供应低电平电压。
在阶段P1，IN＝1，CLKB＝1，CLK＝0，RST＝0。由于IN＝1，所以第一晶体管T1导通，并且将来自第一扫描电平端CN的高电平电压传送到第一节点N1，使得第一节点N1被设定处于有效电位。因此，第六晶体管T6导通。由于CLKB＝1，所以第七晶体管T7导通。导通的第六晶体管T6和第七晶体管T7具有电阻分压效应。第六晶体管T6 和第七晶体管T7被设计使得第六晶体管T6的等效电阻远小于第七晶体管T7的等效电阻。这样，第三节点N3被设定处于无效电位。由于第一节点N1处于有效电位，第三晶体管T3导通，并且将来自第一时钟端CLK的无效时钟信号传送到输出端OUT。
在阶段P2，IN＝0，CLKB＝0，CLK＝1，RST＝0。由于IN＝0且CLKB＝0，所以第一晶体管T1和第七晶体管T7关断。第一电容器C1保持第二节点N2处于有效电位，使得第三晶体管T3和第六晶体管T6导通。导通的第六晶体管T6将来自第一参考电平端VGL的低电平电压传送到第三节点N3，使得第三节点N3保持处于无效电位。导通的第三晶体管T3将来自第一时钟端CLK的有效时钟信号传送到输出端OUT，使得输出端OUT输出有效电平信号。由于第一电容器C1的自举效应，第二节点N2(等价地，第一节点N1)的电位被进一步拉高。由于第二电容器C2的存在，第一节点N1的电位的升高受到限制，从而减小流过第二晶体管T2的漏电流。
在阶段P3，IN＝0，CLKB＝1，CLK＝0，RST＝1。由于RST＝1，所以第二晶体管T2导通，并且将来自第二扫描电平端CNB的低电平电压传送到第一节点N1，使得第一节点N1(等价地，第二节点N2)被设定处于无效电位。因此，第三晶体管T3和第六晶体管T6被关断。由于CLKB＝1，所以第七晶体管T7导通，使得来自第二时钟端CLKB的有效时钟信号被传送到第三节点N3，并且对第三电容器C3充电。因此，第三节点N3被设定处于有效电位，并且第四晶体管T4和第五晶体管T5导通。导通的第四晶体管T4将来自第一参考电平端VGL的低电平电压传送到输出端OUT，使得输出端OUT输出无效电平信号。
此后，第一电容器C1保持第一节点PU处于无效电位，并且第三电容器C3保持第三节点N3处于有效电位。由于第三节点N3处于有效电位，第四晶体管T4和第五晶体管T5导通。导通的第五晶体管T5将来自第一参考电平端VGL的低电平电压传送到第一节点N1，确保第一节点N1处于无效电位。导通的第四晶体管T4将来自第一参考电平端VGL的低电平电压传送到输出端OUT，确保输出端OUT输出无效电平信号。
图7A和7B是根据本公开实施例的栅极驱动电路在不同扫描模式下的框图。参考图7A和7B，栅极驱动电路700A、700B均包括n个 级联的移位寄存器单元电路，其每一个可以是如上面描述的移位寄存器单元电路200。这n个移位寄存器单元电路分别连接到n条栅线G[1]，G[2]，G[3]，...，G[n-1]和G[n]以向它们供应栅极驱动信号。n可以是大于或等于2的整数。
除了第一个移位寄存器单元电路之外，各移位寄存器单元电路中的每一个的输入端IN连接到相邻上一个移位寄存器单元电路的输出端OUT，并且除了第n个移位寄存器单元电路之外，各移位寄存器单元电路中的每一个的复位端RST连接到相邻下一个移位寄存器单元电路的输出端OUT。
在正向扫描模式(图7A)下，第一个移位寄存器单元电路的输入端IN接收起始信号STV作为所述输入脉冲。在反向扫描模式(图7B)下，第n个移位寄存器单元电路的复位端RST接收起始信号STV作为所述输入脉冲。
将理解的是，取决于扫描模式，移位寄存器单元电路的输入端IN和复位端RST可互换地使用，并且第一扫描电平端CN和第二扫描电平端CNB可互换地使用。在正向扫描模式下，第一扫描电平端CN供应有效电平电压，第二扫描电平端CNB供应无效电平电压，并且输入端IN和复位端RST被正常地使用。在反向扫描模式下，第一扫描电平端CN供应无效电平电压，并且第二扫描电平端CNB供应有效电平电压。在这种情况下，如图7B所示，输入端IN充当“复位端”，并且复位端RST充当“输入端”。
图8是根据本公开实施例的显示装置800的框图。参考图8，显示装置800包括显示面板810、时序控制器820、栅极驱动电路830和数据驱动电路840。栅极驱动电路830可以是上面关于图7A和7B所述的栅极驱动电路700A或700B。
显示面板810连接至多个栅极线GL和多个数据线DL。显示面板810基于输出图像数据RGBD’显示具有多个灰度的图像。栅极线GL可在第一方向D1延伸，并且数据线DL可在与第一方向D1交叉(例如，基本垂直)的第二方向D2延伸。显示面板810可包括以矩阵形式排列的多个像素(未示出)。每个像素可电连接至栅极线GL的对应一个栅极线和数据线DL的对应一个数据线。显示面板810可以是液晶显示面板、有机发光二极管(OLED)显示面板或其他合适类型的显示面板。
时序控制器820控制显示面板810、栅极驱动电路830和数据驱动电路840的操作。时序控制器820从外部设备(例如，主机)接收输入图像数据RGBD和输入控制信号CONT。输入图像数据RGBD可包括用于多个像素的多个输入像素数据。每个输入像素数据可包括用于多个像素中的对应一个的红色灰度数据R、绿色灰度数据G和蓝色灰度数据B。输入控制信号CONT可包括主时钟信号、数据使能信号、垂直同步信号、水平同步信号等。时序控制器720基于输入图像数据RGBD和输入控制信号CONT生成输出图像数据RGBD’、第一控制信号CONT1和第二控制信号CONT2。
栅极驱动电路830从时序控制器820接收第一控制信号CONT1。栅极驱动电路830基于第一控制信号CONT1生成用于驱动栅极线GL的多个栅极信号。栅极驱动电路830可顺序地将多个栅极信号施加至栅极线GL。
数据驱动电路840从时序控制器820接收第二控制信号CONT2和输出图像数据RGBD’。数据驱动电路840基于第二控制信号CONT2和输出图像数据RGBD’(例如，数字图像数据)生成多个数据电压(例如，模拟数据电压)。数据驱动电路840可将多个数据电压施加至数据线DL。
在一些示例性实施例中，栅极驱动电路830和/或数据驱动电路840可被设置(例如，直接安装)在显示面板810上，或者可以借助例如带式载体封装(Tape Carrier Package，TCP)连接至显示面板810。在一些实施例中，栅极驱动电路830和/或数据驱动电路840可被集成在显示面板810中。
显示装置800的示例包括但不限于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪。
将理解的是，在各实施例中，虽然各晶体管被图示和描述为n型晶体管，但是p型晶体管是可能的。在p型晶体管的情况下，栅极开启电压具有低电平，并且栅极关闭电压具有高电平。在各实施例中，各晶体管可以例如是薄膜晶体管，其典型地被制作使得它们的第一电极和第二电极可互换地使用。还设想了其他实施例。
以上所述是本公开的具体实施例，而不应解释为限制本公开的范围。本技术领域的普通技术人员在不脱离本公开的精神的前提下可以 对所描述的实施例做出若干变型和修改，这些变型和修改也应视为涵盖在本公开的范围之内。

Claims (19)

  1. 一种移位寄存器单元电路，包括：
    输入电路，被配置成响应于来自输入端的输入脉冲有效而将来自第一扫描电平端的有效电位供应到第一节点，并且响应于来自复位端的复位脉冲有效而将来自第二扫描电平端的无效电位供应到所述第一节点；
    输出电路，被配置成响应于第二节点处于所述有效电位而将来自第一时钟端的第一时钟信号供应到输出端，并且响应于所述输出端的电位从所述无效电位跳变到所述有效电位而引起所述第二节点的电位从所述有效电位被改变为进一步远离所述无效电位；以及
    电位控制电路，被配置成限制由所述输出端的电位从无效电位到有效电位的所述跳变引起的所述第一节点的电位的变化。
  2. 如权利要求1所述的移位寄存器单元电路，其中所述电位控制电路被配置成响应于所述第二节点的电位的变化超过一阈值而使所述第一节点与所述第二节点不导通。
  3. 如权利要求2所述的移位寄存器单元电路，其中所述电位控制电路包括第一控制晶体管，其具有连接到电位控制端的栅极、连接到第一节点的第一电极、以及连接到第二节点的第二电极，并且其中所述第一控制晶体管被配置成响应于来自所述电位控制端的控制信号有效而被开启，并且响应于所述第二节点的电位的所述变化超过所述阈值而被关断。
  4. 如权利要求1所述的移位寄存器单元电路，其中所述第一节点直接连接到所述第二节点，并且其中所述电位控制电路包括第二电容器，其连接在所述第二节点与用于供应所述无效电位的第一参考电平端之间。
  5. 如权利要求4所述的移位寄存器单元电路，其中所述电位控制电路还被配置成响应于所述输出端处于所述有效电位而将来自第二参考电平端的有效电位供应到所述第二扫描电平端。
  6. 如权利要求5所述的移位寄存器单元电路，其中所述电位控制电路还包括第二控制晶体管，其具有连接到所述输出端的栅极、连接到所述第二参考电平端的第一电极、以及连接到所述第二扫描电平端 的第二电极。
  7. 如权利要求1至6中任一项所述的移位寄存器单元电路，其中所述输入电路包括：
    第一晶体管，具有连接到所述输入端的栅极、连接到所述第一节点的第一电极、以及连接到所述第一扫描电平端的第二电极；和
    第二晶体管，具有连接到所述复位端的栅极、连接到所述第二扫描电平端的第一电极、以及连接到所述第一节点的第二电极。
  8. 如权利要求1-6中任一项所述的移位寄存器单元电路，其中所述输出电路包括：
    第三晶体管，具有连接到所述第二节点的栅极、连接到所述输出端的第一电极、以及连接到所述第一时钟端的第二电极；和
    第一电容器，连接在所述第二节点与所述输出端之间。
  9. 如权利要求8所述的移位寄存器单元电路，其中所述输出电路还被配置成响应于第三节点处于所述有效电位而将来自第一参考电平端的所述无效电位供应到所述输出端。
  10. 如权利要求9所述的移位寄存器单元电路，其中所述输出电路还包括第四晶体管，其具有连接到所述第三节点的栅极、连接到所述第一参考电平端的第一电极、以及连接到所述输出端的第二电极。
  11. 如权利要求9所述的移位寄存器单元电路，还包括节点控制电路，其被配置成响应于所述第二节点处于所述有效电位而将所述第三节点设定处于所述无效电位，并且响应于所述第二节点处于所述无效电位而将所述第三节点设定处于所述有效电位。
  12. 如权利要求11所述的移位寄存器单元电路，其中所述节点控制电路包括：
    第六晶体管，具有连接到所述第二节点的栅极、连接到所述第一参考电平端的第一电极、以及连接到所述第三节点的第二电极；
    第七晶体管，具有连接到用于供应具有与所述第一时钟信号相反相位的第二时钟信号的第二时钟端的栅极、连接到所述第三节点的第一电极、以及连接到所述第二时钟端的第二电极；和
    第三电容器，连接在所述第三节点与所述第一参考电平端之间。
  13. 如权利要求11所述的移位寄存器单元电路，其中所述节点控制电路还被配置成响应于所述第三节点处于所述有效电位而将所述第 二节点设定处于所述无效电位。
  14. 如权利要求13所述的移位寄存器单元电路，其中所述节点控制电路还包括第五晶体管，其具有连接到所述第三节点的栅极、连接到所述第二节点的第一电极、以及连接到所述第一参考电平端的第二电极。
  15. 一种驱动如权利要求1-14中任一项所述的移位寄存器单元电路的方法，所述方法包括：
    响应于来自所述输入端的输入脉冲有效而将来自所述第一扫描电平端的有效电位供应到所述第一节点；
    响应于所述第二节点处于所述有效电位而将来自所述第一时钟端的第一时钟信号供应到输出端；
    响应于所述输出端从处于所述无效电位跳变到处于所述有效电位而引起所述第二节点的电位从所述有效电位被改变为进一步远离所述无效电位；
    限制由所述输出端的电位从无效电位到有效电位的所述跳变引起的所述第一节点的电位的变化；以及
    响应于来自所述复位端的复位脉冲有效而将来自所述第二扫描电平端的无效电位供应到所述第一节点。
  16. 如权利要求15所述的方法，其中限制所述第一节点的电位的变化包括：响应于所述第二节点的电位的所述变化超过一阈值而使所述第一节点与所述第二节点不导通。
  17. 如权利要求15所述的方法，还包括响应于所述输出端处于所述有效电位而将来自第二参考电平端的有效电位供应到所述第二扫描电平端。
  18. 一种栅极驱动电路，包括多个级联的如权利要求1至14中任一项所述的移位寄存器单元电路。
  19. 一种显示装置，包括如权利要求18所述的栅极驱动电路。
PCT/CN2017/099871 2017-01-16 2017-08-31 移位寄存器单元电路及其驱动方法、栅极驱动电路和显示装置 Ceased WO2018129932A1 (zh)

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