[go: up one dir, main page]

WO2018127196A1 - Conception de facteurs d'élévation et de coefficients de décalage destinée à un code ldpc nr - Google Patents

Conception de facteurs d'élévation et de coefficients de décalage destinée à un code ldpc nr Download PDF

Info

Publication number
WO2018127196A1
WO2018127196A1 PCT/CN2018/071868 CN2018071868W WO2018127196A1 WO 2018127196 A1 WO2018127196 A1 WO 2018127196A1 CN 2018071868 W CN2018071868 W CN 2018071868W WO 2018127196 A1 WO2018127196 A1 WO 2018127196A1
Authority
WO
WIPO (PCT)
Prior art keywords
lifting
sets
shift
factors
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/071868
Other languages
English (en)
Inventor
Mao-Ching Chiu
Timothy Perrin Fisher-Jeffes
Chong-You Lee
Cheng-Yi Hsu
Yen-Shuo Chang
Wei-Jen Chen
Ju-Ya Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/594,239 external-priority patent/US10164659B2/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to EP18736710.7A priority Critical patent/EP3549264A4/fr
Priority to CN201880006223.5A priority patent/CN110192346B/zh
Publication of WO2018127196A1 publication Critical patent/WO2018127196A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy

Definitions

  • the present disclosure is generally related to information coding and decodingand, more particularly, to shift coefficient and lifting factor design.
  • the 3 rd Generation Partnership Project (3GPP) has approved plans to speed up the development of the 5 th -generation (5G) New Radio (NR) specifications, it thus can be expected that standards-based 5G NR wireless communications services can be launched in the near future.
  • the 3GPP has also agreed that quasi-cyclic low-density parity-check (QC-LDPC) will be used for in 5G NR data channel.
  • QC-LDPC quasi-cyclic low-density parity-check
  • An objective of the present disclosure is to propose various novel concepts and schemes pertaining to structure design of shift coefficients and lifting factors for QC-LDPC coding and decoding, which can be implemented in next-generation communications, whether wired or wireless, including 5G NR wireless communications.
  • a method may involve a processor of an apparatus generating a QC-LDPC code.
  • the method may also involve the processor encoding data using the selected codebook.
  • the method may involve the processor performing the following: (1) defining a plurality of sets of lifting factors; (2) generating a respective table of shift values for each lifting factor of the plurality of sets of lifting factors; and (3) generating the QC-LDPC code using a base matrix and the shift coefficient table.
  • a method may involve a processor of an apparatus generating a QC-LDPC code.
  • the method may also involve the processor encoding data using the selected codebook.
  • the method may involve the processor performing the following: (1) defining a plurality of sets of lifting factors; (2) generating a respective table of shift values for each lifting factor of the plurality of sets of lifting factors; and (3) generating the QC-LDPC code using a base matrix and the shift coefficient table.
  • the method may involve the processor generating the respective table of shift values for each lifting factor of the plurality of sets of lifting factors using a nested design with a mod operation to represent all shift coefficients of different lifting factors with each set of the plurality sets of lifting factors.
  • an apparatus may include a processor capable of generating a QC-LDPC code and encoding data using the QC-LDPC code.
  • the processor may be capable of performing the following: (1) defining a plurality of sets of lifting factors; (2) generating a respective table of shift values for each lifting factor of the plurality of sets of lifting factors; and (3) generating the QC-LDPC code using a base matrix and the shift coefficient table.
  • FIG. 1 is a diagram of an example of QC-LDPC code generation in accordance with an implementation of the present disclosure.
  • FIG. 2 is a table of an example lifting factor in accordance with an implementation of the present disclosure.
  • FIG. 3 is an example of a shift coefficient table in accordance with an implementation of the present disclosure.
  • FIG. 4 is a block diagram of an example communications system in accordance with an implementation of the present disclosure.
  • FIG. 5 is a flowchart of an example process in accordance with an implementation of the present disclosure.
  • FIG. 6 is a flowchart of an example process in accordance with an implementation of the present disclosure.
  • FIG. 1 illustrates an example 100 of QC-LDPC code generation in accordance with an implementation of the present disclosure.
  • FIG. 2 illustrates a table 200 of an example lifting factor in accordance with an implementation of the present disclosure.
  • FIG. 3 illustrates an example 300 of a shift coefficient table in accordance with an implementation of the present disclosure. The following description is provided with reference to FIG. 1 ⁇ FIG. 3.
  • a parity check matrix of QC-LDPC code may be constructed from a base matrix and a shift coefficient table, and a lifting factor is the size of a sub-matrix in the parity check matrix.
  • table 200 in FIG. 2 is an example of eight sets of lifting factors.
  • a respective table of shift values may be generated.
  • the respective table of shift values may be generated to contain a shift coefficient corresponding to a maximal lifting factor with the respective set of lifting factors.
  • shifting values corresponding to the eight sets of lifting factors may be represented by eight shift coefficient tables which correspond to shift coefficients of ⁇ 208, 224, 240, 256, 288, 320, 352, 384 ⁇ .
  • each table of shift values may be generated using nested design to represent all shift coefficients of different lifting factors within each set of the eight sets of lifting factors.
  • a corresponding shift value may be obtained by performing a mod operation with Z (e.g., V %Z) .
  • FIG. 4 illustrates an example communications system 400 in accordance with an implementation of the present disclosure.
  • Communications systems may include a first apparatus 405 and a second apparatus 450, which may be in communications with each other via a communications link 440.
  • Communications link 440 may be a wireless link in some implementations, and may be a wired link in some other implementations.
  • Each of first apparatus 405 and second apparatus 450 may perform various functions as a communication device to implement concepts, schemes, techniques, processes and methods described herein pertaining to shift coefficient and lifting factor design for NR LDPC code, including those described with respect to some or all of FIG. 1 –FIG. 3as well as processes 500 and 600 described below. More specifically, each of first apparatus 405 and second apparatus 450 may implement various aspects of the proposed concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code.
  • first apparatus 405 and second apparatus 450 may be a part of an electronic apparatus which may be a communication device, a computing apparatus, a portable or mobile apparatus, or a wearable apparatus.
  • first apparatus 405 may be implemented in a Wi-Fi access point, a smartphone, a smartwatch, a smart bracelet, a smart necklace, a personal digital assistant, or a computing device such as a tablet computer, a laptop computer, a notebook computer, a desktop computer, or a server.
  • second apparatus 450 may be implemented in a Wi-Fi mobile client or station, a smartphone, a smartwatch, a smart bracelet, a smart necklace, a personal digital assistant, or a computing device such as a tablet computer, a laptop computer, a notebook computer, a desktop computer, or a server.
  • each of first apparatus 405 and second apparatus 450 may be implemented in the form of one or more integrated-circuit (IC) chips such as, for example and not limited to, one or more single-core processors, one or more multi-core processors, or one or more complex-instruction-set-computing (CISC) processors.
  • IC integrated-circuit
  • first apparatus 405 and second apparatus 450 may include at least some of those components shown in FIG. 4, respectively.
  • first apparatus 405 may include at least a processor 410
  • second apparatus 450 may include at least a processor 460.
  • first apparatus 405 may include a memory 420 and/or a transceiver 430 configured to transmit and receive data wirelessly (e.g., in compliance with one or more 3GPP stands, protocols, specifications and/or any applicable wireless protocols and standards) .
  • Each of memory 420 and transceiver 430 may be communicatively and operably coupled to processor 410.
  • second apparatus 450 may also include a memory 470 and/or a transceiver 480 configured to transmit and receive data wirelessly (e.g., in compliance with the IEEE 802.11 specification and/or any applicable wireless protocols and standards) .
  • Each of memory 470 and transceiver 480 may be communicatively and operably coupled to processor 460.
  • Each of first apparatus 405 and second apparatus 450 may further include other components (e.g., power system, display device and user interface device) , which are not pertinent to the proposed scheme of the present disclosure and, thus, are neither shown in FIG. 4 nor described herein in the interest of simplicity and brevity.
  • Transceiver 430 may be configured to communicate wirelessly in a single frequency band or multiple frequency bands.
  • Transceiver 430 may include a transmitter 432 capable of transmitting data wirelessly and a receiver 434 capable of receiving data wirelessly.
  • transceiver 480 may be configured to communicate wirelessly in a single frequency band or multiple frequency bands.
  • Transceiver 480 may include a transmitter 482 capable of transmitting data wirelessly and a receiver 484 capable of receiving data wirelessly.
  • Each of memory 420 and memory 470 may be a storage device configured to store one or more sets of codes, programs and/or instructions and/or data therein.
  • memory 420 stores one or more sets of processor-executable instructions 422 and data 424 therein
  • memory 470 stores one or more sets of processor-executable instructions 472 and data 474 therein.
  • Each of memory 420 and memory 470 may be implemented by any suitable technology and may include volatile memory and/or non-volatile memory.
  • each of memory 420 and memory 470 may include a type of random access memory (RAM) such as dynamic RAM (DRAM) , static RAM (SRAM) , thyristor RAM (T-RAM) and/or zero-capacitor RAM (Z-RAM) .
  • RAM random access memory
  • SRAM static RAM
  • T-RAM thyristor RAM
  • Z-RAM zero-capacitor RAM
  • memory 520 may include a type of read-only memory (ROM) such as mask ROM, programmable ROM (PROM) , erasable programmable ROM (EPROM) and/or electrically erasable programmable ROM (EEPROM) .
  • ROM read-only memory
  • PROM programmable ROM
  • EPROM erasable programmable ROM
  • EEPROM electrically erasable programmable ROM
  • each of memory 420 and memory 470 may include a type of non-volatile random-access memory (NVRAM) such as flash memory, solid-state memory, ferroelectric RAM (FeRAM) , magnetoresistive RAM (MRAM) and/or phase-change memory.
  • NVRAM non-volatile random-access memory
  • flash memory solid-state memory
  • FeRAM ferroelectric RAM
  • MRAM magnetoresistive RAM
  • phase-change memory phase-change memory
  • each of processor 410 and processor 460 may be implemented in the form of one or more single-core processors, one or more multi-core processors, or one or more CISC processors. That is, even though a singular term “a processor” is used herein to refer to each of processor 410 and processor 460, each of processor 410 and processor 460may include multiple processors in some implementations and a single processor in other implementations in accordance with the present disclosure.
  • each of processor 410 and processor 460 may be implemented in the form of hardware (and, optionally, firmware) with electronic components including, for example and without limitation, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors and/or one or more varactors that are configured and arranged to achieve specific purposes in accordance with the present disclosure.
  • each of processor 410 and processor 460 is a special-purpose machine specifically designed, arranged and configured to perform specific tasks including QC-LDPC coding with shift coefficient and lifting factor design in accordance with various implementations of the present disclosure.
  • Processor 410 may include non-generic and specially-designed hardware circuits that are designed, arranged and configured to perform specific tasks pertaining to QC-LDPC coding with shift coefficient and lifting factor design in accordance with various implementations of the present disclosure.
  • processor 410 may execute the one or more sets of codes, programs and/or instructions 422 stored in memory 420 to perform various operations to render QC-LDPC coding with shift coefficient and lifting factor design in accordance with various implementations of the present disclosure.
  • processor 410 may include an encoder 412 and a decoder 414 that, together, perform specific tasks and functions to render QC-LDPC coding with shift coefficient and lifting factor design in accordance with various implementations of the present disclosure.
  • encoder 412 may be configured to encode data in accordance with various concepts and schemes of the present disclosure.
  • decoder 414 may be configured to decode data in accordance with various concepts and schemes of the present disclosure.
  • Processor 460 may include non-generic and specially-designed hardware circuits that are designed, arranged and configured to perform specific tasks pertaining to QC-LDPC coding with shift coefficient and lifting factor design in accordance with various implementations of the present disclosure.
  • processor 460 may execute the one or more sets of codes, programs and/or instructions 472 stored in memory 470 to perform various operations to render power-save operations in accordance with various implementations of the present disclosure.
  • processor 460 may include an encoder 462 and a decoder 464 that performs specific tasks and functions to render QC-LDPC coding with shift coefficient and lifting factor design in accordance with various implementations of the present disclosure.
  • encoder 462 may be configured to encode data in accordance with various concepts and schemes of the present disclosure.
  • decoder 464 may be configured to decode data in accordance with various concepts and schemes of the present disclosure.
  • first apparatus 405 and second apparatus 450 may be configured to implement each of processes 500 and 600 described below. Thus, to avoid redundancy and in the interest of brevity, operations of first apparatus 405 and second apparatus 450, as well as processor 410 and processor 460, are described below in the context of processes 500 and 600. It is noteworthy that, although the description below is provided in the context of first apparatus 405, the description below is also applicable to second apparatus 450.
  • FIG. 5 illustrates an example process 500 in accordance with an implementation of the present disclosure.
  • Process 500 may represent an aspect of implementing the proposed concepts and schemes such as those described with respect to some or all of FIG. 1 –FIG. 3. More specifically, process 500 may represent an aspect of the proposed concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code.
  • Process 500 may include one or more operations, actions, or functions as illustrated by one or more of blocks 510, 520 and 530, as well as sub-blocks 512, 514 and 516. Although illustrated as discrete blocks, various blocks of process 500 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Moreover, the blocks/sub-blocks of process 500 may be executed in the order shown in FIG.
  • Process 500 may be implemented by communications system 400 and any variations thereof. For instance, process 500 may be implemented in or by first apparatus 405and/or second apparatus450. Solely for illustrative purposes and without limiting the scope, process 500 is described below in the context of first apparatus 405. Process 500 may begin at block 510.
  • process 500 may involve processor 410 of first apparatus 405generating a QC-LDPC code.
  • process 500 may involve processor 410 performing a number of operations as represented by sub-blocks 512, 514 and 516 described below.
  • Process 500 may proceed from 510 to 520.
  • process 500 may involve processor 410 encoding data using the QC-LDPC code.
  • Process 500 may proceed from 520 to 530.
  • process 500 may involve processor 410 transmitting, via transceiver 430, the encoded data (e.g., to transceiver 480 of apparatus 450) .
  • process 500 may involve processor 410 defining a plurality of sets of lifting factors. Process 500 may proceed from 512 to 514.
  • process 500 may involve processor 410 generating a respective table of shift values for each lifting factor of the plurality of sets of lifting factors. Process 500 may proceed from 514 to 516.
  • process 500 may involve processor 410 generating the QC-LDPC code using a base matrix and the shift coefficient table.
  • the plurality of sets of lifting factors may include eight sets of lifting factors.
  • process 500 may involve processor 410 generating the respective table of shift values containing a shift coefficient corresponding to a maximal lifting factor with the respective set of lifting factors.
  • shifting values corresponding to the eight sets of lifting factors may be represented by eight shift coefficient tables which correspond to shift coefficients of ⁇ 208, 224, 240, 256, 288, 320, 352, 384 ⁇ .
  • process 500 may involve processor 410 generating each table of shift values using nested design to represent all shift coefficients of different lifting factors within each set of the eight sets of lifting factors.
  • a corresponding shift value may be obtained by performing a mod operation with Z, with J denoting a largest valid value.
  • FIG. 6 illustrates an example process 600 in accordance with an implementation of the present disclosure.
  • Process 600 may represent an aspect of implementing the proposed concepts and schemes such as those described with respect to some or all of FIG. 1 –FIG. 3. More specifically, process 600 may represent an aspect of the proposed concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code.
  • Process 600 may include one or more operations, actions, or functions as illustrated by one or more of blocks 610, 620 and 630, as well as sub-blocks 612, 614, 616 and 618. Although illustrated as discrete blocks, various blocks of process 600 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Moreover, the blocks/sub-blocks of process 600 may be executed in the order shown in FIG.
  • Process 600 may be implemented by communications system 400 and any variations thereof. For instance, process 600 may be implemented in or by first apparatus 405and/or second apparatus 450. Solely for illustrative purposes and without limiting the scope, process 600 is described below in the context of first apparatus 405. Process 600 may begin at block 610.
  • process 600 may involve processor 410 of first apparatus 405generating a QC-LDPC code.
  • process 600 may involve processor 410 performing a number of operations as represented by sub-blocks 612, 614 and 616 described below.
  • Process 600 may proceed from 610 to 620.
  • process 600 may involve processor 410 encoding data using the QC-LDPC code.
  • process 600 may involve processor 410 transmitting, via transceiver 430, the encoded data (e.g., to transceiver 480 of apparatus 450) .
  • process 600 may involve processor 410 defining a plurality of sets of lifting factors. Process 600 may proceed from 612 to 614.
  • process 600 may involve processor 410 generating a respective table of shift values for each lifting factor of the plurality of sets of lifting factors. In generating the respective table of shift values for each lifting factor of the plurality of sets of lifting factors, process 600 may involve processor 410 performing operations as represented by sub-block 618 described below. Process 600 may proceed from 614 to 616.
  • process 600 may involve processor 410 generating the QC-LDPC code using a base matrix and the shift coefficient table.
  • process 600 may involve processor 410 generating the respective table of shift values for each lifting factor of the plurality of sets of lifting factors using a nested design with a mod operation to represent all shift coefficients of different lifting factors with each set of the plurality sets of lifting factors.
  • the plurality of sets of lifting factors comprise eight sets of lifting factors.
  • the respective table may contain a shift coefficient of a maximal lifting factor within the respective set of lifting factors.
  • shifting values corresponding to the eight sets of lifting factors may be represented by eight shift coefficient tables which correspond to shift coefficients of ⁇ 208, 224, 240, 256, 288, 320, 352, 384 ⁇ .
  • any two components so associated can also be viewed as being “operably connected” , or “operably coupled” , to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “operably couplable” , to each other to achieve the desired functionality.
  • operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention concerne des concepts et des procédés se rapportant à la conception de facteurs d'élévation et de coefficients de décalage destinée à un code LDPC NR. Un processeur d'un appareil peut générer un code de contrôle de parité à faible densité quasi cyclique (QC-LDPC) et coder des données à l'aide du livre de codes sélectionné. Lors de la génération du code QC-LDPC, le processeur peut définir une pluralité d'ensembles de facteurs d'élévation, générer un tableau respectif de valeurs de décalage concernant chaque facteur d'élévation de la pluralité d'ensembles de facteurs d'élévation, et générer le code QC-LDPC à l'aide d'une matrice de base et de la table de coefficients de décalage.
PCT/CN2018/071868 2017-01-09 2018-01-09 Conception de facteurs d'élévation et de coefficients de décalage destinée à un code ldpc nr Ceased WO2018127196A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP18736710.7A EP3549264A4 (fr) 2017-01-09 2018-01-09 Conception de facteurs d'élévation et de coefficients de décalage destinée à un code ldpc nr
CN201880006223.5A CN110192346B (zh) 2017-01-09 2018-01-09 低密度奇偶校验码的偏移系数和提升因子设计方法

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201762443852P 2017-01-09 2017-01-09
US62/443,852 2017-01-09
US201762449677P 2017-01-24 2017-01-24
US62/449,677 2017-01-24
US15/594,239 2017-05-12
US15/594,239 US10164659B2 (en) 2016-05-12 2017-05-12 QC-LDPC coding methods and apparatus

Publications (1)

Publication Number Publication Date
WO2018127196A1 true WO2018127196A1 (fr) 2018-07-12

Family

ID=62789321

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/071868 Ceased WO2018127196A1 (fr) 2017-01-09 2018-01-09 Conception de facteurs d'élévation et de coefficients de décalage destinée à un code ldpc nr

Country Status (4)

Country Link
EP (1) EP3549264A4 (fr)
CN (1) CN110192346B (fr)
TW (1) TWI652907B (fr)
WO (1) WO2018127196A1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3469712A1 (fr) * 2016-06-14 2019-04-17 Qualcomm Incorporated Procédés et appareil de description compacte de codes de contrôle de parité de faible densité (ldpc) élevés
CN109952729A (zh) * 2019-01-31 2019-06-28 香港应用科技研究院有限公司 并行ldpc解码器
WO2020155146A1 (fr) * 2019-01-31 2020-08-06 Hong Kong Applied Science and Technology Research Institute Company Limited Décodeur ldpc parallèle
US10826529B2 (en) 2019-01-31 2020-11-03 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Parallel LDPC decoder
US10877729B2 (en) 2019-01-31 2020-12-29 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Reconfigurable segmented scalable shifter
US11575390B2 (en) 2021-07-02 2023-02-07 Hong Kong Applied Science and Technology Research Insitute Co., Ltd. Low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder
US12261693B2 (en) 2017-07-07 2025-03-25 Qualcomm Incorporated Communication techniques applying low-density parity-check code base graph selection
USRE50437E1 (en) * 2017-06-10 2025-05-20 Qualcomm Incorporated Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code
US12476733B2 (en) 2017-06-19 2025-11-18 Qualcomm Incorporated Communication techniques with self-decodable redundancy versions (RVs) using systematic codes

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113131949B (zh) * 2021-03-11 2024-11-08 苏州华兴源创科技股份有限公司 数据预处理方法、装置、电子设备及计算机可读存储介质

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100257425A1 (en) * 2009-04-06 2010-10-07 Nec Laboratories America, Inc. Systems and methods for constructing the base matrix of quasi-cyclic low-density parity-check codes
CN105471547A (zh) * 2014-09-30 2016-04-06 美国博通公司 通信设备及通过其执行的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101005334B (zh) * 2007-01-12 2010-12-29 中兴通讯股份有限公司 一种低密度奇偶校验码的混合自动请求重传包生成方法
CN101141133B (zh) * 2007-10-23 2011-09-14 北京邮电大学 一种结构化低密度校验码的编码方法
CN101771421B (zh) * 2010-03-11 2012-10-17 复旦大学 基于tdmp的超高速低功耗qc-ldpc码解码器
CN103391104A (zh) * 2012-05-10 2013-11-13 中兴通讯股份有限公司 低密度奇偶校验码ldpc编码处理方法及装置
CN104868925B (zh) * 2014-02-21 2019-01-22 中兴通讯股份有限公司 结构化ldpc码的编码方法、译码方法、编码装置和译码装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100257425A1 (en) * 2009-04-06 2010-10-07 Nec Laboratories America, Inc. Systems and methods for constructing the base matrix of quasi-cyclic low-density parity-check codes
CN105471547A (zh) * 2014-09-30 2016-04-06 美国博通公司 通信设备及通过其执行的方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
MEDIATEK INC.: "Implementation considerations on flexible and efficient LDPC decoders", 3GPP TSG-RAN WG1 #86BIS, R1-1609337, 14 October 2016 (2016-10-14), XP051149380 *
See also references of EP3549264A4 *
ZTE CORP. ET AL.: "Consideration on LDPC codes for NR", 3GPP TSG RAN WG1 #85, R1-165409, 27 May 2016 (2016-05-27), XP051111602 *

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3469712A1 (fr) * 2016-06-14 2019-04-17 Qualcomm Incorporated Procédés et appareil de description compacte de codes de contrôle de parité de faible densité (ldpc) élevés
US12191883B2 (en) 2016-06-14 2025-01-07 Qualcomm Incorporated Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes
EP3469712B1 (fr) * 2016-06-14 2025-10-15 Qualcomm Incorporated Procédé et dispositif pour la description compacte des codes levés de contrôle de parité de faible densité (ldpc)
USRE50437E1 (en) * 2017-06-10 2025-05-20 Qualcomm Incorporated Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code
US12476733B2 (en) 2017-06-19 2025-11-18 Qualcomm Incorporated Communication techniques with self-decodable redundancy versions (RVs) using systematic codes
US12261693B2 (en) 2017-07-07 2025-03-25 Qualcomm Incorporated Communication techniques applying low-density parity-check code base graph selection
CN109952729A (zh) * 2019-01-31 2019-06-28 香港应用科技研究院有限公司 并行ldpc解码器
WO2020155146A1 (fr) * 2019-01-31 2020-08-06 Hong Kong Applied Science and Technology Research Institute Company Limited Décodeur ldpc parallèle
US10826529B2 (en) 2019-01-31 2020-11-03 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Parallel LDPC decoder
US10877729B2 (en) 2019-01-31 2020-12-29 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Reconfigurable segmented scalable shifter
CN109952729B (zh) * 2019-01-31 2021-12-03 香港应用科技研究院有限公司 并行ldpc解码器
US11575390B2 (en) 2021-07-02 2023-02-07 Hong Kong Applied Science and Technology Research Insitute Co., Ltd. Low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder

Also Published As

Publication number Publication date
EP3549264A4 (fr) 2020-01-22
CN110192346A (zh) 2019-08-30
TW201832477A (zh) 2018-09-01
TWI652907B (zh) 2019-03-01
CN110192346B (zh) 2023-06-09
EP3549264A1 (fr) 2019-10-09

Similar Documents

Publication Publication Date Title
WO2018127196A1 (fr) Conception de facteurs d'élévation et de coefficients de décalage destinée à un code ldpc nr
US10164659B2 (en) QC-LDPC coding methods and apparatus
US10581457B2 (en) Shift coefficient and lifting factor design for NR LDPC code
US10425186B2 (en) Combined coding design for efficient codeblock extension
US10567116B2 (en) Wireless communication using codebooks from a QC-LDPC code for shorter processing latency and improved decoder throughput efficiency
US10484013B2 (en) Shift-coefficient table design of QC-LDPC code for smaller code block sizes in mobile communications
US10484011B2 (en) Shift-coefficient table design of QC-LDPC code for larger code block sizes in mobile communications
EP3800814A1 (fr) Schémas de codage de joint avec entrelaceur et mappeur de contrastes pour fonctionnement multi-ru
US20180131392A1 (en) NR LDPC With Interleaver
CN113014268B (zh) 用于下一代wlan系统的极高速率编解码方法
US10958290B2 (en) Location of interleaver with LDPC code
WO2019029748A1 (fr) Procédé et dispositif de codage par code polaire
CN108574493B (zh) 数据处理的方法和装置
US12395190B2 (en) Method and apparatus for LDPC code construction in communications
US20250323752A1 (en) Bcc low coding rate designs for next-generation wlan
WO2023241687A1 (fr) Conceptions de faible débit de codage ldpc pour wlan de prochaine génération
CN113938250B (zh) 用于无线通信的方法及装置
CN121079922A (zh) 用于无线通信中的长ldpc码的提升矩阵设计
WO2019001515A1 (fr) Conception de table de coefficient de décalage de code qc-ldpc pour des tailles de blocs de code plus grandes dans des communications mobiles
WO2019001482A1 (fr) Conception de table de coefficient de décalage de code qc-ldpc pour des tailles de blocs de code plus petites dans des communications mobiles

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18736710

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2018736710

Country of ref document: EP

Effective date: 20190701