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WO2018120997A1 - 主动阵列基板及其制造方法 - Google Patents

主动阵列基板及其制造方法 Download PDF

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Publication number
WO2018120997A1
WO2018120997A1 PCT/CN2017/106320 CN2017106320W WO2018120997A1 WO 2018120997 A1 WO2018120997 A1 WO 2018120997A1 CN 2017106320 W CN2017106320 W CN 2017106320W WO 2018120997 A1 WO2018120997 A1 WO 2018120997A1
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Prior art keywords
layer
dielectric constant
silicon
drain electrode
insulating layer
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PCT/CN2017/106320
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English (en)
French (fr)
Inventor
卓恩宗
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US16/462,000 priority Critical patent/US10672798B2/en
Publication of WO2018120997A1 publication Critical patent/WO2018120997A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs

Definitions

  • the present application relates to a method for fabricating an active array substrate, and more particularly to an active array substrate for a display panel and a method of fabricating the same.
  • the thin film transistor display includes a display panel and a backlight module, and the display panel includes a color filter substrate (CF Substrate, also referred to as a color filter substrate) and a thin film transistor array substrate (Thin Film Transistor Substrate, TFT Substrate).
  • CF Substrate also referred to as a color filter substrate
  • TFT Substrate Thin Film Transistor Substrate
  • a transparent electrode exists on the opposite inner side of the substrate.
  • a layer of liquid crystal molecules (LC) is sandwiched between the two substrates.
  • the display panel controls the orientation of the liquid crystal molecules by an electric field, changes the polarization state of the light, and achieves the purpose of display by the penetration and blocking of the optical path by the polarizing plate.
  • the package density of devices continues to increase, so the performance requirements for various aspects of materials continue to increase. Due to the shrinkage of the device, the thickness of the gate oxide insulating layer of the device is very thin. For devices with a small proportion, the thickness of the gate oxide insulating layer will only become thinner and thinner, which requires a new high-K gate oxide insulation. Dielectric material.
  • the technical problem to be solved by the present application is to provide a method of manufacturing an active array substrate having a large dielectric constant of a gate insulating layer.
  • the present application provides a method for manufacturing an active array substrate, including:
  • the gate insulating layer comprises nanoporous silicon and nanoparticles, and the nanoparticle has a dielectric constant greater than a dielectric constant of the nanoporous silicon.
  • the gate insulating layer includes a stacked first insulating layer and a second insulating layer, and the nanoporous silicon and the nanoparticles are formed in the second insulating layer.
  • the nanoparticles comprise two or more nanoparticles of different dielectric constants.
  • Nanoporous silicon can be made very thin, can reduce the thickness of the insulating dielectric layer, and can meet the ever-decreasing requirements of integrated circuits, chips, and TFT-LCDs.
  • the nanoporous silicon itself is hydrophobic.
  • the dielectric constant of germanium is 16, and the dielectric constant of the gate insulating layer is increased by adjusting the proportion of germanium.
  • other metals and other materials having a high dielectric constant can be used.
  • Nanoporous silicon can be made very thin, which can reduce the thickness of the insulating dielectric layer, and can meet the ever-decreasing requirements of integrated circuits, chips, and TFT-LCDs.
  • the nanoporous silicon itself has hydrophobicity and ⁇ dielectric.
  • the constant is 16, the nanoporous silicon itself has many silicon pores, and the ruthenium nanoparticles can be stored in the silicon pores without increasing the thickness of the nanoporous silicon, and the dielectric constant can be controlled by adjusting the loading amount of the ruthenium nanoparticles Ge.
  • the gate insulating layer comprises nanoporous silicon
  • the nanoporous silicon comprises a plurality of hollow columnar sub-assemblies connected to each other, the sub-assembly has a hexagonal shape, and the sub-assembly has a circular through-hole in the middle
  • the circular via hole of the sub-assembly is provided with a plurality of silicon holes, and the silicon holes are provided with germanium nanoparticles.
  • the hexagonal shape of the porous part of the porous silicon facilitates the splicing and arrangement of a plurality of sub-components, and a plurality of bismuth nanoparticles are disposed in the silicon hole, which does not affect the thickness of the porous silicon.
  • the corresponding gate wire segment on the gate insulating layer is provided with an amorphous silicon layer on the amorphous silicon layer
  • An ohmic contact layer corresponding to the amorphous silicon layer is disposed, the ohmic contact layer is provided with a separated source electrode and a drain electrode, and a channel is disposed between the source electrode and the drain electrode, and the channel passes through the ohm a contact layer, the bottom of the channel is an amorphous silicon layer, the source electrode and the drain electrode have a width greater than a width of the amorphous silicon layer, and the source electrode and the drain electrode are provided with a protective layer, and the protective layer is provided with a protective layer a pixel electrode layer, wherein the protective layer is provided with a via hole corresponding to the drain electrode, and the pixel electrode layer is connected to the drain electrode through the via hole.
  • the corresponding gate wire segment of the gate insulating layer is provided with an amorphous silicon layer
  • the amorphous silicon layer is provided with an ohmic contact layer corresponding to the amorphous silicon layer
  • the ohmic contact layer is provided with a separation a source electrode and a drain electrode
  • a channel is disposed between the source electrode and the drain electrode, the channel passes through the ohmic contact layer, the bottom of the channel is an amorphous silicon layer, and the source electrode and the drain electrode width
  • a width corresponding to the width of the ohmic contact layer, the source electrode and the drain electrode are provided with a protective layer
  • the protective layer is provided with a pixel electrode layer
  • the protective layer is provided with a via hole corresponding to the drain electrode
  • the pixel electrode The layer is connected to the drain electrode through a via.
  • the protective layer has a relative dielectric constant smaller than a relative dielectric constant of silicon nitride and silicon oxide.
  • the use of a low dielectric constant protection layer can improve the performance of thin film transistor TFT devices, improve signal crosstalk problems and RC circuit delay problems.
  • the low dielectric constant protective layer comprises mesoporous silica
  • the thickness of the dielectric constant protective layer of course, the low dielectric constant protective layer may also be other low dielectric constant materials such as nanoporous silicon.
  • the mesoporous silica comprises a plurality of subunits, the subunits comprising sub-components arranged in three rows, the middle row of the sub-units comprising three sub-components side by side, the first row and the The three rows respectively comprise two sub-components side by side, the two sub-components of the first row and the third row are respectively arranged between any two sub-components of the middle row of three sub-components, the sub-components are hexagonal,
  • the sub-member has a circular through hole in the middle.
  • the subunit has the sub-components arranged in an orderly manner, has a high specific surface area, good thermal stability and hydrothermal stability, uniform size of the through-hole of the sub-component, and the hexagonal shape of the sub-component is convenient for splicing of the plurality of sub-components. arrangement.
  • the dielectric constant of the gate insulating layer disposed on the first layer of wires is greater than the dielectric constant of the silicon oxide layer and the silicon nitride layer, increasing the ability of the device to store charge
  • the gate insulating layer includes a composition, and the composition includes the first composition
  • a second composition the dielectric constant of the first composition is smaller than the dielectric constant of the silicon oxide layer and the silicon nitride layer
  • the dielectric constant of the second composition is greater than the dielectric constant of the silicon oxide layer and the silicon nitride layer
  • the dielectric constant of the gate insulating layer is adjusted by adjusting the ratio of the first composition and the second composition.
  • FIG. 1 is a schematic diagram of an active array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of an active array substrate according to an embodiment of the present application.
  • FIG 3 is another schematic diagram of an active array substrate according to an embodiment of the present application.
  • FIG. 4 is a schematic view of a nanoporous silicon according to an embodiment of the present application.
  • FIG. 5 is a schematic view of nanoporous silicon and germanium nanoparticles of an embodiment of the present application.
  • FIG. 6 is a schematic view of mesoporous silica according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a gate insulating layer according to an embodiment of the present application.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection or integral connection; may be mechanical connection or electrical connection; may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two components.
  • a display panel of an embodiment of the present application will be described below with reference to FIGS. 1 through 7.
  • the display panel includes a substrate 10 , and the substrate 10 is provided with a plurality of first layers of wires 21 , and the first layer of wires 21 is provided with a gate insulating layer 22 .
  • the gate insulating layer 22 is made of silicon nitride or silicon oxide, and the gate insulating layer 22 corresponds to the gate of the first layer of the wires 21.
  • the line segment 211 is provided with an amorphous silicon layer 23 on which an ohmic contact layer 24 corresponding to the amorphous silicon layer 23 is provided, and the ohmic contact layer 24 is provided with a separated source electrode 25 and a drain electrode.
  • a channel 27 is disposed between the source electrode 25 and the drain electrode 26, the channel 27 passes through the ohmic contact layer 24, and the bottom of the channel 27 is an amorphous silicon layer 23, the source electrode 25 and The width of the drain electrode 26 is larger than the width of the amorphous silicon layer 23.
  • the source electrode 25 and the drain electrode 26 are provided with a protective layer 30.
  • the protective layer 30 is provided with a pixel electrode layer 50, and the protective layer 30 corresponds to leakage.
  • the pole 26 is provided with a via 28 which is connected to the drain electrode 26 via a via 28 .
  • the source electrode 25 is directly connected to the other side of the gate insulating layer 22 on the side of the amorphous silicon layer 23, and directly connected to the protective layer 30.
  • the gate insulating layer 22 corresponds to the portion between the via 28 and the drain electrode 26. connection. Thin film transistor TFTs obtained using 5Mask have better performance.
  • the display panel includes a substrate 10, and the substrate 10 is provided with a plurality of first layer wires 21, and the first layer wires 21 are provided with a gate insulating layer 22,
  • the gate insulating layer 22 is made of silicon nitride or silicon oxide, and the gate wire segment 211 of the gate insulating layer 22 corresponding to the first layer of the wires 21 is provided with an amorphous silicon layer 23 on the amorphous silicon layer 23.
  • An ohmic contact layer 24 corresponding to the amorphous silicon layer 23 is provided, and the ohmic contact layer 24 is provided with a separated source electrode 25 and a drain electrode 26, and a channel 27 is disposed between the source electrode 25 and the drain electrode 26.
  • the channel 27 passes through the ohmic contact layer 24, the bottom of the channel 27 is an amorphous silicon layer 23, and the width of the source electrode 25 and the drain electrode 26 is larger than the width of the amorphous silicon layer 23, and the source electrode 25
  • a protective layer 30 is disposed on the drain electrode 26, and the protective layer 30 is provided with a pixel electrode layer 50.
  • the protective layer 30 is provided with a via 28 corresponding to the drain electrode 26, and the pixel electrode layer 50 passes through the via 28
  • the drain electrode 26 is connected.
  • the protective layer 30 on the outer side of the source electrode 25 is directly connected to the gate insulating layer 22, and the gate insulating layer 22 is sequentially provided with an amorphous silicon layer 23, an ohmic contact layer 24 and a drain electrode 26 corresponding to the via hole 28. .
  • Thin film transistor TFTs obtained using 4Mask have better performance and can save one-step Mask process.
  • a high-k dielectric constant material is selected as the gate oxide dielectric layer material of the thin film crystal. Due to advances in processes and designs, the size of integrated circuits, chips, and TFT-LCDs continues to decrease, and the package density of devices continues to increase, so the performance requirements for all aspects of materials continue to increase. Due to device ratio For example, the thickness of the gate oxide insulating layer of the device becomes very thin. For devices with a small proportion in the future, the thickness of the gate oxide insulating layer will only become thinner and thinner, which requires a new high-K gate oxide insulating dielectric. material. In the above embodiment, a four-pass process or a five-process TFT-Array array is used.
  • the display panel comprises: a substrate 10; a plurality of first layer conductors 21, wherein the plurality of first layer conductors 21 are disposed at On the substrate 10; a gate insulating layer 22, the gate insulating layer 22 is disposed on the plurality of first layer wires 21, and the dielectric constant of the gate insulating layer 22 is greater than that of the silicon oxide layer and the silicon nitride layer.
  • the electrical constant, the gate insulating layer 22 includes a composition comprising a first composition and a second composition.
  • the gate insulating layer 22 disposed on the first layer of wires 21 has a dielectric constant greater than a dielectric constant of the silicon oxide layer and the silicon nitride layer to increase the device's ability to store charge
  • the gate insulating layer 22 includes a composition, and the composition includes the first a composition and a second composition, the dielectric constant of the first composition is smaller than the dielectric constant of the silicon oxide layer and the silicon nitride layer, and the dielectric constant of the second composition is greater than that of the silicon oxide layer and the silicon nitride layer
  • the electric constant, the dielectric constant of the gate insulating layer 22 is adjusted by adjusting the ratio of the first composition and the second composition.
  • the first composition comprises nanoporous silicon.
  • Nanoporous silicon can be made very thin, can reduce the thickness of the insulating dielectric layer, and can meet the ever-decreasing requirements of integrated circuits, chips, and TFT-LCDs.
  • the nanoporous silicon itself is hydrophobic.
  • the second composition comprises ruthenium nanoparticles.
  • the dielectric constant of germanium is 16, and the dielectric constant of the gate insulating layer 22 is increased by adjusting the ratio of germanium.
  • other metals and other materials having a high dielectric constant can be used.
  • the first composition comprises nanoporous silicon and the second composition comprises ruthenium nanoparticles.
  • Nanoporous silicon can be made very thin, can reduce the thickness of the insulating dielectric layer, can be full The demand for integrated circuits, chips, and TFT-LCDs is decreasing.
  • the nanoporous silicon itself is hydrophobic.
  • the dielectric constant of germanium is 16.
  • the nanoporous silicon itself has many silicon pores, and the germanium nanoparticles can be deposited in silicon. Within the pores, the thickness of the nanoporous silicon is not increased, and the dielectric constant can be controlled by adjusting the loading amount of the germanium nanoparticle Ge.
  • the gate insulating layer 22 includes nanoporous silicon, and the nanoporous silicon includes a plurality of hollow columnar sub-assemblies 221 connected to each other.
  • the sub-assembly 221 has a hexagonal shape, and the sub-assembly 221 has a middle portion.
  • the circular through hole is provided with a plurality of silicon holes on the circular through hole of the sub-assembly 221, and the silicon holes are provided with germanium nanoparticles.
  • the cross-section hexagonal shape of the porous silicon sub-member 42 facilitates the splicing arrangement of the plurality of sub-members 42.
  • the silicon holes are provided with a plurality of bismuth nanoparticles, which do not affect the thickness of the porous silicon.
  • the corresponding gate wire segment 211 of the gate insulating layer 22 is provided with an amorphous silicon layer 23, and the amorphous silicon layer 23 is provided with an ohmic contact layer 24 corresponding to the amorphous silicon layer 23, the ohmic layer.
  • the contact layer 24 is provided with a separate source electrode 25 and a drain electrode 26, and a channel 27 is provided between the source electrode 25 and the drain electrode 26, the channel 27 passing through the ohmic contact layer 24, the channel 27
  • the bottom is an amorphous silicon layer 23, the width of the source electrode 25 and the drain electrode 26 is larger than the width of the amorphous silicon layer 23, and the source electrode 25 and the drain electrode 26 are provided with a second insulation 30, and the second insulation 30
  • a pixel electrode layer 50 is disposed thereon, and the second insulating layer 30 is provided with a via hole 28 corresponding to the drain electrode 26, and the pixel electrode layer 50 is connected to the drain electrode 26 through the via hole 28.
  • the source electrode 25 is directly connected to the other side of the gate insulating layer 22 on the side of the amorphous silicon layer 23, and is directly connected to the low dielectric constant protective layer 40.
  • the gate insulating layer 22 corresponds to the via 28 and the leakage.
  • the poles 26 are connected.
  • a thin film transistor TFT with better performance can be obtained using 5Mask.
  • the display panel comprises: a substrate 10; a plurality of first layer conductors 21, and the plurality of first layer conductors 21 are disposed at On the substrate 10; a gate insulating layer 22, the gate insulating layer 22 is disposed on the plurality of first layer wires 21, and the dielectric constant of the gate insulating layer 22 is greater than that of the silicon oxide layer and the silicon nitride layer.
  • the electrical constant, the gate insulating layer 22 includes a composition comprising a first composition and a second composition.
  • the gate insulating layer 22 disposed on the first layer of wires 21 has a dielectric constant greater than a dielectric constant of the silicon oxide layer and the silicon nitride layer to increase the device's ability to store charge
  • the gate insulating layer 22 includes a composition including a first composition and a second composition, the dielectric constant of the first composition being smaller than the dielectric constant of the silicon oxide layer and the silicon nitride layer, and the dielectric constant of the second composition being greater than that of the silicon oxide layer and the silicon nitride layer
  • the dielectric constant, the dielectric constant of the gate insulating layer 22 is adjusted by adjusting the ratio of the first composition and the second composition.
  • the first composition comprises nanoporous silicon.
  • Nanoporous silicon can be made very thin, can reduce the thickness of the insulating dielectric layer, and can meet the ever-decreasing requirements of integrated circuits, chips, and TFT-LCDs.
  • the nanoporous silicon itself is hydrophobic.
  • the second composition comprises ruthenium nanoparticles.
  • the dielectric constant of germanium is 16, and the dielectric constant of the gate insulating layer 22 is increased by adjusting the ratio of germanium.
  • other metals and other materials having a high dielectric constant can be used.
  • the first composition comprises nanoporous silicon and the second composition comprises ruthenium nanoparticles.
  • Nanoporous silicon can be made very thin, which can reduce the thickness of the insulating dielectric layer, and can meet the ever-decreasing requirements of integrated circuits, chips, and TFT-LCDs.
  • the nanoporous silicon itself has hydrophobicity and ⁇ dielectric.
  • the constant is 16, the nanoporous silicon itself has many silicon pores, and the ruthenium nanoparticles can be stored in the silicon pores without increasing the thickness of the nanoporous silicon, and the dielectric constant can be controlled by adjusting the loading amount of the ruthenium nanoparticles Ge.
  • the gate insulating layer 22 includes nanoporous silicon, and the nanoporous silicon includes a plurality of hollow columnar sub-assemblies 221 connected to each other.
  • the sub-assembly 221 has a hexagonal shape, and the sub-assembly 221 has a middle portion.
  • the circular through hole is provided with a plurality of silicon holes on the circular through hole of the sub-assembly 221, and the silicon holes are provided with germanium nanoparticles.
  • the cross-section hexagonal shape of the porous silicon sub-member 42 facilitates the splicing arrangement of the plurality of sub-members 42.
  • the silicon holes are provided with a plurality of bismuth nanoparticles, which do not affect the thickness of the porous silicon.
  • the corresponding gate wire segment 211 of the gate insulating layer 22 is provided with an amorphous silicon layer 23, and the amorphous silicon layer 23 is provided with an ohmic contact layer 24 corresponding to the amorphous silicon layer 23, the ohmic layer.
  • the contact layer 24 is provided with a separate source electrode 25 and a drain electrode 26, and a channel 27 is provided between the source electrode 25 and the drain electrode 26, the channel 27 passing through the ohmic contact layer 24, the channel 27
  • the bottom is an amorphous silicon layer 23, the source electrode 25 and the drain electrode 26 have a width equal to the width of the ohmic contact layer 24 in contact therewith, and the source electrode 25 and the drain electrode 26 are provided with a second insulation 30, the second a pixel electrode layer 50 is disposed on the insulating layer 30, and the second The insulating layer 30 is provided with a via 28 corresponding to the drain electrode 26, and the pixel electrode layer 50 is connected to the drain electrode 26 via the via 28.
  • the low dielectric constant protection layer 40 on the outer side of the source electrode 25 is directly connected to the gate insulating layer 22, and the gate insulating layer 22 is sequentially provided with an amorphous silicon layer 23 and an ohmic contact layer 24 corresponding to the via hole 28. And drain electrode 26.
  • a thin film transistor TFT can be obtained with a four-mask (Mask), and a one-step mask can be saved.
  • the display panel comprises: a substrate 10; a plurality of first layer wires 21, and the plurality of first layer wires 21 are disposed at On the substrate 10; a gate insulating layer 22, the gate insulating layer 22 is disposed on the plurality of first layer wires 21, and the dielectric constant of the gate insulating layer 22 is greater than that of the silicon oxide layer and the silicon nitride layer.
  • the electrical constant, the gate insulating layer 22 includes a composition comprising a first composition and a second composition.
  • the relative dielectric constant of the second insulation 30 is smaller than the relative dielectric constant of silicon nitride and silicon oxide.
  • the use of a low dielectric constant protection layer can improve the performance of thin film transistor TFT devices, improve signal crosstalk problems and RC circuit delay problems.
  • the corresponding gate wire segment 211 on the gate insulating layer 22 is provided with an amorphous silicon layer 23, and the amorphous silicon layer 23 is provided with an ohmic contact layer 24 corresponding to the amorphous silicon layer 23.
  • the ohmic contact layer 24 is provided with a separated source electrode 25 and a drain electrode 26, and a channel 27 is disposed between the source electrode 25 and the drain electrode 26, and the channel 27 passes through the ohmic contact layer 24,
  • the bottom of the channel 27 is an amorphous silicon layer 23, the width of the source electrode 25 and the drain electrode 26 is greater than the width of the amorphous silicon layer 23, and the source electrode 25 and the drain electrode 26 are provided with a second insulation 30.
  • the second insulating layer 30 is provided with a pixel electrode layer 50.
  • the second insulating layer 30 is provided with a via hole 28 corresponding to the drain electrode 26, and the pixel electrode layer 50 is connected to the drain electrode 26 through the via hole 28.
  • the source electrode 25 is directly connected to the other side of the gate insulating layer 22 on the other side of the amorphous silicon layer 23, and is directly connected to the low dielectric constant protective layer.
  • the gate insulating layer 22 corresponds to the via 28 portion and the drain electrode. 26 connections.
  • the corresponding gate wire segment 211 on the gate insulating layer 22 is provided with an amorphous silicon layer 23, and the amorphous silicon layer 23 is provided with an ohmic contact layer 24 corresponding to the amorphous silicon layer 23.
  • the ohmic contact layer 24 is provided with a separated source electrode 25 and a drain electrode 26, and the source electrode 25 and the drain electrode 26 are disposed between a channel 27, the channel 27 passes through the ohmic contact layer 24, the bottom of the channel 27 is an amorphous silicon layer 23, and the width of the source electrode 25 and the drain electrode 26 is equal to the width of the ohmic contact layer 24 in contact therewith,
  • a second insulation 30 is disposed on the source electrode 25 and the drain electrode 26, and a pixel electrode layer 50 is disposed on the second insulation 30.
  • the second insulation 30 is provided with a via 28 corresponding to the drain electrode 26.
  • the electrode layer 50 is connected to the drain electrode 26 through the via 28 .
  • the low dielectric constant protective layer on the outer side of the source electrode 25 is directly connected to the gate insulating layer 22, and the gate insulating layer 22 is sequentially provided with an amorphous silicon layer 23, an ohmic contact layer 24, and Leakage electrode 26.
  • the low dielectric constant protective layer comprises mesoporous silicon oxide.
  • the thickness of the dielectric constant protective layer of course, the low dielectric constant protective layer may also be other low dielectric constant materials such as nanoporous silicon.
  • the mesoporous silica comprises a plurality of sub-units 43 comprising sub-components 42 arranged in three rows, the middle row of the sub-units 43 comprising three sub-components 42 arranged side by side, the sub-unit 43
  • the first row and the third row respectively include two sub-components 42 side by side, and the two sub-components 42 of the first row and the third row are respectively disposed between any two sub-components 42 of the middle row of three sub-components 42.
  • the sub-member 42 has a hexagonal shape and a circular through hole in the middle of the sub-assembly 42.
  • the subunit 43 has a regularly arranged sub-assembly 42 having a high specific surface area, good thermal stability and hydrothermal stability, a uniform through-hole size of the sub-member 42, and a hexagonal shape of the sub-part 42.
  • a plurality of sub-assemblies 42 are arranged in series.
  • the amorphous silicon layer is made of an a-Si material, and of course other semiconductor layer materials may be used.
  • the gate insulating layer 22 may include a stacked first insulating layer 221 and a second insulating layer 222 .
  • the first insulating layer 221 may have no nanoparticles, such as a silicon nitride compound (SiNx) insulating layer, and the nanoporous silicon and nanoparticles are formed in the second insulating layer 222.
  • SiNx silicon nitride compound
  • the material adjustment of the layer 221 and the second insulating layer 222 can further adjust the dielectric constant of the gate insulating layer 22.
  • the nanoparticles can include two or more nanoparticles of different dielectric constants.
  • the dielectric constant of the gate insulating layer 22 can be further adjusted by nanoparticle adjustment of different dielectric constants.
  • the material of the substrate may be glass, plastic or the like.
  • the display panel includes a liquid crystal panel, an OLED panel, a curved panel, a plasma panel, and the like.
  • the liquid crystal panel includes an array substrate and a color filter substrate (CF), and the array substrate is opposite to the color filter substrate.
  • a liquid crystal and a photo spacer (PS) are disposed between the array substrate and the color filter substrate, and a thin film transistor (TFT) is disposed on the array substrate, and a color filter layer is disposed on the color ink substrate.
  • PS photo spacer
  • TFT thin film transistor
  • the color filter substrate may include a TFT array
  • the color film and the TFT array may be formed on the same substrate, and the array may substantially include a color filter layer.
  • the display panel of the present application may be a curved type panel.

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Abstract

一种主动阵列基板及其制造方法，制造方法包括：提供基板(10)；形成栅极于基板(10)上；依序形成栅极绝缘层(22)、半导体层及欧姆接触层(24)于透明基材及所述栅极上；形成源电极(25)及漏电极(26)于所述欧姆接触层(24)上；形成保护层(30)于所述源电极(25)及所述漏电极(26)上；以及形成像素电极层(50)于所述保护层(30)上，其中所述像素电极层(50)是电性连接于所述漏电极(26)；其中，所述栅极绝缘层(22)包括纳米多孔硅及纳米颗粒，所述纳米颗粒的介电常数大于纳米多孔硅的介电常数。

Description

主动阵列基板及其制造方法 【技术领域】
本申请涉及主动阵列基板的制造方法，更具体的说，涉及一种显示面板的主动阵列基板及其制造方法。
【背景技术】
薄膜晶体管显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，目前已经逐渐占据了显示领域的主导地位。同样，薄膜晶体管显示器包含显示面板和背光模组，显示面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)和薄膜晶体管阵列基板(Thin Film Transistor Substrate，TFT Substrate)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(Liquid Crystal，LC)。显示面板是通过电场对液晶分子取向的控制，改变光的偏振状态，并藉由偏光板实现光路的穿透与阻挡，实现显示的目的。
由于集成电路、芯片以及TFT-LCD的尺寸不断的减小，器件的封装密度不停的增大，因此对材料各方面性能的要求不断的提高。由于器件的比例缩小，目前器件的栅氧绝缘层厚度变得非常薄，对于比例小的器件而言，栅氧绝缘层厚度只会越来越薄，这需要有新的高K的栅氧绝缘介电材料。
【发明内容】
本申请所要解决的技术问题是提供一种栅极绝缘层的介电常数大的主动阵列基板的制造方法。
本申请提供一种主动阵列基板的制造方法，其特征在于，包括：
提供基板；
形成栅极于基板上；
依序形成栅极绝缘层、半导体层及欧姆接触层于所述透明基材及所述栅极 上；
形成源电极及漏电极于所述欧姆接触层上；
形成保护层于所述源电极及所述漏电极上；以及
形成像素电极层于所述保护层上，其中所述像素电极层是电性连接于所述漏电极；
其中，所述栅极绝缘层包括纳米多孔硅及纳米颗粒，所述纳米颗粒的介电常数大于纳米多孔硅的介电常数。
在一些实施例中，所述栅极绝缘层包括堆叠的第一绝缘层及第二绝缘层，所述纳米多孔硅及所述纳米颗粒是形成于所述第二绝缘层中。
在一些实施例中，纳米颗粒包括二种以上不同介电常数的纳米颗粒。
纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满足集成电路、芯片以及TFT-LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性。
锗的介电常数为16，通过调节锗的比例提高栅极绝缘层的介电常数，当然也可以采用其他介电常数高的金属和其他材料。
纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满足集成电路、芯片以及TFT-LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性，锗的介电常数为16，纳米多孔硅本身具有很多硅孔，锗纳米颗粒可以存入硅孔内，不会增加通过纳米多孔硅的厚度，通过调节锗纳米颗粒Ge的负载量实现介电系数可控调节。
其中，所述栅极绝缘层包括纳米多孔硅，所述纳米多孔硅包括多个彼此连接的空心柱状的子组件，所述子组件切面为六边形，所述子组件中间具有圆形通孔，所述子组件的圆形通孔上设有多个硅孔，所述硅孔内设有锗纳米颗粒。
多孔硅的子部件切面六边形方便多个子部件拼接排列，硅孔内设有多个锗纳米颗粒，不影响多孔硅厚度。
其中，所述栅极绝缘层上对应栅极导线段设有非晶硅层，所述非晶硅层上 设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源电极和漏电极，所述源电极和漏电极之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源电极和漏电极宽度大于非晶硅层的宽度，所述源电极和漏电极上设有保护层，所述保护层上设有像素电极层，所述保护层对应漏电极设有过孔，所述像素电极层通过过孔与漏电极连接。
其中，所述栅极绝缘层上对应栅极导线段设有非晶硅层，所述非晶硅层上设有与非晶硅层对应的欧姆接触层，所述欧姆接触层上设有分隔的源电极和漏电极，所述源电极和漏电极之间设有沟道，所述沟道穿过欧姆接触层，所述沟道底部为非晶硅层，所述源电极和漏电极宽度等于与其接触的欧姆接触层的宽度，所述源电极和漏电极上设有保护层，所述保护层上设有像素电极层，所述保护层对应漏电极设有过孔，所述像素电极层通过过孔与漏电极连接。
其中，所述保护层的相对介电常数小于氮化硅和氧化硅的相对介电常数。
采用低介电常数保护层可以提高薄膜晶体管TFT器件性能，改善信号串扰问题和RC电路延时问题。
其中，所述低介电常数保护层包括介孔氧化硅
介孔氧化硅的相对介电常数εr＝1.4～2.4，低介电常数保护层采用介孔氧化硅取代5-mask与4-mask工艺TFT器件中的保护层材料SiNx(相对介电常数εr＝7～8)，介孔氧化硅比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，可以提高TFT器件性能，改善信号串扰问题和RC电路延时问题，减小低介电常数保护层的厚度，当然低介电常数保护层也可以采用其他低介电常数的材料，如纳米多孔硅等。
其中，所述介孔氧化硅包括多个子单元，所述子单元包括成三行排列的子部件，所述子单元的中间一行包括并排的三个子部件，所述子单元的第一行和第三行分别包括并排的两个子部件，所述第一行和第三行的两个子部件分别设置在中间一行三个子部件的任意两个子部件之间，所述子部件切面为六边形，所述子部件中间具有圆形通孔。
子单元具有排列规则有序的子部件，具有较高的比表面积，较好的热稳定性和水热稳定性,子部件通孔大小均匀，子部件切面为六边形，方便多个子部件拼接排列。
第一层导线上设置的栅极绝缘层介电常数大于氧化硅层和氮化硅层的介电常数，增大器件存储电荷能力，栅极绝缘层包括组合物，组合物包括第一组成物和第二组成物，第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数，通过调节第一组成物和第二组成物的比例实现栅极绝缘层的介电常数可调。
【附图说明】
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例一种主动阵列基板的示意图；
图2是本申请实施例一种主动阵列基板的示意图；
图3是本申请实施例一种主动阵列基板的另一示意图；
图4是本申请实施例纳米多孔硅示意图；
图5是本申请实施例纳米多孔硅和锗纳米颗粒示意图；
图6是本申请实施例介孔氧化硅示意图；
图7是本申请一实施例栅极绝缘层的示意图。
【具体实施方式】
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并 且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或组件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个组件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和较佳的实施例对本申请作进一步说明。
下面参考图1至图7描述本申请实施例的显示面板。
如图1所示，在图1的实施中显示面板包括基板10，所述基板10上设有若干条第一层导线21，所述第一层导线21上设有栅极绝缘层22，所述栅极绝缘层22采用氮化硅或氧化硅，所述栅极绝缘层22上对应第一层导线21的栅极导 线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源电极25和漏电极26，所述源电极25和漏电极26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源电极25和漏电极26的宽度大于非晶硅层23的宽度，所述源电极25和漏电极26上设有保护层30，所述保护层30上设有像素电极层50，所述保护层30对应漏电极26设有过孔28，所述像素电极层50通过过孔28与漏电极26连接。其中，所述源电极25超出非晶硅层23部分一侧直接连接栅极绝缘层22另一侧直接连接保护层30，所述栅极绝缘层22对应过孔28部分与漏电极26之间连接。使用5Mask获取的薄膜晶体管TFT，具有较好的性能。
如图2所示，在图2的实施中显示面板包括基板10，所述基板10上设有若干条第一层导线21，所述第一层导线21上设有栅极绝缘层22，所述栅极绝缘层22采用氮化硅或氧化硅，所述栅极绝缘层22上对应第一层导线21的栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源电极25和漏电极26，所述源电极25和漏电极26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源电极25和漏电极26宽度大于非晶硅层23的宽度，所述源电极25和漏电极26上设有保护层30，所述保护层30上设有像素电极层50，所述保护层30对应漏电极26设有过孔28，所述像素电极层50通过过孔28与漏电极26连接。其中，所述源电极25外侧的保护层30直接与栅极绝缘层22连接，所述栅极绝缘层22对应过孔28上方依次设有非晶硅层23、欧姆接触层24和漏电极26。使用4Mask获取的薄膜晶体管TFT具有较好的性能，而且可以节省一步Mask工艺。
一般的，选用高K介电常数材料作为薄膜晶体的栅氧介电层材料。由于工艺和设计的进步，集成电路、芯片以及TFT-LCD的尺寸不断的减小，器件的封装密度不停的增大，因此对材料各方面性能的要求不断的提高。由于器件的比 例缩小，目前器件的栅氧绝缘层厚度变得非常薄，对于未来比例小的器件而言，栅氧绝缘层厚度只会越来越薄，这需要有新的高K的栅氧绝缘介电材料。上述实施例采用的四道工艺或五道工艺TFT-Array阵列，在TFT晶体管中，栅介电极与上级的绝缘保护层之间存在很高的电压。栅氧层会受到隧穿电流的影响，当栅极的栅极绝缘层很薄时，电子会在薄膜晶体管中隧穿通过栅极绝缘层。这将导致晶体管阀值电压的漂移，无法切换开关状态导致电路失效。传统的栅氧绝缘介电材料(如SiO2、SiNx)已不满足当前TFT-LCD器件高封装密度发展的需要。
如图3、图4和图5所示，在图3、图4和图5的实施中显示面板包括：基板10；若干条第一层导线21，所述若干条第一层导线21设置在基板10上；栅极绝缘层22，所述栅极绝缘层22设置在若干条第一层导线21上，所述栅极绝缘层22的介电常数大于氧化硅层和氮化硅层的介电常数，所述栅极绝缘层22包括组合物，所述组合物包括第一组成物和第二组成物。
第一层导线21上设置的栅极绝缘层22介电常数大于氧化硅层和氮化硅层的介电常数，增大器件存储电荷能力，栅极绝缘层22包括组合物，组合物包括第一组成物和第二组成物，第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数，通过调节第一组成物和第二组成物的比例实现栅极绝缘层22的介电常数可调。
可选的，其中，所述第一组成物包括纳米多孔硅。纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满足集成电路、芯片以及TFT-LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性。
可选的，其中，所述第二组成物包括锗纳米颗粒。锗的介电常数为16，通过调节锗的比例提高栅极绝缘层22的介电常数，当然也可以采用其他介电常数高的金属和其他材料。
可选的，其中，所述第一组成物包括纳米多孔硅，所述第二组成物包括锗纳米颗粒。纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满 足集成电路、芯片以及TFT-LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性，锗的介电常数为16，纳米多孔硅本身具有很多硅孔，锗纳米颗粒可以存入硅孔内，不会增加通过纳米多孔硅的厚度，通过调节锗纳米颗粒Ge的负载量实现介电系数可控调节。
其中，所述栅极绝缘层22包括纳米多孔硅，所述纳米多孔硅包括多个彼此连接的空心柱状的子组件221，所述子组件221切面为六边形，所述子组件221中间具有圆形通孔，所述子组件221的圆形通孔上设有多个硅孔，所述硅孔内设有锗纳米颗粒。多孔硅的子部件42切面六边形方便多个子部件42拼接排列，硅孔内设有多个锗纳米颗粒，不影响多孔硅厚度。
其中，所述栅极绝缘层22上对应栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源电极25和漏电极26，所述源电极25和漏电极26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源电极25和漏电极26宽度大于非晶硅层23的宽度，所述源电极25和漏电极26上设有第二绝缘30，所述第二绝缘30上设有像素电极层50，所述第二绝缘30对应漏电极26设有过孔28，所述像素电极层50通过过孔28与漏电极26连接。其中，所述源电极25超出非晶硅层23部分一侧直接连接栅极绝缘层22另一侧直接连接低介电常数保护层40，所述栅极绝缘层22对应过孔28部分与漏电极26之间连接。使用5Mask可以获取更好性能的薄膜晶体管TFT。
如图2、图4和图5所示，在图2、图4和图5的实施中显示面板包括：基板10；若干条第一层导线21，所述若干条第一层导线21设置在基板10上；栅极绝缘层22，所述栅极绝缘层22设置在若干条第一层导线21上，所述栅极绝缘层22的介电常数大于氧化硅层和氮化硅层的介电常数，所述栅极绝缘层22包括组合物，所述组合物包括第一组成物和第二组成物。
第一层导线21上设置的栅极绝缘层22介电常数大于氧化硅层和氮化硅层的介电常数，增大器件存储电荷能力，栅极绝缘层22包括组合物，组合物包括 第一组成物和第二组成物，第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数，通过调节第一组成物和第二组成物的比例实现栅极绝缘层22的介电常数可调。
可选的，其中，所述第一组成物包括纳米多孔硅。纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满足集成电路、芯片以及TFT-LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性。
可选的，其中，所述第二组成物包括锗纳米颗粒。锗的介电常数为16，通过调节锗的比例提高栅极绝缘层22的介电常数，当然也可以采用其他介电常数高的金属和其他材料。
可选的，其中，所述第一组成物包括纳米多孔硅，所述第二组成物包括锗纳米颗粒。纳米多孔硅可以做的非常薄，可以减小绝缘介电层的厚度，可以满足集成电路、芯片以及TFT-LCD的尺寸不断的减小的需求，纳米多孔硅本身具有疏水性，锗的介电常数为16，纳米多孔硅本身具有很多硅孔，锗纳米颗粒可以存入硅孔内，不会增加通过纳米多孔硅的厚度，通过调节锗纳米颗粒Ge的负载量实现介电系数可控调节。
其中，所述栅极绝缘层22包括纳米多孔硅，所述纳米多孔硅包括多个彼此连接的空心柱状的子组件221，所述子组件221切面为六边形，所述子组件221中间具有圆形通孔，所述子组件221的圆形通孔上设有多个硅孔，所述硅孔内设有锗纳米颗粒。多孔硅的子部件42切面六边形方便多个子部件42拼接排列，硅孔内设有多个锗纳米颗粒，不影响多孔硅厚度。
其中，所述栅极绝缘层22上对应栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源电极25和漏电极26，所述源电极25和漏电极26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源电极25和漏电极26宽度等于与其接触的欧姆接触层24的宽度，所述源电极25和漏电极26上设有第二绝缘30，所述第二绝缘30上设有像素电极层50，所述第二 绝缘30对应漏电极26设有过孔28，所述像素电极层50通过过孔28与漏电极26连接。其中，所述源电极25外侧的低介电常数保护层40直接与栅极绝缘层22连接，所述栅极绝缘层22对应过孔28上方依次设有非晶硅层23、欧姆接触层24和漏电极26。使用4道光罩(Mask)可以获取更好性能的薄膜晶体管TFT，而且节省一步光罩(Mask)。
如图2、图3和图6所示，在图2、图3和图6的实施中显示面板包括：基板10；若干条第一层导线21，所述若干条第一层导线21设置在基板10上；栅极绝缘层22，所述栅极绝缘层22设置在若干条第一层导线21上，所述栅极绝缘层22的介电常数大于氧化硅层和氮化硅层的介电常数，所述栅极绝缘层22包括组合物，所述组合物包括第一组成物和第二组成物。
其中，所述第二绝缘30的相对介电常数小于氮化硅和氧化硅的相对介电常数。采用低介电常数保护层可以提高薄膜晶体管TFT器件性能，改善信号串扰问题和RC电路延时问题。
可选的，其中，所述栅极绝缘层22上对应栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源电极25和漏电极26，所述源电极25和漏电极26之间设有沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源电极25和漏电极26宽度大于非晶硅层23的宽度，所述源电极25和漏电极26上设有第二绝缘30，所述第二绝缘30上设有像素电极层50，所述第二绝缘30对应漏电极26设有过孔28，所述像素电极层50通过过孔28与漏电极26连接。其中，所述源电极25超出非晶硅层23部分一侧直接连接栅极绝缘层22另一侧直接连接低介电常数保护层，所述栅极绝缘层22对应过孔28部分与漏电极26之间连接。
可选的，其中，所述栅极绝缘层22上对应栅极导线段211设有非晶硅层23，所述非晶硅层23上设有与非晶硅层23对应的欧姆接触层24，所述欧姆接触层24上设有分隔的源电极25和漏电极26，所述源电极25和漏电极26之间设有 沟道27，所述沟道27穿过欧姆接触层24，所述沟道27底部为非晶硅层23，所述源电极25和漏电极26宽度等于与其接触的欧姆接触层24的宽度，所述源电极25和漏电极26上设有第二绝缘30，所述第二绝缘30上设有像素电极层50，所述第二绝缘30对应漏电极26设有过孔28，所述像素电极层50通过过孔28与漏电极26连接。其中，所述源电极25外侧的低介电常数保护层直接与栅极绝缘层22连接，所述栅极绝缘层22对应过孔28上方依次设有非晶硅层23、欧姆接触层24和漏电极26。
其中，所述低介电常数保护层包括介孔氧化硅。介孔氧化硅的相对介电常数εr＝1.4～2.4，低介电常数保护层采用介孔氧化硅取代5-mask与4-mask工艺TFT器件中的保护层材料SiNx(相对介电常数εr＝7～8)，介孔氧化硅比一般氧化硅(相对介电常数εr＝3.9～4.1)的εr更低，可以提高TFT器件性能，改善信号串扰问题和RC电路延时问题，减小低介电常数保护层的厚度，当然低介电常数保护层也可以采用其他低介电常数的材料，如纳米多孔硅等。
其中，所述介孔氧化硅包括多个子单元43，所述子单元43包括成三行排列的子部件42，所述子单元43的中间一行包括并排的三个子部件42，所述子单元43的第一行和第三行分别包括并排的两个子部件42，所述第一行和第三行的两个子部件42分别设置在中间一行三个子部件42的任意两个子部件42之间，所述子部件42切面为六边形，所述子部件42中间具有圆形通孔。子单元43具有排列规则有序的子部件42，具有较高的比表面积，较好的热稳定性和水热稳定性,子部件42通孔大小均匀，子部件42切面为六边形，方便多个子部件42拼接排列。
在上述实施例中，非晶硅层采用a-Si材料，当然也可以采用其他半导体层材料。
如图7所示，在一些实施例中，栅极绝缘层22可包括堆叠的第一绝缘层221及第二绝缘层222。第一绝缘层221可不具有纳米颗粒，例如为氮硅化合物(SiNx)绝缘层，而纳米多孔硅及纳米颗粒是形成于第二绝缘层222中。通过第一绝缘 层221及第二绝缘层222的材料调整，可进一步调整栅极绝缘层22的介电常数。
在一些实施例中，纳米颗粒可包括二种以上不同介电常数的纳米颗粒。通过不同介电常数的纳米颗粒调整，可进一步调整栅极绝缘层22的介电常数。
在上述实施例中，所述基板的材料可以选用玻璃、塑料等。
在上述实施例中，显示面板包括液晶面板、OLED面板，曲面面板，等离子面板等，以液晶面板为例，液晶面板包括阵列基板和彩膜基板(CF)，所述阵列基板与彩膜基板相对设置，所述阵列基板与彩膜基板之间设有液晶和间隔单元(photo spacer，PS)，所述阵列基板上设有薄膜晶体管(TFT)，彩墨基板上设有彩色滤光层。
在上述实施例中，彩膜基板可包括TFT阵列，彩膜及TFT阵列可形成于同一基板上，阵列基本可包括彩色滤光层。
在上述实施例中，本申请的显示面板可为曲面型面板。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (19)

  1. 一种主动阵列基板的制造方法，包括：
    提供基板；
    形成栅极于基板上；
    依序形成栅极绝缘层、半导体层及欧姆接触层于所述透明基材及所述栅极上；
    形成源电极及漏电极于所述欧姆接触层上；
    形成保护层于所述源电极及所述漏电极上；以及
    形成像素电极层于所述保护层上，其中所述像素电极层是电性连接于所述漏电极；
    其中，所述栅极绝缘层包括纳米多孔硅及纳米颗粒，所述纳米颗粒的介电常数大于纳米多孔硅的介电常数。
  2. 如权利要求1所述的一种主动阵列基板的制造方法，其中所述纳米颗粒包括锗纳米颗粒。
  3. 如权利要求1所述的一种主动阵列基板的制造方法，其中所述纳米多孔硅包括多个彼此连接的空心柱状的子组件，所述子组件切面为六边形，所述子组件中间具有圆形通孔，所述子组件的圆形通孔上设有多个硅孔，所述硅孔内设有所述纳米颗粒。
  4. 如权利要求1所述的一种主动阵列基板的制造方法，其中所述源电极和漏电极上设有保护层，所述保护层上设有像素电极层，所述保护层对应漏电极设有过孔，所述像素电极层通过过孔与漏电极连接。
  5. 如权利要求4所述的一种主动阵列基板的制造方法，其中所述保护层的相对介电常数小于纳米多孔硅的相对介电常数。
  6. 如权利要求1所述的一种主动阵列基板的制造方法，其中所述栅极绝缘层包括堆叠的第一绝缘层及第二绝缘层，所述纳米多孔硅及所述纳米颗粒是形 成于所述第二绝缘层中。
  7. 如权利要求1所述的一种主动阵列基板的制造方法，其中纳米颗粒包括二种以上不同介电常数的纳米颗粒。
  8. 如权利要求1所述的一种主动阵列基板的制造方法，其中所述栅极绝缘层包括组合物，所述组合物包括第一组成物和第二组成物，所述第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，所述第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数
  9. 如权利要求8所述的一种主动阵列基板的制造方法，其中所述第一组成物包括纳米多孔硅，所述第二组成物包括锗纳米颗粒。
  10. 一种主动阵列基板的制造方法，包括：
    提供基板；
    形成栅极于基板上；
    依序形成栅极绝缘层、半导体层及欧姆接触层于所述透明基材及所述栅极上；
    形成源电极及漏电极于所述欧姆接触层上；
    形成保护层于所述源电极及所述漏电极上；以及
    形成像素电极层于所述保护层上，其中所述像素电极层是电性连接于所述漏电极；
    其中，所述栅极绝缘层包括纳米多孔硅及纳米颗粒，所述纳米颗粒的介电常数大于纳米多孔硅的介电常数；
    其中，所述源电极和漏电极上设有保护层，所述保护层上设有像素电极层，所述保护层对应漏电极设有过孔，所述像素电极层通过过孔与漏电极连接，所述保护层的相对介电常数小于纳米多孔硅的相对介电常数；
    其中，所述栅极绝缘层包括堆叠的第一绝缘层及第二绝缘层，所述纳米多孔硅及所述纳米颗粒是形成于所述第二绝缘层中；
    其中，纳米颗粒包括二种以上不同介电常数的纳米颗粒。
  11. 一种主动阵列基板，包括：
    基板；
    若干条第一层导线，所述第一层导线设置在所述基板上，所述第一层导线包括透明基材和栅极，所述第一层导线上依序设置有栅极绝缘层、半导体层及欧姆接触层；
    源电极及漏电极，设置于所述欧姆接触层上；
    保护层，设置于所述源电极及所述漏电极上；以及
    像素电极层，设置于所述保护层上，所述像素电极层是电性连接于所述漏电极；
    其中，所述栅极绝缘层包括纳米多孔硅及纳米颗粒，所述纳米颗粒的介电常数大于纳米多孔硅的介电常数。
  12. 如权利要求11所述的一种主动阵列基板，其中所述纳米颗粒包括锗纳米颗粒。
  13. 如权利要求11所述的一种主动阵列基板，其中所述纳米多孔硅包括多个彼此连接的空心柱状的子组件，所述子组件切面为六边形，所述子组件中间具有圆形通孔，所述子组件的圆形通孔上设有多个硅孔，所述硅孔内设有所述纳米颗粒。
  14. 如权利要求11所述的一种主动阵列基板，其中所述源电极和漏电极上设有保护层，所述保护层上设有像素电极层，所述保护层对应漏电极设有过孔，所述像素电极层通过过孔与漏电极连接。
  15. 如权利要求14所述的一种主动阵列基板，其中所述保护层的相对介电常数小于纳米多孔硅的相对介电常数。
  16. 如权利要求11所述的一种主动阵列基板，其中所述栅极绝缘层包括堆叠的第一绝缘层及第二绝缘层，所述纳米多孔硅及所述纳米颗粒是形成于所述第二绝缘层中。
  17. 如权利要求11所述的一种主动阵列基板，其中纳米颗粒包括二种以上 不同介电常数的纳米颗粒。
  18. 如权利要求11所述的一种主动阵列基板，其中所述栅极绝缘层包括组合物，所述组合物包括第一组成物和第二组成物，所述第一组成物的介电常数小于氧化硅层和氮化硅层的介电常数，所述第二组成物的介电常数大于氧化硅层和氮化硅层的介电常数
  19. 如权利要求18所述的一种主动阵列基板，其中所述第一组成物包括纳米多孔硅，所述第二组成物包括锗纳米颗粒。
PCT/CN2017/106320 2016-12-30 2017-10-16 主动阵列基板及其制造方法 Ceased WO2018120997A1 (zh)

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