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WO2018120676A1 - 一种像素充电方法、电路、液晶显示屏及液晶显示装置 - Google Patents

一种像素充电方法、电路、液晶显示屏及液晶显示装置 Download PDF

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Publication number
WO2018120676A1
WO2018120676A1 PCT/CN2017/089086 CN2017089086W WO2018120676A1 WO 2018120676 A1 WO2018120676 A1 WO 2018120676A1 CN 2017089086 W CN2017089086 W CN 2017089086W WO 2018120676 A1 WO2018120676 A1 WO 2018120676A1
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Prior art keywords
time
charging
period
pixels
driving signal
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Ceased
Application number
PCT/CN2017/089086
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English (en)
French (fr)
Inventor
王明良
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US15/562,345 priority Critical patent/US10388241B2/en
Publication of WO2018120676A1 publication Critical patent/WO2018120676A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present application relates to the field of liquid crystal display technologies, and in particular, to a pixel charging method, a circuit, a liquid crystal display, and a liquid crystal display device.
  • the gate drive voltage VGH of the TFT is chamfered, but when the pixel is precharged, the scan voltage waveform of the scan line is processed due to the chamfering process.
  • the scanning potential is lowered, so that the TFT is not turned on sufficiently during charging, thereby affecting the charging effect of the pixel, thereby further reducing the actual effect of pre-charge to some extent.
  • the present application provides a pixel charging method and circuit capable of improving pixel charging effects.
  • an embodiment of the present application provides a pixel charging method, where the method includes:
  • a first driving signal for turning on an active switch of the Nth row of scanning lines, precharging and charging the Nth row of pixels, wherein the first driving signal has no chamfering in a preset first time period, the pre The first time period includes a period of time before the completion of the pre-charging of the pixel in the Nth row and a period of time after the completion, the first driving signal has a chamfer angle in a preset second time period, and the preset second time
  • the segment includes a period of time before the pixel charging of the Nth row is completed, and the N is a natural number;
  • the preset third time period includes a period of time before the completion of the pre-charging of the pixel of the (N+1)th line and a period of time after the completion of the second driving signal, and the second driving signal has a chamfer angle in the preset fourth time period.
  • the preset fourth time period includes a period of time before the charging of the (N+1)th row of pixels is completed, and a difference between a time point at which the pixel of the Nth row is completed and a time point when the second driving signal is outputted is positive It is equal to or smaller than the precharge time of the (N+1)th row of pixels.
  • an embodiment of the present application provides a pixel charging circuit, where the pixel charging circuit includes:
  • a scan driving circuit outputting a first driving signal for turning on an active switch of the Nth row of scanning lines, and outputting a second driving signal for turning on a switch of the (N+1th)th scanning line;
  • a data driving circuit precharging and charging the Nth row of pixels when the first driving signal is output, and precharging and charging the N+1th row of pixels when the second driving signal is outputting;
  • the first driving signal has no chamfering in a preset first time period, and the preset first time period includes a period of time before the completion of the pre-charging of the pixel in the Nth row and a period of time after completion.
  • the first driving signal has a chamfer in a preset second time period, and the preset second time period includes a period of time before the charging of the Nth row of pixels is completed, and the N is a natural number;
  • the second driving signal has no chamfering in a preset third time period, and the preset third time period includes a period of time before the completion of the pre-charging of the (N+1)th row of pixels and a period of time after completion.
  • the second driving signal has a chamfer in a preset fourth time period, and the preset fourth time period includes a period of time before the charging of the (N+1)th row of pixels is completed, and the charging time of the Nth row of pixels is completed.
  • the difference between the point and the time point at which the second driving signal is output is positive and equal to or smaller than the pre-charging time of the (N+1)th row of pixels.
  • the embodiment of the present application provides a liquid crystal display including a pixel charging circuit, wherein the pixel charging circuit includes:
  • a scan driving circuit outputting a first driving signal for turning on an active switch of the Nth row of scanning lines, and outputting a second driving signal for turning on a switch of the (N+1th)th scanning line;
  • a data driving circuit precharging and charging the Nth row of pixels when the first driving signal is output, and precharging and charging the N+1th row of pixels when the second driving signal is outputting;
  • the first driving signal has no chamfering in a preset first time period, and the preset first time period includes a period of time before the completion of the pre-charging of the pixel in the Nth row and a period of time after completion.
  • the first driving signal has a chamfer in a preset second time period, and the preset second time period includes a period of time before the charging of the Nth row of pixels is completed, and the N is a natural number;
  • the second driving signal has no chamfering in a preset third time period, and the preset third time period includes a period of time before the completion of the pre-charging of the (N+1)th row of pixels and a period of time after completion.
  • the second driving signal has a chamfer in a preset fourth time period, and the preset fourth time period includes a period of time before the charging of the (N+1)th row of pixels is completed, and the charging time of the Nth row of pixels is completed.
  • the difference between the point and the time point at which the second driving signal is output is positive and equal to or smaller than the pre-charging time of the (N+1)th row of pixels.
  • the embodiment of the present application provides a liquid crystal display device, where the liquid crystal display device includes a liquid crystal display, wherein the liquid crystal display includes a pixel charging circuit, and the pixel charging circuit includes:
  • a scan driving circuit outputting a first driving signal for turning on an active switch of the Nth row of scanning lines, and outputting a second driving signal for turning on a switch of the (N+1th)th scanning line;
  • a data driving circuit precharging and charging the Nth row of pixels when the first driving signal is output, and precharging and charging the N+1th row of pixels when the second driving signal is outputting;
  • the first driving signal has no chamfering in a preset first time period, and the preset first time period includes a period of time before the completion of the pre-charging of the pixel in the Nth row and a period of time after completion.
  • the first driving signal has a chamfer in a preset second time period, and the preset second time period includes a period of time before the charging of the Nth row of pixels is completed, and the N is a natural number;
  • the second driving signal has no chamfering in a preset third time period, and the preset third time period includes a period of time before the completion of the pre-charging of the (N+1)th row of pixels and a period of time after completion.
  • the second driving signal has a chamfer in a preset fourth time period, and the preset fourth time period includes a period of time before the charging of the (N+1)th row of pixels is completed, and the charging time of the Nth row of pixels is completed.
  • the difference between the point and the time point at which the second driving signal is output is positive and equal to or smaller than the pre-charging time of the (N+1)th row of pixels.
  • the application pre-charges and charges the pixels by driving the adjacent two rows of scanning lines by two driving signals respectively, pre-charging the pixels of the next row when one row of pixels is charged, charging the pixels immediately after the pre-charging is finished, and before and after the pre-charging ends There is no chamfering for a period of time, so that the active switch of the pixel is fully opened when the pixel starts to actually charge after the pre-charging is finished, which does not affect the actual charging process and enhances the charging effect of the pixel.
  • FIG. 1 is a schematic flow chart of a pixel charging method according to an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of a sub-step method of step S101 of a pixel charging method according to an embodiment of the present application;
  • FIG. 3 is a schematic flowchart of a sub-step method of step S102 of a pixel charging method according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of a waveform of a driving signal of a scan line according to an embodiment of the present application
  • FIG. 5 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a scan driving circuit provided in an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present application.
  • FIG. 1 is a method for charging a pixel according to an embodiment of the present application. The method includes the following steps:
  • the preset first time period T1 includes a period of time before the completion of the pre-charging of the pixel in the Nth row and a period of time after the completion, the first driving signal has a chamfer angle in the preset second time period T2,
  • the preset second time period T2 includes a period of time before the charging of the Nth row of pixels is completed, and the N is a natural number.
  • the scan driving circuit outputs a first driving signal to the scan line for opening the active switch connected to the scan line, so that the data driving circuit pre-charges the pixel, and the pixel is actually implemented immediately after the pre-charging is completed. Charging.
  • the first driving signal has no chamfering in the preset first time period T1, and the preset first time period T1 includes a period of time before the completion of the pre-charging of the pixel of the Nth row and a period of time after completion, so that It can still maintain a high level before and after the pixel pre-charging, and will not affect the conduction of the active switch due to the chamfering angle, so that the active switch can still be fully turned on at the beginning of actual charging, avoiding the active switch being incompletely turned on. Reduce the charging effect and maintain the actual effect of pre-charging.
  • the predetermined third time period T3 includes a period of time before the completion of the pre-charging of the (N+1)th row of pixels and a period of time after the completion, the second driving signal is within the preset fourth time period T4
  • the preset fourth time period T4 includes a period of time before the charging of the (N+1)th row of pixels is completed, a time point at which the Nth row of pixels completes charging, and a time when the second driving signal is outputted
  • the difference between the points is positive and equal to or smaller than the precharge time of the (N+1)th row of pixels.
  • the driving signals of two rows adjacent to the scanning line are not driven by the same signal, and the scanning driving circuit outputs a second driving signal to the scanning line of the N+1th row before the end of charging of the pixel in the Nth row, to open The N+1th row active switch, so that the data driving circuit precharges the N+1th row of pixels when the Nth row of pixels is charged, and precharging the next row of pixels when one row of pixels is charged can improve charging due to excessive scanning frequency Insufficient problem; the actual charging of the pixel is performed immediately after the pre-charging is completed, and the second driving signal for opening the active switch is not chamfered for a period of time before the end of the pre-charging, and the high voltage level causes the active switch to remain fully turned on. Therefore, the effect of the actual charging is not affected by the conduction condition of the active switch, and finally the charging effect of the pixel can be improved.
  • the first driving signal and the second driving signal are different, and the first driving signal and the second driving signal output by the scan driving circuit may be generated by a power IC embedded therein, or may be generated by an independent power IC. Scanning the driving circuit input, and then the scan driving circuit sequentially outputs the first driving signal and the second driving signal to the adjacent two rows of scanning lines according to the clock signal, the driving start signal and other control signals, and the clock signal controls when to output the first A driving signal and a second driving signal, the driving start signal controls an output time length of the first driving signal and the second driving signal output to the corresponding scanning lines.
  • the first level signal and the second level signal need to be performed before the driving scanning circuit outputs to the scan line. Zoom in to enhance its driving ability.
  • the active switch is shown as a thin film transistor.
  • the preset first time period T1 is equal to the preset third time period T3, and the preset second time period T2 is equal to the preset fourth time period T4, and the pixel pre-charging is completed.
  • the previous period is equal to half of the precharge time, and the period after the pixel precharge is completed is equal to half of the precharge time.
  • the first driving signal and the second driving signal have a chamfer angle in the same period of time of the output, so that the conduction of the corresponding active switches in the pre-charging or charging of the adjacent two rows of pixels is the same, and is not caused by the active switching of each row.
  • the conduction is uneven and the charging is uneven, which avoids the result of uneven charging.
  • a difference between a time point at which the Nth row of pixels completes charging and a time point at which the second driving signal is output is equal to a precharge time of the (N+1)th row of pixels. That is, when a row of pixels completes charging, the next row of pixels simultaneously completes pre-charging and starts charging, and because pre-charging pulls the pixel voltage of the next row closer to the target voltage, shortening the gap between the original voltage and the target voltage, which can be greatly charged during charging. To improve the problem of insufficient charging.
  • the pre-charge time is equal to the charging time.
  • the step of outputting the first driving signal for opening the active switch of the Nth row of scanning lines in step S101, and the step of precharging and charging the pixels of the Nth row includes S1011- S1012:
  • S1011 outputting a first driving signal on a rising edge of the Mth clock signal to turn on an active switch of the Nth row of scanning lines, and precharging the Nth row of pixels, wherein the M is a natural number;
  • S1012 The Nth row of pixels is charged on a rising edge of the M+1th clock signal, and a period of one clock signal is equal to the precharge time.
  • the step of outputting the second driving signal for opening the switch of the (N+1)th scan line in step S102, and the step of precharging and charging the pixel of the (N+1)th row includes S1011- S1012:
  • S1021 output a second driving signal on a rising edge of the M+1th clock to turn on an active switch of the (N+1)th scanning line, and precharge the N+1th row of pixels;
  • S1022 The N+1th row of pixels is charged on a rising edge of the M+2th clock signal.
  • FIG. 4 is a schematic diagram of a waveform of a driving signal of a scan line according to an embodiment of the present application.
  • VGH1 is an original waveform diagram of a first driving signal
  • VGH2 is a original waveform diagram of a second driving signal
  • CKV is a waveform diagram of a clock signal.
  • STV is a waveform diagram of the driving start signal
  • OUT1 and OUT2 are output states of the first driving signal and the second driving signal, respectively.
  • the first driving signal is outputted to the scanning line of the first row at the rising edge of the first clock signal, and the output time continues to drive a time pulse width of the starting signal.
  • the length of time that is, the output of the first driving signal is ended at the rising edge of the third clock signal, and the state diagram of the OUT1 waveform as shown in FIG. 3, that is, the first driving signal output to the scanning line of the Nth row is obtained.
  • the driving signal is output, the active switch of the scanning line of the first row is turned on, and the pixel of the first row is pre-charged.
  • the pre-charging time is a period of one clock signal, and the pixel of the first row is charged at the rising edge of the two clock signals, and the charging time is charged.
  • the second driving signal is output to the scanning line of the second row at the rising edge of the second clock signal, the switch of the scanning line of the second row is turned on, and the pixel of the second row is precharged, and the first is The pixel voltage of the row is charged to the second row, and the difference between the original voltage of the pixel in the second row and the target voltage is shortened.
  • the pixel charging in the first row is completed (the rising edge of the third clock signal)
  • the pixel in the second row is precharged. Finish and start the charging process, The charging effect is enhanced, the charging time is still a period of one clock signal, and the output of the second driving signal to the (N+1)th scanning line is stopped at the rising edge of the fourth clock signal.
  • the time during which each active switch is turned on lasts for two clock signals, and the chamfer time difference between the first driving signal and the second driving signal is equal to the period of one clock signal, and the chamfer of the first driving signal
  • the voltage is output at the rising edge of the clock signal that appears at the last time of the active switch of the Nth line, that is, the gate start voltage of the active switch is chamfered when the active switch is turned off, and the capacitive coupling effect can be reduced, and the active switch is turned on.
  • the first driving signal has no chamfering, and the active switch is fully turned on before and after the pre-charging, and does not affect the result of charging the pixel target potential; similarly, the charging result of the N+1th row pixel is also the same.
  • the remaining pixels are pre-charged and charged in the same process until the scan is complete.
  • FIG. 5 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present application.
  • the pixel driving circuit can be used for a TFT-LCD (Thin Film). Transistor-Liquid Crystal Display, thin film transistor liquid crystal display).
  • TFT-LCD Thin Film
  • Transistor-Liquid Crystal Display thin film transistor liquid crystal display
  • the pixel charging circuit includes:
  • the scan driving circuit 100 is connected to a plurality of horizontally distributed scan lines, outputs a first driving signal for turning on an active switch of the Nth row of scan lines, and outputs a second driving signal for turning on the switch of the (N+1)th scan line.
  • the data driving circuit 200 is connected to a plurality of vertically distributed data lines, precharging and charging the Nth row of pixels when the first driving signal is output, and N+1 when the second driving signal is outputting Line pixels are precharged and charged.
  • the first driving signal has no chamfering in a preset first time period, and the preset first time period includes a period of time before the completion of the pre-charging of the pixel in the Nth row and a period of time after completion.
  • the first driving signal has a chamfer in a preset second time period, and the preset second time period includes a period of time before the charging of the Nth row of pixels is completed, and the N is a natural number.
  • the second driving signal has no chamfering in a preset third time period, and the preset third time period includes a period of time before the completion of the pre-charging of the (N+1)th row of pixels and a period of time after completion.
  • the second driving signal has a chamfer in a preset fourth time period, and the preset fourth time period includes a period of time before the charging of the (N+1)th row of pixels is completed, and the charging time of the Nth row of pixels is completed.
  • the difference between the point and the time point at which the second driving signal is output is positive and equal to or smaller than the pre-charging time of the (N+1)th row of pixels.
  • the driving signals of two rows adjacent to the scan line are not driven by the same signal, and the scan driving circuit 100 outputs the first driving signal to turn on the active switch of the scanning line of the Nth row, and outputs the signal before the end of the charging of the Nth row of pixels.
  • the second driving signal turns on the active switch of the second row of scanning lines, so that the data driving circuit 200 precharges the N+1th row of pixels when the Nth row of pixels is charged, and precharging the next row of pixels when one row of pixels is charged can be improved due to The problem of insufficient charging caused by excessive scanning frequency; the actual charging of the pixel is performed immediately after the pre-charging is completed, and the second driving signal for opening the active switch is not chamfered for a period of time before and after the pre-charging is completed, and the voltage level is high to cause active
  • the switch remains fully conductive, so the effect of the actual charging is not affected by the conduction of the active switch, and finally the charging effect of the pixel can be improved.
  • the active switch is a thin film transistor.
  • the preset first time period is equal to the preset third time period
  • the preset second time period is equal to the preset fourth time period
  • a period of time before pixel pre-charge is completed. Equal to half of the pre-charging time, a period of time after pixel pre-charging is completed is equal to half of the pre-charging time.
  • the first driving signal and the second driving signal have a chamfer at the same time period of output, that is, the output of the first driving signal and the second driving signal maintain the same or similar waveform, so that the adjacent two rows of pixels are precharged Or the corresponding active switch is turned on the same when charging, and the charging is not uniform due to the difference in the conduction state of each row of active switches, thereby avoiding the result of uneven charging.
  • the pixel charging circuit further includes a clock signal generating circuit that generates a plurality of clock signals, and the plurality of clock signals are sequentially input to the scan driving circuit 100 to control outputs of the first driving signal and the second driving signal, and at the same time,
  • the clock control signal is related to the time at which the data driving circuit 200 outputs the data signal.
  • the first driving signal and the second driving signal are different, and the first driving signal and the second driving signal output by the scan driving circuit 100 may be generated by a power IC embedded therein, or may be generated by an independent power source IC.
  • the backward scan driving circuit 100 inputs, and then the scan driving circuit 100 sequentially outputs the first driving signal and the second driving signal to the adjacent two rows of scanning lines according to the clock signal, the driving start signal, and other control signals, and the clock signal is controlled.
  • the time at which the first driving signal and the second driving signal are output, the driving start signal controls the output time lengths of the first driving signal and the second driving signal output to the corresponding scanning lines.
  • a difference between a time point at which the Nth row of pixels completes charging and a time point at which the second driving signal is output is equal to a precharge time of the (N+1)th row of pixels. That is, when the row of pixels is completed, the next row of pixels simultaneously completes the pre-charging. When one row of pixels is completed, the next row of pixels starts to charge immediately, and because the pre-charging pulls the pixel voltage of the next row closer to the target voltage, the original voltage and the target voltage are shortened. The gap can greatly improve the problem of insufficient charging when charging.
  • the pre-charge time is equal to the charging time.
  • the precharging and charging process of the pixel is identical to that described in FIG. 3 in the above embodiment, as follows:
  • the data driving circuit 200 precharges the Nth row of pixels on the rising edge of the Mth clock signal, and charges the Nth row of pixels on the rising edge of the M+1th clock signal, and the period of one clock signal is equal to
  • the precharge time is described, and the M is a natural number.
  • the scan driving circuit 100 outputs a second driving signal on the rising edge of the M+1th clock to turn on the active switch of the (N+1)th scanning line, and stops at the rising edge of the M+3th clock. Outputting a second driving signal;
  • the data driving circuit 200 precharges the N+1th row of pixels on the rising edge of the M+1th clock, and charges the N+1th row of pixels on the rising edge of the M+2th clock signal.
  • the pixel charging circuit sequentially precharges and charges the remaining pixels in accordance with the above process until the scanning is completed.
  • the time during which each active switch is turned on lasts for two clock signals, and the chamfer time difference between the first driving signal and the second driving signal is equal to the period of one clock signal, and the chamfering voltage of the first driving signal or the second driving signal is at the The rising edge of the clock signal that appears at the end of the time period when the N-line or the (N+1)th active switch is turned on, that is, the gate start voltage of the active switch is chamfered when the active switch is turned off, and the capacitive coupling effect can be reduced.
  • the first driving signal or the second driving signal is not chamfered, and the active switch is fully turned on before and after the pre-charging, and the result of charging the pixel target potential is not affected.
  • the driving ability of the first level signal and the second level signal is not strong enough, it is necessary to amplify the first level signal and the second level signal to enhance its driving capability.
  • the scan driving circuit 100 includes an input buffer 101, a shift register 102, a potential converter 103, and an output buffer 104.
  • the input buffer 101 processes an input control signal and the like to perform driving capability.
  • the enhancement enables the first driving capability and the second driving capability of the input scan driving circuit 100 to be correctly processed.
  • the shift register 102 sequentially turns on the signal output channel of the scan driving circuit 100 according to the clock signal, so that the scan driving signal is turned on.
  • the line outputs a signal to the scan line, and the first drive signal or the second drive signal input from the external power supply IC of the level shifter is amplified to a high level voltage, and the high level signal for driving the scan line is output according to the clock signal and the drive start signal or A low level signal is used to turn on or off the active switch connected to the scan line, and the output buffer 104 amplifies the signal output from the high level converter to enhance the driving capability of the signal.
  • FIG. 7 is a liquid crystal display device according to an embodiment of the present disclosure.
  • the liquid crystal display device includes a liquid crystal display 300 and a housing 400 for fixing the liquid crystal display.
  • the liquid crystal display 300 includes the above.
  • the liquid crystal display further includes a base 500 that allows the display to be smoothly placed on a plane, such as a table top.

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Abstract

一种像素充电方法、电路、液晶显示屏及液晶显示装置，该方法包括：输出第一驱动信号用以打开第N行扫描线的主动开关，对第N行像素进行预充电和充电（S101）；输出第二驱动信号用以打开第N+1行扫描线的开关，对第N+1行像素进行预充电和充电（S102）；第一驱动信号和第二驱动信号在相应的像素预充电完成前的一段时间和完成后的一段时间无削角，在相应的像素充电完成前的一段时间有削角，且第二驱动信号在第N行像素充电结束前输出。通过两个驱动信号分别驱动相邻的两行扫描线对像素充电，在一行像素充电时对下一行像素预充电，预充电结束前后的某一段时间无削角，使得像素在预充电结束后开始实际充电时像素的主动开关充分打开，不影响实际充电过程，增强像素的充电效果。

Description

一种像素充电方法、电路、液晶显示屏及液晶显示装置
技术领域
本申请涉及液晶显示技术领域，尤其涉及一种像素充电方法、电路、液晶显示屏及液晶显示装置。
背景技术
目前一些高帧频液晶电视（120HZ以上），以及Tri-gate（三栅极驱动电路）架构的电视，由于栅极扫描频率过高，造成TFT打开的时间缩短，容易造成充电不足的问题。常用的做法是采用预充电（pre-charge），即提前将第N行的电压充至第N+1行，最后再将正确的电压充至第N+1行。但为了减小TFT（Thin Film Transistor，薄膜晶体管）开关在关闭时产生的电容耦合效应，TFT的栅极驱动电压VGH都会做削角处理，但这样在对像素进行预充电时，扫描线的扫描电压波形会因为削角处理导致扫描电位降低，从而使得充电时TFT导通不充分，从而影响了像素的充电效果，进而一定程度上减弱了预充电（pre-charge）的实际效果。
发明内容
本申请提供了能够提高像素充电效果的像素充电方法及电路。
第一方面，本申请实施例提供了一种像素充电方法，该方法包括：
输出第一驱动信号用以打开第N行扫描线的主动开关，对第N行像素进行预充电和充电，其中，所述第一驱动信号在预设第一时间段无削角，所述预设第一时间段包括所述第N行像素预充电完成前的一段时间和完成后的一段时间，所述第一驱动信号在预设第二时间段有削角，所述预设第二时间段包括所述第N行像素充电完成前的一段时间，所述N为自然数；
输出第二驱动信号用以打开第N+1行扫描线的开关，对第N+1行像素进行预充电和充电，其中，所述第二驱动信号在预设第三时间段无削角，所述预设第三时间段包括所述第N+1行像素预充电完成前的一段时间和完成后的一段时间，所述第二驱动信号在预设第四时间段内有削角，所述预设第四时间段包括所述第N+1行像素充电完成前的一段时间，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差为正且等于或者小于所述第N+1行像素的预充电时间。
第二方面，本申请实施例提供了一种像素充电电路，该像素充电电路包括：
扫描驱动电路，输出第一驱动信号用以打开第N行扫描线的主动开关，及输出第二驱动信号用以打开第N+1行扫描线的开关；
数据驱动电路，在所述第一驱动信号输出时对第N行像素进行预充电和充电，及在所述第二驱动信号输出时对第N+1行像素进行预充电和充电；
其中，所述第一驱动信号在预设第一时间段无削角，所述预设第一时间段包括所述第N行像素预充电完成前的一段时间和完成后的一段时间，所述第一驱动信号在预设第二时间段有削角，所述预设第二时间段包括所述第N行像素充电完成前的一段时间，所述N为自然数；
所述第二驱动信号在预设第三时间段无削角，所述预设第三时间段包括所述第N+1行像素预充电完成前的一段时间和完成后的一段时间，所述第二驱动信号在预设第四时间段内有削角，所述预设第四时间段包括所述第N+1行像素充电完成前的一段时间，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差为正且等于或者小于所述第N+1行像素的预充电时间。
第三方面，本申请实施例提供了一种液晶显示屏，该液晶显示屏包括像素充电电路，其中，所述像素充电电路包括：
扫描驱动电路，输出第一驱动信号用以打开第N行扫描线的主动开关，及输出第二驱动信号用以打开第N+1行扫描线的开关；
数据驱动电路，在所述第一驱动信号输出时对第N行像素进行预充电和充电，及在所述第二驱动信号输出时对第N+1行像素进行预充电和充电；
其中，所述第一驱动信号在预设第一时间段无削角，所述预设第一时间段包括所述第N行像素预充电完成前的一段时间和完成后的一段时间，所述第一驱动信号在预设第二时间段有削角，所述预设第二时间段包括所述第N行像素充电完成前的一段时间，所述N为自然数；
所述第二驱动信号在预设第三时间段无削角，所述预设第三时间段包括所述第N+1行像素预充电完成前的一段时间和完成后的一段时间，所述第二驱动信号在预设第四时间段内有削角，所述预设第四时间段包括所述第N+1行像素充电完成前的一段时间，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差为正且等于或者小于所述第N+1行像素的预充电时间。
第四方面，本申请实施例提供了一种液晶显示装置，该液晶显示装置包括液晶显示屏，其中，所述液晶显示屏包括像素充电电路，所述像素充电电路包括：
扫描驱动电路，输出第一驱动信号用以打开第N行扫描线的主动开关，及输出第二驱动信号用以打开第N+1行扫描线的开关；
数据驱动电路，在所述第一驱动信号输出时对第N行像素进行预充电和充电，及在所述第二驱动信号输出时对第N+1行像素进行预充电和充电；
其中，所述第一驱动信号在预设第一时间段无削角，所述预设第一时间段包括所述第N行像素预充电完成前的一段时间和完成后的一段时间，所述第一驱动信号在预设第二时间段有削角，所述预设第二时间段包括所述第N行像素充电完成前的一段时间，所述N为自然数；
所述第二驱动信号在预设第三时间段无削角，所述预设第三时间段包括所述第N+1行像素预充电完成前的一段时间和完成后的一段时间，所述第二驱动信号在预设第四时间段内有削角，所述预设第四时间段包括所述第N+1行像素充电完成前的一段时间，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差为正且等于或者小于所述第N+1行像素的预充电时间。
本申请通过两个驱动信号分别驱动相邻的两行扫描线对像素预充电和充电，在一行像素充电时对下一行像素预充电，预充电结束后立即对像素充电，预充电结束前后的某一段时间无削角，使得像素在预充电结束后开始实际充电时像素的主动开关充分打开，不影响实际充电过程，增强像素的充电效果。
附图说明
为了更清楚地说明本申请实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例中一种像素充电方法流程示意图；
图2为本申请一实施例中一种像素充电方法的步骤S101的子步骤方法流程示意图；
图3为本申请一实施例中一种像素充电方法的步骤S102的子步骤方法流程示意图；
图4为本申请一实施例中扫描线的驱动信号波形示意图；
图5为本申请一实施例中提供的一种像素驱动电路的结构示意图；
图6为本申请一实施例中提供的扫描驱动电路的结构示意图；
图7为本申请一实施例中提供的一种液晶显示装置的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解，当在本说明书和所附权利要求书中使用时，术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
请参照图1，图1为本申请实施例提供的一种像素充电方法，该方法包括以下步骤：
S101、输出第一驱动信号用以打开第N行扫描线的主动开关，对第N行像素进行预充电和充电，其中，所述第一驱动信号在预设第一时间段T1无削角，所述预设第一时间段T1包括所述第N行像素预充电完成前的一段时间和完成后的一段时间，所述第一驱动信号在预设第二时间段T2有削角，所述预设第二时间段T2包括所述第N行像素充电完成前的一段时间，所述N为自然数。
在本申请实施例中，扫描驱动电路向扫描线输出第一驱动信号用以打开该扫描线连接的主动开关，以便数据驱动电路对像素进行预充电，预充电结束后立即对所述像素进行实际充电。所述第一驱动信号在预设第一时间段T1无削角，所述预设第一时间段T1包括所述第N行像素预充电完成前的一段时间和完成后的一段时间，如此，在像素预充电结束前后依然能保持高电平，不会因为削角而影响主动开关的导通情况，能使主动开关在开始实际充电时依然完全导通，避免因主动开关不完全导通而降低充电效果，保持了预充电的实际效果。
S102、输出第二驱动信号用以打开第N+1行扫描线的开关，对第N+1行像素进行预充电和充电，其中，所述第二驱动信号在预设第三时间段T3无削角，所述预设第三时间段T3包括所述第N+1行像素预充电完成前的一段时间和完成后的一段时间，所述第二驱动信号在预设第四时间段T4内有削角，所述预设第四时间段T4包括所述第N+1行像素充电完成前的一段时间，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差为正且等于或者小于所述第N+1行像素的预充电时间。
在本申请实施例中，不由同一个信号驱动扫描线相邻两行的驱动信号，在第N行像素充电结束前扫描驱动电路向第N+1行扫描线输出第二驱动信号，用以打开第N+1行主动开关，以便数据驱动电路在第N行像素充电时对第N+1行像素预充电，在一行像素充电时对下一行像素预充电能够改善由于扫描频率过高导致的充电不足的问题；预充电结束后立即进行对像素的实际充电，由于预充电结束前后的一段时间内打开主动开关的第二驱动信号无削角，电压准位高致使主动开关保持完全导通的状态，因而不会因主动开关的导通情况影响实际充电的效果，最终能够提高像素的充电效果。
在具体实施例中，第一驱动信号和第二驱动信号不同，扫描驱动电路输出的第一驱动信号和第二驱动信号可以由其内部镶嵌的电源IC产生，亦可由独立的电源IC产生后向扫描驱动电路输入，然后扫描驱动电路根据时钟信号、驱动起始信号以及其他的控制信号向相邻的两行扫描线依序输出第一驱动信号和第二驱动信号，时钟信号控制何时输出第一驱动信号和第二驱动信号，驱动起始信号控制向对应的扫描线输出的第一驱动信号和第二驱动信号的输出时间长度。
在一些实施例中，若第一电平信号和第二电平信号的驱动能力不足够强，则在驱动扫描电路向扫描线输出之前，需要对第一电平信号和第二电平信号进行放大，以增强其驱动能力。
在一些实施例中，所示主动开关为薄膜晶体管。
在一些实施例中，所述预设第一时间段T1等于所述预设第三时间段T3，所述预设第二时间段T2等于所述预设第四时间段T4，像素预充电完成前的一段时间等于所述预充电时间的一半，像素预充电完成后的一段时间等于所述预充电时间的一半。
第一驱动信号和第二驱动信号在输出相同的时间段具有削角，可使得相邻两行像素的在预充电或充电时对应的主动开关的导通情况相同，不因每一行主动开关的导通情况差异而出现充电不均匀，避免了充电不均匀的结果。
在一些实施例中，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差等于所述第N+1行像素的预充电时间。即一行像素完成充电时下一行像素同时完成了预充电并开始充电，而因为预充电把下一行的像素电压拉高接近了目标电压，缩短了原电压与目标电压的差距，在充电时可以很大程度改善充电不足的问题。
在一些实施例中，所述预充电时间等于充电时间。
如图2所示，步骤S101中所述输出第一驱动信号用以打开第N行扫描线的主动开关，对第N行像素进行预充电和充电的步骤包括S1011- S1012：
S1011、在第M个时钟信号的上升沿输出第一驱动信号用以打开第N行扫描线的主动开关，对第N行像素预充电，所述M为自然数；
S1012、在第M+1个时钟信号的上升沿对所述第N行像素充电，一个时钟信号的周期等于所述预充电时间。
如图3所示，步骤S102中所述输出第二驱动信号用以打开第N+1行扫描线的开关，对第N+1行像素进行预充电和充电的步骤包括S1011- S1012：
S1021、在所述第M+1个时钟的上升沿输出第二驱动信号用以打开第N+1行扫描线的主动开关，对第N+1行像素预充电；
S1022、在第M+2个时钟信号的上升沿对所述第N+1行像素充电。
一般情况下，M=N。
参考图4，图4为本申请实施例的扫描线的驱动信号波形示意图，VGH1为第一驱动信号的原始波形图，VGH2为第二驱动信号的原始波形图，CKV为时钟信号的波形图，STV为驱动起始信号的波形图，OUT1和OUT2分别为第一驱动信号和第二驱动信号的输出状态。从图4可以看出，T1=T3=T(2N-1)， T2=T4= T(2N)。
以第1行和第2行扫描线为例，在第1个时钟信号的上升沿向开始向第1行扫描线输出第一驱动信号，输出的时间持续驱动起始信号的一个时间脉宽的时间长度，即在第3个时钟信号的上升沿结束输出第一驱动信号，得到如图3中的OUT1波形图，即输出至第N行扫描线的第一驱动信号的状态图，在第一驱动信号输出时第1行扫描线的主动开关打开，对第1行像素预充电，预充电的时间为一个时钟信号的周期，在2个时钟信号的上升沿对第1行像素充电，充电时间为一个时钟信号的周期，同时在第2个时钟信号的上升沿将第二驱动信号输出至第2行扫描线，打开第2行扫描线的开关，对第2行像素预充电，将第1行的像素电压充至第2行，缩短第2行像素原电压与目标电压之间的差距，在第1行像素充电完成时（第3个时钟信号的上升沿），第2行像素预充电完成且开始充电过程，增强充电的效果，充电时间依然为一个时钟信号的周期，在第4个时钟信号的上升沿停止输出第二驱动信号至第N+1行扫描线。
从图4中可以看出，每个主动开关打开的时间持续两个时钟信号的周期，第一驱动信号和第二驱动信号的削角时间差等于一个时钟信号的周期，第一驱动信号的削角电压在第N行主动开关打开的时间阶段最后出现的时钟信号的上升沿输出，即在充电完成关闭主动开关时主动开关的栅极启动电压有削角，能够减小电容耦合效应，主动开关打开的其他时间第一驱动信号无削角，预充电结束前后主动开关完全导通，不会影响到像素目标电位充电的结果；同理，第N+1行像素的充电结果也是如此。
以此类推，按照相同的过程对剩余的其他像素预充电和充电，直至扫描完成。
参考图5，图5为本申请实施例提供的一种像素驱动电路的结构示意图，该像素驱动电路可用于TFT-LCD（Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器）中。
所述像素充电电路包括：
扫描驱动电路100，连接多条水平分布的扫描线，输出第一驱动信号用以打开第N行扫描线的主动开关，及输出第二驱动信号用以打开第N+1行扫描线的开关。
数据驱动电路200，连接多条竖直分布的数据线，在所述第一驱动信号输出时对第N行像素进行预充电和充电，及在所述第二驱动信号输出时对第N+1行像素进行预充电和充电。
其中，所述第一驱动信号在预设第一时间段无削角，所述预设第一时间段包括所述第N行像素预充电完成前的一段时间和完成后的一段时间，所述第一驱动信号在预设第二时间段有削角，所述预设第二时间段包括所述第N行像素充电完成前的一段时间，所述N为自然数。
所述第二驱动信号在预设第三时间段无削角，所述预设第三时间段包括所述第N+1行像素预充电完成前的一段时间和完成后的一段时间，所述第二驱动信号在预设第四时间段内有削角，所述预设第四时间段包括所述第N+1行像素充电完成前的一段时间，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差为正且等于或者小于所述第N+1行像素的预充电时间。
在本申请实施例中，不由同一个信号驱动扫描线相邻两行的驱动信号，扫描驱动电路100输出第一驱动信号打开第N行扫描线的主动开关，在第N行像素充电结束前输出第二驱动信号打开第二行扫描线的主动开关，以便数据驱动电路200在第N行像素充电时对第N+1行像素预充电，在一行像素充电时对下一行像素预充电能够改善由于扫描频率过高导致的充电不足的问题；预充电结束后立即进行对像素的实际充电，由于预充电结束前后的一段时间内打开主动开关的第二驱动信号无削角，电压准位高致使主动开关保持完全导通的状态，因而不会因主动开关的导通情况影响实际充电的效果，最终能够提高像素的充电效果。
在一些实施例中，所述主动开关为薄膜晶体管。
在一些实施例中，所述预设第一时间段等于所述预设第三时间段，所述预设第二时间段等于所述预设第四时间段，像素预充电完成前的一段时间等于所述预充电时间的一半，像素预充电完成后的一段时间等于所述预充电时间的一半。
第一驱动信号和第二驱动信号在输出相同的时间段具有削角，即使得输出的第一驱动信号和第二驱动信号保持相同或相近的波形，可使得相邻两行像素的在预充电或充电时对应的主动开关的导通情况相同，不因每一行主动开关的导通情况差异而出现充电不均匀，避免了充电不均匀的结果。
所述像素充电电路还包括产生多个时钟信号的是时钟信号产生电路，所述多个时钟信号依次输入至扫描驱动电路100，控制第一驱动信号和第二驱动信号的输出，同时，所述时钟控制信号与数据驱动电路200输出数据信号的时间有关。
在本申请实施例中，第一驱动信号和第二驱动信号不同，扫描驱动电路100输出的第一驱动信号和第二驱动信号可以由其内部镶嵌的电源IC产生，亦可由独立的电源IC产生后向扫描驱动电路100输入，然后扫描驱动电路100根据时钟信号、驱动起始信号以及其他的控制信号向相邻的两行扫描线依序输出第一驱动信号和第二驱动信号，时钟信号控制输出第一驱动信号和第二驱动信号的时间，驱动起始信号控制向对应的扫描线输出的第一驱动信号和第二驱动信号的输出时间长度。
在一些实施例中，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差等于所述第N+1行像素的预充电时间。即一行像素完成充电时下一行像素同时完成了预充电，当一行像素完成充电下一行像素立即开始充电，而因为预充电把下一行的像素电压拉高接近了目标电压，缩短了原电压与目标电压的差距，在充电时可以很大程度改善充电不足的问题。
在一些实施例中，所述预充电时间等于充电时间。
在像素的预充电时间等于充电时间，且在一行像素开始充电的时刻对下一行像素预充电的情况下，像素的预充电和充电过程与上述实施例中的图3描述一致，具体如下：
所述扫描驱动电路100在第M个时钟信号的上升沿输出第一驱动信号用以打开第N行扫描线的主动开关，在第M+2个时钟信号的上升沿停止输出所述第一驱动信号，所述M为自然数，一般M=N。
所述数据驱动电路200在第M个时钟信号的上升沿对第N行像素预充电，在第M+1个时钟信号的上升沿对所述第N行像素充电，一个时钟信号的周期等于所述预充电时间，所述M为自然数。
所述扫描驱动电路100在所述第M+1个时钟的上升沿输出第二驱动信号用以打开第N+1行扫描线的主动开关，在所述第M+3个时钟的上升沿停止输出第二驱动信号；
所述数据驱动电路200在所述第M+1个时钟的上升沿对第N+1行像素预充电，在第M+2个时钟信号的上升沿对所述第N+1行像素充电。
像素充电电路按照上述过程依次对剩余的像素进行预充电和充电，直至扫描完成。
每个主动开关打开的时间持续两个时钟信号的周期，第一驱动信号和第二驱动信号的削角时间差等于一个时钟信号的周期，第一驱动信号或第二驱动信号的削角电压在第N行或第N+1行主动开关打开的时间阶段最后出现的时钟信号的上升沿输出，即在充电完成关闭主动开关时主动开关的栅极启动电压有削角，能够减小电容耦合效应，在主动开关打开的其他时间第一驱动信号或第二驱动信号无削角，预充电结束前后主动开关完全导通，不会影响到像素目标电位充电的结果。
在一些实施例中，若第一电平信号和第二电平信号的驱动能力不足够强，则需要对第一电平信号和第二电平信号进行放大，以增强其驱动能力。
具体地，如图6所示，扫描驱动电路100包括输入缓冲器101、移位寄存器102、电位变换器103和输出缓冲器104，输入缓冲器101对输入的控制信号等进行处理，做驱动能力的增强，使得输入扫描驱动电路100的第一驱动能力和第二驱动能力能得到正确的处理，移位寄存器102根据时钟信号逐行打开扫描驱动电路100的信号输出通道，以使扫描驱动信号逐行向扫描线输出信号，电平转换器外部电源IC输入的第一驱动信号或第二驱动信号放大为高电平电压，根据时钟信号和驱动起始信号输出驱动扫描线的高电平信号或低电平信号，以打开或关闭扫描线连接的主动开关，输出缓冲器104对高电平转换器输出的信号进行放大，以增强信号的驱动能力。
图7为本申请实施例提供的一种液晶显示装置，如图7所示，所述液晶显示装置包括液晶显示屏300和固定所述液晶显示屏的外壳400，所述液晶显示屏300包括上述实施例的像素充电电路。
进一步地，所述液晶显示器还包括底座500，底座500使该显示器平稳地放置于平面上，例如桌面。
需要说明的是，在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详细描述的部分，可以参见其他实施例的相关描述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种像素充电方法，包括：
    输出第一驱动信号用以打开第N行扫描线的主动开关，对第N行像素进行预充电和充电，其中，所述第一驱动信号在预设第一时间段无削角，所述预设第一时间段包括所述第N行像素预充电完成前的一段时间和完成后的一段时间，所述第一驱动信号在预设第二时间段有削角，所述预设第二时间段包括所述第N行像素充电完成前的一段时间，所述N为自然数；
    输出第二驱动信号用以打开第N+1行扫描线的开关，对第N+1行像素进行预充电和充电，其中，所述第二驱动信号在预设第三时间段无削角，所述预设第三时间段包括所述第N+1行像素预充电完成前的一段时间和完成后的一段时间，所述第二驱动信号在预设第四时间段内有削角，所述预设第四时间段包括所述第N+1行像素充电完成前的一段时间，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差为正且等于或者小于所述第N+1行像素的预充电时间。
  2. 如权利要求1所述的方法，其中，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差等于所述第N+1行像素的预充电时间。
  3. 如权利要求1所述的方法，其中，所述预充电时间等于充电时间；
    所述输出第一驱动信号用以打开第N行扫描线的主动开关，对第N行像素进行预充电和充电，包括：
    在第M个时钟信号的上升沿输出第一驱动信号用以打开第N行扫描线的主动开关，对第N行像素预充电；在第M+1个时钟信号的上升沿对所述第N行像素充电，一个时钟信号的周期等于所述预充电时间，所述M为自然数。
  4. 如权利要求3所述的方法，其中，所述输出第二驱动信号用以打开第N+1行扫描线的开关，对第N+1行像素进行预充电和充电，包括：
    在所述第M+1个时钟的上升沿输出第二驱动信号用以打开第N+1行扫描线的主动开关，对第N+1行像素预充电，在第M+2个时钟信号的上升沿对所述第N+1行像素充电。
  5. 如权利要求1所述的方法，其中，所述预设第一时间段等于所述预设第三时间段，所述预设第二时间段等于所述预设第四时间段，像素预充电完成前的一段时间等于所述预充电时间的一半，像素预充电完成后的一段时间等于所述预充电时间的一半。
  6. 一种像素充电电路，包括：
    扫描驱动电路，输出第一驱动信号用以打开第N行扫描线的主动开关，及输出第二驱动信号用以打开第N+1行扫描线的开关；
    数据驱动电路，在所述第一驱动信号输出时对第N行像素进行预充电和充电，及在所述第二驱动信号输出时对第N+1行像素进行预充电和充电；
    其中，所述第一驱动信号在预设第一时间段无削角，所述预设第一时间段包括所述第N行像素预充电完成前的一段时间和完成后的一段时间，所述第一驱动信号在预设第二时间段有削角，所述预设第二时间段包括所述第N行像素充电完成前的一段时间，所述N为自然数；
    所述第二驱动信号在预设第三时间段无削角，所述预设第三时间段包括所述第N+1行像素预充电完成前的一段时间和完成后的一段时间，所述第二驱动信号在预设第四时间段内有削角，所述预设第四时间段包括所述第N+1行像素充电完成前的一段时间，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差为正且等于或者小于所述第N+1行像素的预充电时间。
  7. 如权利要求6所述的像素充电电路，其中，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差等于所述第N+1行像素的预充电时间。
  8. 如权利要求7所述的像素充电电路，其中，所述预设第一时间段等于所述预设第三时间段，所述预设第二时间段等于所述预设第四时间段，像素预充电完成前的一段时间等于所述预充电时间的一半，像素预充电完成后的一段时间等于所述预充电时间的一半。
  9. 如权利要求8所述的像素充电电路，其中，还包括时钟信号产生电路，所述时钟信号产生电路用于产生多个时钟信号；
    所述预充电时间等于所述充电时间；
    所述扫描驱动电路在第M个时钟信号的上升沿输出第一驱动信号用以打开第N行扫描线的主动开关，在第M+2个时钟信号的上升沿停止输出所述第一驱动信号，所述M为自然数；
    所述数据驱动电路在第M个时钟信号的上升沿对第N行像素预充电，在第M+1个时钟信号的上升沿对所述第N行像素充电，一个时钟信号的周期等于所述预充电时间，所述M为自然数。
  10. 如权利要求9所述的像素充电电路，其中，所述扫描驱动电路在所述第M+1个时钟的上升沿输出第二驱动信号用以打开第N+1行扫描线的主动开关，在所述第M+3个时钟的上升沿停止输出第二驱动信号；
    所述数据驱动电路在所述第M+1个时钟的上升沿对第N+1行像素预充电，在第M+2个时钟信号的上升沿对所述第N+1行像素充电。
  11. 一种液晶显示屏，包括像素充电电路，其中，所述像素充电电路包括：
    扫描驱动电路，输出第一驱动信号用以打开第N行扫描线的主动开关，及输出第二驱动信号用以打开第N+1行扫描线的开关；
    数据驱动电路，在所述第一驱动信号输出时对第N行像素进行预充电和充电，及在所述第二驱动信号输出时对第N+1行像素进行预充电和充电；
    其中，所述第一驱动信号在预设第一时间段无削角，所述预设第一时间段包括所述第N行像素预充电完成前的一段时间和完成后的一段时间，所述第一驱动信号在预设第二时间段有削角，所述预设第二时间段包括所述第N行像素充电完成前的一段时间，所述N为自然数；
    所述第二驱动信号在预设第三时间段无削角，所述预设第三时间段包括所述第N+1行像素预充电完成前的一段时间和完成后的一段时间，所述第二驱动信号在预设第四时间段内有削角，所述预设第四时间段包括所述第N+1行像素充电完成前的一段时间，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差为正且等于或者小于所述第N+1行像素的预充电时间。
  12. 如权利要求11所述的液晶显示屏，其中，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差等于所述第N+1行像素的预充电时间。
  13. 如权利要求12所述的液晶显示屏，其中，所述预设第一时间段等于所述预设第三时间段，所述预设第二时间段等于所述预设第四时间段，像素预充电完成前的一段时间等于所述预充电时间的一半，像素预充电完成后的一段时间等于所述预充电时间的一半。
  14. 如权利要求13所述的液晶显示屏，其中，还包括时钟信号产生电路，所述时钟信号产生电路用于产生多个时钟信号；
    所述预充电时间等于所述充电时间；
    所述扫描驱动电路在第M个时钟信号的上升沿输出第一驱动信号用以打开第N行扫描线的主动开关，在第M+2个时钟信号的上升沿停止输出所述第一驱动信号，所述M为自然数；
    所述数据驱动电路在第M个时钟信号的上升沿对第N行像素预充电，在第M+1个时钟信号的上升沿对所述第N行像素充电，一个时钟信号的周期等于所述预充电时间，所述M为自然数。
  15. 如权利要求14所述的液晶显示屏，其中，所述扫描驱动电路在所述第M+1个时钟的上升沿输出第二驱动信号用以打开第N+1行扫描线的主动开关，在所述第M+3个时钟的上升沿停止输出第二驱动信号；
    所述数据驱动电路在所述第M+1个时钟的上升沿对第N+1行像素预充电，在第M+2个时钟信号的上升沿对所述第N+1行像素充电。
  16. 一种液晶显示装置，包括液晶显示屏，其中，所述液晶显示屏包括像素充电电路，所述像素充电电路包括：
    扫描驱动电路，输出第一驱动信号用以打开第N行扫描线的主动开关，及输出第二驱动信号用以打开第N+1行扫描线的开关；
    数据驱动电路，在所述第一驱动信号输出时对第N行像素进行预充电和充电，及在所述第二驱动信号输出时对第N+1行像素进行预充电和充电；
    其中，所述第一驱动信号在预设第一时间段无削角，所述预设第一时间段包括所述第N行像素预充电完成前的一段时间和完成后的一段时间，所述第一驱动信号在预设第二时间段有削角，所述预设第二时间段包括所述第N行像素充电完成前的一段时间，所述N为自然数；
    所述第二驱动信号在预设第三时间段无削角，所述预设第三时间段包括所述第N+1行像素预充电完成前的一段时间和完成后的一段时间，所述第二驱动信号在预设第四时间段内有削角，所述预设第四时间段包括所述第N+1行像素充电完成前的一段时间，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差为正且等于或者小于所述第N+1行像素的预充电时间。
  17. 如权利要求16所述的液晶显示装置，其中，所述第N行像素完成充电的时间点与所述输出第二驱动信号的时间点之差等于所述第N+1行像素的预充电时间。
  18. 如权利要求17所述的液晶显示装置，其中，所述预设第一时间段等于所述预设第三时间段，所述预设第二时间段等于所述预设第四时间段，像素预充电完成前的一段时间等于所述预充电时间的一半，像素预充电完成后的一段时间等于所述预充电时间的一半。
  19. 如权利要求18所述的液晶显示装置，其中，还包括时钟信号产生电路，所述时钟信号产生电路用于产生多个时钟信号；
    所述预充电时间等于所述充电时间；
    所述扫描驱动电路在第M个时钟信号的上升沿输出第一驱动信号用以打开第N行扫描线的主动开关，在第M+2个时钟信号的上升沿停止输出所述第一驱动信号，所述M为自然数；
    所述数据驱动电路在第M个时钟信号的上升沿对第N行像素预充电，在第M+1个时钟信号的上升沿对所述第N行像素充电，一个时钟信号的周期等于所述预充电时间，所述M为自然数。
  20. 如权利要求19所述的液晶显示装置，其中，所述扫描驱动电路在所述第M+1个时钟的上升沿输出第二驱动信号用以打开第N+1行扫描线的主动开关，在所述第M+3个时钟的上升沿停止输出第二驱动信号；
    所述数据驱动电路在所述第M+1个时钟的上升沿对第N+1行像素预充电，在第M+2个时钟信号的上升沿对所述第N+1行像素充电。
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