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WO2018119967A1 - Goa电路 - Google Patents

Goa电路 Download PDF

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Publication number
WO2018119967A1
WO2018119967A1 PCT/CN2016/113324 CN2016113324W WO2018119967A1 WO 2018119967 A1 WO2018119967 A1 WO 2018119967A1 CN 2016113324 W CN2016113324 W CN 2016113324W WO 2018119967 A1 WO2018119967 A1 WO 2018119967A1
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WO
WIPO (PCT)
Prior art keywords
goa circuit
node
circuit unit
gate
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/113324
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English (en)
French (fr)
Inventor
李亚锋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to EP16925452.1A priority Critical patent/EP3564941B1/en
Priority to KR1020197022101A priority patent/KR102210845B1/ko
Priority to US15/508,106 priority patent/US10102820B2/en
Priority to JP2019534972A priority patent/JP6783943B2/ja
Publication of WO2018119967A1 publication Critical patent/WO2018119967A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal displays, and more particularly to a GOA circuit.
  • LCDs liquid crystal displays
  • LTPS Low temperature polysilicon
  • Low-temperature polysilicon liquid crystal displays have many advantages such as high resolution, fast response speed, and high aperture ratio.
  • the Gate Driver On Array (GOA) technology utilizes an existing thin film transistor liquid crystal display array (Array) process to fabricate a gate scan driving signal circuit on an array substrate to realize gate-by-row operation.
  • Array thin film transistor liquid crystal display array
  • the corresponding panel peripheral integrated circuits have also become the focus of attention, and many people have invested in the related technology research of the System on Panel (SOP), and gradually become a reality.
  • FIG. 1 it is a schematic diagram of a conventional GOA circuit, which can be used in an LTPS panel, and mainly includes eight thin film transistors (TFTs) and two capacitors.
  • the existing GOA circuit includes a plurality of cascaded GOA circuit units, wherein the nth stage GOA circuit unit that outputs the nth horizontal scan signal includes: TFT T1 whose gate is connected to the signal output of the n-1th stage GOA circuit unit Point Gn-1, the source and the drain are respectively connected to the node H and the constant voltage high potential VGH; the TFT T2 has a gate connected to the node Q, and the source and the drain are respectively connected to the signal output point Gn of the nth stage GOA circuit unit and Input clock signal CKV1; TFT T3, whose gate is connected to signal output point Gn+1 of the n+1th GOA circuit unit, source and drain are respectively connected to node H and constant voltage high potential VGH; TFT T4, gate thereof Connecting the node P,
  • Phase 1 pre-charging: Gn-1 is high level, T1 is turned on, H point is pre-charged, T8 is always in conduction state, and Q point is pre-charged;
  • phase 2 In phase 2, Gn outputs a high level: in phase 1, Q point is precharged, C1 has a certain holding effect on the charge, T2 is in the on state, and the high level of CKV1 is output to the Gn terminal;
  • Gn outputs a low level: C1 has a hold effect on the high level of Q point, while the low level of CKV1 pulls the Gn point low; while Gn+1 is high, T3 is on, and Q is high. Level is maintained;
  • stage 4 Q is pulled low to VGL:
  • CKV3 is high, T5 is turned on, P is pulled high, T6 is turned on, and Q is pulled low;
  • Phase 5 Q point and Gn point low level maintenance phase: When Q point becomes low level, T7 is in the off state. When CKV3 is high, P is charged to a high level, T4 and T6 are in an on state, and Q and Gn are maintained at a low level.
  • FIG. 3 is a schematic diagram of the reverse scan timing of the GOA circuit of FIG. 1, the specific working process (reverse scan) of the circuit is described below with reference to FIG.
  • Phase 1 pre-charge: Gn+1 is high level, T3 is turned on, H point is pre-charged, T8 is always in conduction state, and Q point is pre-charged;
  • phase 2 In phase 2, Gn outputs a high level: in phase 1, Q point is precharged, C1 has a certain holding effect on the charge, T2 is in the on state, and the high level of CKV1 is output to the Gn terminal;
  • Gn outputs a low level: C1 has a hold effect on the high level of Q point, while the low level of CKV1 pulls the Gn point low; while Gn-1 is high, T1 is on, and Q is high. Level is maintained;
  • stage 4 Q is pulled low to VGL:
  • CKV3 is high, T5 is turned on, P is pulled high, T6 is turned on, and Q is pulled low;
  • Phase 5 Q point and Gn point low level maintenance phase: When Q point becomes low level, T7 is in the off state. When CKV3 is high, P is charged to a high level, T4 and T6 are in an on state, and Q and Gn are maintained at a low level.
  • the existing GOA circuit shown in Fig. 1 introduces Q point and H point.
  • the Q point is automatically bootstrapped by C1 when the Gn output is high.
  • the detailed waveform is shown in Figure 2 and Figure 3.
  • T7 TFT stress Stress
  • Add a TFT T8, and the gate of T8 is connected to VGH.
  • T8 is always in the on state.
  • the object of the present invention is to propose a new GOA circuit based on the existing GOA circuit, and solve the problem that the output of the existing GOA circuit Gn is unstable.
  • the present invention provides a GOA circuit comprising a plurality of cascaded GOA circuit units, wherein n is a natural number greater than 0, and the nth-level GOA circuit unit comprises:
  • the first thin film transistor has a source and a drain connected to the first node and a constant voltage high potential VGH, respectively.
  • the gate is connected to the signal output point of the n-1th stage GOA circuit unit. Otherwise, its gate inputs the first start signal;
  • the third thin film transistor has a source and a drain connected to the first node and a constant voltage high potential VGH, respectively.
  • the gate is connected to the signal output point of the n+1th GOA circuit unit. Otherwise, its gate inputs a second start signal;
  • a seventh thin film transistor having a gate connected to the first node, a source and a drain connected to the third node and a constant voltage low potential VGL;
  • a sixth thin film transistor having a gate connected to the third node, the source and the drain being respectively connected to the first node and the constant voltage low potential VGL;
  • a fifth thin film transistor the gate thereof inputs a second clock signal, and the source and the drain are respectively connected to the third node and the constant voltage high potential VGH;
  • a fourth thin film transistor having a gate connected to the third node, the source and the drain being respectively connected to the signal output point of the nth stage GOA circuit unit and the constant voltage low potential VGL;
  • a second thin film transistor having a gate connected to a second node of the nth stage GOA circuit unit, a source and a drain respectively connected to a signal output point of the nth stage GOA circuit unit and an input first clock signal;
  • the eighth thin film transistor has a source and a drain connected to the second node of the first node and the nth stage GOA circuit unit, respectively.
  • the gate is connected to the n-1th stage GOA circuit.
  • the second node of the cell otherwise its gate inputs a third enable signal;
  • a ninth thin film transistor having a source and a drain connected to a second node of the first node and the nth stage GOA circuit unit, respectively.
  • the gate is connected to the n+1th stage GOA circuit
  • the second node of the cell otherwise its gate inputs a fourth enable signal;
  • a first capacitor the two ends of which are respectively connected to the signal output points of the second node of the nth stage GOA circuit unit and the nth stage GOA circuit unit;
  • the second capacitor has two ends connected to the third node and the constant voltage low potential VGL.
  • the first clock signal and the second clock signal are rectangular waves having a duty ratio of 0.25, and the waveforms between the first clock signal and the second clock signal are different by one-half cycle.
  • the first start signal is initially Starting from a high level
  • the first enable signal goes low
  • the signal output point of the nth stage GOA circuit unit becomes a high level
  • the second start signal when the reverse scan is performed, the second start signal is initially at a high level, and when the second start signal is turned to a low level, the signal output point of the nth stage GOA circuit unit is changed. Is high.
  • the third start signal is at a high level.
  • the fourth start signal is at a high level.
  • the present invention also provides a GOA circuit comprising a plurality of cascaded GOA circuit units, wherein n is a natural number greater than 0, and the nth-level GOA circuit unit comprises:
  • a first thin film transistor having a source and a drain connected to the first node and a constant voltage high potential, respectively.
  • the gate is connected to the signal output point of the n-1th stage GOA circuit unit. Otherwise, its gate inputs a first enable signal;
  • a third thin film transistor having a source and a drain connected to the first node and a constant voltage high potential, respectively.
  • a seventh thin film transistor having a gate connected to the first node, a source and a drain respectively connected to the third node and a constant voltage low potential;
  • a sixth thin film transistor having a gate connected to the third node, a source and a drain respectively connected to the first node and a constant voltage low potential;
  • a fifth thin film transistor having a gate inputting a second clock signal, and a source and a drain respectively connected to the third node and a constant voltage high potential;
  • a fourth thin film transistor having a gate connected to the third node, wherein the source and the drain are respectively connected to the signal output point of the nth stage GOA circuit unit and the constant voltage low potential;
  • a second thin film transistor having a gate connected to a second node of the nth stage GOA circuit unit, a source and a drain respectively connected to a signal output point of the nth stage GOA circuit unit and an input first clock signal;
  • the eighth thin film transistor has a source and a drain connected to the second node of the first node and the nth stage GOA circuit unit, respectively.
  • the gate is connected to the n-1th stage GOA circuit.
  • the second node of the cell otherwise its gate inputs a third enable signal;
  • a ninth thin film transistor having a source and a drain connected to a second node of the first node and the nth stage GOA circuit unit, respectively.
  • the gate is connected to the n+1th GOA
  • the second node of the road unit, otherwise the gate thereof inputs a fourth start signal;
  • a first capacitor the two ends of which are respectively connected to the signal output points of the second node of the nth stage GOA circuit unit and the nth stage GOA circuit unit;
  • the first clock signal and the second clock signal are rectangular waves with a duty ratio of 0.25, and the waveforms between the first clock signal and the second clock signal are different by one-half period;
  • the GOA circuit of the present invention can prevent the Gn output from being unstable in addition to the function of the conventional GOA circuit to prevent the stress of the thin film transistor T7 from being severe.
  • 1 is a schematic diagram of a conventional GOA circuit
  • FIG. 2 is a schematic diagram of a forward scan timing of the GOA circuit of FIG. 1;
  • FIG. 3 is a schematic diagram of a reverse scan timing of the GOA circuit of FIG. 1;
  • FIG. 4 is a schematic diagram of a GOA circuit of the present invention.
  • FIG. 5 is a schematic diagram of a forward scan timing of the GOA circuit of FIG. 4;
  • FIG. 6 is a schematic diagram showing the reverse scan timing of the GOA circuit of FIG. 4.
  • FIG. 4 it is a schematic diagram of a GOA circuit of the present invention, which can be used for an LTPS panel.
  • the GOA circuit includes a plurality of cascaded GOA circuit units, wherein n is a natural number greater than 0, and the nth stage GOA circuit unit that outputs the nth horizontal scan signal includes: TFT T1, when the nth stage is not the head end In the stage, the gate is connected to the signal output point Gn-1 of the n-1th stage GOA circuit unit, the source and the drain are respectively connected to the node H and the constant voltage high potential VGH; the TFT T2 is connected to the nth stage GOA The node Qn of the circuit unit, the source and the drain are respectively connected to the signal output point Gn of the nth stage GOA circuit unit and the input clock signal CKV1; and the TFT T3, when the nth stage is not the end stage, the gate is connected to the nth The signal output point Gn+1 of the +1 level GOA circuit unit,
  • TFT T5 its gate input clock signal CKV3, source and drain are respectively connected to node P and constant voltage high potential VGH; TFT T6, its gate is connected to node P, source and drain Connect node H and constant voltage low potential VGL respectively; TFT T7, The gate is connected to the node H, the source and the drain are respectively connected to the node P and the constant voltage low potential VGL; and the TFT T8, when the nth stage is not the first stage, the gate is connected to the n-1th stage GOA circuit unit The node Qn-1, the source and the drain are respectively connected to the node H and the node Qn; and the TFT T9, when the nth stage is not the end stage, the gate thereof is connected to the node Qn+1 of the n+1th GOA circuit unit, The source and the drain are respectively connected to the node H and the node Qn; the capacitor C1 has two ends connected to the node Qn and the signal output point Gn respectively; the capacitor C
  • FIG. 5 it is a schematic diagram of the forward scan timing of the GOA circuit of FIG.
  • the specific working process of the circuit is as follows:
  • Phase 1 pre-charge: Gn-1 is high, T1 is on, and H is pre-charged. At this time, Qn-1 is high, T8 is in conduction state, and Qn is pre-charged.
  • Gn outputs a high level: in phase 1, the Qn point is precharged, C1 has a certain holding effect on the charge, T2 is in a conducting state, and a high level of CKV1 is output to the Gn terminal;
  • Gn outputs a low level: C1 has a holding effect on the high level of Qn point, while the low level of CKV1 pulls the Gn point low; while Gn+1 is high, T3 is on, and Qn is high. Level is maintained;
  • phase 4 Qn is pulled low to VGL:
  • CKV3 is high, T5 is turned on, P is pulled high, T6 is turned on, and Qn is pulled low;
  • Phase 5 Qn point and Gn point low level maintenance phase: When Qn point becomes low level, T7 is in the off state. When CKV3 is high, P is charged to a high level, T4 and T6 are in an on state, and Qn and Gn are maintained at a low level.
  • the clock signal CKV1 and the clock signal CKV3 are rectangular waves having a duty ratio of 0.25, and the waveforms between the clock signal CKV1 and the clock signal CKV3 are different by one-half cycle.
  • the present invention can use the input enable signal instead of the missing signal input for the first and last cascaded GOA units.
  • the gate of T1 inputs the first start signal, which is initially at a high level, and when it becomes a low level, the signal output point Gn Goes high.
  • the third start signal of the T8 gate input is high level.
  • FIG. 6 is a schematic diagram of the reverse scan timing of the GOA circuit of FIG.
  • Reverse scan the specific working process of the circuit (reverse scan) is introduced as follows:
  • Phase 1 pre-charge: Gn+1 is high level, T3 is on, H point is pre-charged, then Qn+1 is high, T9 is in conduction state, and Qn point is pre-charged.
  • Gn outputs a high level: in phase 1, the Qn point is precharged, C1 has a certain holding effect on the charge, T2 is in a conducting state, and a high level of CKV1 is output to the Gn terminal;
  • Gn outputs a low level: C1 has a holding effect on the high level of the Qn point, and at this time, the low level of CKV1 pulls the Gn point low; while Gn-1 is high, T1 is turned on, and Qn is high. Level is maintained;
  • phase 4 Qn is pulled low to VGL:
  • CKV3 is high, T5 is turned on, P is pulled high, T6 is turned on, and Qn is pulled low;
  • Phase 5 Qn point and Gn point low level maintenance phase: When Qn point becomes low level, T7 is in the off state. When CKV3 is high, P is charged to a high level, T4 and T6 are in an on state, and Qn and Gn are maintained at a low level.
  • the clock signal CKV1 and the clock signal CKV3 are rectangular waves having a duty ratio of 0.25, and the waveforms between the clock signal CKV1 and the clock signal CKV3 are different by one-half cycle.
  • n is the end level one GOA circuit unit
  • the gate of T3 inputs a second start signal, which is initially at a high level, and when it becomes a low level, the signal output point Gn becomes a high level.
  • the fourth start signal of the T9 gate input is high level.
  • the present invention is based on the existing GOA circuit, and the H8 and Qn points are electrically connected in parallel with T8 and T9, and the gate terminal of T8 is connected to Qn-1 (previous stage Qn point), the gate of T9 is terminated by Qn+1 (the Qn point of the latter stage). Because the Qn point corresponds to a high level only when the Gn output is high, most of the time corresponds to a low level.
  • This new connection method in addition to having the existing GOA circuit, prevents the Q (ie, Qn) point from being high-level when the bootstrap is high level, and the high level is reversed to the H point, causing the T7 TFT stress to be severe.
  • the sustain phase when leakage occurs at point H, this effect is transmitted to the Qn point, and T2 will leak to some extent, causing the Gn output to be unstable.
  • the known and potential technology/product application fields of the GOA circuit of the present invention and their application modes are as follows: 1. A liquid crystal display (Gate) driving circuit integrated on an array substrate; 2. A grid applied to a mobile phone, a display, and a television Extreme drive field; 3, can cover the advanced technology of LCD and OLED industry; 4, the stability of this circuit is suitable for high-resolution panel design.
  • Gate liquid crystal display
  • the GOA circuit of the present invention can prevent the Gn output from being unstable in addition to the function of the conventional GOA circuit to prevent the stress of the thin film transistor T7 from being severe.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)

Abstract

公开了一种GOA电路。该GOA电路包括级联的多个GOA电路单元，其中，设n为大于0的自然数，第n级GOA电路单元包括：第一薄膜晶体管（T1），第二薄膜晶体管（T2），第三薄膜晶体管（T3），第四薄膜晶体管（T4），第五薄膜晶体管（T5），第六薄膜晶体管（T6），第七薄膜晶体管（T7），第八薄膜晶体管（T8），第九薄膜晶体管（T9），第一电容（CI），以及第二电容（C2）。该GOA电路在现有的GOA电路基础上使得第一节点、第二节点之间用第八薄膜晶体管与第九薄膜晶体管并联的方式导通，第八薄膜晶体管的栅极端接前一级的第二节点，第九薄膜晶体管的栅极端接后一级的第二节点。该GOA电路除具有现有GOA电路防止造成第七薄膜晶体管应力严重的功能外，也可以防止输出端输出不稳定。

Description

GOA电路 技术领域
本发明涉及液晶显示器领域，尤其涉及一种GOA电路。
背景技术
液晶显示器(LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。低温多晶硅(LTPS)是广泛用于中小电子产品中的一种液晶显示技术，低温多晶硅液晶显示器具有高解析度、反应速度快、高开口率等诸多优点。
阵列基板行驱动(Gate Driver On Array，简称GOA)技术是利用现有薄膜晶体管液晶显示器阵列(Array)制程将栅极(Gate)行扫描驱动信号电路制作在阵列基板上，实现对栅极逐行扫描的驱动方式的一项技术。相应的面板周边集成电路也成为大家关注的焦点，并且很多人投入到板上系统(System on Panel，简称SOP)的相关技术研究，并逐步成为现实。
参见图1，其为现有的GOA电路示意图，可用于LTPS面板，主要包括8个薄膜晶体管(TFT)及2个电容。现有的GOA电路包括级联的多个GOA电路单元，其中输出第n级水平扫描信号的第n级GOA电路单元包括：TFT T1，其栅极连接第n-1级GOA电路单元的信号输出点Gn-1，源极和漏极分别连接节点H和恒压高电位VGH；TFT T2，其栅极连接节点Q，源极和漏极分别连接第n级GOA电路单元的信号输出点Gn和输入时钟信号CKV1；TFT T3，其栅极连接第n+1级GOA电路单元的信号输出点Gn+1，源极和漏极分别连接节点H和恒压高电位VGH；TFT T4，其栅极连接节点P，源极和漏极分别连接信号输出点Gn和恒压低电位VGL；TFT T5，其栅极输入时钟信号CKV3，源极和漏极分别连接节点P和恒压高电位VGH；TFT T6，其栅极连接节点P，源极和漏极分别连接节点H和恒压低电位VGL；TFT T7，其栅极连接节点H，源极和漏极分别连接节点P和恒压低电位VGL；TFT T8，其栅极连接恒压高电位VGH，源极和漏极分别连接节点H和节点Q；电容C1，其两端分别连接节点Q和信号输出点Gn；电容C2，其两端分别连接节点P和恒压低电位VGL。节点Q为用于控制栅极驱动信号输出的点；节点P为用于维持Q点及Gn点低电平的稳定点。
参见图2，其为图1的GOA电路正向扫描时序示意图，现结合图1， 对电路的具体工作过程(正向扫描)介绍如下：
阶段1，预充电：Gn-1为高电平，T1导通，H点被预充电，T8一直处于导通状态，Q点被预充电；
阶段2，Gn输出高电平：在阶段1中，Q点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV1的高电平输出到Gn端；
阶段3，Gn输出低电平：C1对Q点的高电平具有保持作用，而此时CKV1的低电平将Gn点拉低；同时Gn+1为高，T3导通，Q点高电平被维持；
阶段4，Q点拉低到VGL：当CKV3为高电平时，T5导通，P点被拉高，T6导通，Q点被拉低；
阶段5，Q点及Gn点低电平维持阶段：当Q点变为低电平后，T7处于截止状态。当CKV3为高电平时，P点被充电到高电平，T4和T6处于导通状态，Q及Gn点被维持在低电平。
参见图3，其为图1的GOA电路反向扫描时序示意图，现结合图1，对电路的具体工作过程(反向扫描)介绍如下：
阶段1，预充电：Gn+1为高电平，T3导通，H点被预充电，T8一直处于导通状态，Q点被预充电；
阶段2，Gn输出高电平：在阶段1中，Q点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV1的高电平输出到Gn端；
阶段3，Gn输出低电平：C1对Q点的高电平具有保持作用，而此时CKV1的低电平将Gn点拉低；同时Gn-1为高，T1导通，Q点高电平被维持；
阶段4，Q点拉低到VGL：当CKV3为高电平时，T5导通，P点被拉高，T6导通，Q点被拉低；
阶段5，Q点及Gn点低电平维持阶段：当Q点变为低电平后，T7处于截止状态。当CKV3为高电平时，P点被充电到高电平，T4和T6处于导通状态，Q及Gn点被维持在低电平。
图1所示的现有的GOA电路引入Q点及H点。Q点在Gn输出为高电平时会被C1自举。详细波形见图图2及图3，为了防止Q点在被自举为高电平时Q点的高电平反灌到H点造成T7 TFT应力(Stress)严重，会在Q点与H点之间增加一个TFT T8，T8的栅极(Gate)接VGH。这种方式的GOA电路中，T8一直处于导通的状态，在低电平维持阶段时，当H点产生漏电时，这种效应会被传送到Q点，T2一定程度上会漏电，造成Gn输出不稳定，亟需改善。
发明内容
本发明的目的在于在现有的GOA电路基础上提出新的GOA电路，解决现有GOA电路Gn输出不稳定的问题。
为实现上述目的，本发明提供了一种GOA电路，包括级联的多个GOA电路单元，其中，设n为大于0的自然数，第n级GOA电路单元包括：
第一薄膜晶体管，其源极和漏极分别连接第一节点和恒压高电位VGH，当第n级非为首端一级时，其栅极连接第n-1级GOA电路单元的信号输出点，否则其栅极输入第一启动信号；
第三薄膜晶体管，其源极和漏极分别连接第一节点和恒压高电位VGH，当第n级非为末端一级时，其栅极连接第n+1级GOA电路单元的信号输出点，否则其栅极输入第二启动信号；
第七薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第三节点和恒压低电位VGL；
第六薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第一节点和恒压低电位VGL；
第五薄膜晶体管，其栅极输入第二时钟信号，源极和漏极分别连接第三节点和恒压高电位VGH；
第四薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和恒压低电位VGL；
第二薄膜晶体管，其栅极连接第n级GOA电路单元的第二节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和输入第一时钟信号；
第八薄膜晶体管，其源极和漏极分别连接第一节点和第n级GOA电路单元的第二节点，当第n级非为首端一级时，其栅极连接第n-1级GOA电路单元的第二节点，否则其栅极输入第三启动信号；
第九薄膜晶体管，其源极和漏极分别连接第一节点和第n级GOA电路单元的第二节点，当第n级非为末端一级时，其栅极连接第n+1级GOA电路单元的第二节点，否则其栅极输入第四启动信号；
第一电容，其两端分别连接第n级GOA电路单元的第二节点和第n级GOA电路单元的信号输出点；
第二电容，其两端分别连接第三节点和恒压低电位VGL。
其中，该第一时钟信号和第二时钟信号为占空比为0.25的矩形波，该第一时钟信号和第二时钟信号之间波形相差二分之一周期。
其中，对于首端一级GOA电路单元，正向扫描时，该第一启动信号初 始为高电平，当该第一启动信号变为低电平时，该第n级GOA电路单元的信号输出点变为高电平。
其中，对于末端一级GOA电路单元，反向扫描时，该第二启动信号初始为高电平，当该第二启动信号变为低电平时，该第n级GOA电路单元的信号输出点变为高电平。
其中，对于首端一级GOA电路单元，正向扫描时，当该第一启动信号为高电平时，该第三启动信号为高电平。
其中，对于末端一级GOA电路单元，反向扫描时，当该第二启动信号为高电平时，该第四启动信号为高电平。
其中，其为LTPS面板的GOA电路。
其中，其为OLED面板的GOA电路。
本发明还提供一种GOA电路，包括级联的多个GOA电路单元，其中，设n为大于0的自然数，第n级GOA电路单元包括：
第一薄膜晶体管，其源极和漏极分别连接第一节点和恒压高电位，当第n级非为首端一级时，其栅极连接第n-1级GOA电路单元的信号输出点，否则其栅极输入第一启动信号；
第三薄膜晶体管，其源极和漏极分别连接第一节点和恒压高电位，当第n级非为末端一级时，其栅极连接第n+1级GOA电路单元的信号输出点，否则其栅极输入第二启动信号；
第七薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第三节点和恒压低电位；
第六薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第一节点和恒压低电位；
第五薄膜晶体管，其栅极输入第二时钟信号，源极和漏极分别连接第三节点和恒压高电位；
第四薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和恒压低电位；
第二薄膜晶体管，其栅极连接第n级GOA电路单元的第二节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和输入第一时钟信号；
第八薄膜晶体管，其源极和漏极分别连接第一节点和第n级GOA电路单元的第二节点，当第n级非为首端一级时，其栅极连接第n-1级GOA电路单元的第二节点，否则其栅极输入第三启动信号；
第九薄膜晶体管，其源极和漏极分别连接第一节点和第n级GOA电路单元的第二节点，当第n级非为末端一级时，其栅极连接第n+1级GOA电 路单元的第二节点，否则其栅极输入第四启动信号；
第一电容，其两端分别连接第n级GOA电路单元的第二节点和第n级GOA电路单元的信号输出点；
第二电容，其两端分别连接第三节点和恒压低电位；
其中，该第一时钟信号和第二时钟信号为占空比为0.25的矩形波，该第一时钟信号和第二时钟信号之间波形相差二分之一周期；
其中，其为LTPS面板的GOA电路。
综上，本发明的GOA电路除具有现有GOA电路防止造成薄膜晶体管T7应力严重的功能外，也可以防止Gn输出不稳定。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有的GOA电路示意图；
图2为图1的GOA电路正向扫描时序示意图；
图3为图1的GOA电路反向扫描时序示意图；
图4为本发明的GOA电路示意图；
图5为图4的GOA电路正向扫描时序示意图；
图6为图4的GOA电路反向扫描时序示意图。
具体实施方式
参见图4，其为本发明的GOA电路示意图，可用于LTPS面板。该GOA电路包括级联的多个GOA电路单元，其中，设n为大于0的自然数，输出第n级水平扫描信号的第n级GOA电路单元包括：TFT T1，当第n级非为首端一级时，其栅极连接第n-1级GOA电路单元的信号输出点Gn-1，源极和漏极分别连接节点H和恒压高电位VGH；TFT T2，其栅极连接第n级GOA电路单元的节点Qn，源极和漏极分别连接第n级GOA电路单元的信号输出点Gn和输入时钟信号CKV1；TFT T3，当第n级非为末端一级时，其栅极连接第n+1级GOA电路单元的信号输出点Gn+1，源极和漏极分别连接节点H和恒压高电位VGH；TFT T4，其栅极连接节点P，源极和漏极分别连接信号输出点Gn和恒压低电位VGL；TFT T5，其栅极输入时钟信号CKV3，源极和漏极分别连接节点P和恒压高电位VGH；TFT T6，其栅极连接节点P，源极和漏极分别连接节点H和恒压低电位VGL；TFT T7， 其栅极连接节点H，源极和漏极分别连接节点P和恒压低电位VGL；TFT T8，当第n级非为首端一级时，其栅极连接第n-1级GOA电路单元的节点Qn-1，源极和漏极分别连接节点H和节点Qn；TFT T9，当第n级非为末端一级时，其栅极连接第n+1级GOA电路单元的节点Qn+1，源极和漏极分别连接节点H和节点Qn；电容C1，其两端分别连接节点Qn和信号输出点Gn；电容C2，其两端分别连接节点P和恒压低电位VGL。
参见图5，其为图4的GOA电路正向扫描时序示意图。现结合图4，对电路的具体工作过程(正向扫描)介绍如下：
阶段1，预充电：Gn-1为高电平，T1导通，H点被预充电，此时Qn-1为高，T8处于导通状态，Qn点被预充电。
阶段2，Gn输出高电平：在阶段1中，Qn点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV1的高电平输出到Gn端；
阶段3，Gn输出低电平：C1对Qn点的高电平具有保持作用，而此时CKV1的低电平将Gn点拉低；同时Gn+1为高，T3导通，Qn点高电平被维持；
阶段4，Qn点拉低到VGL：当CKV3为高电平时，T5导通，P点被拉高，T6导通，Qn点被拉低；
阶段5，Qn点及Gn点低电平维持阶段：当Qn点变为低电平后，T7处于截止状态。当CKV3为高电平时，P点被充电到高电平，T4和T6处于导通状态，Qn及Gn点被维持在低电平。
从图5中还可知时钟信号CKV1和时钟信号CKV3为占空比为0.25的矩形波，时钟信号CKV1和时钟信号CKV3之间波形相差二分之一周期。
本发明对于首、末端级联的GOA单元可以采用输入启动信号的方式来代替缺少的信号输入。正向扫描时，当n＝1时，即首端一级GOA电路单元中，T1的栅极输入第一启动信号，其初始为高电平，当其变为低电平时，信号输出点Gn变为高电平。
首端一级GOA电路单元中，正向扫描时，当第一启动信号为高电平时，T8栅极输入的第三启动信号为高电平。
参见图6，其为图4的GOA电路反向扫描时序示意图。现结合图4，对电路的具体工作过程(反向扫描)介绍如下：
阶段1，预充电：Gn+1为高电平，T3导通，H点被预充电，此时Qn+1为高，T9处于导通状态，Qn点被预充电。
阶段2，Gn输出高电平：在阶段1中，Qn点被预充电，C1对电荷具有一定的保持作用，T2处于导通状态，CKV1的高电平输出到Gn端；
阶段3，Gn输出低电平：C1对Qn点的高电平具有保持作用，而此时CKV1的低电平将Gn点拉低；同时Gn-1为高，T1导通，Qn点高电平被维持；
阶段4，Qn点拉低到VGL：当CKV3为高电平时，T5导通，P点被拉高，T6导通，Qn点被拉低；
阶段5，Qn点及Gn点低电平维持阶段：当Qn点变为低电平后，T7处于截止状态。当CKV3为高电平时，P点被充电到高电平，T4和T6处于导通状态，Qn及Gn点被维持在低电平。
从图6中还可知时钟信号CKV1和时钟信号CKV3为占空比为0.25的矩形波，时钟信号CKV1和时钟信号CKV3之间波形相差二分之一周期。
对于反向扫描，当n为末端一级GOA电路单元时，T3的栅极输入第二启动信号，其初始为高电平，当其变为低电平时，信号输出点Gn变为高电平。
对于末端一级GOA电路单元，反向扫描时，当第二启动信号为高电平时，T9栅极输入的第四启动信号为高电平。
如图4中虚线框部分所示，本发明在现有的GOA电路基础上H点、Qn点之间用T8与T9并联的方式导通，T8的栅极端接Qn-1(前一级的Qn点)，T9的栅极端接Qn+1(后一级的Qn点)。因为Qn点只有在Gn输出为高电平时对应为高电平，大部分时间对应为低电平。这种新的连接方式，除了具有现有GOA电路防止Q(即Qn)点在被自举为高电平时高电平反灌到H点造成T7 TFT应力严重功能外，也可以防止在低电平维持阶段时，当H点产生漏电时，这种效应会被传送到Qn点，T2一定程度上会漏电，造成Gn输出不稳定。
本发明的GOA电路已知和潜在的技术/产品应用领域及其应用方式如下：1、集成在阵列基板上的液晶显示器行扫描(Gate)驱动电路；2、应用于手机，显示器，电视的栅极驱动领域；3、可涵盖LCD和OLED的行业先进技术；4、本电路的稳定性适用于高解析度的面板设计当中。
综上，本发明的GOA电路除具有现有GOA电路防止造成薄膜晶体管T7应力严重的功能外，也可以防止Gn输出不稳定。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (13)

  1. 一种GOA电路，包括级联的多个GOA电路单元，其中，设n为大于0的自然数，第n级GOA电路单元包括：
    第一薄膜晶体管，其源极和漏极分别连接第一节点和恒压高电位，当第n级非为首端一级时，其栅极连接第n-1级GOA电路单元的信号输出点，否则其栅极输入第一启动信号；
    第三薄膜晶体管，其源极和漏极分别连接第一节点和恒压高电位，当第n级非为末端一级时，其栅极连接第n+1级GOA电路单元的信号输出点，否则其栅极输入第二启动信号；
    第七薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第三节点和恒压低电位；
    第六薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第一节点和恒压低电位；
    第五薄膜晶体管，其栅极输入第二时钟信号，源极和漏极分别连接第三节点和恒压高电位；
    第四薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和恒压低电位；
    第二薄膜晶体管，其栅极连接第n级GOA电路单元的第二节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和输入第一时钟信号；
    第八薄膜晶体管，其源极和漏极分别连接第一节点和第n级GOA电路单元的第二节点，当第n级非为首端一级时，其栅极连接第n-1级GOA电路单元的第二节点，否则其栅极输入第三启动信号；
    第九薄膜晶体管，其源极和漏极分别连接第一节点和第n级GOA电路单元的第二节点，当第n级非为末端一级时，其栅极连接第n+1级GOA电路单元的第二节点，否则其栅极输入第四启动信号；
    第一电容，其两端分别连接第n级GOA电路单元的第二节点和第n级GOA电路单元的信号输出点；
    第二电容，其两端分别连接第三节点和恒压低电位。
  2. 如权利要求1所述的GOA电路，其中，该第一时钟信号和第二时钟信号为占空比为0.25的矩形波，该第一时钟信号和第二时钟信号之间波形相差二分之一周期。
  3. 如权利要求1所述的GOA电路，其中，对于首端一级GOA电路单 元，正向扫描时，该第一启动信号初始为高电平，当该第一启动信号变为低电平时，该第n级GOA电路单元的信号输出点变为高电平。
  4. 如权利要求1所述的GOA电路，其中，对于末端一级GOA电路单元，反向扫描时，该第二启动信号初始为高电平，当该第二启动信号变为低电平时，该第n级GOA电路单元的信号输出点变为高电平。
  5. 如权利要求1所述的GOA电路，其中，对于首端一级GOA电路单元，正向扫描时，当该第一启动信号为高电平时，该第三启动信号为高电平。
  6. 如权利要求1所述的GOA电路，其中，对于末端一级GOA电路单元，反向扫描时，当该第二启动信号为高电平时，该第四启动信号为高电平。
  7. 如权利要求1所述的GOA电路，其中，其为LTPS面板的GOA电路。
  8. 如权利要求1所述的GOA电路，其中，其为OLED面板的GOA电路。
  9. 一种GOA电路，包括级联的多个GOA电路单元，其中，设n为大于0的自然数，第n级GOA电路单元包括：
    第一薄膜晶体管，其源极和漏极分别连接第一节点和恒压高电位，当第n级非为首端一级时，其栅极连接第n-1级GOA电路单元的信号输出点，否则其栅极输入第一启动信号；
    第三薄膜晶体管，其源极和漏极分别连接第一节点和恒压高电位，当第n级非为末端一级时，其栅极连接第n+1级GOA电路单元的信号输出点，否则其栅极输入第二启动信号；
    第七薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第三节点和恒压低电位；
    第六薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第一节点和恒压低电位；
    第五薄膜晶体管，其栅极输入第二时钟信号，源极和漏极分别连接第三节点和恒压高电位；
    第四薄膜晶体管，其栅极连接第三节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和恒压低电位；
    第二薄膜晶体管，其栅极连接第n级GOA电路单元的第二节点，源极和漏极分别连接第n级GOA电路单元的信号输出点和输入第一时钟信号；
    第八薄膜晶体管，其源极和漏极分别连接第一节点和第n级GOA电路 单元的第二节点，当第n级非为首端一级时，其栅极连接第n-1级GOA电路单元的第二节点，否则其栅极输入第三启动信号；
    第九薄膜晶体管，其源极和漏极分别连接第一节点和第n级GOA电路单元的第二节点，当第n级非为末端一级时，其栅极连接第n+1级GOA电路单元的第二节点，否则其栅极输入第四启动信号；
    第一电容，其两端分别连接第n级GOA电路单元的第二节点和第n级GOA电路单元的信号输出点；
    第二电容，其两端分别连接第三节点和恒压低电位；
    其中，该第一时钟信号和第二时钟信号为占空比为0.25的矩形波，该第一时钟信号和第二时钟信号之间波形相差二分之一周期；
    其中，其为LTPS面板的GOA电路。
  10. 如权利要求9所述的GOA电路，其中，对于首端一级GOA电路单元，正向扫描时，该第一启动信号初始为高电平，当该第一启动信号变为低电平时，该第n级GOA电路单元的信号输出点变为高电平。
  11. 如权利要求9所述的GOA电路，其中，对于末端一级GOA电路单元，反向扫描时，该第二启动信号初始为高电平，当该第二启动信号变为低电平时，该第n级GOA电路单元的信号输出点变为高电平。
  12. 如权利要求9所述的GOA电路，其中，对于首端一级GOA电路单元，正向扫描时，当该第一启动信号为高电平时，该第三启动信号为高电平。
  13. 如权利要求9所述的GOA电路，其中，对于末端一级GOA电路单元，反向扫描时，当该第二启动信号为高电平时，该第四启动信号为高电平。
PCT/CN2016/113324 2016-12-27 2016-12-30 Goa电路 Ceased WO2018119967A1 (zh)

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