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WO2018192326A1 - Unité d'attaque de grille, procédé d'attaque associé, circuit d'attaque de grille et dispositif d'affichage - Google Patents

Unité d'attaque de grille, procédé d'attaque associé, circuit d'attaque de grille et dispositif d'affichage Download PDF

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Publication number
WO2018192326A1
WO2018192326A1 PCT/CN2018/078958 CN2018078958W WO2018192326A1 WO 2018192326 A1 WO2018192326 A1 WO 2018192326A1 CN 2018078958 W CN2018078958 W CN 2018078958W WO 2018192326 A1 WO2018192326 A1 WO 2018192326A1
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WO
WIPO (PCT)
Prior art keywords
pull
clock signal
transistor
node
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/078958
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English (en)
Chinese (zh)
Inventor
李艳
时凌云
孙伟
谢晓波
金美灵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/094,615 priority Critical patent/US11114004B2/en
Publication of WO2018192326A1 publication Critical patent/WO2018192326A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas

Definitions

  • Embodiments of the present disclosure relate to the field of display driving technologies, and in particular, to a gate driving unit, a driving method thereof, a gate driving circuit, and a display device.
  • a gate driving unit including: an input reset module, a memory module, a pull-up node control module, a pull-down node control module, and an output module; and the input reset module and the pull-up node Connecting; the pull-up node control module is respectively connected to the pull-down node and the pull-up node; the storage module is respectively connected to the pull-up node and the gate drive signal output end;
  • the pull-down node control module is respectively connected to the first clock signal end, the pull-up node and the pull-down node, for when the potential of the pull-up node is at a first level and the first clock signal end is input Controlling, by the second level, the pull-down node is connected to the first clock signal end;
  • the output module is respectively connected to the pull-up node, the pull-down node, the second clock signal end, and the gate driving signal output end, and is configured to control the gate when the potential of the pull-up node is at a second level
  • the pole drive signal output end is connected to the second clock signal end;
  • the gate driving unit further includes a clock signal control module
  • the clock signal control module is respectively connected to the first control signal end, the second control signal end, the first reference clock signal end, the second reference clock signal end, the first clock signal end, and the second clock signal end, for Controlled by a first control signal from the first control signal terminal and a second control signal from the second control signal terminal, based on a first reference clock signal from the first reference clock signal terminal and from the second And a second reference clock signal of the reference clock signal end, and simultaneously outputting a clock signal with the same frequency inversion to the first clock signal end and the second clock signal end.
  • the first reference clock signal and the second reference clock signal are inverted in phase.
  • the clock signal control module includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube, where
  • a gate of the first switch tube is connected to the first control signal end, a first pole of the first switch tube is connected to the first reference clock signal end, and a second pole of the first switch tube is Connecting the first clock signal end;
  • a gate of the second switch tube is connected to a second control signal end, a first pole of the second switch tube is connected to the first clock signal end, and a second pole of the second switch tube is The second reference clock signal terminal is connected;
  • a gate of the third switch tube is connected to the first control signal end, a first pole of the third switch tube is connected to the second reference clock signal end, and a second pole of the third switch tube Connected to the second clock signal end;
  • a gate of the fourth switch tube is connected to the second control signal end, a first pole of the fourth switch tube is connected to the second clock signal end, and a second pole of the fourth switch tube is The first reference clock signal ends are connected.
  • the clock signal control module includes a first switch tube, a second switch tube, and an inverter, where
  • a gate of the first switch tube is connected to the first control signal end, a first pole of the first switch tube is connected to the first reference clock signal end, and a second pole of the first switch tube is Connecting the first clock signal end;
  • a gate of the second switch tube is connected to a second control signal end, a first pole of the second switch tube is connected to the first clock signal end, and a second pole of the second switch tube is The second reference clock signal terminal is connected;
  • An input end of the inverter is connected to the first clock signal end, and an output end of the inverter is connected to the second clock signal end.
  • the pull-down node control module is further connected to the gate driving signal output end and the first level input end, respectively, and is further configured to: when the potential of the pull-up node is the second power Normally controlling the pull-down node to be connected to the first level input terminal, and controlling the pull-down node and the first power when a potential of a gate driving signal outputted by the gate driving signal output terminal is a second level Flat input connection;
  • the output module is further connected to the first level input end, and is further configured to control the gate driving signal output end to be connected to the first level input end when the potential of the pull-down node is at a second level .
  • the pull-down node control module includes a first pull-down node control transistor, a second pull-down node control transistor, a third pull-down node control transistor, and a pull-down node potential maintaining capacitor, where
  • a gate of the first pull-down node control transistor is connected to the pull-up node, and a first pole of the first pull-down node control transistor is connected to the first level input terminal, the first pull-down a second pole of the node control transistor is connected to the pull-down node;
  • a gate of the second pull-down node control transistor is connected to the gate driving signal output end, a second pole of the second pull-down node control transistor is connected to the pull-down node, and the second pull-down node controls a transistor a second pole is connected to the first level input terminal;
  • the gate of the third pull-down node control transistor and the first pole of the third pull-down node control transistor are both connected to the first clock signal end, and the third pull-down node controls the second pole of the transistor and the Pull down the node connection;
  • a first end of the pull-down node potential maintaining capacitor is connected to the pull-down node, and a second end of the pull-down node potential maintaining capacitor is connected to the first level input end;
  • the output module includes a pull-up transistor and a pull-down transistor, wherein
  • a gate of the pull-up transistor is connected to the pull-up node, a first pole of the pull-up transistor is connected to the second clock signal terminal, and a second pole of the pull-up transistor is driven by the gate Signal output connection;
  • a gate of the pull-down transistor is connected to the pull-down node, a first pole of the pull-down transistor is connected to the gate drive signal output terminal, and a second pole of the pull-down transistor and the first level input terminal connection.
  • the input reset module includes an input transistor and a reset transistor, wherein
  • a gate of the input transistor is coupled to the input terminal, a first pole of the input transistor is coupled to the first scan level input terminal, and a second pole of the input transistor is coupled to the pull up node;
  • a gate of the reset transistor is connected to the reset terminal, a first pole of the reset transistor is connected to the pull-up node, and a second pole of the reset transistor is connected to a second scan level input end;
  • the storage module includes a storage capacitor; a first end of the storage capacitor is connected to the pull-up node, and a second end of the storage capacitor is connected to the gate drive signal output end;
  • the pull-up node control module includes a pull-up node control transistor; a gate of the pull-up node control transistor is connected to the pull-down node, and a first pole of the pull-up node control transistor is connected to the pull-up node, The second pole of the pull-up node control transistor is coupled to the first level input.
  • a driving method of a gate driving unit which is applied to the above-described gate driving unit, and the driving method of the gate driving unit includes:
  • the clock signal control module Under the control of the first control signal and the second control signal, the clock signal control module provides the first clock signal to the first clock signal input terminal according to the first reference clock signal and the second reference clock signal. And providing a second clock signal to the second clock signal input end; the first clock signal and the second clock signal are inverted at the same frequency; the first control signal and the second control signal are at a fixed level signal;
  • the clock signal control module under the control of the first control signal and the second control signal, provides a third clock signal to the first clock signal input terminal according to the first reference clock signal and the second reference clock signal, and Providing a fourth clock signal to the second clock signal input end; the third clock signal and the fourth clock signal are in phase inverted; the first control signal and the second control signal have the same frequency; a reference clock signal and a second reference clock signal are inverted in phase; the period of the first reference clock signal and the period of the second reference clock signal are both T; the first control signal is delayed by T from the first reference clock signal /4;
  • the frequency of the third clock signal is greater than the frequency of the first clock signal.
  • a gate driving circuit comprising a plurality of cascaded gate driving units as described above.
  • a display device comprising the above-described gate driving circuit.
  • FIG. 1 is a structural diagram of a gate driving unit according to an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a gate driving unit according to an embodiment of the present disclosure
  • FIG. 3 is an operational timing diagram of an embodiment of the gate driving unit shown in FIG. 2 of the present disclosure
  • FIG. 4 is a circuit diagram of a first embodiment of a gate driving unit of the present disclosure
  • FIG. 5 is an operational timing diagram of a first embodiment of a gate driving unit of the present disclosure
  • FIG. 6 is a circuit diagram of a second embodiment of a gate drive unit of the present disclosure.
  • the gate driving unit includes an input reset module 11 , a storage module 12 , a pull-up node control module 13 , a pull-down node control module 14 , and an output module 15 .
  • the input reset module 11 is connected to the pull-up node PU.
  • the pull-up node control module 13 is connected to the pull-down node PD and the pull-up node PU, respectively.
  • the memory module 12 is respectively connected to the pull-up node PU and the gate driving signal output terminal OUT.
  • the pull-down node control module 14 is respectively connected to the first clock signal terminal CKB_N, the pull-up node PU, and the pull-down node PD, for when the potential of the pull-up node PU is at a first level and the When the clock signal terminal CKB_N outputs the second level, the pull-down node PD is controlled to be connected to the first clock signal terminal CKB_N.
  • the output module 15 is connected to the pull-up node PU, the pull-down node PD, the second clock signal terminal CK_N and the gate driving signal output terminal OUT, respectively, for when the potential of the pull-up node PU is the second
  • the gate driving signal output terminal OUT is connected to the second clock signal terminal CK_N at the level.
  • the gate drive unit also includes a clock signal control module 16.
  • the clock signal control module 16 is respectively connected to the first control signal terminal EN1, the second control signal terminal EN2, the first reference clock signal terminal CKB, the second reference clock signal terminal CK, the first clock signal terminal CKB_N, and the second clock signal.
  • a terminal CK_N connected for controlling the first reference clock signal from the first control signal from the first control signal terminal EN1 and the second control signal from the second control signal terminal EN2 a first reference clock signal of the CKB and a second reference clock signal from the second reference clock signal terminal CK, and simultaneously output clocks of the same frequency inversion to the first clock signal terminal CKB_N and the second clock signal terminal CK_N signal.
  • the gate driving unit of the embodiment of the present disclosure adds a clock signal control module 16 capable of simultaneously controlling the first reference clock signal and the second reference clock signal under the control of the first control signal and the second control signal.
  • the first clock signal terminal CKB_N and the second clock signal terminal CK_N respectively output clock signals of the same frequency inversion.
  • the frequency of the clock signal supplied to the first clock signal terminal CKB_N and the second clock signal terminal CK_N can be adjusted at any time, and the frequency of the clock signal can be switched at any time, so that the display panel can be at any time.
  • the different resolutions are switched to realize the Smart View function, and the high-definition display mode and the low-power display mode can be switched at will, thereby satisfying the visual requirements and effectively reducing the power consumption.
  • the first reference clock signal and the second reference clock signal are inverted in the same frequency.
  • the clock signal control module includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube.
  • a gate of the first switch tube is connected to the first control signal end, a first pole of the first switch tube is connected to the first reference clock signal end, and a second pole of the first switch tube is The first clock signal terminal is connected.
  • a gate of the second switch tube is connected to a second control signal end, a first pole of the second switch tube is connected to the first clock signal end, and a second pole of the second switch tube is The second reference clock signal terminal is connected.
  • a gate of the third switch tube is connected to the first control signal end, a first pole of the third switch tube is connected to the second reference clock signal end, and a second pole of the third switch tube Connected to the second clock signal terminal.
  • a gate of the fourth switch tube is connected to the second control signal end, a first pole of the fourth switch tube is connected to the second clock signal end, and a second pole of the fourth switch tube is The first reference clock signal ends are connected.
  • the clock signal control module 16 includes a first switch tube MK1, a second switch tube MK2, a third switch tube MK3, and a fourth switch tube MK4. among them,
  • the gate of the first switch MK1 is connected to the first control signal terminal EN1, the drain of the first switch MK1 is connected to the first reference clock signal terminal CKB, and the source of the first switch MK1 The pole is connected to the first clock signal terminal CKB_N.
  • a gate of the second switch MK2 is connected to a second control signal terminal EN2, a drain of the second switch transistor MK2 is connected to the first clock signal terminal CKB_N, and a source of the second switch transistor MK2 Connected to the second reference clock signal terminal CK.
  • the gate of the third switch tube MK3 is connected to the first control signal terminal EN1, the drain of the third switch tube MK3 is connected to the second reference clock signal terminal CK, and the third switch tube MK3 The source is connected to the second clock signal terminal CK_N.
  • the gate of the fourth switch tube MK4 is connected to the second control signal terminal EN2, the drain of the fourth switch tube MK4 is connected to the second clock signal terminal CK_N, and the fourth switch tube MK4 The source is connected to the first reference clock signal terminal CKB.
  • each of the switching transistors is an n-type transistor, but here only the n-type is taken as an example. In actual operation, each of the switching transistors may also be a p-type transistor, and the type of the transistor is not limited herein.
  • the clock signals output to CKB_N, CK_N are the clock signals required for the gate drive unit display.
  • EN1 In the low power display phase T1, EN1 outputs a high level, and EN2 outputs a low level. At this time, MK1 and MK3 are turned on, and MK2 and MK4 are turned off.
  • CKB_N is connected to CKB, and the clock signal output to CKB_N is the first reference clock signal output by CKB.
  • CK is connected to CK_N, and the clock signal output to CK_N is the second reference clock signal of the CK output.
  • the first control signal and the second control signal are both clock signals.
  • EN1 When EN1 outputs a high level, EN2 outputs a low level, MK1 turns on, MK2 turns off, MK3 turns on, MK4 turns off, CKB_N is connected to CKB, and CK_N is connected to CK.
  • EN1 When EN1 outputs a low level and EN2 outputs a high level, MK1 is turned off, MK2 is turned on, MK3 is turned off, MK4 is turned on, CKB_N is connected to CK, and CK_N is connected to CKB.
  • EN1 When EN1 outputs a low level, EN2 outputs a high level, MK2 turns on, MK1 turns off, MK4 turns on, MK3 turns off, CKB_N is connected to CK, and CK_N is connected to CKB.
  • EN2 When EN2 outputs a low level and EN1 outputs a high level, MK2 is turned off, MK1 is turned on, MK4 is turned off, MK3 is turned on, CKB_N is connected to CKB, and CK_N is connected to CK.
  • the frequency of the clock signal outputted to CKB_N, CK_N can be made twice the frequency of the first reference clock signal to achieve high definition. display.
  • the first reference clock signal and the second reference clock signal are inverted in the same frequency, and the period of the first reference clock signal and the period of the second reference clock signal are both T.
  • the waveform of the first control signal is delayed by T/4 from the first reference clock signal in the high definition display phase T2.
  • the waveform of the second control signal is inverted in the high-definition display phase T2 and the waveform of the first control signal in the high-definition display phase T2.
  • the embodiment of the gate driving unit shown in FIG. 2 adopts a clock signal control module to control MK1, MK2, MK3, and MK4 through EN1 and EN2, and the first reference clock signal and the CK output according to the CKB output.
  • the two reference clock signals output clock signals of the same frequency inversion to CKB_N and CK_N.
  • the waveform of the first control signal and the waveform of the second control signal are set in different stages, so that the frequency of the clock signal outputted to the CKB_N, CK_N in the high-definition display stage T2 is the frequency of the first reference clock signal.
  • the corresponding gate line charging time becomes half of the original, thereby adjusting the high resolution and realizing the function of high definition display.
  • the frequency of the clock signal output to CKB_N, CK_N is equal to the frequency of the first reference clock signal, thereby achieving a low power consumption function.
  • the waveform of the first control signal and the waveform of the second control signal may be internally controlled by a display driver IC (Integrated Circuit).
  • the clock signal control module includes a first switch tube, a second switch tube, and an inverter, where
  • a gate of the first switch tube is connected to the first control signal end, a first pole of the first switch tube is connected to the first reference clock signal end, and a second pole of the first switch tube is Connecting the first clock signal end;
  • a gate of the second switch tube is connected to a second control signal end, a first pole of the second switch tube is connected to the first clock signal end, and a second pole of the second switch tube is The second reference clock signal terminal is connected;
  • An input end of the inverter is connected to the first clock signal end, and an output end of the inverter is connected to the second clock signal end;
  • the inverter ensures that the clock signal outputted to the first clock signal terminal is inverted with the clock signal outputted to the second clock signal terminal.
  • the pull-down node control module is further connected to the gate driving signal output end and the first level input end, and is further configured to control the pull-down node when the potential of the pull-up node is at a second level And connecting to the first level input terminal, and controlling the pull-down node to be connected to the first level input terminal when a potential of the gate driving signal outputted by the gate driving signal output terminal is a second level.
  • the output module is further connected to the first level input end, and is further configured to control the gate driving signal output end to be connected to the first level input end when the potential of the pull-down node is at a second level .
  • the pull-down node control module may include a first pull-down node control transistor, a second pull-down node control transistor, a third pull-down node control transistor, and a pull-down node potential maintaining capacitor, where
  • a gate of the first pull-down node control transistor is connected to the pull-up node, and a first pole of the first pull-down node control transistor is connected to the first level input terminal, the first pull-down a second pole of the node control transistor is connected to the pull-down node;
  • a gate of the second pull-down node control transistor is connected to the gate driving signal output end, a second pole of the second pull-down node control transistor is connected to the pull-down node, and the second pull-down node controls a transistor a second pole is connected to the first level input terminal;
  • the gate of the third pull-down node control transistor and the first pole of the third pull-down node control transistor are both connected to the first clock signal end, and the third pull-down node controls the second pole of the transistor and the Drop-down node connection; and,
  • a first end of the pull-down node potential maintaining capacitor is connected to the pull-down node, and a second end of the pull-down node potential maintaining capacitor is connected to the first level input end;
  • the output module may include a pull-up transistor and a pull-down transistor, wherein
  • a gate of the pull-up transistor is connected to the pull-up node, a first pole of the pull-up transistor is connected to the second clock signal terminal, and a second pole of the pull-up transistor is driven by the gate Signal output connection;
  • a gate of the pull-down transistor is connected to the pull-down node, a first pole of the pull-down transistor is connected to the gate drive signal output terminal, and a second pole of the pull-down transistor and the first level input terminal connection.
  • the input reset module may include an input transistor and a reset transistor, where
  • a gate of the input transistor is coupled to the input terminal, a first pole of the input transistor is coupled to the first scan level input terminal, and a second pole of the input transistor is coupled to the pull up node;
  • a gate of the reset transistor is connected to the reset terminal, a first pole of the reset transistor is connected to the pull-up node, and a second pole of the reset transistor is connected to a second scan level input end;
  • the storage module may include a storage capacitor; a first end of the storage capacitor is connected to the pull-up node, and a second end of the storage capacitor is connected to the gate drive signal output end;
  • the pull-up node control module may include a pull-up node control transistor; the gate of the pull-up node control transistor is connected to the pull-down node, and the first pole of the pull-up node control transistor is connected to the pull-up node The second pole of the pull-up node control transistor is coupled to the first level input terminal.
  • the gate driving unit described in the embodiment of the present disclosure will be described below by two specific embodiments.
  • a first embodiment of the gate driving unit of the present disclosure includes an input reset module, a memory module, a pull-up node control module, a pull-down node control module, an output module, and a clock signal control module.
  • the clock signal control module includes a first switch tube MK1, a second switch tube MK2, a third switch tube MK3, and a fourth switch tube MK4. among them,
  • the gate of the first switch MK1 is connected to the first control signal terminal EN1, the drain of the first switch MK1 is connected to the first reference clock signal terminal CKB, and the source of the first switch MK1 The pole is connected to the first clock signal terminal CKB_N.
  • a gate of the second switch MK2 is connected to a second control signal terminal EN2, a drain of the second switch transistor MK2 is connected to the first clock signal terminal CKB_N, and a source of the second switch transistor MK2 Connected to the second reference clock signal terminal CK.
  • the gate of the third switch tube MK3 is connected to the first control signal terminal EN1, the drain of the third switch tube MK3 is connected to the second reference clock signal terminal CK, and the third switch tube MK3 The source is connected to the second clock signal terminal CK_N.
  • the gate of the fourth switch tube MK4 is connected to the second control signal terminal EN2, the drain of the fourth switch tube MK4 is connected to the second clock signal terminal CK_N, and the fourth switch tube MK4 The source is connected to the first reference clock signal terminal CKB.
  • the pull-down node control module includes a first pull-down node control transistor MDC1, a second pull-down node control transistor MDC2, a third pull-down node control transistor MDC3, and a pull-down node potential holding capacitor Cd. among them,
  • the gate of the first pull-down node control transistor MDC1 is connected to the pull-up node PU, and the drain of the first pull-down node control transistor MDC1 is connected to the low-level input terminal of the input low level VGL.
  • the source of the first pull-down node control transistor MDC1 is connected to the pull-down node PD.
  • a gate of the second pull-down node control transistor MDC2 is connected to the gate driving signal output terminal OUT, and a drain of the second pull-down node control transistor MDC2 is connected to the pull-down node PD, the second pull-down node
  • the source of the control transistor MDC2 is connected to the low level input of the input low level VGL.
  • the gate of the third pull-down node control transistor MDC3 and the drain of the third pull-down node control transistor MDC3 are both connected to the first clock signal terminal CKB_N, and the third pull-down node controls the second pole of the transistor MDC3. Connected to the pulldown node PD.
  • the first end of the pull-down node potential maintaining capacitor Cd is connected to the pull-down node PD, and the second end of the pull-down node potential maintaining capacitor Cd is connected to the low-level input terminal of the input low level VGL.
  • the output module includes a pull-up transistor MU and a pull-down transistor MD. among them,
  • a gate of the pull-up transistor MU is connected to the pull-up node PU, a drain of the pull-up transistor MU is connected to the second clock signal terminal CK_N, and a source and a gate of the pull-up transistor MU The drive signal output terminal OUT is connected.
  • a gate of the pull-down transistor MD is connected to the pull-down node PD, a drain of the pull-down transistor MD is connected to the gate driving signal output terminal OUT, and a source of the pull-down transistor MD and an input low level VGL The low level input is connected.
  • the input reset module includes an input transistor MI and a reset transistor MR. among them,
  • a gate of the input transistor MI is connected to an input terminal STV, a drain of the input transistor MI is connected to a first scan level input terminal CN, and a source of the input transistor MI is connected to the pull-up node PU; as well as,
  • the gate of the reset transistor MR is connected to the reset terminal RESET, the drain of the reset transistor MR is connected to the pull-up node PU, and the source of the reset transistor MR is connected to the second scan level input terminal CNB.
  • the storage module includes a storage capacitor Cs.
  • the first end of the storage capacitor Cs is connected to the pull-up node PU, and the second end of the storage capacitor Cs is connected to the gate drive signal output end OUT.
  • the pull-up node control module includes a pull-up node control transistor MUC.
  • a gate of the pull-up node control transistor MUC is connected to the pull-down node PD, a first pole of the pull-up node control transistor MUC is connected to the pull-up node PU, and the pull-up node controls a transistor MUC
  • the two poles are connected to the low level input of the input low level VGL.
  • CKB_N, CK_N provide a clock signal required for display by the gate driving unit.
  • all of the transistors are n-type transistors.
  • the transistor used may also be a p-type transistor.
  • the timing of the control signal needs to be adjusted, and the type of the transistor is not limited herein.
  • the CN outputs a high level and the CNB outputs a low level.
  • EN1 outputs a high level
  • EN2 outputs a low level
  • CK_N is connected to CK
  • CKB_N is connected to CKB.
  • the input signal output by the STV turns on the MI, and the CN outputs a high level, so that the voltage of the PU is pulled high, the MDC1 is turned on, and the potential of the PD is pulled low, because the clock signal output to the CK_N is Low level, so OUT output is low.
  • the potential of the PU is lifted up by Cs.
  • the clock signal output to CK_N is high level, MU is turned on, and the MU pulls the potential of the gate drive signal of the OUT output to the high level.
  • the gate line driven by the gate drive signal is fully turned on and charged.
  • the opening time of the gate line is the high level time of the clock signal outputted to CK_N. Since it is in the low power mode at this time, the opening time of the gate line is higher than that of the gate line in the clear display mode. The opening time is longer. Both MDC1 and MDC2 are turned on, pulling the potential of the PD low.
  • CK In the first reset period T13, CK outputs a low level, CKB outputs a high level, MDC3 turns on, the potential of the PD rises to a high level, and the MD and MUC are turned on, at which time the RESET output is high, so the PU will be The potential of the gate drive signal of the potential and the OUT output is directly pulled down to the low level VGL, thereby turning off the gate line in time.
  • the first control signal and the second control signal are both clock signals.
  • the frequency of the clock signal output to CKB_N, CK_N can be made twice the frequency of the first reference clock signal. Since the gate line is turned on for a high time of the clock signal output to CK_N, the time when the gate line is turned on in the high definition display mode becomes half of that in the low power display mode, and two times in the same time The multiple number of gate lines complete the charge and discharge function, so high definition display is achieved.
  • a second embodiment of the gate driving unit of the present disclosure includes an input reset module, a memory module, a pull-up node control module, a pull-down node control module, an output module, and a clock signal control module.
  • the clock signal control module includes a first switch tube MK1, a second switch tube MK2, and an inverter F1. among them,
  • the gate of the first switch MK1 is connected to the first control signal terminal EN1, the drain of the first switch MK1 is connected to the first reference clock signal terminal CKB, and the source of the first switch MK1 The pole is connected to the first clock signal terminal CKB_N.
  • a gate of the second switch MK2 is connected to a second control signal terminal EN2, a drain of the second switch transistor MK2 is connected to the first clock signal terminal CKB_N, and a source of the second switch transistor MK2 Connected to the second reference clock signal terminal CK_N.
  • the input end of the inverter F1 is connected to the first clock signal terminal CKB_N, and the output terminal of the inverter F1 is connected to the second clock signal terminal CK_N.
  • the pull-down node control module includes a first pull-down node control transistor MDC1, a second pull-down node control transistor MDC2, a third pull-down node control transistor MDC3, and a pull-down node potential holding capacitor Cd. among them,
  • the gate of the first pull-down node control transistor MDC1 is connected to the pull-up node PU, and the drain of the first pull-down node control transistor MDC1 is connected to the low-level input terminal of the input low level VGL.
  • the source of the first pull-down node control transistor MDC1 is connected to the pull-down node PD.
  • a gate of the second pull-down node control transistor MDC2 is connected to the gate driving signal output terminal OUT, and a drain of the second pull-down node control transistor MDC2 is connected to the pull-down node PD, the second pull-down node
  • the source of the control transistor MDC2 is connected to the low level input of the input low level VGL.
  • the gate of the third pull-down node control transistor MDC3 and the drain of the third pull-down node control transistor MDC3 are both connected to the first clock signal terminal CKB_N, and the third pull-down node controls the second pole of the transistor MDC3. Connected to the pulldown node PD.
  • the first end of the pull-down node potential maintaining capacitor Cd is connected to the pull-down node PD, and the second end of the pull-down node potential maintaining capacitor Cd is connected to the low-level input terminal of the input low level VGL.
  • the output module includes a pull-up transistor MU and a pull-down transistor MD. among them,
  • a gate of the pull-up transistor MU is connected to the pull-up node PU, a drain of the pull-up transistor MU is connected to the second clock signal terminal CK_N, and a source and a gate of the pull-up transistor MU The drive signal output terminal OUT is connected.
  • a gate of the pull-down transistor MD is connected to the pull-down node PD, a drain of the pull-down transistor MD is connected to the gate driving signal output terminal OUT, and a source of the pull-down transistor MD and an input low level VGL The low level input is connected.
  • the input reset module includes an input transistor MI and a reset transistor MR. among them,
  • a gate of the input transistor MI is connected to an input terminal STV, a drain of the input transistor MI is connected to a first scan level input terminal CN, and a source of the input transistor MI is connected to the pull-up node PU; as well as,
  • the gate of the reset transistor MR is connected to the reset terminal RESET, the drain of the reset transistor MR is connected to the pull-up node PU, and the source of the reset transistor MR is connected to the second scan level input terminal CNB.
  • the storage module includes a storage capacitor Cs.
  • the first end of the storage capacitor Cs is connected to the pull-up node PU, and the second end of the storage capacitor Cs is connected to the gate drive signal output end OUT.
  • the pull-up node control module includes a pull-up node control transistor MUC.
  • a gate of the pull-up node control transistor MUC is connected to the pull-down node PD, a first pole of the pull-up node control transistor MUC is connected to the pull-up node PU, and the pull-up node controls a transistor MUC
  • the two poles are connected to the low level input of the input low level VGL.
  • the second embodiment of the gate driving unit shown in FIG. 6 differs from the first embodiment of the gate driving unit shown in FIG. 4 only in that the inverter F1 is used instead of the first embodiment.
  • the driving method of the gate driving unit in the embodiment of the present disclosure is applied to the above-mentioned gate driving unit, and the driving method of the gate driving unit includes:
  • the clock signal control module Under the control of the first control signal and the second control signal, the clock signal control module provides the first clock signal to the first clock signal input terminal according to the first reference clock signal and the second reference clock signal. And providing a second clock signal to the second clock signal input end; the first clock signal and the second clock signal are inverted at the same frequency; the first control signal and the second control signal are at a fixed level signal;
  • the clock signal control module under the control of the first control signal and the second control signal, provides the third clock signal to the first clock signal terminal according to the first reference clock signal and the second reference clock signal, and provides a fourth clock signal to the second clock signal end; the third clock signal and the fourth clock signal are inverted at the same frequency; the first control signal and the second control signal have the same frequency, it being understood that
  • the transistors in the gate driving unit are all transistors of the same type, both are n-type transistors or both are p-type transistors, and the first control signal and the second control signal are inverted at the same frequency; the first The reference clock signal and the second reference clock signal are inverted at the same frequency; the period of the first reference clock signal and the period of the second reference clock signal are both T; the first control signal is delayed by T/ from the first reference clock signal 4;
  • the frequency of the third clock signal is greater than the frequency of the first clock signal.
  • the driving method of the gate driving unit controls the frequency of the clock signal supplied to the first clock signal end and the second clock signal end in the high-definition display stage by using the clock signal control module to be provided in the low power consumption display stage.
  • the frequency of the clock signal to the first clock signal end and the second clock signal end is large to realize a Smart (View) display, and the display panel is switched between the high-definition display and the low-power mode, which can meet the visual requirement. At the same time effectively reduce power consumption.
  • the gate driving circuit of the embodiment of the present disclosure includes a plurality of cascaded gate driving units.
  • the display device includes the above-described gate driving circuit.

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Abstract

L'invention concerne une unité d'attaque de grille, un procédé d'attaque, un circuit d'attaque de grille et un dispositif d'affichage. L'unité d'attaque de grille comprend un module de réinitialisation d'entrée (11), un module de mémoire (12), un module de commande de nœud d'excursion haute (13), un module de commande de nœud d'excursion basse (14), et un module de sortie (15). L'unité d'attaque de grille comprend également un module de commande de signal d'horloge (16). Le module de commande de signal d'horloge (16) est connecté séparément à une première extrémité de signal de commande (EN1), à une seconde extrémité de signal de commande (EN2), à une première extrémité de signal d'horloge de référence (CKB), à une seconde extrémité de signal d'horloge de référence (CK), à une première extrémité de signal d'horloge (CKB_N), et à une seconde extrémité de signal d'horloge (CK _N), et sert à émettre simultanément des signaux d'horloge d'une même fréquence mais de différentes phases à la première extrémité de signal d'horloge (CKB_N) et à la seconde extrémité de signal d'horloge (CK _N) en fonction du premier signal d'horloge de référence et du second signal d'horloge de référence, sous la commande d'un premier signal de commande provenant de la première extrémité de signal de commande (EN1) et d'un second signal de commande provenant de la seconde extrémité de signal de commande (EN2).
PCT/CN2018/078958 2017-04-21 2018-03-14 Unité d'attaque de grille, procédé d'attaque associé, circuit d'attaque de grille et dispositif d'affichage Ceased WO2018192326A1 (fr)

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