WO2018189288A1

WO2018189288A1 - Short pulse suppression for phase/frequency detector

Info

Publication number: WO2018189288A1
Application number: PCT/EP2018/059385
Authority: WO
Inventors: Staffan Ek; Tony Påhlsson; Henrik Sjöland
Original assignee: Telefonaktiebolaget LM Ericsson AB
Current assignee: Telefonaktiebolaget LM Ericsson AB
Priority date: 2017-04-12
Filing date: 2018-04-12
Publication date: 2018-10-18
Anticipated expiration: 2019-10-12

Abstract

An asynchronous state machine (30) for a phase/frequency detector (12) operative in a phase locked loop (10) includes a short pulse suppression circuit (40, 50, 60, 70, 80) operative to suppress output pulses of duration on the order of the propagation delay of combinatorial logic (36) in the state machine (30). Particularly in phase locked loop (10) applications where the short pulses are not required to linearize the phase/frequency detector (12) and associated charge pump (14), suppression of the short pulses reduces current ripple and phase noise, and relaxes design constraints in the charge pump (14) such as transistor size and pulse edge slope, all without significantly increasing silicon area or power consumption.

Description

SHORT PULSE SUPPRESSION FOR PHASE/FREQUENCY DETECTOR

STATEMENT REGARDING GOVERNMENT SPONSORED RESEARCH OR DEVELOPMENT

This work was supported by the European Commission in the framework of the H2020- ICT-2014-2 project Flex5Gware (Grant agreement no. 671563).

FIELD OF INVENTION

The present invention relates generally to circuits operative in a phase locked loop, such as used to generate local oscillator signals in phased-array beamformed wireless

communication applications, and in particular to a short pulse suppression circuit for a state machine in a phase/frequency detector of such a phase locked loop.

BACKGROUND

Wireless communications networks are widely deployed, with over seven billion subscribers worldwide. Due to increasing demand and advances in technology state of the art, each "generation" of wireless communication network technology enables more subscribers to be serviced, at increased bandwidth and data rates. The first generation (1 G) were analog, voice-only radio systems, such as AMPS. Second generation (2G) networks, such as GSM and CDMAOne, introduced digital communications but were still circuit-switched. Third generation (3G) networks, such as UMTS, CDMA2000, WCDMA, and EDGE, offered increased data rates, improved security, and a mix of circuit-switched and packet-switched technologies. Fourth generation (4G) networks include LTE and WiMAX; these are fully digital, fully packet-switched networks with many advanced features, such as carrier aggregation, Coordinated Multipoint, MIMO, IPv6 support, and the like. The Third Generation Partnership Project (3GPP) is currently developing the technical standards for fifth generation (5G) networks, also known as New Radio (NR).

From 3G on, Orthogonal Frequency Division Multiplexing (OFDM) has been utilized as a multiple access technology. In OFDM, a large number of orthogonal subcarriers (e.g., each 15kHz wide) each carry data in parallel channels, each channel modulating the data into time-domain symbols. An OFDM resource is thus (conceptually) a block, or Resource Element (RE), in a time/frequency grid. To avoid inter-symbol interference, symbols are separated in the time domain by appending a cyclic prefix of redundant data to each symbol. It is foreseen that 5G cellular systems will use millimeter wave (mmW) frequencies. The frequencies currently in discussion range from about 15 to 60GHz. In order to use the system outdoors, a longer cyclic prefix is required, compared to newly released 60GHz indoor systems. This necessitates a closer sub-carrier spacing in the OFDM modulation, posing stringent phase noise requirements. At the same time, beamforming should be supported to increase the range and capacity of the system. Phased-array beamforming is implemented by a large array of individual antenna elements, each receiving or transmitting a phase-shifted signal. By controlling the phase shifts of each antenna element, constructive and destructive interference is exploited to amplify signal transmission in some directions, and attenuate or eliminate it in others. The transmission signal at each antenna array element will thus have an individual phase shift which controls the beam direction. One important implementation option is to impose phase shifts in the local oscillator signal. Programmable phase can also be used to compensate for phase deviations due to, e.g., temperature changes. The local oscillator frequency should also be made programmable, to be able to operate on different channels and in different bands.

There are numerous challenges in local oscillator generation circuitry design, including achieving low phase noise, individually programmable phase, programmable frequency, and distributing the signals to all transceivers in a beamforming system, all without consuming excessive power. Known architectures for local oscillator generation may be unable to meet these challenges.

The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.

SUMMARY

The following presents a simplified summary of the disclosure in order to provide a basic understanding to those of skill in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key/critical elements of embodiments of the invention or to delineate the scope of the invention. The sole purpose of this summary is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

According to embodiments of the present invention described and claimed herein, a digital, asynchronous state machine for a phase/frequency detector operative in a phase locked loop includes a short pulse suppression circuit operative to suppress output pulses of duration on the order of the propagation delay of combinatorial logic in the state machine. Particularly in phase locked loop applications where the short pulses are not required to linearize the phase/frequency detector and associated charge pump, suppression of the short pulses reduces current ripple and phase noise, and relaxes design constraints in the charge pump such as transistor size and pulse edge speed, all without significantly increasing silicon area or power consumption.

One embodiment relates to a digital state machine for a Phase/Frequency Detector, having reduced transient outputs. The state machine includes a first storage element operative to latch an asserted logic level on an active edge of a reference clock signal and a second storage element operative to latch the asserted logic level on an active edge of a divided clock signal having a phase offset from the reference clock signal. The state machine also includes reset logic operative to reset both the first and second storage element when both storage elements output an asserted logic level. The state machine further includes a short pulse suppression circuit connected to the outputs of the first and second storage elements and operative to suppress an asserted logic level output of one of the storage elements having a duration of substantially the reset logic propagation delay.

Another embodiment relates to a method of providing a stable, high-frequency, periodic signal. A phase locked loop is provided. The phase locked loop includes a frequency/phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider. In a state machine in the frequency/phase detector, the phase and frequency of a reference clock signal and a divided clock signal output by the frequency divider are compared to generate both Up and Down pulses. One of the pulses has a duration proportional to the phase difference between the clock signals. The other pulse has a duration of substantially the propagation delay of combinatorial logic in the state machine. Only the pulse reflecting the phase difference is output to the charge pump, to control current output by the charge pump to the loop filter.

Yet another embodiment relates to a Phase Locked Loop (PLL). The PLL includes a phase/frequency detector operative to generate UP or DOWN pulsed outputs in response to the relative timing of active edges of a first clock signal and a second clock signal. The PLL further includes a short pulse suppression circuit connected to at least one of the UP and DOWN outputs and operative to suppress pulses having a duration of substantially the propagation delay of combinatorial logic in the phase/frequency detector.

Still another embodiment relates to a wireless device operative in a wireless

communication network. The wireless device includes processing circuitry and radio circuitry. The radio circuitry includes a phase locked loop, including a phase/frequency detector operative to generate UP or DOWN pulsed outputs in response to the relative timing of active edges of a first clock signal and a second clock signal. The phase locked loop also includes a short pulse suppression circuit connected to at least one of the UP and DOWN outputs and operative to suppress pulses having a duration of substantially the propagation delay of combinatorial logic in the phase/frequency detector. BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

Figure 1 is a block diagram of a phase locked loop.

Figure 2 is a circuit schematic diagram of a digital PFD state machine.

Figure 3 is a state diagram of the state machine of Fig. 2.

Figure 4 is a timing diagram of input and output signals of the state machine of Fig. 2.

Figure 5 is a circuit schematic diagram of a short pulse suppression circuit for one signal, according to one embodiment.

Figure 6 is a graph of simulated waveforms depicting the operation of the short pulse suppression circuit of Figure 5 for short pulses.

Figure 7 is a graph of simulated waveforms depicting the operation of the short pulse suppression circuit of Figure 5 for long pulses.

Figure 8 is a circuit schematic diagram of an alternative embodiment of the short pulse suppression circuit of Figure 5 (for asserted-low signals).

Figure 9 is a circuit schematic diagram of a short pulse suppression circuit for two signals, according to one embodiment.

Figure 10 is a graph of simulated waveforms depicting the operation of the short pulse suppression circuit of Figure 9.

Figure 1 1 is a circuit schematic diagram of an alternative embodiment of the short pulse suppression circuit of Figure 9.

Figure 12 is a graph of simulated waveforms depicting the operation of the short pulse suppression circuit of Figure 1 1.

Figure 13 is a circuit schematic diagram of an alternative embodiment of the short pulse suppression circuit of Figure 9 (for asserted-low signals).

Figure 14 is a graph of simulated waveforms depicting the operation of the short pulse suppression circuit of Figure 12.

Figure 15 is a circuit schematic diagram of a short pulse suppression circuit according to another embodiment.

Figure 16 is a circuit schematic diagram of a short pulse suppression circuit according to another embodiment.

Figure 17 is a flow diagram of a method of generating a stable, high-frequency, periodic signal. Figure 18 is a block diagram of a wireless device operative in a wireless communication network.

DETAILED DESCRIPTION

For simplicity and illustrative purposes, the present invention is described by referring mainly to an exemplary embodiment thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention.

However, it will be readily apparent to one of ordinary skill in the art that the present invention may be practiced without limitation to these specific details. In this description, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present invention.

Figure 1 is a block diagram of a phase locked loop (PLL) 10. A properly designed PLL 10 is a well-known circuit for generating a stable, high-frequency, low noise, periodic output signal, such as for use as a local oscillator (LO) or radio frequency (RF) clock signal for modulating a baseband communication signal onto (or demodulating it from) an RF carrier. As well known in the art, a PLL 10 commonly includes a Phase/Frequency Detector (PFD) 12, a charge pump (CP) 14, a loop filter 16, a voltage controlled oscillator (VCO) 18 and a frequency divider 20 in a feedback path. The heart of the PLL 10 is the VCO 18, which generates the PLL 10 output. The output signal is fed back, through the frequency divider 20, generating a signal labeled clk_div. This signal is compared to a stable input reference signal, labeled clk_ref, in the PFD circuit 12. The PFD 12 generates Up and Down signals to the CP 14 in response to the comparison. The CP 14 responsively increases, decreases, or maintains (in the absence of an asserted input) the change in the loop filter using an output current lctri- A loop filter 16 (typically a low-pass filter to attenuate harmonics and the like) applies a control voltage V_cw to the input of the VCO 18, which determines the VCO 18 output signal frequency.

In the case of mmW LO generation, a high reference frequency clk_ref is required for low phase noise. This lowers the phase noise multiplication factor of the PLL 10 and hence the effect of reference phase noise. Utilizing a higher reference frequency also increases the distance between the desired tone and the spurious tones caused by the reference at the PLL 10 output. However, a high reference frequency requires the CP 14 to switch its current rapidly, and in a precise manner, in order to minimize the CP 14 duty-cycle and deliver as little device noise as possible to the loop filter 16, and further on to the frequency control input of the VCO 18. A common design for the PFD 12 in analog PLLs 10, utilizing tri-state components, produces pulses (i.e., Up and Down outputs) having a duration that is a small fraction of the reference clock cycle. Decreasing the clk_ref cycle time (by increasing its frequency) requires a further shortening of these pulses, making linear and well-controlled behavior difficult to achieve, due to current injection during switching. Figure 2 depicts one embodiment of an asynchronous digital state machine 30 in the PFD 12, which generates the UP and DOWN PFD 12 outputs. Figure 3 depicts a state diagram of this state machine, and Figure 4 depicts the input and output waveforms, in the case where clk_div lags clk_ref in phase. As indicated by Fig. 2, the signals clk_ref and clk_div clock a hard- wired, asserted-high logic level (i.e., a "1 ") into the respective flip-flops 32, 34 at each rising edge of the respective clock signals, clocking an asserted level (in this case, a "1 ", or high voltage level) to the respective output. At the time arbitrarily denoted to in Figure 4, the state machine is in an Idle state. The next rising edge of clk_ref clocks a 1 to the Up output, moving to state Up. The next rising edge of clk_div clocks a 1 to the Down output. This asserts the output of the AND gate 36, resetting both flip-flops 32, 34, deasserting both Up and Down outputs, and moving the state machine 30 back to Idle state.

Considering only the Up output, the PFD 12 appears to cycle between the Idle and Up states, with the duration of the Up state (and hence output pulse) dependent on the degree of phase lag of clk_div as compared to clk_ref - which is the expected behavior. However, due to the asynchronous nature of the state machine 30, a fourth state effectively exists, for a brief duration, in which both Up and Down outputs are asserted. The duration of this state is substantially on the order of the propagation delay of combinatorial logic 36 in the PFD 12. Note that the same behavior will occur in transitions between Down and Idle, if the relative phase delays were reversed. Although this behavior does not comply with the state machine diagram of Figure 3, the intermediate state has traditionally been desired, as this makes the CP 14 current pulses always have a minimum width, in a locked state. The minimum length pulses mitigate the so-called dead zone, just around zero phase difference at the PFD 12 input. This is referred to as linearizing the PFD/CP. However, this technique produces short pulses for each reference cycle. These pulses increase the spurs and also the noise from the CP 14. When increasing the reference frequency, this noise will increase because of more pulses per time unit.

A fractional-N PLL 10 is one in which the frequency divider circuit 20 (see Fig. 1 ) allows division by a non-integer average value. For example, the divider circuit 20 may include a delta- sigma modulator, as known in the art. One advantage of a delta-sigma modulator is "noise shaping," or the ability to move quantization noise due to fractional division outside of the passband of the PLL loop filter 16, thus improving the SNR of the PLL 10. In a fractional-N PLL 10, a common way of linearizing the PFD/CP transfer (and avoid folding shaped

quantization noise back in-band) is to leak current from the CP 14 output node, and to let only one of the Up or Down pulse durations control the loop in locked state. In this case, the effective fourth state does not serve the purpose of linearizing the PFD/CP, and the short pulses will only pass undesired current ripple to the loop filter 16.

According to embodiments of the present invention, in PLLs 10 where the steady state has a phase offset between clk_ref and clk_div, as depicted in Figure 4 (which may occur, for example, in phased-array beamforming), additional digital logic in the tri-state PFD 12, referred to herein as a "short pulse suppression circuit," prevents the shortest pulses from passing to the CP 14. This minimizes the average switch on-time of the CP 14, improving the phase noise contribution from the CP 14 to the PLL 10 output. The high frequency content fed to the loop filter 16 is also reduced, thereby improving spurious and noise performance of the PLL 10.

Furthermore, the short pulse suppression circuit relaxes the speed requirement on the CP 14 switching, enabling longer transistors with higher output impedance and lower 1/f noise contribution. The wider pulses fed to the CP 14 could also be slowed down to cause less current injection to the CP 14 output node during switching. These improvements are achieved while maintaining the powerful feature of the PFD 12 of not only phase detection, but also frequency detection.

Figure 5 depicts a representative short pulse suppression circuit 40 which may be added to one or both of the Up and Down outputs of PFD state machine 30, such as that depicted in Fig. 2, to remove undesired short pulses. In this embodiment, an AND gate 42 receives the input signal in directly at one input. The signal in traverses a delay circuit 44 - an even number of inverters 44a, 44b in the embodiment depicted in Figure 5 - generating the signal in_delayed. The delayed input in_delayed is connected to the other input of the AND gate 42. The circuit 40 assumes asserted-high logic. Initially, in=0 and out=0. A short, positive pulse on the in signal will appear at the first input of the AND gate 42; however, the output signal out will remain at 0, as the inputs to the AND gate 42 are (1 ,0). Some time later, determined by the propagation delay of the delay circuit 44, the intermediate signal in_delayed will switch to positive, presenting a 1 to the other AND gate 42 input. If the propagation delay of the delay circuit 44 exceeds the duration of the pulse on the input, by the time in_delayed becomes 1 , the original input in=0. The AND gate 42 inputs are now (0,1 ), and the output remains at 0.

Figure 6 shows this behavior in circuit simulation, using a 28nm SOI CMOS technology, and in which the delay circuit 44 comprises 16 cascaded inverters. Although Figure 6 appears to show glitches in the output signal, note the scale of the plots - the signals in and in_delayed are plotted on a V scale; the output signal out is plotted on a mV scale. Hence, the apparent output glitches are merely perturbations far below the noise threshold.

Figure 7 depicts the behavior of the short pulse suppression circuit 40 for longer pulses

- e.g., a desired UP or DOWN pulse from the PFD 12. The AND gate 42 passes on only the overlapping portion of signals in and in_delayed, effectively shortening the pulse by the amount of propagation delay in the delay circuit 44. In a PLL 10, this shortening of the UP or DOWN pulse from the PFD 12 will not affect the lock of the PLL 10. However, if it is desired to restore the full length of the pulse, it can easily be done by subsequent use of a similar circuit using an OR gate and a delay circuit having the same propagation delay as delay circuit 44, which would effectively lengthen the pulse by that propagation delay. As those of skill in the art are aware, the state machine 30 may be implemented in complimentary (inverted) logic - or indeed, the logic values at the D inputs of flip-flops 32, 34 could be any combination, with appropriate combinatorial logic in the reset circuit 36 and short pulse suppression circuit(s) 40 ensuring desired behavior. Figure 8 depicts a representative short pulse suppression circuit 50 operative for asserted-low signals. It operates similarly to the circuit 40 for asserted-high signals. An OR gate 52 receives the asserted-low input /in directly at one input, and the asserted-low signal /in_delayed at the other input, where /in_delayed is delayed from /in by the propagation delay of delay circuit 54. If that delay is greater than the width of a short pulse, the output signal will remain a "1 ", as the input (0,0) will not be presented to the OR gate 52. Conversely, for a longer negative-going pulse on /in, the short pulse suppression circuit 50 will pass the pulse, but shorten it by the propagation delay of delay circuit 54.

The key to both short pulse suppression circuits 40, 50 is the "one different" nature of the truth tables of the AND and OR logic functions. In general, for n inputs, there are 2ⁿ possible combinations of input logic levels. For (2ⁿ-1 ) of these, the outputs are the same; and for one combination of inputs, the gates generate a different output. The same is true, of course, for inverting versions (NAND and NOR gates) which may also be used, with an inverter, in the circuits 40, 50. The short pulse suppression circuits 40, 50 operate to prevent the "one different" combination of inputs from appearing during short pulses, by delaying one input, relative to the other, by a delay equal to or greater than the width of the pulse to be suppressed. The table below summarizes the truth tables for these logic functions.

Figure 9 depicts a representative short pulse suppression circuit 60 operative to suppress short pulses of the UP or DOWN signals output from the asynchronous digital state machine 30 of Figures 2 and 3. This state machine 30 outputs short pulses of one of these signals only when both outputs are asserted, and only for a duration substantially equal to the propagation delay of the combinatorial logic 36 implementing a reset of the flip-flops 32, 34. In the circuit of Figure 9, each input signal, and the inverse of the other input signal, are inputs to each of the NOR gates 62, 64. The inverters 66, 68 are not primarily delay circuits, as in the short pulse suppression circuits 40, 50, but rather are logical inverters operative to change the logic state of each input signal. Since the brief duration of the undesired short pulse only occurs when both state machine outputs are asserted, the NO operation of one signal and the inverse of the other provides a low output which blocks this condition from propagating to the output. Appropriate digital logic other than a simple inverter 66, 68, may be used in the case where the outputs of the state machine 30 are other than simple asserted-high (or low) signals. Such modification is well within the skill of those of skill in the art, given the teachings of the present disclosure

Assuming asserted-high signals, consider first the idle condition, in which neither input is asserted. Both NOR gates 62, 64 have (1 ,0) at their inputs, and the outputs are unasserted. When the up_in signal is asserted for a long pulse - that is, before dn_in is also asserted (see Figure 4) - the inputs to NOR gate 62 are (0,0), yielding a 1 at the output up_out. In this condition, the inputs to the NOR gate 64 are (1 ,1 ), maintaining a 0 at the output dn_out. When the dn_in signal is also briefly asserted, the inputs to NOR gate 62 are (1 ,0) and the output up_out goes to 0 (the inputs to NOR gate 64 are (0,1 ), so dn_out remains a 0). Hence, during the brief duration in which both UP and DOWN outputs of the state machine 30 are asserted, both outputs are blocked. This has the dual effect of shortening, e.g., the long UP pulse, and suppressing the short DOWN pulse. Of course, the circuit 60 is symmetric, so when the PLL 10 experiences the opposite phase relationship between clk_div and clk_ref, a long DOWN pulse is shortened, and a short UP pulse is suppressed.

Figure 10 depicts the waveforms of a simulation of the short pulse suppression circuit 60. Here again, the scale of the dn_out signal is in mV, so the apparent glitch is really minor noise. Note that the duration of the up_out pulse is shorter than the up_in pulse, by approximately the duration of the dn_in short pulse.

Figure 1 1 depicts another embodiment of a short pulse suppression circuit 70, implemented with AND gates 72, 74. Two additional inverters 78, 79 are used at the inputs to flip the logic levels. When both input signals are asserted, each AND gate 72, 74 input is (1 ,0), thus deasserting both outputs and blocking the short pulse. When both input signals are deasserted each AND gate input is (1 ,0), deasserting both output signals. When one input signal is asserted and the other is deasserted, the corresponding AND gate input is (1 , 1 ), asserting the output, whereas the other AND gate input is (0,0), deasserting the output.

Figure 12 depicts the simulation waveforms for the short pulse suppression circuit 70 of Figure 1 1. Note that in this plot the scale of dn_out waveform is uV.

For completeness, Figure 13 depicts a short pulse suppression circuit 80 operative for asserted-low signals. This circuit 80 is the short pulse suppression circuit 60, with input inverters 84a, 84b and output inverters 85a, 85b to flip the input and output logic levels, to provide asserted-low outputs (if required or desired). A second set of output inverters 86a, 86b set the outputs at asserted-high levels.

Figure 14 depicts the simulated waveforms for the short pulse suppression circuit 80 of Figure 13. The two (asserted-high) output signals up_out and dn_out are superimposed in the lower waveform plot. Figure 15 depicts a short pulse suppression circuit 90, comprising a NOR gate 91 an inverter 92, operative to suppress short pulses on one of the two outputs of state machine 30. The short pulse suppression circuit 90 may be advantageously employed in applications where only one, known, output of the state machine 30 will generate short pulses (that is, where it is known that, e.g., clk_div will always lead clk_ref). In this circuit 90, short pulses are suppressed by considering both state machine outputs UP and DOWN. The circuit 90 may be

advantageously used in lieu of the short pulse suppression circuit 40, for example. The circuit 90 utilizes the fact that, in the embodiment of state machine 30 depicted in Figure 2, the short pulse to be suppressed only occurs when both outputs UP and DOWN are briefly asserted - as opposed to the delay principle of short pulse suppression circuit 40. The circuit 90 assumes asserted-high signals - the combinatorial logic gates 91 , 92 may be changed to accommodate asserted-low signals, or indeed arbitrary logic level outputs of the state machine 30.

Figure 16 depicts a short pulse suppression circuit 95 comprising an AND gate 96 and inverter 97. Note that the inputs are reversed from those in the short pulse suppression circuit 90 of Figure 15. The circuit 95 also assumes asserted-high inputs, and that the short pulse only occurs when both UP and DOWN signals are asserted.

The pulse area of the up_in signal minus the area of the dn_in signal represents substantially the actual charge content delivered to the loop filter 16 by the charge pump 14. However, the thermal noise energy delivered is proportional to the sum of the pulse areas. Hence, as can be seen in the waveforms of Figures 10, 12 and 14, the CP 14 noise contribution to PLL 10 phase noise is reduced.

As described above, the noise improvement is not limited to the thermal noise. Using only the PFD 12 of Figure 2, the switches for the Down- (or Up-) current in the CP 14 would have to be made with short channel length, to be able to switch on and off at a high speed in a controlled manner. However, the small area of the transistor makes it prone to high levels of 1/f noise, which would contribute to the PLL 10 output phase noise. The short pulse suppression circuits of Figures 5, 8, 9, 1 1 , and 13 remove the 1/f noise contribution from the Down- (or Up-) switches completely. The Up- (or Down-) switches still need to be able to switch, but its pulse width can be prolonged, thus enabling longer transistors with less 1/f noise.

Another important aspect is the current injection also mentioned above. By relaxing the speed requirements by removing the very short pulse, a higher degree of freedom is achieved in choosing the Up/Down pulse rise and fall times, which allows minimizing the current injected from the CP 14 switch control signal to the CP 14 output through capacitive coupling.

Figure 17 depicts the steps of a method 100 of providing a stable, high-frequency, periodic signal. A phase locked loop 10 is provided (block 102). The phase locked loop 10 comprises a phase/frequency detector 12, a charge pump 14, a loop filter 16, a voltage controlled oscillator 18, and a frequency divider 20. In a state machine 30 in the

phase/frequency detector 12, the phase and frequency of a reference clock signal and a divided clock signal output by the frequency divider 20 are compared (block 104). The state machine 30 generates pulses responsive to the phase comparison. Pulses that have a duration proportional to the phase difference between the clock signals are output to the charge pump 14 (block 106), to control current output by the charge pump 14 to the loop filter 16. Pulses that have a duration of substantially the propagation delay of combinatorial logic 36 in the state machine 30 are suppressed (block 108). The clock comparison, pulse generation, and pulse output or suppression repeat for every reference clock cycle.

Those of skill in the art will readily recognize that the entire state machine circuit 30, including the basic circuit of Figure 2 and any of the short pulse suppression circuits of

Figures 5, 8, 9, 1 1 , 13, 15, or 16 may be designed to operate with either asserted-high or asserted-low logic levels. Similarly, those of skill in the art will recognize that the flip-flops 32, 34 of Figure 2 may be selected such that an asserted logic level hardwired at the input is latched to the output using either the rising or falling edge of the respective clock signals. Additionally, the reset signal to the flip-flops 32, 34 may be asserted high or low.

Figure 18 depicts a wireless device 200, operative in a wireless communication network, according to one embodiment of the present invention. A wireless device 200 is any type device capable of communicating with a base station (e.g., eNB, gNB) of a wireless communication network over radio signals. A wireless device 200 may therefore refer to a machine-to-machine (M2M) device, a machine-type communications (MTC) device, a Narrowband Internet of Things (NB-loT) device, etc. The radio network device may also be a User Equipment (UE); however it should be noted that the UE does not necessarily have a "user" in the sense of an individual person owning and/or operating the device. A wireless device 200 may also be referred to as a radio device, a radio communication device, a wireless communication device, a wireless terminal, or simply a terminal. In general, a wireless device 200 includes device-to-device UEs or devices, machine-type devices or devices capable of machine-to-machine communication, sensors equipped with a radio network device, wireless-enabled table computers, mobile terminals, smart phones, laptop-embedded equipped (LEE), laptop-mounted equipment (LME), USB dongles, wireless customer-premises equipment (CPE), etc.

In some embodiments, the wireless device 200 includes a user interface 202 (display, touchscreen, keyboard or keypad, microphone, speaker, and the like); in other embodiments, such as in many M2M, MTC, or NB-loT scenarios, the wireless device 200 may include only a minimal, or no, user interface 202 (as indicated by the dashed lines of block 202 in Figure 18). The wireless device 200 also includes processing circuitry 204; memory 206; and radio circuits, such a transceiver 208, one or more antennas 210, and the like, to effect wireless

communication across an air interface to one or more nodes of a wireless communication network. As indicated by the dashed lines, the antenna(s) 210 may protrude externally from the wireless device 200, or the antenna(s) 210 may be internal. In some embodiments, the wireless device 200 may additionally include features such as a camera, removable memory interface, short-range communication interface (Wi-Fi, Bluetooth, and the like), wired interface (USB), battery recharge port, and the like (these features are not shown in Figure 18). The memory 206 is operative to store, and the processing circuitry 204 operative to execute, software 212 which controls the operation of the wireless device 200.

The transceiver 208 includes a Phase Locked Loop 10 operative to generate a stable, high-frequency, low noise, periodic output signal, such as for use as a local oscillator (LO) or radio frequency (RF) clock signal for modulating a baseband communication signal onto (or demodulating one from) an RF carrier. As described herein, the PLL 10 includes one or more short pulse suppression circuits 40, 50, 60, 70, 80, 90, 95 to suppress short pulses that would otherwise introduce noise into the PLL 10. As used herein a "short pulse" is a logic level on a signal line having a duration of only the propagation delay of simple combinatorial logic, such as the reset logic 36 of the state machine 30 depicted in Figure 2. Although depicted as a transceiver 208, the radio circuitry may include only a transmitter or receiver, such as in the case of dedicated M2M type devices (e.g., meter-reading monitors, location-tracking devices, and the like). In this case, the transmitter or receiver includes a PLL 10 having a short pulse suppression circuit 40, 50, 60, 70, 80, 90, or 95.

Embodiments of the present invention present numerous advantages over the prior art, particularly where linearization of the transfer characteristics of the PFD/CP are achieved by means other than very short pulses output by the PFD 12, such as by leaking current from the CP 14 output node. By eliminating very short duration pulses output by a PFD 12 state machine 30, both current ripple in the loop filter and high-speed switching in the CP 14 are avoided. The latter allows the use of longer transistors with higher output impedance, and lower 1/f noise contribution. Additionally the phase noise contribution from the CP 14 to the PLL 10 output is improved by minimizing the average switch on-time of the CP 14, reducing noise injection to the loop filter 16. Spurious and noise performance of the PLL 10 is also improved by reducing the highest frequency signals entering the loop filter. These advantages accrue using only combinatorial logic, and hence without significantly increasing silicon area or power consumption.

The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.

Claims

1 . A phase/frequency detector (12) operative in a phase locked loop (10) and having reduced transient outputs, characterized by:

a state machine (30) operative to generate UP or DOWN pulsed outputs in response to the relative timing of active edges of a first clock signal (clk_ref) and a second clock signal (clk_div); and

a short pulse suppression circuit (40, 50, 60, 70, 80, 90, 95) connected to at least one of the UP and DOWN outputs and operative to suppress a pulse having a duration of substantially the propagation delay of combinatorial logic (36) in the state machine.

2. The phase/frequency detector (12) of claim 1 wherein the state machine (30) comprises: a first storage element (32) operative to latch a first predetermined logic level on an active edge of the first clock signal (clk_ref);

a second storage element (34) operative to latch a second predetermined logic level on an active edge of the second clock signal (clk_div); and

reset logic (36) operative to reset both the first and second storage element (32, 34) when both storage elements (32, 34) output a predetermined combination of logic levels.

3. The phase/frequency detector (12) of claim 1 wherein the short pulse suppression circuit (40, 50, 60, 70, 80, 90, 95) comprises combinatorial logic.

4. The phase/frequency detector (12) of claim 3 wherein the short pulse suppression circuit (40, 50) is connected to the UP or DOWN outputs where short pulses should be suppressed, and characterized by:

a logic gate (42, 52) having n inputs and generating the same output for (2ⁿ-1 ) input value combinations and a different output for one input value combination;

wherein the UP or DOWN output where short pulses should be suppressed is connected to one or more inputs of the logic gate (42, 52); and

wherein the UP or DOWN output to where short pulses should suppressed is further connected to one or more different inputs of the logic gate (42, 52) via one or more delay circuits (44, 54), wherein the combined delay of the delay circuits (44, 54) equals or exceeds the duration of the pulse to be suppressed.

5. The phase/frequency detector (12) of claim 4 wherein the UP or DOWN output to be suppressed is asserted high, and wherein the logic gate (42) implements an AND or NAND function.

6. The phase/frequency detector (12) of claim 4 wherein the UP or DOWN output to be suppressed is asserted low, and wherein the logic gate (52) implements an OR or NOR function.

7. The phase/frequency detector (12) of claim 4, wherein a short pulse suppression circuit is connected to each of the UP and DOWN outputs.

8. The phase/frequency detector (12) of claim 3 wherein the short pulse suppression circuit (90, 95) is connected to the UP or DOWN outputs where short pulses should be suppressed, and characterized by:

a logic gate (91 , 96) having n inputs and generating the same output for (2ⁿ-1 ) input value combinations and a different output for one input value combination;

an inverter circuit (92, 97); and

wherein one of the UP or DOWN output is connected to one or more inputs of the logic gate (91 , 96) and the inverse of the other of the UP or DOWN output is connected to one or more different inputs of the logic gate (91 , 96) via the inverter circuit (92, 97).

9. The phase/frequency detector (12) of claim 3 wherein the short pulse suppression circuit (60, 70, 80) is characterized by:

first and second logic gates (62, 64), each having n inputs and generating the same output for (2ⁿ-1 ) input value combinations and a different output for one input value combination;

wherein the first logic gate receives the UP output and an inverse of the DOWN output; and

the second logic gate receives the DOWN output and an inverse of the UP output.

10. A method (100) of providing a stable, high-frequency, periodic signal, characterized by: providing (102) a phase locked loop (10) comprising a phase/frequency detector (12), a charge pump (14), a loop filter (16), a voltage controlled oscillator (18), and a frequency divider (20);

in a state machine (30) in the phase/frequency detector (12), comparing (104) the phase and frequency of a first clock signal (clk_ref) and a second clock signal (clk_div) output by the frequency divider (20), to generate both Up and Down pulses; outputting (106) one of the Up and Down pulses having a duration proportional to the phase difference between the clock signals to the charge pump (14), to control current output by the charge pump (14) to the loop filter (16); and suppressing (108) one of the Up and Down pulses having a duration of substantially the propagation delay of combinatorial logic (36) in the state machine (30).

1 1. The method (100) of claim 8 wherein outputting (106) one of the Up or Down pulses and suppressing (108) the other, is characterized by:

generating an Up pulse at the output of a first storage element (32) by latching a

predetermined logic level on an active edge of the first clock signal; generating a Down pulse at the output of a second storage element (34) by latching a predetermined logic level on an active edge of the second clock signal;

resetting both the first and second storage elements when outputs of the first (32) and second (34) storage elements assume a predetermined value; and suppressing either the Up or Down pulse having a duration of substantially the

propagation delay of logic used to reset the storage elements (32, 34).

12. The method (100) of claim 9 wherein suppressing either the Up or Down pulse having a duration of substantially the propagation delay of logic (36) used to reset the storage elements (32, 34) is characterized by:

providing a short pulse suppression circuit (40, 50) comprising a logic gate (42, 52) and delay circuits (44, 54), wherein the logic gate (42, 52) has n inputs and generates the same output for (2ⁿ-1 ) input value combinations and a different output for one input value combination;

directing the Up or Down pulse to be suppressed to one or more first inputs of the logic gate (42, 52); and

further directing the Up or Down pulse to be suppressed to one or more delay circuits

(44, 54), and connecting an output of the one or more delay circuits (44, 54) to at least one input of the logic gate (42, 52) other than the first inputs, wherein the combined delay of the delay circuits (44, 54) equals or exceeds the duration of the Up or Down pulse to be suppressed.

13. The method (100) of claim 10 wherein the Up or Down pulse to be suppressed is asserted high, and wherein the logic gate (42) implements an AND or NAND function.

14. The method (100) of claim 10 wherein the Up or Down pulse to be suppressed is asserted low, and wherein the logic gate (52) implements an OR or NOR function.

15. The method (100) of claim 10, wherein the short pulse suppression circuit (40, 50) is connected to both the Up and Down pulses.

16. The method (100) of claim 9 wherein suppressing either the Up or Down pulse having a duration of substantially the propagation delay of logic (36) used to reset the storage elements

(32, 34) is characterized by:

providing a short pulse suppression circuit (90, 95) comprising a logic gate (91 , 96) and an inverter circuit (92, 98), wherein the logic gate (91 , 96) has n inputs and generates the same output for (2ⁿ-1 ) input value combinations and a different output for one input value combination;

directing the Up or Down pulse to be suppressed to one or more first inputs of the logic gate (91 , 96); and

directing an inverse of the other of the Up or Down pulse to at least one input of the logic gate (91 , 96) other than the first inputs.

17. The method (100) of claim 9 wherein suppressing either the Up or Down pulse having a duration of substantially the propagation delay of logic (36) used to reset the storage elements (32, 34) is characterized by:

providing a short pulse suppression circuit (60, 70, 80) comprising first and second logic gates (62, 64, 72, 74, 81 , 82), each having n inputs and generating the same output for (2ⁿ-1 ) input value combinations and a different output for one input value combination;

directing the Up pulse and an inverse of the Down pulse to the first logic gate

(62, 72, 81 ); and

directing the Down pulse and an inverse of the Up pulse to the second logic gate

(64, 74, 82).

18. A Phase Locked Loop (10) comprising:

a phase/frequency detector (12) operative to generate UP or DOWN pulsed outputs in response to the relative timing of active edges of a first clock signal (clk_ref) and a second clock signal (clk_div); and

a short pulse suppression circuit (40, 50, 60, 70, 80, 90, 95) connected to at least one of the UP and DOWN outputs and operative to suppress pulses having a duration of substantially the propagation delay of combinatorial logic (36) in the phase/frequency detector (12).

19. A wireless device operative in a wireless communication network, the wireless device comprising: processing circuitry (204); and

radio circuitry (208) including a phase locked loop (10) including

a phase/frequency detector (12) operative to generate UP or DOWN pulsed

outputs in response to the relative timing of active edges of a first clock signal (clk_ref) and a second clock signal (clk_div); and