WO2018182675A1

WO2018182675A1 - Finfet with angled source and drain regions

Info

Publication number: WO2018182675A1
Application number: PCT/US2017/025290
Authority: WO
Inventors: Raseong KIM; Uygar E. Avci; Ian A. Young
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2018-10-04
Anticipated expiration: 2019-09-30

Abstract

Techniques are disclosed for forming semiconductor integrated circuits including a source region adjacent to the channel region and having a first interface angled with respect to the channel region at a first angle in a range of between less than 90° and greater than or equal to 0°, the first angle of the first interface measured with respect to an imaginary horizontal line that passes through the channel region and the source region. Similarly, techniques are also disclosed for forming semiconductor integrated circuits including a drain region adjacent to the channel region and having a second interface angled with respect to the channel region at a second angle in a range of between less than 90° and greater than or equal to 0° with respect to the imaginary horizontal line, the imaginary horizontal line also passing through the drain region.

Description

FINFET WITH ANGLED SOURCE AND DRAIN REGIONS

BACKGROUND

Increased performance of circuit devices including transistors, diodes, resistors, capacitors, and other passive and active electronic devices formed on a semiconductor substrate is typically a major factor considered during design, manufacture, and operation of those devices. For example, during design and manufacture or forming of metal oxide semiconductor (MOS) transistor semiconductor devices, such as those used in a complementary metal oxide semiconductor (CMOS), it is often desired to increase movement of electrons in N-type MOS device (NMOS) and P-type MOS device (PMOS) and contact regions. Source-to-drain resistance (RS_D) affects the ability to drive current through MOS field effect transistors

(MOSFETs). As device scaling continues, RS_D becomes more important, because the intrinsic resistance of the device is reduced. Known solutions to decreasing RS_D have been based on a classical resistance model, such as increasing the source and drain doping density, thereby having more carriers, decreasing the metal-semiconductor contact resistance, and increasing the source and drain contact area. As aggressive device scaling continues, there are a number of non-trivial issues that arise.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 A is a schematic illustration of a standard FinFET.

FIG. IB is a schematic illustration of a cross-section along line A-A' of the FinFET shown in FIG. 1A.

FIG. 2A is a schematic illustration of a FinFET with angled source and drain regions according to an embodiment of this disclosure.

FIG. 2B is a schematic illustration of a FinFET with source and drain regions angled at 0° according to another embodiment of this disclosure.

FIG. 3 A is a method for forming a transistor structure with angled source and drain regions according to an embodiment of this disclosure.

FIG. 3B is a method for forming a transistor structure with source and drain regions angled at 0° according to another embodiment of this disclosure.

FIGS. 4 A to 4D illustrate structures that are formed when carrying out the method of FIG. 3 A, in accordance to an embodiment of this disclosure. FIGS. 5A to 5G illustrate structures that are formed when carrying out the method of FIG. 3B, in accordance to another embodiment of this disclosure.

FIG. 6 is a graph of Monte Carlo simulation results of drain current I_D as a function of gate voltage VG at high drain voltage V_D for two standard Ino_.7Gao_.3As FinFETs and three Ino_.7Gao_.3As FinFETs configured according to an embodiment of this disclosure.

FIG. 7 is a graph of Monte Carlo simulation results of drain current I_D as a function of gate voltage VQ at high drain voltage V_D for two standard silicon FinFETs and three silicon FinFETs configured according to another embodiment of this disclosure.

FIGS. 8 A and 8B show examples of the epitaxial growth angle that can be exploited according to various embodiments of this disclosure.

FIG. 9 is a depiction of a computing system configured according to an embodiment of this disclosure.

The figures depict various embodiments of the present disclosure for purposes of illustration only. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. As will be appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific

configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of a transistor structure may have less than perfect straight lines, right angles, and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. In short, the figures are provided merely to show example structures.

Numerous variations, configurations, and other embodiments will be apparent from the following detailed discussion.

DETAILED DESCRIPTION

Techniques are disclosed for forming semiconductor integrated circuits including fin- based or so-called FinFET transistors having angled source and drain regions. In more detail, a doped source region adjacent to a channel region has a first interface angled with respect to the channel region at a first angle in a range of between less than 90° and greater than or equal to 0°, the first angle of the first interface measured with respect to an imaginary horizontal line that passes through the channel region and the doped source region. By facing the doped source region at an angle toward the channel region, carriers injected from the doped source region can enter the channel without scattering (herein also denoted as "ballistic" carriers), or undergo a smaller number of scattering events (herein also denoted as "quasi-ballistic" carriers) with a smaller change in angle and carrier momentum, relative to a standard doped source region structure that is oriented at 90° to the channel region. Similarly, techniques are also disclosed for forming semiconductor integrated circuits including a doped drain region adjacent to the channel region and having a second interface angled with respect to the channel region at a second angle in a range of between less than 90° and greater than or equal to 0° with respect to the imaginary horizontal line, the imaginary horizontal line also passing through the doped drain region. By facing the doped drain region at an angle toward the channel region, ballistic carriers exiting the channel region can either be directly collected by the drain as ballistic carriers, or collected as quasi -ballistic carriers after a smaller number of scattering events, relative to a standard doped drain region structure that is oriented at 90° to the channel region. While non-planar transistors (FinFETs and nanowire transistors) are a point of focus in this disclosure, it will be appreciated that the techniques provided herein can be used to implement planar transistor configurations as well.

The disclosed techniques may provide various advantages over standard MOSFETs, such as reduced RSD in scaled devices with ballistic or quasi -ballistic carriers, and higher drive currents.

General Overview

As previously noted, there are a number of non-trivial issues that arise as device scaling continues. For instance, ballistic carriers, injected from the doped source region and transported through the channel nearly or entirely without scattering, begin to predominate, especially for light effective mass (m*) channel materials (e.g., group III-V semiconductor materials). In such cases, the classical diffusive model of source and drain resistance may break down, and a consideration of fundamental physical effects, such as carrier momentum distribution and directionality, may be needed to improve access to the source and drain. In more detail, in a standard fin-based or multi-gate non-planar transistor device (herein also denoted as a

"FinFET") shown in FIG. 1 A, the source and drain metal contacts face the sides of the doped source and drain regions, respectively. As can be seen, a standard FinFET 100 includes gate electrode 1 10 isolated by gate spacer 120 and gate spacer 130 from source contact 145 and drain contact 155, respectively. The doped source region 140 (not shown) and doped drain region 150 are topped by source metal contact 145 and drain metal contact 155, respectively. A cross- section along line A-A' in FIG. 1 A in the X-Y plane, shown in FIG. IB, reveals the doped source region 140 and doped drain region 150. As shown in FIG. IB, the source metal contact 145 and drain metal contact 155 both contact the doped source region 140 and doped drain region 150 from the sides, at a 90° angle to an imaginary horizontal line 123. As will be appreciated, the channel region 125 is effectively contained in the gate covered portion of a semiconductor body or "fin" that extends from an underlying substrate out of the X-Y plane shown in FIG. IB, the doped source region 140 is epitaxially provided on the fin to one side of the channel region 125, and the doped drain region 150 is epitaxially provided on the fin to the other, opposing side of the channel region 125. So, the imaginary horizontal line 123 lies in a plane parallel to the channel region 125 and is also parallel to the fin and passes through each of the source region 140, channel region 125, and doped drain region 150. The gate dielectric layer 1 15 between the gate 1 10 and the channel region 125 is also shown in the top-down horizontal cross-section of FIG. IB. In the standard configuration shown in FIG. IB, carriers are injected from the source contact 145 into the first interface 139 with the doped source region 140, turn 90° following solid arrow 141 to enter the channel 125, are transported through and exit the channel 125 into the doped drain region 150, and then turn 90° following solid arrow 151 toward a second interface 149 with the doped drain region 150 and get collected by the drain contact 155. The 90° turns require a significant change in carrier momentum, to create current flow from doped source region 140 to doped drain region 150. In standard devices with long source and drain regions, substantial carrier scattering in the source and drain regions produces this change in carrier momentum. For reduced scale devices with comparatively short source and drain regions, however, the probability of carrier scattering in the source and drain regions is relatively low, with many carriers being ballistic or quasi-ballistic, with a zero or very minor scattering and consequently a zero or very minor change in momentum, especially for light m* material (e.g., group III-V semiconductor materials, such as Ino_.7Gao_.3As, Ge). As shown by dashed arrows in FIG. IB, ballistic carriers emitted by the source contact 145 may not be able to get injected into the channel 125 and are lost following arrow 142, and ballistic carriers exiting the channel 125 may not be collected by the drain contact 155 and are lost following arrow 152. Such carrier loss results in a reduced source-to-drain current, or an increased effective source-to- drain resistance. Embodiments of the present disclosure recognize this problem and are configured to help to mitigate or otherwise reduce such carrier loss.

FinFET with Angled Source and Drain Regions

In an embodiment according to this disclosure, shown in FIG. 2A, the doped source and drain regions adjacent to the channel region have a first interface and a second interface, respectively, angled with respect to the channel region. Turning to FIG. 2A, a cross-section along the same A- A' plane of a FinFET 200 shows carriers injected from source metal contact 245 and doped source region 240 entering the adjacent channel region 225 from a first interface 239, between source metal contact 245 and doped source region 240, either directly along arrow 241 with no scattering (ballistic carriers), or along path 242 consisting of two connected arrows, one at a first angle θι less than 90° that allows a lower probability of scattering events (quasi- ballistic carriers) relative to a standard source contact structure that is oriented at an angle θι equal to 90° to the channel region. In some embodiments of the present disclosure, the first angle θι is in a range of between less than 90° and greater than or equal to 0°, the first angle θι of the first interface 239 measured with respect to an imaginary horizontal line 223 that passes through the channel region 225 and the doped source region 240. In the doped drain region 250, carriers exit the channel region 225 into the doped drain region 250 adjacent the channel region 225 and into a second interface 249, between the drain metal contact 255 and the doped drain region 250, the second interface 249 being angled with respect to the channel region 225 at a second angle θ₂. These carriers are either directly collected by the drain metal contact 255 along arrow 251 as ballistic carriers, or collected along path 252 consisting of two connected arrows, one at the second angle θ₂ less than 90°, the latter collection being enabled by a lower probability of scattering events (quasi-ballistic carriers) relative to a standard drain contact structure that is oriented at an angle θ₂ equal to 90° to the channel region. In some embodiments of the present disclosure, the second angle θ₂ is in a range of between less than 90° and greater than or equal to 0° with respect to the imaginary horizontal line 223, the imaginary horizontal line 223 also passing through the doped drain region 250. The gate electrode 210, gate dielectric layer 215, gate spacer 220 that isolates the gate electrode 210 from doped source region 240 and source metal contact 245, and gate spacer 230 that isolates the gate electrode 210 from doped drain region 250 and drain metal contact 255 are also shown in FIG. 2 A.

FIG. 2B is a schematic illustration of the doped source and drain regions facing the channel region at an angle of 0°, according to another embodiment of the present disclosure. Turning to FIG. 2B, a cross-section along the same A-A' plane of a FinFET 200 shows carriers injected from source metal contact 245 and first interface 239 with the doped source region 240 entering the channel region 225 directly along arrow 241 at an angle θι (not shown) of 0° with respect to the imaginary horizontal line 223 with no scattering (ballistic carriers). In the doped drain region 250, carriers exiting the channel region 225 into the second interface 249 with the doped drain region 250 are directly collected ballistically along arrow 251 by the drain metal contact 255 at an angle θ₂ (not shown) of 0° with respect to the imaginary horizontal line 223. The gate electrode 210, gate dielectric layer 215, gate spacer 220 that isolates the gate 210 from doped source region 240 and source metal contact 245, and gate spacer 230 that isolates the gate electrode 210 from doped drain region 250 and drain metal contact 255 are also shown in FIG. 2B.

As will be appreciated, the fins on which the transistor devices having angled source/drain regions are built can be formed using any suitable fin forming techniques, such as one or more patterning and etching processes, for example. In some embodiments, the fins are native to the substrate, in that the fins are formed on and from the substrate, with a trench between fins. The fins may be formed by etching trenches out of a bulk of substrate material such as a bulk silicon substrate, for example. In other embodiments, the fins are so-called replacement fins that are not native to the substrate, but instead are fins deposited onto the substrate within relatively deep trenches previously occupied by placeholder fins native to the substrate, via an aspect ratio trapping process. In some such cases, the fins are formed as multilayer stacks of different materials, to facilitate later formation of nanowires during a gate last process. Example replacement fin forming techniques are provided, for instance, in U.S. Patent Application Publication No. 2014/0027860 and U.S. Patent No. 9,343,559. As will be further appreciated, the channel region 225 may be implemented with a double-gate

configuration, or a tri-gate configuration, or a nanowire configuration (channel includes one or more nanowires to provide a gate-all-around configuration). In any such cases, the crystal orientation of the fin can be configured so as to provide a desired growth surface in the source/drain regions, which in turn causes a desired source/drain region angle relative to the channel, as will be appreciated in light of this disclosure. Further note that the crystal orientation of the fin also impacts the transport of carriers within the channel region. Thus, tradeoffs/constraints associated with such features may be made if needed. Said differently, optimal source/drain angle and carrier transport are not required for all embodiments. For instance, in some embodiments, crystal orientation of the fin may be set to provide a specific desired source/drain angle in conjunction with less than optimal level of carrier transport, while in other embodiments crystal orientation of the fin may be set to provide a specific desired level of carrier transport in conjunction with less than optimal source/drain angle. To this end, optimal source/drain angles and carrier transport levels are not required. Rather, either or both features may be set to be within an acceptable tolerance of a desired value/level. Methodology and Architecture

FIG. 3 A is a method for forming a transistor structure with angled source and drain regions in accordance with an embodiment of the present disclosure. FIGS. 4A through 4D illustrate example structures that are formed as the method is carried out, and in accordance with some embodiments.

As can be seen, the method includes forming 3 10 a gate stack on a semiconductor substrate upon which a MOS device, such as a PMOS or NMOS transistor, may be formed. The semiconductor substrate may be implemented, for example, with a bulk silicon or a silicon-on- insulator substrate configuration. In some implementations, the semiconductor substrate may be formed using crystalline silicon. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, such as germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, indium gallium arsenide (e.g., Ino_.7Gao_.3As), gallium arsenide, or gallium antimonide. In a more general sense, any material that may serve as a foundation upon which a

semiconductor device may be built or otherwise formed can be used in accordance with embodiments of the present disclosure. The gate stack can be formed as typically done or using any suitable custom techniques. In some embodiments of the present disclosure, the gate stack may be formed by depositing and then patterning a gate dielectric layer and a gate electrode layer. For instance, in one example case, a gate dielectric layer may be blanket deposited onto the semiconductor substrate using standard deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), spin-on deposition (SOD), or physical vapor deposition (PVD). Alternate deposition techniques may be used as well, for instance, the gate dielectric layer may be thermally grown. The gate dielectric material may be formed, for example, from materials such as silicon dioxide or high-k dielectric materials or a combination of such materials. Examples of high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some specific example embodiments, the high-k gate dielectric layer may be between around 5 A to around 200 A thick (e.g., 20 A to 50 A). In general, the thickness of the gate dielectric layer should be sufficient to electrically isolate the gate electrode from the neighboring source and drain contacts. In further embodiments, additional processing may be performed on the high-k gate dielectric layer, such as an annealing process to improve the quality of the high-k material. Next, a gate electrode material may be deposited on the gate dielectric layer using similar deposition techniques such as ALD, CVD, or PVD. In some such specific embodiments, the gate electrode material is polysilicon or a metal layer (e.g., tungsten, titanium, copper, aluminum tungsten, titanium nitride, tantalum, and tantalum nitride, or a combination of such materials), although other suitable gate electrode materials can be used as well. The gate electrode material, which may be a sacrificial material that is later removed for a replacement metal gate (RMG) process, has a thickness in the range of 50 A to 500 A (e.g., 100 A), in some example embodiments. A standard patterning process may then be carried out to etch away portions of the gate electrode layer and the gate dielectric layer to form the gate stack shown in FIG. 4A. A hardmask can be used to protect the gate stack while the extra gate materials are etched away or otherwise removed.

As can be seen, FIG. 4A illustrates a semiconductor-on-insulator configuration that includes a semiconductor substrate 400 (or fin 400) on insulator layer 401, although bulk substrates and other suitable configurations can be used as well. Insulator layer 401 can be formed from any suitable insulator material, such as, for example, silicon dioxide, and substrate 400 can be a crystalline layer of silicon. In this example embodiment, the gate stack includes a gate dielectric layer 402 (which may be high-k gate dielectric material) and a gate electrode 404. In one specific example case, the gate stack includes a silicon dioxide gate dielectric layer 402 and a polysilicon or tungsten gate electrode 404. In still other embodiments, the gate dielectric layer 402 includes multiple components such as a lower layer of silicon dioxide on the channel, and a upper layer of hafnium oxide on the silicon dioxide layer. Likewise, the gate electrode structure 404 may include multiple components in some embodiments, such as work function metals and/or barrier materials surrounding a metal core or plug. FIG. 4A further illustrates gate spacers 410 formed on either side of the stack that isolate the gate electrode 404 from the doped source region and source metal contacts, and doped drain region and drain metal contacts described below. The gate spacers 410 may be formed, for example, using standard gate spacer materials such as silicon dioxide, silicon nitride, or other suitable spacer materials. The width of the gate spacers 410 may generally be chosen based on design requirements for the transistor being formed.

With further reference to FIG. 3A, the method further includes defining 320 the source and drain regions of the transistor structure. The source and drain regions can be, for example, group IV semiconductor materials or group III-V semiconductor materials, and have any desired doping scheme/polarity (e.g., silicon or SiGe alloy, InGaAs, InAlAs, InGaSb, InSb, p-type and/or n-type). In the example embodiment shown in FIG. 4B, substrate 400 has been etched to provide cavities 412 and 414 to either side of channel regions 406. The channel regions 406 may be undoped or light doped, as the case may be. With further reference to FIG. 3 A, the method further includes depositing 330 the source and drain materials at an angle, as described further below, by exploiting the epitaxial growth angle. FIG. 4C illustrates the substrate 400 after cavities 412 and 414 have been filled at an angle, to provide the source regions 415 with a first interface 433 and drain regions 420 with a second interface 434. Any number of source and drain layer configurations can be used here, with respect to materials (e.g., silicon, SiGe, III-V materials, etc.), dopant (e.g., boron, arsenic, phosphorous, or other suitable dopant), and dimension (e.g., thickness of source and drain regions may range, for instance, from 50 to 500 nm).

Any suitable molecular beam, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or lateral epitaxial growth method that can yield a deposit of source and drain material at an angle in a range of between less than 90° and greater than or equal to 0° can be used to form the source regions 415 and drain regions 420. In one embodiment, lateral epitaxial growth is used on crystalline silicon having (110) side surfaces and a (100) top surface, as generally shown in FIGS. 8A-8B. In this example configuration, the growth surface is typically the (1 1 1) silicon crystal plane which gives an angle Θ of

approximately 55° (as shown in FIG. 8 A) or the (311) silicon crystal plane which gives an angle Θ of approximately 25° (as shown in FIG. 8B). As will be appreciated in light of this disclosure, the angle Θ significantly varies with the deposited source and drain material, crystal orientation of the underlying substrate, and growth conditions. Therefore, for the lateral epitaxial growth process, the angle Θ can be in a range of between 25° and 55°, in this example embodiment, where the crystalline silicon substrate is oriented so as to provide a channel region (or fin) having (1 10) side surfaces and a (100) top surface. Other substrate orientations can be used as well as any number of different crystalline materials upon which growth of the source/drain regions can be carried out.

With further reference to FIG. 3 A, the method further includes depositing 340 source and drain metal contact plugs or other suitable contact structure. FIG. 4D shows the source metal contact plug 429 and drain metal contact plug 431. In some example embodiments, the metal for the contact plugs 429 and 431 may include, for instance, aluminum, tungsten, copper, titanium, silver, nickel-platinum or nickel-aluminum or any other suitably conductive contact metal or alloy. The contact metals can be provisioned using any number of standard deposition processes. In some cases, source/drain contact structures are provided that include multiple components, such as a liner or barrier layer, resistance reducing metal, work function metals, and a plug. With further reference to FIG. 4D, carriers injected from source metal contact plug 429 and doped source region 415 enter the channel region 406 either directly along arrow 416 with no scattering (ballistic carriers), or along arrow 417 at a first angle θι of the first interface 433 less than 90°, measured with respect to an imaginary horizontal line 435 that passes through the channel region 406 and the source region 415, that allows a lower probability of scattering events (quasi -ballistic carriers) relative to the standard source contact structure that is oriented at an angle θι equal to 90° to the channel region. In the doped drain region 420, carriers exit the channel region 406 into the drain region 420 adjacent the channel region 406 and into the second interface 434 of the drain region 420 and are either directly collected by the drain metal contact plug 431 ballistically along arrow 421, or collected along arrow 422 at a second angle θ₂ less than 90° with respect to the imaginary horizontal line 435, the imaginary horizontal line 435 also passing through the doped drain region 420, the latter collection being enabled by a lower probability of scattering events (quasi-ballistic carriers) relative to the standard drain contact structure that is oriented at an angle θ₂ equal to 90° to the channel region.

FIG. 3B is a method for forming a transistor structure with source and drain regions angled at 0° in accordance with another embodiment of the present disclosure. FIGS. 5A through 5G illustrate example structures that are formed as the method is carried out, and in accordance with some embodiments. The previous relevant discussion with respect to the method of FIG. 3A and FIGS. 4A-4D is equally applicable here as will be appreciated, and not all details and variations are repeated for sake of brevity.

As can be seen, the method includes forming 310 a gate stack on a semiconductor substrate upon which a MOS device, such as a PMOS or MOS transistor, may be formed as described above. As can be seen, FIG. 5A illustrates a substrate 500 (or fin 500) on insulator layer 501 upon which a gate stack is formed. Insulator layer 501 can be formed from any suitable insulator material, such as, for example, silicon dioxide. In this example embodiment, the gate stack includes a gate dielectric layer 502 (which may be high-k gate dielectric material) and a gate electrode 504. In one specific example case, the gate stack includes a silicon dioxide gate dielectric layer 502 and a polysilicon gate electrode 504. FIG. 5A further illustrates gate spacers 510 formed on either side of the stack that isolate the gate electrode 504 from the source region and source metal contact, and drain region and drain metal contact described below. The gate spacers 510 may be formed, for example, using standard dielectric materials such as silicon dioxide, silicon nitride, hafnium oxide, or other suitable spacer materials. The width of the gate spacers 510 may generally be chosen based on design requirements for the transistor being formed. With further reference to FIG. 3B, the method further includes defining 320 the source and drain regions of the transistor structure as described above. In the example embodiment shown in FIG. 5B, substrate 500 has been etched to provide cavities 512 and 514, adjacent to channel region 506. With further reference to FIG. 3B, the method further includes depositing 325 the source and drain materials into cavities 512 and 514. FIG. 5C illustrates the substrate 500 after cavities 512 and 514 have been filled with source material 513 and drain material 516. The source and drain layer configurations with respect to materials, dopant, and dimension are as described above, except that, as shown in FIG. 5C, the source material 513 and drain material 516 fill the cavities 512 and 514, respectively, up to being co-planar with the channel regions 506, in accordance with some embodiments. In other embodiments, the source material 513 and drain material 516 may be raised or otherwise taller than the channel regions 506.

With further reference to FIG. 3B, the method further includes forming 326 sacrificial dielectric spacers on the source and drain regions. FIG. 5D illustrates a pair of sacrificial dielectric spacers 525 that are formed along the side walls of the cavities 512 and 514 in accordance with an implementation of this disclosure. The sacrificial dielectric spacers 525 may be formed using deposition and etching processes similar to the fabrication of gate dielectric spacers 510. For instance, a conformal layer of an insulating material may be deposited within the cavities 512 and 514, resulting in the insulating material being deposited along the side walls and bottom surface of the cavities 512 and 514. The insulating material may be, for example, silicon dioxide, silicon nitride, silicon oxynitride (SiON), carbon-doped silicon oxynitride, any other oxide, any other nitride, or any low-k dielectric material. Next, an anisotropic etching process is used to remove the insulating material from the bottom of the cavities 512 and 514. This yields the sacrificial dielectric spacers 525 that are shown in FIG. 5D. With further reference to FIG. 3B, the method further includes anisotropically etching 327 the source and drain regions. FIG. 5E illustrates the cavities 512 and 514 after the source material 513 and drain material 516 have been anisotropically etched to form source regions 515 with a first interface 533 and drain regions 520 with a second interface 534, respectively. Any etching process suitable for anisotropically etching the source and drain materials 513 and 516 described above can be used to form source regions 515 and drain regions 520. With further reference to FIG. 3B, the method further includes removing 328 the sacrificial spacers 525. FIG. 5F illustrates the cavities 512 and 514 after the sacrificial dielectric spacers 525 have been removed. Any wet or dry etching process suitable for selectively removing the materials described above for the sacrificial dielectric spacers 525 can be used. With further reference to FIG. 3B, the method further includes depositing 340 source and drain metal contact plugs. FIG. 5G shows the source metal contact plug 529 and drain metal contact plug 531. The materials and deposition processes for the source metal contact plug 529 and drain metal contact plug 531 are as described above for metal contact plugs 429 and 431. With further reference to FIG. 5G, carriers injected from source metal contact plug 529 and first interface 533 of the doped source region 515 enter the channel region 506 directly along arrow 517 at an angle θι (not shown) of 0° with respect to the imaginary horizontal line 535 with no scattering (ballistic carriers). In the doped drain region 520, carriers exiting the channel region 506 into the second face 534 of the doped drain region 520 are directly collected by the drain metal contact plug 531 ballistically along arrow 518 at an angle Θ2 (not shown) of 0° with respect to the imaginary horizontal line 535.

Simulation Results

Monte Carlo (MC) simulations were carried out on standard FinFETs and FinFETs with angled source and drain regions according to this disclosure. Two kinds of FinFETs were investigated, the first being an Ino_.7Gao_.3As dual gate n-FinFET, and the second being a silicon (Si) dual gate n-FinFET. The two materials (Ino_.7Gao_.3As and Si) were investigated as example materials, while the disclosed techniques are also applicable to other semiconductor materials, as discussed above. The first FinFET is a light electron effective mass (m*), low electron density- of-states (DOS) material, with low scattering rates, so that carriers flow through the device nearly entirely ballistically. The second FinFET has a higher electron m* and DOS, and a higher scattering rate, so that carriers have a higher probability of scattering (more diffusive, less ballistic), relative to the first. Both FinFETs were simulated with relatively thick and thin source and drain regions. The thickness of the source region was equal to the thickness of the drain region for all FinFETs. For the standard FinFETS, the thick and thin source and drain regions were 16 nm and 9 nm, respectively. For the angled FinFETs, the thick and thin source and drain regions were 16 nm and 9 nm, respectively, while the width tapers according to the angle. The channel thickness was 5 nm in all cases. FIG. 6 shows the results for the drain current I_D as a function of gate voltage VQ at high (0.5 V) drain voltage (V_D) for the Ino_.7Gao_.3As FinFET for the standard (90°) thick (A), thin (B) FinFETs, and angled (45°) thick (C), thin (D), and zero degrees (0°) (E) FinFETs according to this disclosure. The results are also tabulated in Table I. Table I.

The thick (90°) standard structure (A) delivers a higher current compared to the thin structure (B), because the thick structure has larger doped source and drain regions, which provide carriers with a higher probability of scattering and momentum change to get injected into the channel and collected by the drain. However, the FinFETs with angled source and drain regions according to this disclosure deliver substantially higher currents relative to the standard structure, with the zero degree (E) FinFET showing more than 100% improvement.

FIG. 7 shows the results for the drain current I_D as a function of gate voltage VG at high (0.5 V) drain voltage (V_D) for a silicon (Si) FinFET for the standard (90°) thick (A), thin (B) FinFETs, and angled (45°) thick (C), thin (D), and zero degrees (0°) (E) FinFETs according to this disclosure. The results are also tabulated in Table II.

Table II.

For the silicon FinFET, the difference in drain current I_D is small between the thick (A) and thin (B) standard (90°) FinFET, because both structures provide similar carrier injection and collection efficiency due to the increased scattering rate in silicon, as explained above. For the angled (45°) FinFETs, however, the difference in drain current between thick (C) and thin (D) source and drain regions is still significant, although smaller than that obtained for Ino_.7Gao_.3As, because ballistic and quasi-ballistic transport is still relevant due to the short source and drain lengths, even with the increased scattering rate in silicon.

Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SFMS); time-of-flight SFMS (ToF- SFMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate the presence of FinFETs and even planar transistors with angled source and drain regions in a semiconductor integrated circuit.

Example System

FIG. 9 is an example computing system implemented with one or more of the integrated circuit structures as disclosed herein, in accordance with some embodiments of the present disclosure. As can be seen, the computing system 900 houses a motherboard 902. The motherboard 902 may include a number of components, including, but not limited to, a processor 904 and at least one communication chip 906, each of which can be physically and electrically coupled to the motherboard 902, or otherwise integrated therein. As will be appreciated, the motherboard 902 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 900, etc.

Depending on its applications, computing system 900 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 902. These other components may include, but are not limited to, volatile memory {e.g., DRAM), non-volatile memory (e.g., read only memory (ROM)), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 900 may include one or more integrated circuit structures or devices configured in accordance with an example embodiment (e.g., to include one or more FinFETs with angled source and drain regions, as variously provided herein). In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 906 can be part of or otherwise integrated into the processor 904).

The communication chip 906 enables wireless communications for the transfer of data to and from the computing system 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), lx evolution-data optimized (Ev-DO), high speed packet access (HSPA+), high speed downlink packet access (HSDPA+), high speed uplink packet access (HSUPA+), enhanced data rates for GSM evolution (EDGE), global system for mobile communication (GSM), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. In some embodiments, communication chip 906 may include one or more transistor structures having FinFETs with angled source and drain regions as variously described herein.

The processor 904 of the computing system 900 includes an integrated circuit die packaged within the processor 904. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 906 also may include an integrated circuit die packaged within the communication chip 906. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices as variously described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 904 (e.g., where functionality of any chips 906 is integrated into processor 904, rather than having separate communication chips). Further note that processor 904 may be a chip set having such wireless capability. In short, any number of processor 904 and/or communication chips 906 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 900 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is a semiconductor integrated circuit, comprising: a channel region; a gate electrode above the channel region; a gate dielectric layer between the gate electrode and the channel region; a source region adjacent to the channel region and having a first interface angled with respect to the channel region at a first angle in a range of between less than 90° and greater than or equal to 0°, the first angle of the first interface measured with respect to an imaginary horizontal line that passes through the channel region and the source region; a source metal contact on the source region; a drain region adjacent to the channel region and having a second interface angled with respect to the channel region at a second angle in a range of between less than 90° and greater than or equal to 0° with respect to the imaginary horizontal line, the imaginary horizontal line also passing through the drain region; and a drain metal contact on the drain region.

Example 2 includes the subject matter of Example 1, wherein the first angle is equal to

0°.

Example 3 includes the subject matter of Example 1 or Example 2, wherein the second angle is equal to 0°.

Example 4 includes the subject matter of Example 1, wherein the first angle is in the range of between less than or equal to 55° and greater than or equal to 25°.

Example 5 includes the subject matter of Example 1 or Example 4, wherein the first angle is equal to 45°.

Example 6 includes the subject matter of Examples 4 or 5, wherein the second angle is in the range of between less than or equal to 55° and greater than or equal to 25°.

Example 7 includes the subject matter of Example 6, wherein the second angle is equal to 45°.

Example 8 includes the subject matter of any of Examples 1 to 7, wherein the source region has a thickness in a range of between 1 nm and 16 nm.

Example 9 includes the subject matter of Example 8, wherein the thickness of the source region is in the range of between 1 nm and 9 nm.

Example 10 includes the subject matter of any of Examples 1 to 9, wherein the drain region has a thickness in a range of between 1 nm and 16 nm.

Example 1 1 includes the subject matter of Example 10, wherein the thickness of the drain region is in the range of between 1 nm and 9 nm.

Example 12 includes the subject matter of any of Examples 1 to 1 1, wherein the channel region is formed in a substrate. Example 13 includes the subject matter of Example 12, wherein the substrate comprises one of silicon and InGaAs.

Example 14 includes a computing device that includes the subject matter of any of Examples 1 to 13.

Example 15 includes a method for forming a semiconductor integrated circuit, the method comprising: forming a channel region; forming a gate structure, the gate structure including a gate electrode above the channel region and a gate dielectric layer between the gate electrode and the channel region; forming a source region adjacent to the channel region and having a first interface angled with respect to the channel region at a first angle in a range of between less than 90° and greater than or equal to 0°, the first angle of the first interface measured with respect to an imaginary horizontal line that passes through the channel region and the source region; forming a source metal contact on the channel region; forming a drain region adjacent to the channel region and having a second interface angled with respect to the channel region at a second angle in a range of between less than 90° and greater than or equal to 0° with respect to the imaginary horizontal line, the imaginary horizontal line also passing through the drain region; and forming a drain metal contact on the drain region.

Example 16 includes the subject matter of Example 15, wherein the first angle is equal to

0°.

Example 17 includes the subject matter of either of Examples 15 or 16, wherein the second angle is equal to 0°.

Example 18 includes the subject matter of any of Examples 15 to 17, wherein forming the source region includes lateral beam epitaxial growth of the source region.

Example 19 includes the subject matter of any of Examples 15 to 18, wherein the first angle is in the range of between less than or equal to 55° and greater than or equal to 25°.

Example 20 includes the subject matter of any of Examples 15 to 19, wherein forming the drain region includes lateral beam epitaxial growth of the drain region. Example 21 includes the subject matter of any of Examples 15 to 20, wherein the second angle is in the range of between less than or equal to 55° and greater than or equal to 25°.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS s claimed is:

1. A semiconductor integrated circuit, comprising: a channel region;

a gate electrode above the channel region;

a gate dielectric layer between the gate electrode and the channel region;

a source region adjacent to the channel region and having a first interface angled with respect to the channel region at a first angle in a range of between less than 90° and greater than or equal to 0°, the first angle of the first interface measured with respect to an imaginary horizontal line that passes through the channel region and the source region;

a source metal contact on the first interface of the source region;

a drain region adjacent to the channel region and having a second interface angled with respect to the channel region at a second angle in a range of between less than 90° and greater than or equal to 0° with respect to the imaginary horizontal line, the imaginary horizontal line also passing through the drain region; and

a drain metal contact on the second interface of the drain region.

2. The semiconductor integrated circuit of claim 1, wherein the first angle is equal to 0°.

3. The semiconductor integrated circuit of claim 1, wherein the second angle is equal to 0°.

4. The semiconductor integrated circuit of claim 1, wherein the first angle is in the range of between less than or equal to 55° and greater than or equal to 25°.

5. The semiconductor integrated circuit of claim 4, wherein the first angle is equal to 45°.

6. The semiconductor integrated circuit of claim 1, wherein the second angle is in the range of between less than or equal to 55° and greater than or equal to 25°.

7. The semiconductor integrated circuit of claim 6, wherein the second angle is equal to 45°.

8. The semiconductor integrated circuit of claim 1, wherein the source region has a thickness in a range of between 1 nm and 16 nm.

9. The semiconductor integrated circuit of claim 8, wherein the thickness of the source region is in the range of between 1 nm and 9 nm.

10. The semiconductor integrated circuit of claim 1, wherein the drain region has a thickness in a range of between 1 nm and 16 nm.

11. The semiconductor integrated circuit of claim 10, wherein the thickness of the drain region is in the range of between 1 nm and 9 nm.

12. The semiconductor integrated circuit of claim 1, wherein the channel region is formed in a substrate.

13. The semiconductor integrated circuit of claim 12, wherein the substrate comprises one of silicon and InGaAs.

14. A computing device comprising the semiconductor integrated circuit of any of claims 1-13.

15. A method for forming a semiconductor integrated circuit, the method comprising: forming a channel region;

forming a gate structure, the gate structure including a gate electrode above the channel region and a gate dielectric layer between the gate electrode and the channel region;

forming a source region adjacent to the channel region and having a first interface angled with respect to the channel region at a first angle in a range of between less than 90° and greater than or equal to 0°, the first angle of the first interface measured with respect to an imaginary horizontal line that passes through the channel region and the source region;

forming a source metal contact on the first interface of the source region;

forming a drain region adjacent to the channel region and having a second

interface angled with respect to the channel region at a second angle in a range of between less than 90° and greater than or equal to 0° with respect to the imaginary horizontal line, the imaginary horizontal line also passing through the drain region; and

forming a drain metal contact on the second interface of the drain region.

16. The method of claim 15, wherein the first angle is equal to 0°.

17. The method of claim 15 or 16, wherein the second angle is equal to 0°.

18. The method of claim 15, wherein forming the source region includes lateral beam epitaxial growth of the source region.

19. The method of claim 18, wherein the first angle is in the range of between less than or equal to 55° and greater than or equal to 25°.

20. The method of claim 15, wherein forming the drain region includes lateral beam epitaxial growth of the drain region.

21. The method of claim 20, wherein the second angle is in the range of between less than or equal to 55° and greater than or equal to 25°.