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WO2018180235A1 - Dispositif de boîtier semi-conducteur et son procédé de fabrication - Google Patents

Dispositif de boîtier semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2018180235A1
WO2018180235A1 PCT/JP2018/008270 JP2018008270W WO2018180235A1 WO 2018180235 A1 WO2018180235 A1 WO 2018180235A1 JP 2018008270 W JP2018008270 W JP 2018008270W WO 2018180235 A1 WO2018180235 A1 WO 2018180235A1
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WO
WIPO (PCT)
Prior art keywords
transistor
package
wiring
semiconductor package
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2018/008270
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English (en)
Japanese (ja)
Inventor
細美　英一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nidec Corp
Original Assignee
Nidec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nidec Corp filed Critical Nidec Corp
Priority to JP2019509079A priority Critical patent/JPWO2018180235A1/ja
Priority to CN201880021991.8A priority patent/CN110462825B/zh
Publication of WO2018180235A1 publication Critical patent/WO2018180235A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits

Definitions

  • the present invention relates to a semiconductor package device and a manufacturing method thereof.
  • Patent Document 1 An example of a conventional package device is disclosed in Patent Document 1.
  • a first integrated circuit die is fixed on a package substrate by adhesion.
  • the first integrated circuit die and the package substrate are connected by wire bonding.
  • the adhesive spacer is disposed between the first integrated circuit die and the integrated circuit package system.
  • the integrated circuit package system includes a second integrated circuit die, a terminal, and a sealing resin.
  • the second integrated circuit die is connected to the terminal by a bonding wire.
  • the second integrated circuit die and the terminal are sealed with a sealing resin.
  • the terminals and the package substrate are connected by bonding wires.
  • the package substrate, the first integrated circuit die, the adhesive spacer, and the integrated circuit package system are packaged by sealing with a sealing resin, thereby forming an integrated circuit package-in-package system.
  • the integrated circuit package system having the second integrated circuit die is disposed above the first integrated circuit die, so that the integrated circuit package system and the first integrated circuit die are electrically connected. Therefore, it is necessary to connect the terminals of the integrated circuit package system to the package substrate by wire bonding. When wire bonding is performed, a corresponding space is required for routing the wire.
  • Patent Document 1 when a similar package device is further stacked above the integrated circuit package system, the length of the bonding wire for connecting to the package substrate becomes longer as the upper package device is formed. . Therefore, in Patent Document 1, the number of package devices to be packaged is greatly limited. *
  • an object of the present invention is to provide a semiconductor package device that eliminates the need for wire bonding for wiring and reduces the number of semiconductor packages to be mounted.
  • An exemplary semiconductor package device of the present invention includes a wiring layer having an insulating part and a conductive part, a plurality of semiconductor packages arranged in contact with the upper surface of the wiring layer, a resin part for sealing the semiconductor package, It is set as the structure provided with.
  • the exemplary method for manufacturing a semiconductor package device of the present invention includes a first step of disposing a plurality of semiconductor packages on an adhesive disposed on a support substrate, and a second step of sealing the semiconductor package with a resin.
  • the exemplary semiconductor package device of the present invention it is not necessary to use wire bonding for wiring, and the number of semiconductor packages to be mounted is reduced.
  • FIG. 1 is a diagram showing a circuit configuration of a semiconductor package device according to an embodiment of the present invention.
  • FIG. 2A is a schematic cross-sectional side view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2B is a schematic cross-sectional side view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2C is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2D is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2E is a schematic cross-sectional side view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2F is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2A is a schematic cross-sectional side view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2B is a schematic cross-sectional side view showing one step in the manufacturing process of
  • FIG. 2G is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 3A is a bottom view showing one process in the manufacturing process of the semiconductor package device.
  • FIG. 3B is a bottom view showing one process in the manufacturing process of the semiconductor package device.
  • FIG. 3C is a bottom view showing one process in the manufacturing process of the semiconductor package device.
  • FIG. 3D is a bottom view showing one process in a manufacturing process of the semiconductor package device.
  • FIG. 1 shows a circuit configuration of a semiconductor package device 50 according to an embodiment of the present invention.
  • the semiconductor package device 50 has a function of driving the motor 60.
  • the semiconductor package device 50 includes a first package 1, a second package 2, a third package 3, a fourth package 4, a fifth package 5, a sixth package 6, 7 package 7.
  • the semiconductor package device 50 according to the present embodiment is configured by packaging a plurality of semiconductor packages that are the first package 1 to the seventh package 7 into one. *
  • the first package 1 includes a microcomputer 1A and a gate driver 1B.
  • the second package 2 includes a first transistor M1 configured by an n-channel MOSFET (metal-oxide-semiconductor field-effect transistor).
  • the third package 3 includes a second transistor M2 configured with a p-channel MOSFET.
  • the fourth package 4 includes a third transistor M3 configured with an n-channel MOSFET.
  • the fifth package 5 includes a fourth transistor M4 configured by a p-channel MOSFET.
  • the sixth package 6 includes a fifth transistor M5 configured with an n-channel MOSFET.
  • the seventh package 7 includes a sixth transistor M6 configured by a p-channel MOSFET. *
  • the first transistor M1 to the sixth transistor M6 constitute an inverter IV. *
  • the application terminal of the input voltage Vin which is a DC voltage is connected to the source of the second transistor M2.
  • the drain of the second transistor M2 is connected to the drain of the first transistor M1.
  • the source of the first transistor M1 is connected to a ground potential application terminal. That is, the first transistor M1 and the second transistor M2 are connected in series.
  • the application terminal of the input voltage Vin is connected to the source of the fourth transistor M4.
  • the drain of the fourth transistor M4 is connected to the drain of the third transistor M3.
  • the source of the third transistor M3 is connected to a ground potential application terminal. That is, the third transistor M3 and the fourth transistor M4 are connected in series.
  • the application terminal of the input voltage Vin is connected to the source of the sixth transistor M6.
  • the drain of the sixth transistor M6 is connected to the drain of the fifth transistor M5.
  • the source of the fifth transistor M5 is connected to a ground potential application terminal. That is, the fifth transistor M5 and the sixth transistor M6 are connected in series.
  • the motor 60 that is the driving target of the semiconductor package device 50 is a three-phase brushless DC motor.
  • a connection node P1 to which the fifth transistor M5 and the sixth transistor M6 are connected is connected to the U-phase input terminal of the motor 60.
  • a connection node P2 to which the third transistor M3 and the fourth transistor M4 are connected is connected to a V-phase input terminal of the motor 60.
  • a connection node P3 to which the first transistor M1 and the second transistor M2 are connected is connected to the W-phase input terminal of the motor 60.
  • the gate driver 1B switches the transistors M1 to M6 by applying a driving voltage to the gates of the transistors M1 to M6 based on a command from the microcomputer 1A.
  • the motor 60 is driven by, for example, sinusoidal driving.
  • the upper transistor (for example, the second transistor M2) and the lower transistor (for example, the first transistor M1) constituting one arm are p-channel MOSFET and n-channel MOSFET, respectively.
  • both the upper transistor and the lower transistor may be constituted by n-channel MOSFETs.
  • a bootstrap capacitor for driving the upper transistor is included in the semiconductor package device.
  • FIGS. 2A to 2G are schematic side sectional views in each step. *
  • a support substrate 52 having an adhesive 51 disposed on the upper surface is prepared, and seven semiconductor packages, which are the first package 1 to the seventh package 7, are arranged on the adhesive 51.
  • the fourth package 4 to the seventh package 7 are not shown in FIG. 2A, they are actually arranged on the back side of the sheet of FIG. 2A.
  • a glass substrate or a silicon substrate is used as the support substrate 52. *
  • the process proceeds to the step shown in FIG. 2B.
  • the resin part (mold resin) 501 is sealed so as to cover the whole of the first package 1 to the seventh package 7. *
  • the process proceeds to the step shown in FIG. 2D, and the first insulating layer 502 is formed on the lower surface side of the first package 1 to the seventh package 7.
  • a via 502A is formed by laser processing or the like.
  • the via 502A is a through-hole penetrating in the thickness direction of the first insulating layer 502, and is formed at a position corresponding to each terminal of the first package 1 to the seventh package.
  • the first wiring pattern portion 503 is formed by plating on the inside of the via 502A and the lower surface of the first insulating layer 502.
  • the plating for example, copper plating is used.
  • a conductive material (such as copper) used for plating may be filled inside the via, or the conductive material may be formed only along the inner wall of the via.
  • the process proceeds to the step shown in FIG. 2F, and the second insulating layer 504 is formed on the lower surface side of the first insulating layer 502. Then, a via 504A is formed in the second insulating layer 504. The via 504A is formed at a position corresponding to a predetermined location of the first wiring pattern portion 503. Then, as shown in FIG. 2F, the second wiring pattern portion 505 is formed by plating on the inside of the via 504A and the lower surface of the second insulating layer 504. *
  • the process proceeds to the step shown in FIG. 2G, and the semiconductor package device 50 is completed by forming the resist layer 506 on the lower surface side of the second insulating layer 504.
  • the resist layer 506 is laminated so as not to be formed at a position corresponding to a portion exposed downward in the second wiring pattern portion 505.
  • the portion exposed below is a terminal portion that is electrically connected to a printed board on which the semiconductor package device 50 is mounted.
  • solder ball can be provided at the lower exposed portion of the second wiring pattern portion 505.
  • an insulating portion 5001A is configured from the first insulating layer 502 and the second insulating layer 504.
  • the first wiring pattern portion 503 and the second wiring pattern portion 505 constitute a conductor portion 5001B. That is, the semiconductor package device 50 includes a wiring layer 5001 including an insulating part 5001A and a conductor part 5001B.
  • the semiconductor package device 50 according to the present embodiment manufactured by such a manufacturing process can perform wiring by forming the conductor portion 5001B by plating the insulating portion 5001A, wire bonding is not necessary. . Further, compared to the conventional configuration in which the above-described package devices are stacked in the vertical direction (vertical direction), the number of semiconductor packages to be mounted is less likely to be limited. *
  • wiring is performed on a plurality of stacked insulating layers such as the first insulating layer 502 and the second insulating layer 504, so that the degree of freedom of wiring can be increased in a limited space. . *
  • the semiconductor package device 50 is a wide variety when dealing with various motors. However, since a prepackaged device is used, the semiconductor package device 50 is compatible with a wide variety. It is easy. *
  • FIG. 3A shows a plan view seen from below in the state shown in FIG. 2C in the manufacturing process described above.
  • 3A is a bottom view of the first package 1 to the seventh package sealed by the resin portion 501.
  • FIG. 3A the plurality of terminals 10 of the first package 1 are arranged on each side of the outer edge of the rectangular lower surface of the first package 1 and exposed downward.
  • the terminal 10 includes driving terminals 10A to 10F described later. *
  • the second package 2 has a control terminal 2A, a current outflow terminal 2B, and a current inflow terminal 2C, and these terminals are exposed downward.
  • the second package 2 has a chip of the first transistor M1 inside.
  • the control terminal 2A is connected to the gate of the first transistor M1.
  • the current outflow terminal 2B is connected to the source of the first transistor M1.
  • the current inflow terminal 2C is connected to the drain of the first transistor M1.
  • the third package 3 has a control terminal 3A, a current outflow terminal 3B, and a current inflow terminal 3C, and these terminals are exposed downward.
  • the third package 3 has a chip of the second transistor M2 inside.
  • the control terminal 3A is connected to the gate of the second transistor M2.
  • the current outflow terminal 3B is connected to the drain of the second transistor M2.
  • the current inflow terminal 3C is connected to the source of the second transistor M2. *
  • the fourth package 4 has a control terminal 4A, a current outflow terminal 4B, and a current inflow terminal 4C, and these terminals are exposed downward.
  • the fourth package 4 has a third transistor M3 chip inside.
  • the control terminal 4A is connected to the gate of the third transistor M3.
  • the current outflow terminal 4B is connected to the source of the third transistor M3.
  • the current inflow terminal 4C is connected to the drain of the third transistor M3. *
  • the fifth package 5 has a control terminal 5A, a current outflow terminal 5B, and a current inflow terminal 5C, and these terminals are exposed downward.
  • the fifth package 5 has a chip of a fourth transistor M4 inside.
  • the control terminal 5A is connected to the gate of the fourth transistor M4.
  • the current outflow terminal 5B is connected to the drain of the fourth transistor M4.
  • the current inflow terminal 5C is connected to the source of the fourth transistor M4. *
  • the sixth package 6 has a control terminal 6A, a current outflow terminal 6B, and a current inflow terminal 6C, and these terminals are exposed downward.
  • the sixth package 6 has a chip of a fifth transistor M5 inside.
  • the control terminal 6A is connected to the gate of the fifth transistor M5.
  • the current outflow terminal 6B is connected to the source of the fifth transistor M5.
  • the current inflow terminal 6C is connected to the drain of the fifth transistor M5. *
  • the seventh package 7 has a control terminal 7A, a current outflow terminal 7B, and a current inflow terminal 7C, and these terminals are exposed downward.
  • the seventh package 7 has a sixth transistor M6 chip inside.
  • the control terminal 7A is connected to the gate of the sixth transistor M6.
  • the current outflow terminal 7B is connected to the drain of the sixth transistor M6.
  • the current inflow terminal 7C is connected to the source of the sixth transistor M6. *
  • FIG. 3B is a plan view of the state of the process shown in FIG. 2D described above viewed from below. That is, FIG. 3B shows a state in which the first insulating layer 502 is formed and the via 502A is formed in the first insulating layer 502 with respect to the state of FIG. 3A. *
  • vias 502 ⁇ / b> A are formed at positions corresponding to the terminals 10 of the first package 1.
  • vias 502A are formed at positions corresponding to the control terminals 2A to 7A, the current outflow terminals 2B to 7B, and the current inflow terminals 2C to 7C of the second package 2 to the seventh package 7, respectively.
  • four vias 502A are formed for each of the current inflow terminals 2C to 7C.
  • FIG. 3C is a plan view of the state of the process shown in FIG. 2E described above as viewed from below. That is, FIG. 3C shows a state in which the first wiring pattern portion 503 is formed by plating on the inside of the via 502A and the lower surface of the first insulating layer 502 in the state of FIG. 3B. *
  • the first wiring pattern portion 503 includes control wiring portions 503A to 503F, connection wiring portions 503G to 503I, a common connection wiring portion 503J, and a wiring portion 503K. *
  • the control wiring portions 503A to 503F electrically connect the driving terminals 10A to 10F of the first package 1 and the control terminals 2A to 7A, respectively.
  • the first package 1 can apply a driving voltage to the control terminals 2A to 7A via the control wiring portions 503A to 503F.
  • connection wiring portions 503G to 503I are respectively connected to the current outflow terminals 3B, 5B, and 7B of the third, fifth, and seventh packages, and the current inflow terminals 2C, 4C, and 6C of the second, fourth, and sixth packages, respectively. , Connect electrically. *
  • the common connection wiring portion 503J electrically connects the current inflow terminals 3C, 5C, and 7C of the third, fifth, and seventh packages in common. *
  • wiring portions 503K are electrically connected to the terminals 10 other than the driving terminals 10A to 10F of the first package 1, respectively.
  • FIG. 3D is a plan view of the state of the process shown in FIG. 2F described above viewed from below. That is, FIG. 3D shows the state of FIG. 3C in which the second insulating layer 504 is formed, the via 504A is formed in the second insulating layer 504, and the inside of the via 504A and the lower surface of the second insulating layer 504 are plated. A state in which the second wiring pattern portion 505 is formed is shown. *
  • the second wiring pattern portion 505 includes ground wiring portions 505A to 505C, output wiring portions 505D to 505F, an input voltage application wiring portion 505G, and a circular wiring portion 505H.
  • the ground wiring portion 505A is electrically connected to the current outflow terminal 2B of the second package 2 through the via 504A and the via 502A.
  • the ground wiring portion 505B is electrically connected to the current outflow terminal 4B of the fourth package 4 through the via 504A and the via 502A.
  • the ground wiring portion 505C is electrically connected to the current outflow terminal 6B of the sixth package 6 through the via 504A and the via 502A.
  • a ground potential is applied to the ground wiring portions 505A to 505C when the semiconductor package device 50 is mounted. *
  • the ground wiring portion 505B overlaps with the control wiring portion 503B in plan view.
  • the ground wiring portion 505C overlaps with the control wiring portions 503A to 503F in plan view.
  • the ground wiring portions 505B and 505C are formed in different layers from the control wiring portions 503A to 503F, it is possible to avoid interference between the control wiring of each transistor and the ground wiring in a limited wiring space. it can. *
  • Output wiring portions 505D to 505F are electrically connected to connection wiring portions 503G to 503I through vias 504A, respectively.
  • the output wiring portions 505D to 505F are electrically connected to the input terminals of the respective phases of the motor 60. *
  • the input voltage application wiring portion 505G is electrically connected to the common connection wiring portion 503J through the via 504A.
  • the input voltage Vin is applied to the input voltage application wiring portion 505G by mounting the semiconductor package device 50.
  • the input voltage Vin is, for example, 200V to 300V. *
  • the output wiring portions 505D to 505F overlap with the common connection wiring portion 503J in plan view. However, since the output wiring portions 505D to 505F are formed in different layers from the common connection wiring portion 503J, it is possible to avoid interference between the output wiring and the input voltage application wiring in a limited wiring space. *
  • the circular wiring portion 505H is electrically connected to the connection terminal portion Tc via the via 504A, the wiring portion 503K, and another via 504A.
  • the connection terminal portion Tc is disposed at a position corresponding to each circular wiring portion 505H.
  • the connection terminal portion Tc is included in the second wiring pattern portion 505.
  • the circular wiring portion 505H is connected to the circular wiring portion 503K via the via 504A, and the circular wiring portion 505H and the connection terminal portion Tc are connected to each other by a wiring (not shown) in the second wiring pattern portion 505. Also good. *
  • the semiconductor package device 50 is completed by forming the resist layer 506 as in the step shown in FIG. 2G.
  • Input terminals Tin1 and Tin2 are formed at the ends of the input voltage application wiring portion 505G.
  • Output terminals Tout1 to Tout3 are formed at the end portions of the output wiring portions 505D to 505F, respectively.
  • Ground terminals Tg1 to Tg3 are formed at respective end portions of the ground wiring portions 505A to 505C.
  • the resist layer 506 is formed so that the input terminals Tin1, Tin2, Tout1 to Tout3, Tg1 to Tg3, and the connection terminal portion Tc are exposed downward. *
  • connection terminal portion Tc is on one side of the first side of the rectangular outer edge of the semiconductor package device 50, one side of the second side opposite to the first side, and a third side sandwiched between the first side and the second side. Arranged along.
  • the input terminal Tin1 is disposed along the other side of the second side.
  • the output terminals Tout1 to Tout3 and the input terminal Tin2 are arranged along the fourth side opposite to the third side.
  • the output terminals Tout1 to Tout3 and the input terminals Tin1 and Tin2 are adjacent to each other to form the first group G1.
  • the connection terminal portions Tc are adjacent to each other to form the second group G2. Since the first group G1 and the second group G2 are arranged at positions far apart from each other, the high voltage connected to the output terminals Tout1 to Tout3 and the input terminals Tin1 and Tin2 when the semiconductor package device 50 is mounted on the printed board. The insulation between the system wiring and the low voltage system wiring connected to the connection terminal portion Tc can be ensured.
  • the third group G3 including the ground terminals Tg1 to Tg3 is arranged along the first side as in the second group G2, but the third group G3 and the second group G2 are arranged apart from each other. Therefore, it is possible to ensure insulation between the ground wiring connected to the ground terminals Tg1 to Tg3 and the wiring connected to the connection terminal portion Tc when the semiconductor package device 50 is mounted.
  • the semiconductor package device (50) of the present embodiment is in contact with the wiring layer (5001) having the insulating portion (5001A) and the conductive portion (5001B), and the upper surface of the wiring layer. And a plurality of semiconductor packages (1 to 7) disposed in a row, and a resin portion (501) for sealing the semiconductor package.
  • wiring can be performed by forming a conductive portion by plating the insulating portion, and wire bonding is not necessary.
  • the limitation on the number of semiconductor packages to be mounted can be reduced.
  • the insulating portion includes a plurality of insulating layers (502, 504) stacked in the vertical direction, and the conductive portion is a wiring pattern portion (503, 503) disposed on the lower surface of the insulating layer. 505).
  • the freedom degree of wiring can be made high in the limited wiring space.
  • the said structure WHEREIN The resist layer (506) arrange
  • the semiconductor package includes a first package (1) having a microcomputer (1A) and a gate driver (1B), a second package (2) including a first transistor (M1), and the first transistor in series. And a third package (3) including a second transistor (M2) to be connected. Since the required transistor capacity varies depending on the motor to be driven by the semiconductor package device, there are many types of semiconductor package devices to support various motors. It is easy to respond. *
  • the semiconductor package includes a fourth package (4) including a third transistor (M3) and a fifth package (5) including a fourth transistor (M4) connected in series to the third transistor. ), A sixth package (6) including a fifth transistor (M5), and a seventh package (7) including a sixth transistor (M6) connected in series to the fifth transistor.
  • the insulating part includes a first insulating layer (502) and a second insulating layer (504) located below the first insulating layer.
  • the conductive portion is disposed on the lower surface of the first insulating layer, and electrically connects the terminals (10A to 10F) of the first package and the control terminals (2A to 7A) of the second to seventh packages.
  • Control wiring portions (503A to 503F) connected to the second insulation layer, and the current outflow terminals (2B, 4B, 6B) of the second package, the fourth package, and the sixth package. And at least one of the control wiring portions overlaps at least one of the ground wiring portions in a plan view.
  • the conductive portion is disposed on the lower surface of the first insulating layer, and the current outflow terminals (3B, 5B, 7B) of the third, fifth, and seventh packages and the second and second 4.
  • the connection wiring portions (503G to 503I) that electrically connect the current inflow terminals (2C, 4C, 6C) of the sixth package and the lower surface of the first insulating layer are disposed, and the third, third, 5, common connection wiring part (503J) for electrically connecting the current inflow terminals (3C, 5C, 7C) of the seventh package, and the connection wiring part disposed on the lower surface of the second insulating layer,
  • the common connection wiring portion is for each output Overlap in the line portion in plan view.
  • the semiconductor package device for driving a motor including the inverter it is possible to avoid interference between the output wiring and the input voltage application wiring by forming the insulating layer with two layers in a limited wiring space.
  • the conductive portion includes the current outflow terminals (3B, 5B, and 7B) of the third, fifth, and seventh packages and the current inflow terminals of the second, fourth, and sixth packages ( 2C, 4C, and 6C), each output wiring portion (505D to 505F) electrically connected to each connection point, and each current inflow terminal (3C, 5C, 7C) and a voltage application wiring portion (505G) electrically connected to each terminal, and each connection terminal portion (Tc) for electrical connection to each terminal (10) of the first package.
  • Each end (Tout1 to Tout3, Tin1, Tin2) of the output wiring section and the voltage applying wiring section is located on the outer edge of the wiring layer and constitutes the first group (G1) adjacent to each other.
  • Each of the connection terminal portions is located on the outer edge of the wiring layer and is adjacent to each other to form a second group (G2), and the first group and the second group are located at positions separated from each other.
  • each end of the output wiring portion and the voltage applying wiring portion which is a high voltage system and each connection terminal portion which is a low voltage system are different from each other. Since the group is formed and located at positions separated from each other, insulation between the high voltage system wiring and the low voltage system wiring can be ensured in the substrate on which the semiconductor package device is mounted.
  • the manufacturing method of the semiconductor package device (50) of the present embodiment includes a first step of disposing a plurality of semiconductor packages (1-7) on an adhesive (51) disposed on a support substrate (52). A second step of sealing the semiconductor package with a resin (501); a third step of removing the support substrate and the adhesive from the resin; and an insulating layer (502, 504) on the lower surface side of the resin. Forming a via (502A, 504A) in the insulating layer, and forming a wiring pattern portion (503, 505) by plating on the via and the lower surface of the insulating layer at least once. And including. *
  • the semiconductor package device has an inverter composed of six transistors, but the semiconductor package device for driving a motor is not limited to having an inverter, but only two transistors connected in series. It is good also as a structure to have.
  • the use of the semiconductor package device is not limited to motor driving.
  • a package including components such as a chip capacitor may be included.
  • the present invention can be suitably used for a semiconductor package device for driving a motor, for example.
  • 50 Semiconductor package device, 60 ... Motor, 1 ... 1st package, 2 ... 2nd package, 3 ... 3rd package, 4 ... 4th package, 5 ... 5th package, 6 ... 6th package, 7 ... 7th package, 1A ... microcomputer, 1B ... gate driver, M1 ... 1st transistor, M2 ... 2nd transistor, M3 ... 3rd transistor, M4 ... 4th transistor, M5 ... 5th transistor, M6 ... 6th transistor, IV ... Inverter, P1-P3 ... Connection node, 51 ... Support substrate, 52... Adhesive, 501... Resin part, 502... First insulating layer, 502 A... Via, 503...
  • First wiring pattern part 504. 504A ... via 505 ..Second wiring pattern part, 506... Resist layer, 5001 .. wiring layer, 5001A .. insulating part, 5001B .. conductor part, 10 .. terminal, 10A to 10F. Terminals, 2A-7A ... Control terminals, 2B-7B ... Current outflow terminals, 2C-7C ... Current inflow terminals, 503A-503F ... Control wiring, 503G-503I ...
  • Connection wiring 503J Common connection wiring section
  • 503K Wiring section
  • 505A to 505C Ground wiring section
  • 505D to 505F Output wiring section
  • 505G Input voltage applying wiring section
  • 505H Circular wiring section
  • Tg1 to Tg3 Ground terminal
  • Tin1, Tin2 Input terminal
  • Tout1 to Tout3 Output terminal
  • Tc Connection terminal section
  • G1 First group , 2,... The second group, G3 ⁇ third group

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Inverter Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

L'invention concerne un dispositif de boîtier semi-conducteur comprenant : une couche de câblage qui a une section isolante et une section conductrice; une pluralité de boîtiers semi-conducteurs disposés en contact avec la surface supérieure de la couche de câblage ; et une section de résine pour sceller les boîtiers semi-conducteurs.
PCT/JP2018/008270 2017-03-29 2018-03-05 Dispositif de boîtier semi-conducteur et son procédé de fabrication Ceased WO2018180235A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2019509079A JPWO2018180235A1 (ja) 2017-03-29 2018-03-05 半導体パッケージ装置、およびその製造方法
CN201880021991.8A CN110462825B (zh) 2017-03-29 2018-03-05 半导体封装装置及其制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017064909 2017-03-29
JP2017-064909 2017-03-29

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WO2018180235A1 true WO2018180235A1 (fr) 2018-10-04

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CN (1) CN110462825B (fr)
WO (1) WO2018180235A1 (fr)

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