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WO2018166650A1 - Procédé pour faire fonctionner un premier convertisseur et un deuxième convertisseur - Google Patents

Procédé pour faire fonctionner un premier convertisseur et un deuxième convertisseur Download PDF

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Publication number
WO2018166650A1
WO2018166650A1 PCT/EP2018/000090 EP2018000090W WO2018166650A1 WO 2018166650 A1 WO2018166650 A1 WO 2018166650A1 EP 2018000090 W EP2018000090 W EP 2018000090W WO 2018166650 A1 WO2018166650 A1 WO 2018166650A1
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WO
WIPO (PCT)
Prior art keywords
converter
phase
switching times
inverter
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2018/000090
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German (de)
English (en)
Inventor
Ricardo RICHTER
Stefan Zeh
Martin Weinmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Diehl AKO Stiftung and Co KG
Original Assignee
Diehl AKO Stiftung and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Diehl AKO Stiftung and Co KG filed Critical Diehl AKO Stiftung and Co KG
Priority to EP18710758.6A priority Critical patent/EP3596818A1/fr
Publication of WO2018166650A1 publication Critical patent/WO2018166650A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/539—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
    • H02M7/5395—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters
    • H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P5/00—Arrangements specially adapted for regulating or controlling the speed or torque of two or more electric motors
    • H02P5/74—Arrangements specially adapted for regulating or controlling the speed or torque of two or more electric motors controlling two or more AC dynamo-electric motors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/008—Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators

Definitions

  • the invention relates to a method for operating a first converter and a second converter, each having a bridge circuit with switchable semiconductor switches.
  • the invention further relates to a device with a first converter and with a second converter.
  • US 7,584,009 B2 describes the parallel operation of single-phase converters for audio applications, where the audio inverters are controlled by various digital controllers to increase the audio quality. Synchronization is achieved by supplying all digital controllers with the same CPU clock line. In addition, a control line is used, on which the master transmits synchronization pulses. However, this synchronization pulse only has the purpose that the slaves can check their synchronicity and can switch off if necessary. The problem with this design is that the inverters interfere with each other. From EP 1 995 863 A2 converters are known, which are connected in parallel to a three-phase network. In order to keep the harmonic voltage distortions in the connected three-phase network low, the PWM periods are synchronized and operated out of phase. Synchronization occurs when a master sends out pulses and the slaves adjust their PWM carrier.
  • DE 10 2005 052 702 B4 describes a hardware circuit which can delay PWM signals.
  • the invention is based on the object, a particularly suitable method for operating a first inverter and a second converter, each having a bridge circuit with switchable semiconductor switches, and a particularly suitable device with a driven by a first inverter first load and one by means of a second Specify inverter driven second load, advantageously a disturbance of the inverter is reduced and advantageously avoided.
  • the method is used to operate a first converter and a second converter.
  • the first converter in particular serves the energization of a first load and the second converter of the energization of a second load.
  • the first and the second load are different and, for example, each an electric motor, in particular a brushless electric motor, such as a brushless DC motor (BLDC).
  • the electric motors are synchronous motors.
  • at least one of the electric motors is an asynchronous motor.
  • Each inverter has a number of switchable semiconductors, which are each connected together to form a bridge circuit.
  • Bridge circuits are each arranged in particular between an upper and a lower potential, wherein the two potentials are electrical potentials between which, for example, an electrical voltage between 100 volts and 2,000 volts, between 200 volts and 800 volts and for example equal to 500 volts is applied.
  • Each bridge circuit preferably comprises a number of bridge branches, which are connected in parallel between the two potentials.
  • each of the Bridge branches in each case two of the switchable semiconductor switches, which are suitably connected in series.
  • each bridge circuit expediently has three half-bridges (bridge branches), which each comprise two of the switchable semiconductor switches.
  • the switchable semiconductor switches are expediently power semiconductor switches, which are in particular provided and configured to switch an electrical voltage greater than 200 volts, 300 volts, 400 volts, 500 volts or 1,000 volts.
  • the semiconductor switches are provided and configured to carry an electrical current greater than 2 amperes, 5 amps or 10 amps.
  • the switchable semiconductor switches are, for example, field-effect transistors, in particular MOSFETs, JFETs, GTOs or IGBTs.
  • a diode in particular a free-wheeling diode, is connected in parallel with each of the switchable semiconductor switches.
  • each inverter has six such switchable semiconductor switches, and the switchable semiconductor switches are each connected to a B6 bridge, which thus has three bridge arms.
  • the inverters are designed as inverters, by means of which a three-phase alternating current is expediently generated during operation.
  • the first converter and the second converter expediently each have a control, by means of which the respective switchable semiconductor switches are controlled.
  • the controls are expediently signal-technically and / or electrically coupled to the respective switchable semiconductor switches.
  • the method is for operating a device having the two inverters.
  • the device itself is for example a heat pump.
  • the method provides that the switchable semiconductor switches of the first inverter are driven to first switching times.
  • Each of the switchable semiconductor switches of the first converter is assigned at least a portion of the first switching times.
  • the switching state of the respectively associated switchable semiconductor switch is changed and this thus offset from an electrically conductive to an electrically non-conductive or from an electrically non-conductive to an electrically conductive state.
  • the switchable semiconductor switches of the second inverter are driven to second switching times.
  • each of the switchable semiconductor switches is assigned in each case at least a number of the second switching times.
  • the first and second switching times are determined in particular based on an operating point, wherein the operating point for the first inverter, for example, is different from the operating point of the second inverter, so that the first switching times differ from the second switching points.
  • the first switching times and the second switching times are determined such that repeatedly occurring time windows are formed within which neither first switching times nor second switching times are present.
  • the time windows are in particular time corridors. Suitably, the time windows occur periodically repeatedly.
  • the two inverters are driven in such a way that overlap the time windows occurring at least partially in time.
  • the method is used for the operation of other converters, wherein here, the switching points of the other inverter are set so that they are outside the time window.
  • Each switching operation of the switchable semiconductor switches generates electromagnetic waves, which couple to any lines, any electronics and / or control of the respective inverter and the other inverter and can lead to significant disturbances there. Switching disturbances are observed from one inverter to the other. Due to the method, the turn-on time for the upper and lower switchable semiconductor switches of the respective bridge circuit is limited, which is why the temporal corridors (time window) arise in which there are no switching faults. As a result, a disturbance of the inverter is avoided or at least reduced in the temporal corridors.
  • one or more measured values are recorded during the time window.
  • the detection of the measured value or of the multiple measured values takes place within each of the occurring time windows, and for example at least one assigned measured value is detected in the first converter and in the second converter, so that two or more measured values are recorded after the time window has expired.
  • the same measured value is in turn recorded in the temporally subsequent time window.
  • other readings are collected. Due to the detection of the measured values, measurement data are therefore available, by means of which the state of the respective converter can be determined, for example, and / or which serve to drive the inverters, and in particular to generate the (first and / or second) switching times.
  • the mutual influencing of the converters due to the switching operations of the switchable semiconductor switches is particularly disturbing if the measured values are recorded in the same way.
  • analogue measurement Signals falsified due to mutual interference Due to the time window thus adulteration is avoided.
  • the measured value is, for example, an electrical current flow, so that during the time window the electric current flow is detected. In this way, a power of the respective converter is comparatively easily determinable, and the electric current flow can be detected unadulterated during the time window.
  • measurement data are acquired at least in part of the time windows.
  • each of the inverters comprises a number of terminals, the number being conveniently equal to the number of electrical phases created by the respective inverter.
  • each terminal is electrically contacted with a bridge branch of the respective bridge circuit.
  • the current load is supplied by means of the connection terminals, which are electrically connected to the respective load.
  • the first and / or second switching times are preferably created such that during the time window no electrical potential difference between the terminals of the first inverter is applied. Also, there is no electrical potential difference between the terminals of the second inverter during the time window.
  • the electrical potential of the electrical phases of each inverter is the same.
  • the electrical potential of the terminals of the first inverter is equal to the electrical potential of the terminals of the second inverter.
  • all electrical current phases of the bridge circuit are clamped to the lower (electrical) potential (the negative pole of a possible voltage intermediate circuit).
  • the same voltage intermediate circuit is assigned to the first converter and the second converter, or each of the two converters is assigned a different voltage intermediate circuit in each case.
  • an electric current flow and / or an electrical voltage generated by the converter is generated by means of space vector modulation.
  • space vector modulation is preferably used, wherein the converters are expediently 3-phase (current phase).
  • control is done by means of space vector modulation.
  • space vector modulation there are a total of 8 switching states for the three electrical current phases, which can each be connected to the upper or the lower potential.
  • Those switching states which establish a connection of the upper potential via the respective load, in particular the motor, to the lower potential are called in particular active switching states.
  • the two switching states which connect all current phases at the same potential are referred to as free-wheeling state, also referred to as zero vector.
  • the zero vector is applied in the time windows.
  • the measured value is detected in the zero vector, where preferably all terminals and thus also the current phases of the bridge circuits are clamped to the negative pole (lower potential) of the potential voltage intermediate circuit.
  • the first switching times or the second switching times suitably both the first switching times and the second switching times, by means of pulse width modulation (PWM) created.
  • PWM pulse width modulation
  • the first converter and the second converter are operated with pulse width modulation.
  • the first converter is assigned a first frequency and a first phase and the second converter has a second frequency and a second phase.
  • the first and second frequencies are suitably between 4 kHz and a few hundred kHz, such as 800 kHz, 700 kHz, 600 kHz, 500 kHz, 400 kHz, 300 kHz or 200 kHz.
  • the first frequency and / or the second frequency is between 4 kHz and 100 kHz.
  • the first frequency and / or the second frequency is 8 kHz. Due to the frequencies, periods of pulse width modulation are defined.
  • the first phase or the second phase determines the respective time at which the periods corresponding to the respective frequency start, and is determined, for example, with respect to an absolute time or with respect to a relative time, such as the switching on of one of the two converters.
  • the first inverter and the second inverter assigned to different PWM carrier signals, which expediently each have the associated frequency.
  • the position of the PWM carrier signals in particular is determined by means of the respective phase (first phase and / or second phase).
  • the PWM carrier signals of the first and the second converter are similar, for example, a sawtooth function, wherein the PWM carrier signals of the two converters expediently only due to the respective frequency and / or the respective phase se differentiate.
  • a centered or an asymmetric pulse width modulation is used.
  • the switching times of the respective switchable semiconductor switches are created by means of pulse width modulation.
  • the first converter or the second converter, expediently both converters are digitally controlled in pulse-width modulation, wherein, for example, one controller is assigned to each converter, so that a different digital controller is used as controller for each converter.
  • the bridge circuits are operated with the pulse width modulation (PWM).
  • PWM pulse width modulation
  • the output terminals (current phases) of each inverter are electrically connected via the switchable semiconductor switches of the respective half-bridge either to the upper or to the lower potential (DC link potential).
  • the change between the potentials takes place, for example, periodically with a carrier frequency (first frequency, second frequency) from 4 kHz to a few 100 kHz.
  • the pulse width - the duration of the dwell time at the upper potential (DC link potential) - varies, in particular as a function of a voltage requirement. In this way, the resulting average electrical voltage per period is adjusted and by modulation of the pulse width in each phase, the current size is suitably regulated.
  • Each inverter preferably comprises a phase counter for generating a PWM carrier signal, which is reset after a PWM period and repeats the process cyclically.
  • the phase counter is reset at the first and second frequencies, respectively.
  • the switching times (on and off timing) of each switchable semiconductor switch are placed symmetrically about the middle of each period (period center). In this way, for example, the turn-on of one of the switchable semiconductor switch (upper semiconductor switch) is determined, and preferably the connection of the associated terminal to the upper potential. The rest of the time, while this switchable semiconductor switch is turned off, the further switchable semiconductor switch of the same bridge branch (lower semiconductor switch) is driven to connect the terminal and thus the current phase with the low lower potential.
  • the first and the second inverter pulse width modulated inverter each with the bridge circuit, wherein the pulse width of each Inverter is controlled such that the time window (temporal corridor) arise in which no semiconductor switch of the bridge circuits is switched. If several inverters are present, they also have additional frequencies and further phases.
  • the time windows are expediently determined on the basis of the first phase and the first frequency.
  • the time windows thus periodically occur at the first frequency, an integer multiple of the first frequency, or a rational fraction of the first frequency.
  • an end or a beginning of the time window is selected such that it corresponds to the end or the beginning of each of the periods defined by means of the first phase and the first frequency.
  • the time window exists in the middle of each period and thus corresponds to the beginning of the first period plus half of the period defined by means of the first frequency.
  • each period which is defined by means of the first frequency
  • a further time window which, for example, is associated with the beginning and / or the end of the respective period.
  • the time window is symmetrical with respect to the mid-point of the period and / or the beginning or end of each period defined by the first frequency. Due to the determination of the time window based on the first phase and the first frequency, the time windows are known in advance. Therefore, especially when a measured value is detected, operation is simplified.
  • a power request to the first inverter or to the second inverter is determined.
  • the power requirement is determined for both the first inverter and the second inverter, for example, with different power requirements to the two inverters.
  • the first switching times and the second switching times are determined. Those first switching times and those second switching times that are outside the time windows are used unchanged as first or second switching times. For example, those first switching times and those second switching times that are within at least one of the time slots are discarded in one alternative. Conveniently, the temporally following switching time is also discarded, so that discarded at each rejection two switching times and thus ignored. As a result- of which two operations of one of the switchable semiconductor switches are not performed so that the time slots are present.
  • those first switching times and those second switching times that are within at least one of the time windows are shifted to a limit of the time window within which the first or second switching times were originally. These shifted first and second switching times are now used as the first and second switching times.
  • the totality of any shifted and non-shifted switching times forms the first and second switching times. Due to the shift or discarding the output by means of the two inverter power does not correspond to the power requirement, which is why provided by the two converters either a slightly too large or a slightly too small power. However, it is ensured in this case that during the time window no first and second switching times are present, so that any detection of a measured value is not disturbed.
  • the active switching states are suitably limited in time or lengthened and / or the freewheeling states, if necessary, preferably extended or shortened, in particular for the creation of the time windows. If the switch-on time of a switchable semiconductor switch undershoots or exceeds the limit of one of the time windows, then either the switch-on time is limited to the corridor limit (limitation of the time window) or the switchable semiconductor switch, in particular one of the current phases, lingers at the original / closest potential for the entire cycle duration ,
  • the carrier frequencies of the pulse width modulation of the two inverters differ by a whole multiple, wherein the first and the second frequency are each a carrier frequency.
  • the lower carrier frequency is for example between 4 kHz and 10 kHz and suitably between 4 kHz and 8 kHz.
  • the higher carrier frequency, ie the second frequency is for example between 8 kHz and 20 kHz and expediently between 8 kHz and 16 kHz.
  • the second free frequency twice as high as the first frequency. If a plurality of inverters are present, all frequencies are expediently integer multiples of the first frequency, so that the first frequency represents the lowest frequency of the device comprising the inverters.
  • the two inverters are operated at different PWM carrier frequencies (first frequency, second frequency).
  • the second converter is operated with a PWM carrier frequency (the second frequency), which is an integer multiple of the first frequency.
  • the first inverter is for operating a high power motor and has the first frequency (lowest carrier frequency) of 8 kHz.
  • a lower power motor is operated at the second frequency of 16 kHz.
  • the time slots with a frequency of 16 kHz result for both frequencies, which enables a sampling of the possible measured values recorded with a sampling rate of 16 kHz.
  • the time slots occur at a frequency of 8 kHz, and the sampling of the acquired measured values is filtered accordingly, so that the measured values recorded within the time windows are weighted more heavily.
  • the second phase is shifted such that the first phase corresponds to the second phase.
  • the distance of the second phase to the first phase, if any, is reduced so that it is converted to zero (0), and therefore, after the displacement, the distance of the two phases from each other is zero (0).
  • the time window is also determined based on the second phase and the second frequency and occurs only at certain times, for example, at the beginning or end of each period with the second frequency. A difference between the two phases occurs, for example, at a start of the inverter / the method, unless the two pulse width modulations are started simultaneously.
  • phase offset occurs if a fault occurs in one of the two inverters during operation, such as the PWM carrier signal.
  • a period is changed, in particular one of the periods of the second converter.
  • one of the periods is lengthened or shortened, so that the distance between the two phases relative to one another is zero (0).
  • Particularly preferred is the shift or adaptation of the second phase. In other words, a shift of the second phase takes place at most around a certain section. In other words, one of the periods of the second inverter is only shortened or shortened by the section. If, following this, the second phase still does not correspond to the first phase, a new shift takes place.
  • the shift is carried out at several periods in succession, so that the second phase of the first phase corresponds to the number of shifts. In this way, there is no abrupt transition during the displacement of the second phase, so that a load driven by means of the second converter is loaded comparatively little mechanically.
  • a synchronization pulse is emitted by the first converter via a synchronization line connecting the first converter with at least one further converter, by means of which a switch-free time window is formed in a predetermined time relation in the at least one further converter.
  • the first and the second inverter are interconnected, suitably by means of a BUS system.
  • the first converter is used as a master converter and the second converter as a slave converter.
  • the pulse width modulation of the slave converter that is to say of the second converter
  • the master converter that is to say of the first converter.
  • the second phase is shifted such that the first phase corresponds to the second phase.
  • a synchronization line is used for this, by means of which the two converters are connected to each other by signal technology.
  • the synchronization line is in particular a temporary and / or functional component of the possible BUS system.
  • phase difference of the pulse width modulation of the further slave converters for pulse width modulation of the master inverter is measured and the phases of the further converters are adapted such that they also correspond to the first phase.
  • the period duration of the pulse width modulation of the respective bridge circuits is synchronized with the pulse width modulation of the master bridge.
  • Inverter first inverter set, in particular adjusted.
  • the pulse width of the second converter and of any further converter is controlled, for example regulated, by limiting and synchronizing the pulse width of the second and any further converters.
  • the first inverter is the master inverter and the second inverter is a slave inverter, whereby the slave
  • the pulse width modulation of the slave inverter is synchronized to the pulse width modulation of the master inverter, preferably via the synchronization line.
  • the phase difference of the pulse width modulation for pulse width modulation of the master inverter is measured on each additional (slave) converter.
  • Bridge circuits adjusted to a synchronization with the master pulse width modulation.
  • the device is, for example, a heat pump and has a first load which is driven by means of a first converter.
  • the device comprises a second load which is driven by means of a second converter.
  • the first load or load is suitably a brushless motor, the first load being suitably mechanically separated from the second load.
  • the loads are, for example, brushless electric motors, in particular synchronous or asynchronous motors.
  • the inverters are inverters.
  • Each converter has, for example, a control unit (control), which is in particular a digital controller.
  • Each inverter has a bridge circuit with switchable semiconductors.
  • each bridge circuit thus has three bridge branches (half bridges), each of which comprises two of the switchable semiconductor switches.
  • a current phase is preferably conducted against a connection terminal of the respective converter.
  • the converters are operated in accordance with a method in which the switchable semiconductor switches of the first converter are driven at first switching times, and in which the switchable semiconductor switches of the second converter are driven at second switching times.
  • the first switching times and the second switching times are set such that recurring time windows are formed, within which neither first switching times nor second switching times are present.
  • the time windows occur periodically.
  • includes the device is a control unit, for example a microcontroller, which is suitable, in particular provided and configured to carry out the method.
  • both converters are controlled by means of a common digital control.
  • the possible pulse width modulations of the current phases can be easily synchronized, since all pulse width modulations are connected to the same clock line and the possible phase counters can be started simultaneously.
  • a realization of the time windows is simplified, and any detection of measured values, in particular a scanning process for the electrical currents, can take place within the time windows.
  • At least two different digital controllers are preferably used for the control of the bridge circuits.
  • different is meant, in particular, that any pulse width modulations, in particular any PWM generators, of the different digital controllers do not per se know the phase position (phase) of the other digital controller.
  • these at least two different digital controllers also each have their own clock in the form of a quartz oscillator.
  • the pulse width modulations are independent of each other.
  • the pulse width modulations have no common clock line, and pulse width modulation of the respective inverter start at different times.
  • the pulse width modulations of the two inverters are preferably synchronized, and the respective pulse widths of the two inverters are particularly limited so that the time windows are formed.
  • the switching state of no switchable semiconductor switch is changed. Any sampling of the measured values takes place during one of the time windows, wherein the sampled value is, for example, an analog value which is converted into a digital value by means of an AD conversion.
  • a measured value is detected for each current phase.
  • both inverters are guided against a common intermediate circuit (voltage intermediate circuit), which has two different potentials, namely a lower and an upper potential.
  • the potential difference between the two potentials is suitably between 100 volts and 1,000 volts.
  • the inverters preferably the bridge circuits of the inverters, are fed from two different intermediate circuits (DC intermediate circuits).
  • the intermediate circuit or the intermediate circuits are each a component of the device.
  • the intermediate circuit is fed by means of a rectifier.
  • the inverters are digitally controlled inverters.
  • the two bridge circuits are electrically connected to the same DC voltage intermediate circuit.
  • the bridge circuits are fed from different DC voltage intermediate circuits.
  • one of the inverters associated DC link is fed by means of an active front end (PFC), and the other inverter is associated with a further DC link, which in turn is fed without active PFC from a (utility) network.
  • PFC active front end
  • the first inverter is connected to at least one other inverter via a synchronization line.
  • the invention further relates to the parallel operation of at least two brushless motors such.
  • Each motor is powered by one inverter.
  • the inverters are, for example, digitally controlled (drive)
  • Inverter As a “digitally controlled (drive) inverter” in particular a power electronics in the form of a self-commutated six-pulse bridge circuit (converter bridge) with six switchable semiconductor switches, such as power transistors, and its digital control understood.
  • the bridge circuits are supplied with a DC electrical voltage from a DC intermediate circuit and supply at the output terminals a three-phase current (current phases) for the connected motor.
  • the control of the switchable semiconductor switch (power transistors) is advantageously carried out by means of a digital control unit such.
  • a digital control unit such as a microcontroller or digital signal processor.
  • the feeding DC voltage of the inverter is preferably generated from the AC voltage network by means of a mains rectifier (rectifier).
  • 1 is a simplified equivalent circuit diagram of a device with a first converter and with a second converter
  • Fig. 5-7 simplifies the creation of the switching times
  • Fig. 8 shows a shift of a second phase of the second inverter.
  • FIG. 1 shows a simplified equivalent circuit diagram of a device 2 with a first converter 4 and a second converter 6.
  • the first converter 4 By means of the first converter 4, a first load 8 and by means of the second converter 6, a second load 10 is driven.
  • the first load 8 and the second load 10 are each three-phase brushless synchronous motors, and the first inverter 4 is the same, preferably identical, to the second inverter 6.
  • the first inverter 4 has three first terminals 12, which are electrically connected to the first load eighth are contacted.
  • One of the connection terminals 12 is assigned to a first current phase 13a, a further one of the connection terminals 12 to a second current phase 13b and the remaining terminal 12 to a third current phase 13c.
  • the first inverter 4 is three-phase.
  • each one is the terminals 12 each contacted with a bridge branch 14 of a bridge circuit 16.
  • each of the bridge branches 14 has two switchable semiconductor switches 18 in the form of MOSFETs.
  • the bridge circuit 16 is a switching circuit, and between the series-connected switchable semiconductor switches 18 of each of the bridge branches 14 is a contact point with the terminals 12th
  • the bridge branches 18 are connected between an upper potential 20 and a lower potential 22, which are each electrical potentials.
  • an upper potential 20 is connected to a lower potential 22.
  • the switchable semiconductor switch 18 is connected to a lower potential 22.
  • the terminals 12 against the upper potential 20 feasible.
  • the terminals 12 are set to the upper potential 20.
  • the lower semiconductor switches 18, that is, the remaining semiconductor switches 18 of the first inverter 14 are actuated, and the terminals 12 are electrically contacted with the lower potential 22, so that the terminals 12 and the respective terminal 12 has the lower potential 22.
  • the upper potential 20 and the lower potential 22 are conducted against a DC link capacitor 24, by means of which the potential difference between the upper and the lower potential 20, 22 in the amount of, for example, 500 volts is provided.
  • the intermediate circuit capacitor 24 itself is a component of a (DC) intermediate circuit 26, which is fed by means of a rectifier, not shown, which is coupled to a utility network.
  • the first converter 4 has a control unit 28, by means of which the semiconductor switches 18 are actuated as a function of requirements.
  • the control unit 18 is electrically contacted in a manner not shown with the gates of the switchable semiconductor switch 18.
  • the second inverter 6 is the same principle, preferably identical, to the first inverter 4 and thus also has the bridge circuit 16 with the semiconductor switches 18 and the terminals 12 and the control unit 28.
  • the control unit 28 of the first converter 4 is signal-connected by means of a synchronization line (SYNC line) 30 to the control unit 28 of the second converter 6.
  • SYNC line synchronization line
  • the lower potential 22 of the second inverter 6 is directed against the lower potential 22 of the first converter 4, and the upper potential 20 of the second converter 6 is directed against the upper potential 20 of the first converter 4, so that the second converter 6 is also electrically connected to the intermediate circuit capacitor 24 connected is.
  • the two inverters 4, 6 are guided against the common (direct current) intermediate circuit 26.
  • the device 2 has a number of other inverters 32, which are connected by means of the synchronization line 30 with the first inverter 4 and the second inverter 6 signal technology.
  • the other inverters 32 are also of the same principle, preferably of identical construction, to the first and the second converter 4, 6 and the synchronization line 30 is a component of a BUS system, by means of which all converters 4, 6, 32 are connected to each other by signal technology.
  • the first inverter 4 forms a master inverter and the second inverter 6 and the other inverter 32 form slave inverters.
  • the setting or assignment as a master inverter or slave inverter by means of programming the respective control unit 28. If only the first and the second inverter 4, 6 are present, they are also interconnected as a bus system, and the first inverter 4 is the master inverter, and the second inverter 6 is the slave inverter.
  • FIG. 3 shows a method 34 for operating the device 2.
  • a power demand 38 to the first inverter 4 and to the second inverter 6 is determined.
  • the power requirement 38 corresponds to the power by means of which the respective load 8, 10 is to be operated.
  • the power demand 38 varies over time and / or the power demand 8 to the first inverter 4 is different from the power demand 38 to the second inverter.
  • first switching times 42 are determined for the switchable semiconductor switches 18 of the first converter 4 and second switching times 44 for the switchable semiconductor switches 18 of the second converter 6, as shown in FIG. 4.
  • the switching times 42, 44 are each assigned to one of the switchable semiconductor switches 18 of the respective converter 4, 6, and at the respective switching times 42, 44 by means of the control unit 28 of the respective half conductor switch 18 is actuated, so that it is set from the electrically conductive to the electrically non-conductive state or from the electrically non-conductive to the electrically conductive state.
  • the first switching times 42 are created by means of pulse width modulation, wherein the first inverter 4 is assigned a first frequency 46 and a first phase 48. On the basis of the first frequency 46, a period 50 is determined, and based on the first phase 48 it is determined at which absolute or relative time the respective periods 50 start.
  • a phase counter 52 is counted, which is set to an initial value at the beginning of the period 50 and continuously counted up to the end of the period 50.
  • each of the periods 50 has a period midpoint 54 that characterizes the midpoint of each of the periods 50.
  • the period centers 54 also occur at the first frequency 46.
  • the first switching times 42 of each of the periods 50 are arranged symmetrically in time about the period center point 54 of the respective period 50.
  • the upper semiconductor switches 18, ie those connected between the upper potential 20 and the terminals 12 are in the electrically non-conducting state, so that the first, second and third current phases 13a, 13b, 13c the lower potential 22 has.
  • the actuation of the two takes place
  • time windows 56 are formed, within which no first switching times 42 are present, namely the period center 54 and the beginning or the end of each of the periods 50th
  • the time window 56 based on the period center 54 and / or the beginning of the period or which in turn are determined based on the first phase 48 and the first frequency 46. Therefore, the time slots 56 are determined based on the first phase 48 and the first frequency 46.
  • the second switching times 44 are also created in the same manner.
  • the second switching times 44 are also created by means of pulse width modulation, the second switching times 44 in turn being arranged symmetrically with respect to each of the period centers 54 of each of the periods 50 of the second converter 6. In other words, it is again a centered PWM method.
  • the second inverter 6, a second frequency 58 and a second phase 60 are assigned. Consequently, the duration of the period 50 of the second inverter 6 differs from the period 50 of the first converter 4.
  • the second inverter 6 a second frequency 58 and a second phase 60 are assigned. Consequently,
  • Frequency 58 is 16 kHz and the first frequency 46 is 8 kHz. Thus, an integer multiple, namely twice the first frequency 46 is selected as the second frequency 58.
  • Periods 50 of the second inverter 6 are formed second time windows 62, during which the first phase 13a, the second phase 13b and the third phase 13c of the second inverter 6 either at the lower potential 22 or at the upper potential 20, wherein either all upper Semiconductor switch 18 or all lower semiconductor switches 18 are actuated. Every second of the second time windows 62 is simultaneously one of
  • Time window 56 so that during the time window 56, neither the first switching times 42, nor the second switching times 44 are present.
  • the first switching times 42 and the second switching times 44 are placed such that neither the first switching times 42 nor the second switching times are present during the repeatedly occurring time windows 56.
  • the second phase 60 is such synchronized with the first phase 48, for which the synchronization line 30 is used, so that every other of the periods 50 of the second inverter 6 starts simultaneously with one of the periods 50 of the first inverter 4.
  • Barrier 64 a second barrier 66, a third barrier 68 and a fourth
  • the second barrier 66 and the third barrier 68 as well as the first barrier 64 and the fourth barrier 70 are arranged symmetrically about the period center 54 of the respective period 50 and are the same for all periods 50 of the first converter 4 and of the second converter 6.
  • the first switching times 42 lie between the second barrier 66 and the third barrier 68, for example based on the power requirement 38, the first switching times 42 would be within the time window 56. If this is the case, those switching times which are within the time window 56 are shifted to the limit of the time window 56, ie to the second and third barrier 66, 68, as shown in FIG. In a further alternative, which is shown in FIG. 7, the switching instants 42, which would lie within the time window 56, are rejected, so that there are fewer first switching times 42 for the third current phase 13c. This adjustment of the first switching times is carried out in the same way for the second switching times 44 for the second inverter 6.
  • those switching times 42, 44, not between the first barrier 64 and the second barrier 66 or between the third barrier 68 and the fourth Barrier 70 are located, so are located in particular between the fourth barrier 70 and the first barrier 64, the limitation of the respective time window 56, ie on the first barrier 64 and the fourth barrier 70, moved or rejected. Also, the shift or the throw, provided that the second switching times 44 within the second time window
  • a measured value 76 is recorded during the time window 56.
  • the measured value 76 is an electric current flow which is associated with the respective electrical phase 13a, 13b, 13c and which consequently leads the respective electrical phase 13a, 13b, 13c.
  • a fifth step 78 is carried out, which adjusts the second phase 60 of the first phase 48, so that the second period 50 of the second converter 6 start at the same time as the periods 50 of the first converter 4.
  • the fifth step 78 is executed so that the second phase 60 corresponds to the first phase 48, and the period centers 54 are the same time.
  • the second frequency 58 is equal to the first frequency 46, so that the duration of the periods 50 of the first inverter 4 correspond to the duration of the periods 50 of the second inverter 6.
  • the first phase 48 and the second phase 56 are unequal, so that a phase offset 80 arises between the period centers 54 of the two phase counters 42. As a result, the time slots 56 are not present or shortened.
  • a synchronization pulse 81 is transmitted via the synchronization line by means of the control unit 28 of the first converter 4
  • phase offset 80 in the second inverter 6 which acts as a slave inverter is calculated.
  • Phase offset 80 is fed to a controller 82 of control unit 28, which is, for example, a PI controller.
  • the controller 82 the period 50 of the second inverter is adjusted, which is thus the manipulated variable of the controller 82.
  • the period 50 is shortened or extended by a portion 84, so that the second frequency 58 is changed.
  • the phase counter 52 restarts and the next period 50 starts.
  • phase offset 80 Due to the shortening of the period 50, the phase offset 80 is reduced during the subsequent period 50, and by means of the regulator 82 a shortening of the period is again effected. 50. After repeated execution, the phase offset 80 is thus removed, and the first phase 48 corresponds to the second phase 60.
  • the controller output - the phase offset 80 - is limited to a maximum portion 84 in the positive or negative direction. Due to the section 84, the shift to a tolerance band is limited by the duration of the period 50 of the second converter 6, which is why a change of the second frequency 58, ie the PWM frequency of the second converter 6, is comparatively small. Due to the constant repetition of the shift until the phase offset 80 equals zero (0), the controller 82 oscillates and synchronizes the periods 50 of the two inverters 4, 6. Here, the synchronization to the periods 50 of the first inverter 4, which is the master -Umrichter is.
  • the device 2 has the DC link capacitor 24 and
  • the bridge circuit 16 in the form of a six-pulse bridge circuit.
  • the three terminals 12 are respectively connected in the middle, between the upper and lower semiconductor switches 18, which are power switches.
  • the respective terminal 12 and thus also the associated current phase 13a, 13b, 13c optionally connected to the upper or to the lower potential 20, 22, which are provided by the DC link capacitor 24, and it can be an electric current via the terminals 12 flow.
  • the pulse width modulation (PWM) of the first inverter 4 is a master PWM
  • the pulse width modulation of the second inverter 6 is a slave PWM.
  • the three current phases 13a, 13b, 13c are controlled or created.
  • the on and off timings of the upper (switchable) semiconductor switches 18 are placed symmetrically about the period centers 54.
  • the barriers 64, 66, 68, 70 each form an intersection point with the phase counter 52 and define a minimum and maximum turn-on time of the switchable semiconductor switches 18.
  • the time window 56 arise in which none of the switchable semiconductor switch 18 changes its state.
  • the lower half of the figure shows the same principle for the slave PWM, which has the second frequency 58, which for example is twice the first frequency 46, ie twice the frequency to the master PWM.
  • the pulse width modulation each guarantees two time windows 56 within a period 50.
  • the time windows 56, 62 are possible for both pulse width modulations. Within these time windows 56, 62 correspondingly low-noise measurements can take place.
  • FIG. 2 illustrates the connection of the different control units 28 of the inverters 4, 6, 32, which are digital controllers (microcontrollers), each with its own PWM unit.
  • One of the digital controllers (microcontroller), namely the control unit 28 of the first converter 4, assumes the role of the master, which transmits a synchronization signal, namely the synchronization pulse 81 occurring at the first frequency 46.
  • All other digital controllers (microcontrollers) act as slaves (14) and receive the synchronization signal. All subscribers of this network, among other possible communication circuits, are connected to the common synchronization line 30 (SYNC line) on which the synchronization signal passes from the master to the slaves.
  • SYNC line common synchronization line 30
  • FIG. 8 shows signals of the two inverters 4, 6, whose two control units 28 (digital controllers / microcontrollers) are connected via the synchronization line 30 (SYNC line) as in FIG. 2.
  • the upper PWM of the first inverter 4 operates as a master and transmits the synchronization pulse 81 on the synchronization line 30 at a defined time.
  • the underlying PWM of the second inverter 6 assumes the role of a slave and synchronizes via the Regler82, which slightly changes the second frequency.
  • Phase offset 80 (phase error) and serves as an input to the controller 82.
  • the controller output of the controller 82 then changes the period of the next PWM cycle. If the phase offset 80 has been canceled by the control, the master of the first converter 4 and slave PWM of the second converter and any further converter 32 run synchronously.
  • the time windows 56 represent a time range, a time interval, in which none of the switchable semiconductor switches 18 switches.
  • the switch-on of the respective upper switchable semiconductor switch 18 are limited by the first and fourth barrier 64, 70 and the second and third barrier 66, 68 such that within the time window 56 none of the three bridge arms 14 of each inverter 4, 6, 32 performs a switching operation ,
  • the duty cycle of the affected current phase 3a, 3b, 3c is corrected to the respective, in particular nearest, barrier 64, 66 or to 0% - per after which border is closer. If a duty cycle were to be requested which would fall within the time window 56 formed at the beginning / end of the respective periods, the duty cycle of the affected phase is corrected to the first or fourth limit 64, 70 or to the period limit ( ⁇ 100% or Phase counter start or end value) - whichever is closer.
  • the scanning of the phase currents preferably takes place in the region of the time windows 56.
  • the phase counter 52 is reset to its initial value.
  • the terminals 12 (motor terminals) are clamped to the lower potential 22 (negative pole) of the DC intermediate circuit 26, which can measure the electric currents directly via simple current measuring resistors of the microcontroller.
  • the method 34 describes the synchronization of the PWMs on different inverters 4, 6, 32 by means of their respective control units 28 (digital control units / microcontroller).
  • the method is illustrated in FIGS. 3 to 8.
  • one of the control units 28 acts as a master and transmits the synchronization pulse 81 (SYNC pulse) in each PWM cycle on the synchronization line 30 (SYNC line) provided for this purpose.
  • This synchronization line 30 connects all the controllers 28 to each other, the master can send on this line and all slaves can receive on it.
  • the synchronization pulse 81 is generated directly by the master controller (control unit 28 of the first inverter 4).
  • Each participating PWM control preferably has its own phase counter 52 which linearly resolves the period 50 (PWM carrier period) determined by means of the respective frequency 46, 58 into a few hundred finely granular steps. If the phase counter 52 of the first inverter 4 passes a certain value (SYNC time), in the example shown the period center 54, the synchronization pulse 81 is set to the
  • the SYNC timing of the first inverter 4 - ie the timing of the synchronization pulse 81 (SYNC pulse) within the period 50 of the first inverter 4 (master PWM period / CNTRsync master key) - is the other converters 6, 32 participants due to appropriate initialization known.
  • the second inverter 6 and any further converters 32 hold the state of their own phase counter 52 as CNTR_SlavePhase upon receipt of the synchronization pulse 81.
  • This phase offset 80 is used as input to the controller 82 (eg, PI controller).
  • the output of the controller 82 - the manipulated variable - is the duration of the own period 50.
  • the controller 82 influences the duration of the current period 50, ie the current PWM cycle T PW M (n), or the subsequent period 50 , ie the next PWM cycle TpwM (n + 1):
  • Phase offset 80 CNTRsyncMasterPase - CNTRsiavePhase
  • TPWM (n + 1) TPW - f re g ier (phase offset 80)
  • the output of the regulator is limited by the section 84 to a tolerance band around the nominal period so that the change of the PWM frequency is only very small.
  • the controller 82 oscillates and synchronizes with the master PWM.
  • the susceptibility of the synchronizing Slaves can be improved by attenuating the SYNC line with an RC filter.
  • the present method 34 is used inter alia, the low-interference measurement of analog signals in a plurality of digitally controlled pulse width modulated drive inverters 4, 6, 32 in parallel with at least two different digital control units 28.
  • the pulse widths of the bridge circuits 16 each inverter 4, 6, 32 are limited so that in each inverter 4, 6, 32 cyclically recurring time window 56 (temporal corridor) arise in which no circuit breaker (switchable semiconductor switch 18) switches.
  • the phases 48, 60 of the pulse width modulations of the individual digital controllers 28 are synchronized so that these time slots 56 of all the inverters 4, 6, 32 involved occur simultaneously.
  • the master controller 28 repetitively sends the synchronization pulse 81 (master SYNC signal) to the slaves, and these optionally change their PWM frequency minimally so that their phase 60 coincides with the synchronization pulse 81 (master SYNC signal).
  • the invention relates to a method for operating at least two pulse width modulated converters 4, 6, 32 with a bridge circuit 16 (converter bridge) for controlling motors 8, 10, with at least two controllers 28, wherein the pulse width of each inverter 4, 6, 32 is controlled such that a time window 56 (temporal corridor) arises in which no switchable semiconductor switch 18 (power switch) of the bridge circuit 16 is switched.
  • a time window 56 temporary corridor

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  • Physics & Mathematics (AREA)
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  • Inverter Devices (AREA)

Abstract

L'invention concerne un procédé (34) pour faire fonctionner un premier convertisseur (4) et un deuxième convertisseur (6) comprenant respectivement un montage en pont (16) comportant des interrupteurs à semiconducteurs (18) commutables. Les interrupteurs à semiconducteurs (18) commutables du premier convertisseur (4) sont commandés à de premiers instants de commutation (42), et les interrupteurs à semiconducteurs (18) commutables du deuxième convertisseur (6) sont commandés à de deuxièmes instants de commutation (44). Les premiers instants de commutation (42) et les deuxièmes instants de commutation (44) sont établis de manière que des fenêtres temporelles (56) récurrentes comportant ni des premiers instants de commutation (42), ni des deuxièmes instants de commutation (44) sont générées.
PCT/EP2018/000090 2017-03-14 2018-03-06 Procédé pour faire fonctionner un premier convertisseur et un deuxième convertisseur Ceased WO2018166650A1 (fr)

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DE102017009836.0A DE102017009836A1 (de) 2017-03-14 2017-10-23 Verfahren zum Betrieb eines ersten Umrichters und eines zweiten Umrichters
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DE102023207171A1 (de) * 2023-07-27 2024-09-05 Zf Friedrichshafen Ag Verfahren zur elektrischen Ansteuerung von mindestens zwei als Synchronmaschinen ausgeführten Antriebsmotoren eines Antriebssystems eines Fahrzeugs, und Antriebssystem

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