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WO2018163011A1 - Dispositif à semi-conducteur et système de diffusion - Google Patents

Dispositif à semi-conducteur et système de diffusion Download PDF

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Publication number
WO2018163011A1
WO2018163011A1 PCT/IB2018/051209 IB2018051209W WO2018163011A1 WO 2018163011 A1 WO2018163011 A1 WO 2018163011A1 IB 2018051209 W IB2018051209 W IB 2018051209W WO 2018163011 A1 WO2018163011 A1 WO 2018163011A1
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WIPO (PCT)
Prior art keywords
transistor
circuit
image data
insulator
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2018/051209
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English (en)
Japanese (ja)
Inventor
岡本佑樹
黒川義元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2019503814A priority Critical patent/JP7208889B2/ja
Publication of WO2018163011A1 publication Critical patent/WO2018163011A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/117—Filters, e.g. for pre-processing or post-processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/12—Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
    • H04N19/122—Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/136—Incoming video signal characteristics or properties
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/46—Embedding additional information in the video signal during the compression process
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values

Definitions

  • One embodiment of the present invention relates to a semiconductor device and a broadcasting system.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a processor, an electronic device,
  • the driving method, the manufacturing method, the inspection method, or the system thereof can be given as an example.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • a transistor and a semiconductor circuit are one embodiment of a semiconductor device.
  • a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device.
  • Ultra high definition TV UHDTV
  • CS communication
  • BS broadcasting
  • Non-Patent Document 2 describes a technique related to a chip having a self-learning function using an artificial neural network.
  • Patent Document 1 discloses an invention in which weight data necessary for calculation using an artificial neural network is held by a memory device using a transistor having an oxide semiconductor in a channel formation region.
  • a new standard H.264 is used for video encoding in 8K broadcasting.
  • H.265 MPEG-H HEVC (High Efficiency Video Coding) has been adopted.
  • the resolution (the number of horizontal and vertical pixels) of 8K broadcast video is 7680 ⁇ 4320, which is 4 times 4K (3840 ⁇ 2160) and 16 times 2K (1920 ⁇ 1080). Therefore, it is necessary to handle a large amount of image data in 8K broadcasting. Therefore, it is preferable to compress and transmit image data in a transmission device provided in an artificial satellite or a radio tower. In this case, it is necessary to decompress the received image data in a receiving device provided in a TV or the like.
  • Compressing image data can be performed using an encoder. Further, decompression of the compressed image data can be performed using a decoder.
  • the encoder is provided, for example, in the transmission device, and the decoder is provided, for example, in the reception device.
  • An artificial neural network is a network that can perform calculations that mimic brain functions, and obtains an optimal answer to a desired problem by performing learning (parameter optimization) using a large number of learning data. be able to.
  • the auto encoder uses input image data as teacher data (or a label). That is, it corresponds to unsupervised learning.
  • teacher data or a label
  • One of the features of the auto encoder is that the input image can be compressed inside the artificial neural network and expanded when it is output. Therefore, the auto encoder can be regarded as an artificial neural network having an encoder and a decoder.
  • the circuit configuration of the auto encoder is complicated by increasing the number of dimensions of each intermediate layer of the auto encoder or increasing the depth (number of layers) of the intermediate layer included in the auto encoder, for example, the auto encoder There is a problem that the time required for learning becomes long and the number of parameters necessary for compression and expansion of image data increases.
  • it is an object to provide a novel broadcasting system, a semiconductor device, and an operation method thereof.
  • problems of one embodiment of the present invention are not limited to the problems listed above.
  • the problems listed above do not disturb the existence of other problems.
  • Other issues are issues not mentioned in this section, which are described in the following description. Problems not mentioned in this item can be derived from descriptions of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one embodiment of the present invention solves at least one of the above-described description and other problems. Note that one embodiment of the present invention does not have to solve all of the above listed description and other problems.
  • One embodiment of the present invention includes a first circuit and an encoder, the first circuit and the encoder have a function of receiving first image data, and the first circuit includes a first circuit
  • the first circuit has a function of extracting image data, and the first circuit has a function of generating attribute information representing the attributes of the first image data by extracting the features of the first image data.
  • a second circuit and a group of memories having two or more memory elements and the second circuit has a function of selecting one memory element from the group of memories based on the attribute information
  • the memory element has a function of holding first data corresponding to the attribute information, and the memory element corresponds to the second image data corresponding to the first image data when selected by the second circuit.
  • 3rd data is generated based on this data and the retained first data That is a semiconductor device.
  • the third data may be a product of the first data and the second data.
  • the encoder has a function of outputting the second image data obtained by compressing the first image by extracting the features of the first image data based on the attribute information. You may have a function which outputs the attribute information received from the 1st circuit.
  • the memory element may include a first transistor, and the first transistor may include a metal oxide in a channel formation region.
  • the memory element includes a second transistor and a first capacitor, and one of the source and the drain of the first transistor is the gate of the second transistor, and the first transistor
  • the first capacitor is electrically connected to one of the pair of electrodes of the capacitor, the first data is input to the other of the source and the drain of the first transistor, and the first capacitor corresponds to the first data.
  • Another embodiment of the present invention includes a transmission device and a reception device, the transmission device includes a first circuit and an encoder, the reception device includes a decoder, An auto encoder is configured by the decoder, and the first circuit and the encoder have a function of receiving the first image data, and the first circuit has a function of extracting the first image data.
  • the first circuit has a function of generating attribute information representing the attribute of the first image data by extracting the features of the first image data, and the encoder performs the first operation based on the attribute information.
  • the decoder has a function of generating the second image data obtained by compressing the first image data by extracting the features of the image data.
  • the decoder expands the second image data based on the attribute information to generate the first image data. Broadcast system with a function to restore It is a non.
  • the encoder and the decoder each include a second circuit and a group of memories having two or more memory elements, and the second circuit includes a group of memories based on the attribute information.
  • the memory element has a function of selecting one memory element, the memory element has a function of holding first data corresponding to attribute information, and when the memory element is selected by the second circuit, You may have a function which produces
  • the third data may be a product of the first data and the second data.
  • the memory element may include a first transistor, and the first transistor may include a metal oxide in a channel formation region.
  • the memory element includes a second transistor and a first capacitor, and one of the source and the drain of the first transistor is the gate of the second transistor, and the first transistor
  • the first capacitor is electrically connected to one of the pair of electrodes of the capacitor, the first data is input to the other of the source and the drain of the first transistor, and the first capacitor corresponds to the first data.
  • a broadcasting system provided with an auto encoder having a small number of dimensions of each intermediate layer and a small number of intermediate layers, and an operation method thereof.
  • a broadcasting system including an auto encoder with a simple circuit configuration and an operation method thereof can be provided.
  • Another object of one embodiment of the present invention is to provide a broadcasting system including an auto encoder that operates at high speed and an operation method thereof.
  • a broadcasting system provided with an auto encoder capable of performing highly accurate compression and expansion and an operation method thereof.
  • a broadcasting system provided with an auto encoder with low power consumption and an operation method thereof can be provided.
  • a broadcasting system including an arithmetic processing device with high calculation accuracy and an operation method thereof can be provided.
  • a semiconductor device with a simple circuit configuration and an operation method thereof can be provided.
  • a semiconductor device with a small number of parameters required for operation and an operation method thereof can be provided.
  • a semiconductor device that operates at high speed and an operation method thereof can be provided.
  • a semiconductor device capable of highly accurate processing and an operation method thereof can be provided.
  • a semiconductor device with low power consumption and an operation method thereof can be provided.
  • a semiconductor device with high calculation accuracy and an operation method thereof can be provided.
  • a novel broadcasting system, a semiconductor device, and an operation method thereof can be provided.
  • the effects of one embodiment of the present invention are not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects.
  • the other effects are effects not mentioned in this item described in the following description. Effects that are not mentioned in this item can be derived from descriptions of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one embodiment of the present invention has at least one of the effects listed above and other effects. Accordingly, one embodiment of the present invention may not have the above-described effects depending on circumstances.
  • the block diagram which shows the structural example of a broadcast system The block diagram which shows the structural example of a broadcast system.
  • the schematic diagram which shows the structural example of a broadcast system.
  • the flowchart which shows an example of the operation method of an auto encoder.
  • the flowchart which shows an example of the operation method of an auto encoder.
  • the block diagram which shows the structural example of an image recognition circuit.
  • the block diagram which shows the structural example of an auto encoder.
  • the figure which shows an example of a hierarchical artificial neural network The figure which shows an example of a hierarchical artificial neural network.
  • 10A and 10B each illustrate a configuration example of a circuit.
  • the block diagram which shows the structural example of a circuit.
  • the block diagram and circuit diagram which show the structural example of an arithmetic processing circuit.
  • the block diagram explaining a programmable switch.
  • the block diagram which shows the structural example of an auto encoder.
  • the circuit diagram which shows the structural example of a product arithmetic circuit.
  • the circuit diagram which shows the structural example of a product arithmetic circuit. 6 is a timing chart illustrating an example of an operation method of the product operation circuit. 6 is a timing chart illustrating an example of an operation method of the product operation circuit.
  • Sectional drawing which shows the structural example of a display apparatus.
  • Sectional drawing which shows the structural example of a display apparatus.
  • Sectional drawing which shows the structural example of a display apparatus.
  • Sectional drawing which shows the structural example of a display apparatus.
  • Sectional drawing which shows the structural example of a display apparatus.
  • Sectional drawing which shows the structural example of a display apparatus.
  • Sectional drawing which shows the structural example of a display apparatus.
  • Sectional drawing which shows the structural example
  • FIG. 10 is a cross-sectional view illustrating a structural example of a transistor.
  • 10A and 10B are a top view and a cross-sectional view illustrating a structure example of a transistor.
  • FIG. 10 is a cross-sectional view illustrating a structural example of a transistor.
  • FIG. 10 is a cross-sectional view illustrating a structural example of a transistor.
  • 10A and 10B are a top view and a cross-sectional view illustrating a structure example of a transistor.
  • FIG. 6 is a circuit diagram and a timing chart illustrating a configuration example of a pixel circuit.
  • FIG. 14 illustrates an example of an electronic device.
  • an artificial neural network refers to all models simulating biological neural networks.
  • a neural network has a configuration in which units simulating neurons are connected to each other via units simulating synapses.
  • the strength of synaptic connection (connection between neurons) (also called weighting factor) can be changed by giving existing information to the neural network. In this way, the process of giving existing information to the neural network and determining the coupling strength is sometimes called “learning”.
  • new information can be output based on the connection strength by giving some information to the neural network that has been “learned” (the connection strength is determined).
  • the connection strength is determined.
  • a process of outputting new information based on given information and connection strength may be referred to as “inference” or “cognition”.
  • Examples of neural network models include a hop field type and a hierarchical type.
  • a neural network having a multilayer structure is referred to as “deep neural network” (DNN), and machine learning by the deep neural network is referred to as “deep learning”.
  • DNN deep neural network
  • a metal oxide is a metal oxide in a broad expression.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OS).
  • oxide semiconductors also referred to as oxide semiconductors or simply OS.
  • the metal oxide may be referred to as an oxide semiconductor.
  • a metal oxide semiconductor metal oxide semiconductor
  • OS metal oxide semiconductor
  • the metal oxide is abbreviated as a metal oxide semiconductor (metal oxide semiconductor).
  • OS in the case of describing an OS FET (or an OS transistor), it can be referred to as a transistor including a metal oxide or an oxide semiconductor.
  • the semiconductor impurity refers to, for example, a component other than the main component constituting the semiconductor layer.
  • an element having a concentration of less than 0.1 atomic% is an impurity.
  • impurities for example, DOS (Density of States) may be formed in a semiconductor, carrier mobility may be reduced, and crystallinity may be reduced.
  • examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and components other than main components Examples include transition metals, and particularly include hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like.
  • oxygen vacancies may be formed by mixing impurities such as hydrogen.
  • impurities such as hydrogen.
  • examples of impurities that change the characteristics of the semiconductor include Group 1 elements other than oxygen and hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.
  • the ordinal numbers “first”, “second”, and “third” are given to avoid confusion between the constituent elements. Therefore, the number of components is not limited. Further, the order of the components is not limited. Further, for example, a component referred to as “first” in one embodiment of the present specification or the like is a component referred to as “second” in another embodiment or in the claims. It is also possible. In addition, for example, the constituent elements referred to as “first” in one embodiment of the present specification and the like may be omitted in other embodiments or in the claims.
  • the terms “upper” and “lower” do not limit that the positional relationship of the constituent elements is directly above or directly below and in direct contact with each other.
  • the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.
  • the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale.
  • the drawings are schematically shown for clarity, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift, or the like can be included.
  • one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other of these is described as “the other of the source and the drain” (or the second electrode or the second terminal).
  • the source and drain of the transistor vary depending on the structure or operating conditions of the transistor.
  • the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.
  • two terminals other than the gate may be referred to as a first terminal and a second terminal, or may be referred to as a third terminal and a fourth terminal.
  • these gates may be referred to as a first gate and a second gate, , Sometimes called back gate.
  • the phrase “front gate” can be rephrased as simply the phrase “gate”.
  • the phrase “back gate” can be rephrased simply as the phrase “gate”.
  • a bottom gate refers to a terminal formed before a channel formation region when a transistor is manufactured, and a “top gate” is formed after a channel formation region when a transistor is manufactured. Terminal.
  • the transistor has three terminals called gate, source, and drain.
  • the gate is a terminal that functions as a control terminal for controlling the conduction state of the transistor.
  • One of the two input / output terminals functioning as a source or a drain serves as a source and the other serves as a drain depending on the type of the transistor and the potential applied to each terminal. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.
  • two terminals other than the gate may be referred to as a first terminal and a second terminal, or may be referred to as a third terminal and a fourth terminal.
  • Electrode and “wiring” do not functionally limit these components.
  • an “electrode” may be used as part of a “wiring” and vice versa.
  • the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.
  • the voltage is a potential difference from a reference potential.
  • the reference potential is a ground potential (ground potential)
  • the voltage can be rephrased as a potential.
  • the ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.
  • conductive layer may be changed to the term “conductive film”.
  • insulating film may be changed to the term “insulating layer” in some cases.
  • conductive layer or conductive film may be changed to the term “conductor” in some cases.
  • the terms “insulating layer” and “insulating film” may be changed to the term “insulator”.
  • wiring can be interchanged depending on the case or circumstances.
  • the term “wiring” may be changed to a term such as “power supply line”.
  • the reverse is also true, and it may be possible to change terms such as “signal line” and “power supply line” to the term “wiring”.
  • a term such as “power line” may be changed to a term such as “signal line”.
  • the reverse is also true, and a term such as “signal line” may be changed to a term such as “power line”.
  • the term “potential” applied to the wiring may be changed to a term “signal” or the like depending on circumstances or circumstances.
  • the reverse is also true, and a term such as “signal” may be changed to a term “potential”.
  • each embodiment can be combined with the structure described in any of the other embodiments as appropriate, for one embodiment of the present invention.
  • any of the structure examples can be combined with each other as appropriate.
  • the content described in one embodiment (may be a part of content) is different from the other content described in the embodiment (may be a part of content) and one or more other implementations.
  • Application, combination, replacement, or the like can be performed on at least one of the contents described in the form (may be part of the contents).
  • a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, another drawing (may be a part) described in the embodiment, or one or more different drawings.
  • more drawings can be formed.
  • One embodiment of the present invention relates to a broadcast system including an imaging device, a transmission device, a reception device, and a display device, and a semiconductor device included in the broadcast system.
  • the imaging device, the transmission device, the reception device, the display device, and the like can be referred to as semiconductor devices.
  • a circuit or the like provided in the imaging device, the transmission device, the reception device, the display device, and the like can also be referred to as a semiconductor device.
  • the imaging device has a function of generating image data and supplying it to the transmission device.
  • the transmission device has a function of transmitting image data to the reception device.
  • the receiving device has a function of receiving image data from the transmitting device.
  • the display device has a function of displaying an image based on image data received by the receiving device.
  • the transmission device is provided with an image recognition circuit and an encoder
  • the reception device is provided with a decoder.
  • a neural network is used for the image recognition circuit, the encoder, and the decoder, and an auto encoder is configured by the encoder and the decoder.
  • the encoder and decoder are provided with a memory having a function of holding a weight coefficient.
  • the image recognition circuit has a function of extracting features of image data and performing image recognition and sorting the image data according to attributes.
  • the image recognition circuit can classify the image data according to an object included in the image data, such as an animal, a plant, and an artificial object. In this case, animals, plants, and artifacts can be called attributes. Information indicating which attribute the image data belongs to can be referred to as attribute information.
  • the image recognition circuit has a function of generating attribute information of image data.
  • the encoder has a function of receiving attribute information from the image recognition circuit and compressing image data based on the attribute information. Specifically, for example, a weighting factor corresponding to each attribute is acquired in advance by learning. When the attribute information is received, arithmetic processing is performed using the weighting coefficient corresponding to the attribute information and the data corresponding to the image data. As a result, the encoder has a circuit configuration corresponding to the attribute of the image data, and the image data can be compressed. The compressed image data and the attribute information received from the image recognition circuit can be transmitted to the decoder.
  • the decoder has a function of expanding the image data compressed by the encoder based on the attribute information. Specifically, for example, a weighting factor corresponding to each attribute is acquired in advance by learning. When the attribute information is received, arithmetic processing is performed using the weighting coefficient corresponding to the attribute information and the data corresponding to the compressed image data. As a result, the decoder has a circuit configuration corresponding to the attribute of the image data, and the image data compressed by the encoder can be expanded.
  • the present invention while simplifying the circuit configuration of an auto encoder, for example, while reducing the number of dimensions of each intermediate layer of the auto encoder, or while reducing the number of intermediate layers included in the auto encoder, Accurate compression and expansion can be performed. As a result, it is possible to perform highly accurate compression and expansion while reducing the number of parameters required when the auto encoder compresses and expands image data. In addition, highly accurate compression and expansion can be performed while operating the auto encoder at high speed.
  • One embodiment of the present invention is particularly effective when the display device has a function of performing extremely high-resolution display such as 2K, 4K, or 8K.
  • an encoder that can perform high-precision compression of image data with a simple circuit configuration, and a transmission apparatus including the encoder. Accordingly, it is possible to provide an encoder that can perform high-precision compression with a small number of parameters, and a transmission apparatus including the encoder. In addition, an encoder capable of performing high-accuracy compression with a small learning time and a transmission apparatus including the encoder can be provided. Further, according to one embodiment of the present invention, a decoder capable of performing high-precision decompression of image data with a simple circuit configuration and a receiving device including the decoder can be provided.
  • FIG. 1 is a block diagram schematically illustrating a configuration example of a broadcasting system 10 that is a broadcasting system according to an aspect of the present invention.
  • the broadcast system 10 includes an imaging device 11, a transmission device 12, a reception device 13, and a display device 14.
  • the imaging device 11 includes an image sensor IS and an image processing circuit PP1.
  • the transmission device 12 includes an image recognition circuit PR and an encoder AIE.
  • the receiving device 13 has a decoder AID.
  • the display device 14 includes an image processing circuit PP2 and a display unit PA.
  • a neural network is used for the image recognition circuit PR, the encoder AIE, and the decoder AID, and the encoder AIE and the decoder AID constitute an auto encoder 20. Although details will be described later, the encoder AIE and the decoder AID are provided with a memory having a function of holding a weight coefficient.
  • the image sensor IS has the number of pixels that can capture an 8K color image. For example, when one pixel is composed of one red (R) subpixel, one green (G) subpixel, and one blue (B) subpixel, the image sensor IS has at least 7680 ⁇ 4320 ⁇ . 3 [R, G, B] sub-pixels are required, and in the case of a 4K imaging device, the number of sub-pixels of the image sensor IS is at least 3840 ⁇ 2160 ⁇ 3, and the 2K imaging device is used. If present, the number of subpixels is at least 1920 ⁇ 1080 ⁇ 3.
  • the image sensor IS has a function of acquiring imaging data.
  • the image processing circuit PP1 has a function of generating image data 31 by performing image processing (noise removal, interpolation processing, gamma correction, light adjustment, color adjustment, etc.) on the captured data.
  • the image data 31 can be output to the image recognition circuit PR and encoder AIE included in the transmission device 12.
  • the image recognition circuit PR has a function of extracting features of the image data 31 and performing image recognition, and sorting the image data 31 by attribute.
  • the image recognition circuit PR can classify the image data 31 according to objects included in the image data 31, such as animals, plants, and artificial objects. Further, the image recognition circuit PR may be classified into dogs, cats, horses and the like, for example, among animals. Further, the image recognition circuit PR may further perform sorting according to the breed of dogs, for example.
  • Information indicating to which attribute the image data 31 belongs can be referred to as attribute information 32.
  • the image recognition circuit PR has a function of generating attribute information 32. Although details will be described later, the image recognition circuit PR can have a function of sorting the image data 31 by supervised learning, for example.
  • the encoder AIE has a function of receiving the attribute information 32 from the image recognition circuit PR and compressing the image data 31 based on the attribute information 32. Specifically, for example, a weighting factor corresponding to each attribute is acquired in advance by learning, and the weighting factor is held in a memory provided in the encoder AIE.
  • the encoder AIE has a circuit configuration corresponding to the attribute of the image data 31, and the compressed image data 33 can be generated by compressing the image data 31.
  • the compressed image data 33 and the attribute information 32 can be transmitted to the decoder AID included in the receiving device 13.
  • the transmission device 12 has a function of performing, for example, processing for adding broadcast control data (for example, authentication data) to the image data 31, encryption processing, scramble processing (data rearrangement processing for spread spectrum), and the like. You may have.
  • the function can be included in the encoder AIE included in the transmission device 12.
  • the transmission device 12 may have a function of, for example, performing IQ modulation (quadrature phase amplitude modulation) on the compressed image data 33 and outputting the result to the reception device 13.
  • the transmitter 12 may be provided with a modulator, and the compressed image data 33 may be IQ-modulated by the modulator.
  • the decoder AID has a function of decompressing the compressed image data 33 based on the attribute information 32 and restoring it to the image data 31. Specifically, for example, a weighting factor corresponding to each attribute is acquired in advance by learning, and the weighting factor is held in a memory provided in the decoder AID.
  • the attribute information 32 is received, the weighting coefficient corresponding to the attribute information 32 is read from the memory, and arithmetic processing is performed using the weighting coefficient read from the memory and the data corresponding to the compressed image data 33.
  • the decoder AID has a circuit configuration corresponding to the attribute of the image data 31, and the compressed image data 33 can be decompressed and restored to the image data 31.
  • the decoder AID may receive the attribute information 32 from the image recognition circuit PR.
  • the image recognition circuit PR may be provided in the receiving device 13.
  • an image recognition circuit may be provided in both the transmission device 12 and the reception device 13.
  • the image recognition circuit included in the reception device 13 may receive attribute information from the image recognition circuit included in the transmission device 12 and transmit the attribute information to the decoder AID.
  • the receiving device 13 may have a function of executing various processes on the compressed image data 33, for example.
  • This processing includes frame separation, LDPC (Low Density Parity Check) code decoding, separation of broadcast control data, descrambling processing, and the like.
  • the decoder AID provided in the receiving device 13 can have the function of performing such processing.
  • the receiving device 13 has a function of demodulating the IQ-modulated compressed image data 33.
  • the receiving device 13 can be provided with a demodulator and can be demodulated by the demodulator.
  • the decoder AID can transmit the restored image data 31 to the image processing circuit PP2 included in the display device 14.
  • the image processing circuit PP2 has a function of performing image processing (noise removal, interpolation processing, gamma correction, dimming, toning, etc.) on the image data 31 and transmitting it to the display unit PA. Pixels are arranged in a matrix on the display unit PA, and when the pixels receive the image data 31, the display unit PA can display an image.
  • the pixels provided in the display portion PA have display elements.
  • the display element for example, a transmissive liquid crystal element, a reflective liquid crystal element, an organic EL element, or the like can be used.
  • the image recognition circuit PR sorts the image data 31 by attribute, and the auto encoder 20 compresses and decompresses the image data 31 using the attribute information 32 that is the result of sorting.
  • the image recognition circuit PR sorts the image data 31 by attribute, and the auto encoder 20 compresses and decompresses the image data 31 using the attribute information 32 that is the result of sorting.
  • FIG. 2 is a modification of the broadcast system 10 shown in FIG. 1, and differs from the configuration shown in FIG. 1 in that the auto encoder 20 includes an external memory EM1 and an external memory EM2.
  • the external memory EM1 is provided in the transmission device 12, and the external memory EM2 is provided in the reception device 13. In this case, weight coefficients are held in the external memory EM1 and the external memory EM2.
  • the external memory EM1 has a function of receiving the attribute information 32 from the image recognition circuit PR and transmitting a weighting factor corresponding to the attribute information 32 to the encoder AIE.
  • the external memory EM2 has a function of receiving the attribute information 32 from the encoder AIE and transmitting a weighting factor corresponding to the attribute information 32 to the decoder AID.
  • the memory capacity of the encoder AIE and the memory capacity of the decoder AID can be reduced. Thereby, the encoder AIE and the decoder AID can be reduced in size.
  • a storage device using a volatile storage element such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM), a flash memory, an MRAM (Magnetic Resistive RAM), and a PRAM (Phase change).
  • RAM Random Access Memory
  • ReRAM Resistive RAM
  • storage devices using non-volatile storage elements such as FeRAM (Ferroelectric RAM), or hard disk drives (Hard Disc Drives: HDDs) and solid state drives (Solid State Drives: SSDs).
  • FeRAM Feroelectric RAM
  • HDDs Hard Disc Drives
  • SSDs Solid State Drives
  • FIG. 3 schematically shows data transmission in a broadcasting system.
  • FIG. 3 shows a route through which a radio wave (broadcast signal) including image data transmitted from the broadcast station 61 is delivered to the television receiver 60 (TV 60) in each home.
  • the TV 60 includes a receiving device 13 and a display device 14.
  • Examples of the artificial satellite 62 include CS (communication satellite) and BS (broadcast satellite).
  • Examples of the antenna 64 include a BS / 110 ° CS antenna and a CS antenna.
  • Examples of the antenna 65 include a UHF (Ultra High Frequency) antenna.
  • the radio waves 66A and 66B are broadcast signals for satellite broadcasting.
  • the artificial satellite 62 receives the radio wave 66A
  • the artificial satellite 62 transmits the radio wave 66B toward the ground.
  • the radio wave 66B is received by the antenna 64, and the TV 60 can watch a satellite TV broadcast.
  • the radio wave 66B is received by an antenna of another broadcasting station and processed into a signal that can be transmitted to an optical cable by a receiving device in the broadcasting station.
  • the broadcast station transmits a broadcast signal to the TV 60 in each home using an optical cable network.
  • the radio wave 67A and the radio wave 67B are broadcast signals for terrestrial broadcasting.
  • the radio tower 63 amplifies the received radio wave 67A and transmits the radio wave 67B.
  • the terrestrial TV broadcast can be viewed on the TV 60 by receiving the radio wave 67 ⁇ / b> B with the antenna 65.
  • the transmission device 12 can be provided in the broadcasting station 61, the artificial satellite 62, or the radio tower 63, for example.
  • the receiving device 13 can be provided in the TV 60, for example.
  • the receiving device 13 may be provided outside the TV 60.
  • the broadcasting system of the present embodiment is not limited to a TV broadcasting system.
  • the image data to be distributed may be moving image data or still image data.
  • FIG. 4 is a flowchart illustrating an example of a learning method in the image recognition circuit PR and the auto encoder 20.
  • image data is input to the image recognition circuit PR, and the image recognition circuit PR performs learning.
  • the image recognition circuit PR can output the attribute information 32 corresponding to the attribute of the image data (step S01).
  • the image recognition circuit PR can perform learning by supervised learning. Specifically, for example, when sorting image data into animals, plants, and artifacts, image data to be recognized as animals is input to the image recognition circuit PR, and an answer of animals is prepared as teacher data. Subsequently, a weighting coefficient in the image recognition circuit PR is set so that the image data is recognized as an animal. Further, image data to be recognized as a plant is input to the image recognition circuit PR, and an answer of plant is prepared as teacher data.
  • the weighting coefficient in the image recognition circuit PR is updated so that the image data is recognized as a plant. Further, next, image data to be recognized as an artifact is input to the image recognition circuit PR, and an answer of an artifact is prepared as teacher data. Subsequently, the weighting coefficient in the image recognition circuit PR is updated so that the image data is recognized as an artifact. As described above, the weight coefficient in the image recognition circuit PR can be set so that the image data can be properly sorted and the appropriate attribute information 32 can be output. Although details will be described later, in the case of performing supervised learning, for example, learning by an error back propagation method can be performed.
  • image data with the same type of attribute is not continuously input to the image recognition circuit PR, and the image type is set to random as the image type. It is preferable to input to the recognition circuit PR.
  • the recognition circuit PR For example, when the image data is sorted into animals, plants, and artifacts, it is preferable that the animal image data, the plant image data, and the artifact image data are randomly input to the image recognition circuit PR.
  • the image recognition circuit PR has a function of classifying image data into n types (n is an integer of 2 or more) attributes (attribute [1] to attribute [n]).
  • n is an integer of 2 or more
  • attributes attribute [1] to attribute [n].
  • n 3.
  • an animal can be attribute [1]
  • a plant can be attribute [2]
  • an artifact can be attribute [3].
  • variable i is prepared, i is set to 1, and the image recognition circuit PR and the encoder AIE receive the image data of the attribute [i] (step S02, step S03). Thereafter, the image recognition circuit PR transmits the attribute information 32 of the attribute [i] to the encoder AIE and the decoder AID (step S04).
  • the attribute information 32 of the attribute [i] is represented as attribute information 32 [i].
  • the auto encoder 20 that is, the encoder AIE and the decoder AID performs learning to acquire learning data (step S05).
  • the learning data for example, a weight coefficient can be cited.
  • the learning can be, for example, unsupervised learning.
  • the variable i is incremented by 1 (step S06).
  • step S07 it is determined whether or not the variable i is larger than n (step S07). If the variable i is n or less, the steps S03 to S07 are executed again. If the variable i is larger than n, the auto encoder 20 has completed learning, that is, any image of the attribute [1] to the attribute [n]. The learning operation is terminated on the assumption that the data can be appropriately compressed and expanded. The above is an example of the learning operation in the auto encoder 20.
  • the learning operation shown in FIG. 4 can actually be performed by a server or the like provided outside the broadcasting system 10.
  • the image processing circuit PR, the encoder AIE, and the decoder AID are modeled in the server or the like, and learning is performed using the model.
  • a learning result that is, learning data such as a weight coefficient is transmitted from the server or the like to the image recognition circuit PR, the encoder AIE, and the decoder AID.
  • the image processing circuit PR, the encoder AIE, and the decoder AID can perform learning.
  • FIG. 5 is a flowchart showing an example of an operation method of each device constituting the broadcast system 10.
  • the imaging device 11 generates image data 31 and transmits the image data 31 to the image recognition circuit PR and the encoder AIE included in the transmission device 12. Specifically, the image data is acquired by the image sensor IS included in the image pickup device 11, and the image processing circuit PP1 performs image processing on the image pickup data to generate image data 31 (step S11). .
  • the image recognition circuit PR extracts the features of the image data 31 to perform image recognition, and generates attribute information 32 corresponding to the attributes of the image data 31. That is, when the image data 31 is image data having the attribute [i], the attribute information 32 [i] is generated.
  • the generated attribute information 32 is transmitted to the encoder AIE (step S12).
  • the encoder AIE compresses the image data 31 based on the attribute information 32 and generates compressed image data 33 (step S13). For example, the encoder AIE generates the compressed image data 33 by performing arithmetic processing using the weighting coefficient corresponding to the attribute information 32 and the data corresponding to the image data 31. Thereafter, the decoder AID receives the compressed image data 33 and the attribute information 32 from the encoder AIE (step S14).
  • the decoder AID decompresses the compressed image data 33 based on the attribute information 32 and restores it to the image data 31.
  • the decoder AI restores the image data 31 by performing arithmetic processing using the weighting coefficient corresponding to the attribute information 32 and the data corresponding to the compressed image data 33.
  • the restored image data 31 is transmitted to the display device 14 (step S15). Specifically, the restored image data 31 is transmitted to the image processing circuit PP2 included in the display device 14 to perform image processing and the like. Thereafter, an image corresponding to the image data 31 is displayed on the display unit PA.
  • step S11 the imaging device 11 generates the image data 31 and transmits the image data 31 to the image recognition circuit PR and the encoder AIE included in the transmission device 12.
  • the imaging device 11 generates the image data 31 and transmits the image data 31 to the image recognition circuit PR and the encoder AIE included in the transmission device 12.
  • the above is an example of the operation method of each device constituting the broadcasting system 10.
  • the image recognition circuit PR and the auto encoder 20 have learned according to the procedure shown in FIG. 4 and are operated according to the procedure shown in FIG.
  • the image recognition circuit PR may perform learning, and the auto encoder 20 may perform learning accordingly.
  • the auto encoder 20 can perform more accurate compression and expansion.
  • FIG. 6 is a configuration example of the image recognition circuit PR.
  • an image processing circuit PP1 and an encoder AIE are also illustrated.
  • the image recognition circuit PR includes an input layer IL1, an intermediate layer ML1 [1], an intermediate layer ML1 [2], and an output layer OL1. That is, in the image recognition circuit PR, the input layer IL1, the intermediate layer ML1 [1], the intermediate layer ML1 [2], and the output layer OL1 form a hierarchical neural network.
  • Image data 31 sent from the image processing circuit PP1 is input to the input layer IL1 of the image recognition circuit PR. That is, the image data 31 is handled as input data of a hierarchical neural network.
  • the hierarchical neural network will be described later.
  • the hierarchical neural network in the image recognition circuit PR has a configuration in which the number of neurons decreases as the hierarchy progresses. That is, the number of neurons included in the intermediate layer ML1 [1] is smaller than the number of neurons included in the input layer IL1, and the number of neurons included in the intermediate layer ML1 [2] is the number of neurons included in the intermediate layer ML1 [1]. Less than the number of Furthermore, the number of neurons included in the output layer OL1 is smaller than the number of neurons included in the intermediate layer ML1 [2].
  • FIG. 6 shows the number of neurons by the number of arrows connecting the respective layers.
  • the image recognition circuit PR By configuring the image recognition circuit PR so that the number of neurons decreases as the hierarchy progresses, it is possible to extract features of the image data 31 and generate attribute information 32 corresponding to the attributes of the image data 31.
  • a configuration in which the number of neurons gradually decreases is shown, but the configuration of the neural network is not limited to this.
  • the number of neurons may increase in the intermediate layer, or the number of neurons may not change.
  • FIG. 7 is a configuration example of the auto encoder 20.
  • an image processing circuit PP1 and an image processing circuit PP2 are also illustrated.
  • the number of neurons of each layer is indicated by the number of arrows connecting the respective layers.
  • the encoder AIE included in the auto encoder 20 includes the input layer IL2, the intermediate layer ML2 [1], and the intermediate layer ML2 [2].
  • the decoder AID included in the auto encoder 20 includes the intermediate layer ML2 [3].
  • the intermediate layer ML2 [4] and the output layer OL2 are included. That is, in the auto encoder 20, a hierarchical neural network is configured by the input layer IL2, the intermediate layer ML2 [1] to the intermediate layer ML2 [4], and the output layer OL2.
  • the image data 31 sent from the image processing circuit PP1 is input to the input layer IL2 of the encoder AIE included in the auto encoder 20. That is, the image data 31 is handled as input data of a hierarchical neural network.
  • the hierarchical neural network will be described later.
  • the hierarchical neural network in the encoder AIE has a configuration in which the number of neurons decreases as the hierarchy progresses. That is, the number of neurons included in the intermediate layer ML2 [1] is smaller than the number of neurons included in the input layer IL2, and the number of neurons included in the intermediate layer ML2 [2] is the number of neurons included in the intermediate layer ML2 [1]. Less than the number of By configuring the encoder AIE as described above, the data amount of data output from the intermediate layer ML2 [2] can be reduced, that is, compressed, with respect to the input data amount.
  • the hierarchical neural network in the decoder AID has a configuration in which the number of neurons increases as the hierarchy progresses. That is, the number of neurons included in the intermediate layer ML2 [4] is larger than the number of neurons included in the intermediate layer ML2 [3], and the number of neurons included in the output layer OL2 is the number of neurons included in the intermediate layer ML2 [4]. More than the number of.
  • the encoder AIE generates a compressed image data 33 by compressing the image data 31 based on the attribute information 32 by extracting features of the image data 31 as a circuit configuration corresponding to the attribute information 32.
  • the decoder AID restores the compressed image data 33, which is the image data from which the features have been extracted, to the image data 31, and outputs it from the output layer OL2.
  • all layers can be combined, or convolution layers and pooling can be formed between the layers.
  • a configuration using layers, that is, a CNN can be employed.
  • the number of intermediate layers in the image recognition circuit PR and the number of intermediate layers in the auto encoder 20 are not limited, and can be provided as necessary. Further, the number of neurons included in the input layer, the intermediate layer, and the output layer in the image recognition circuit PR is not limited to the number shown in FIG. 6, but can be provided as necessary. In addition, the number of neurons included in the input layer, the intermediate layer, and the output layer in the auto encoder 20 is not limited to the number illustrated in FIG. 7, and can be provided as necessary.
  • simplifying the circuit configuration of the auto encoder 20 means, for example, reducing the number of intermediate layers of the auto encoder 20. Or, for example, it means reducing the number of neurons in each layer of the auto encoder 20.
  • Hierarchical neural network will be described as one type of neural network that can be used for the image recognition circuit PR and the auto encoder 20.
  • FIG. 8 is a diagram showing an example of a hierarchical neural network.
  • the (k ⁇ 1) th layer (where k is an integer of 2 or more) has P neurons (where P is an integer of 1 or more), and the kth layer is a neuron.
  • Q (here, Q is an integer of 1 or more)
  • the (k + 1) -th layer has R neurons (where R is an integer of 1 or more).
  • the product of the output signal z p (k ⁇ 1) and the weighting factor w qp (k) of the p-th neuron in the (k ⁇ 1) -th layer (where p is an integer of 1 or more and P or less) is It is assumed that the input signal is input to the q-th neuron in the k-th layer (where q is an integer of 1 to Q), and the output signal z q (k) of the q-th neuron in the k-th layer and the weight coefficient w rq.
  • the output signal z q (k) from the q-th neuron in the k-th layer is defined by the following equation.
  • the activation function may be the same or different in all neurons. In addition, the activation function may be the same or different for each layer.
  • a hierarchical neural network composed of all L layers (L is an integer of 3 or more) shown in FIG. 9 is considered. That is, k here is an integer of 2 or more and (L-1) or less.
  • the first layer is an input layer of the hierarchical neural network
  • the Lth layer is an output layer of the hierarchical neural network
  • the second to (L-1) layers are intermediate layers.
  • the first layer has P neurons
  • the kth layer intermediate layer
  • Q [k] neurons Q [k] is an integer equal to or greater than 1).
  • the L layer output layer has R neurons.
  • the output signal of the s [1] neuron in the first layer (s [1] is an integer between 1 and P) is z s [1] (1), and the s [k] neuron in the kth layer.
  • the output signal (s [k] is an integer between 1 and Q [k]) is z s [k] (k), and the s [L] neuron (s [L] is 1 in the Lth layer.
  • the output signal is an integer less than or equal to R.) z s [L] (L) .
  • the output signal z s [k ⁇ 1 ] of the s [k ⁇ 1] th neuron (s [k ⁇ 1] is an integer of 1 to Q [k ⁇ 1]) in the (k ⁇ 1) th layer.
  • Product k s [k] (k ) and weight coefficient w s [k] s [k ⁇ 1] (k) are input to the s [k] neuron in the k-th layer.
  • the output signal z s [L ⁇ ] of the s [L ⁇ 1] neuron (s [L ⁇ 1] is an integer of 1 to Q [L ⁇ 1]) in the (L ⁇ 1) th layer.
  • 1] (L ⁇ 1) and the weight coefficient w s [L] s [L ⁇ 1] (L) and the product u s [L] (L) are input to the s [L] neuron in the Lth layer.
  • Supervised learning is a function of the hierarchical neural network when the output result differs from a desired result (sometimes referred to as teacher data or a teacher signal) in the function of the hierarchical neural network. This is an operation for updating all the weight coefficients based on the output result and the desired result.
  • FIG. 10 is a diagram for explaining a learning method based on the error back propagation method.
  • the error back-propagation method is a method of changing the weighting coefficient so that the error between the output of the hierarchical neural network and the teacher data becomes small.
  • the update amount of the weight coefficient w s [k] s [k ⁇ 1] (k) of the s [k] neuron in the k-th layer is expressed as ⁇ E / ⁇ w s [k] s [k ⁇ 1]
  • the weighting factor can be newly changed.
  • f ′ (u s [k] (k) ) is a derivative of the activation function.
  • Expression (3) can be realized by, for example, the circuit 163 illustrated in FIG.
  • the calculation of Formula (4) is realizable by the circuit 164 shown in FIG.11 (C), for example.
  • the derivative of the activation function can be realized, for example, by connecting an arithmetic circuit corresponding to a desired derivative to the output terminal of the operational amplifier.
  • ⁇ s [L] (L) and ⁇ E / ⁇ w s [L] s [L -1] (L) can be represented by the following formulas.
  • Equation (5) can be realized by a circuit 165 shown in FIG. Further, the calculation of Expression (6) can be realized by a circuit 164 shown in FIG.
  • the errors ⁇ s [k] (k) and ⁇ s [L] (L) of all the neuron circuits can be obtained by the equations (1) to (6).
  • the weight coefficient update amount is set based on the errors ⁇ s [k] (k) , ⁇ s [L] (L), desired parameters, and the like.
  • a hierarchical neural network to which supervised learning is applied can be calculated by using the circuits shown in FIGS. 11A to 11D and a product-sum operation circuit described later.
  • FIG. 12 is a block diagram illustrating a configuration example of a circuit of a hierarchical neural network.
  • An NN (neural network) circuit 100 includes input terminals PDL [1] to PDL [1] (where l is an integer equal to or greater than 1), output terminals PDR [1] to output terminals PDR [v]. (Where v is an integer of 1 or more), programmable logic element PLE [1] to programmable logic element PLE [m] (here, m is an integer of 1 or more), and wiring L [1].
  • P [1] to wiring P [m] wiring R [1] to wiring R [v]
  • wiring Q [1] to wiring Q [m] a plurality of programmable switches PSW1, a plurality of Programmable switch PSW2 and a plurality of programmable switches PSW3.
  • one embodiment of the present invention is a multi-context programmable operation processing device using the programmable logic element PLE [1] to the programmable logic element PLE [m] and the programmable switch PSW1 to the programmable switch PSW3.
  • the arithmetic processing device associates the connection state of the networks between the layers with each context, and performs the arithmetic processing of the neural network by sequentially switching the context.
  • the input terminal PDL [i] (where i is an integer of 1 to 1) is electrically connected to the wiring L [i].
  • the output terminal PDR [k] (where k is an integer greater than or equal to 1 and less than or equal to v) is electrically connected to each of the wirings R [1] to R [v] via the programmable switch PSW3.
  • a first terminal of the programmable logic element PLE [j] (where j is an integer of 1 to m) is electrically connected to the wiring Q [j], and the wiring Q [j]
  • Each of L [1] to L [l] is electrically connected through the programmable switch PSW1.
  • the wiring Q [j] is electrically connected to each of the wirings P [1] to P [m] through the programmable switch PSW2.
  • the second terminal of the programmable logic element PLE [j] is electrically connected to the wiring R [j].
  • the wirings P [1] to P [m] are electrically connected to the wirings R [1] to R [v], respectively.
  • the programmable switches PSW1 to PSW3 included in the NN circuit 100 are switches that can be switched between a conductive state and a non-conductive state according to data stored in a memory MS described later.
  • Each of the programmable switches PSW1 to PSW3 includes a switch circuit SWC. Details of the programmable switches PSW1 to PSW3 will be described later.
  • FIG. 13A is a circuit diagram illustrating a configuration example of the arithmetic processing circuit 150 included in the NN circuit 100 provided in the auto encoder 20.
  • the arithmetic processing circuit 150 includes a controller CNT, a product arithmetic circuit MAC [1] to a product arithmetic circuit MAC [s] (s is an integer of 2 or more), an adder circuit AD, an activation function circuit AFC, and a memory MF. And a holding circuit KC.
  • the product operation circuit MAC [h] (h is an integer of 1 to s) includes a multiplication circuit MLT [h], memories MW [h] (1) to MW [h] (t), and a multiplexer MUX1 [h ].
  • t can be an integer greater than or equal to n. That is, the product operation circuit MAC [h] has more memories MW [h] than the number of types of attribute information 32 that can be output by the image recognition circuit PR described above.
  • the memory MW [h] (1) to the memory MW [h] (t) may be collectively referred to as the memory MW [h].
  • t can be an integer smaller than n. That is, the number of memories MW [h] included in the product operation circuit MAC [h] can be made smaller than the number of types of attribute information 32 that can be output by the image recognition circuit PR described above.
  • the memory MW [h] (1) to the memory MW [h] (t) may be collectively referred to as a group of memories.
  • the memory MW [h] (1) to the memory MW [h] (t) may be referred to as memory elements. That is, it can be said that the product operation circuit MAC [h] includes a group of memories including the memories MW [h] (1) to MW [h] (t) which are memory elements.
  • FIG. 13A illustrates the function of the arithmetic processing circuit 150 to the last, and the circuits illustrated in FIG. 13A are not necessarily provided as separate circuits.
  • the memory MW [h] (1) to the memory MW [h] (t) included in the product operation circuit MAC [h] can have the function of the multiplication circuit MLT [h]. That is, a circuit different from the memories MW [h] (1) to MW [h] (t) may not be provided as the multiplier circuit MLT [h].
  • the multiplexers MUX1 [1] to MUX1 [s] may not be provided in the product operation circuits MAC [1] to MAC [s].
  • the controller CNT can have a function as the multiplexer MUX1 [1] to the multiplexer MUX1 [s]. In the following circuit diagrams, all the illustrated circuits may not necessarily be provided as separate circuits.
  • Attribute information 32 is input to the controller CNT.
  • the controller CNT is electrically connected to the selection signal input terminals of the multiplexers MUX1 [1] to MUX1 [s].
  • the memories MW [h] (1) to MW [h] (t) are electrically connected to the input terminal of the multiplexer MUX1 [h].
  • the output terminal of the multiplexer MUX1 [h] is electrically connected to the first input terminal of the multiplication circuit MLT [h].
  • the input terminal In [h] is electrically connected to the second input terminal of the multiplication circuit MLT [h], and the output terminal of the multiplication circuit MLT [h] is electrically connected to the input terminal of the addition circuit AD. ing.
  • the output terminal of the adder circuit AD is electrically connected to the input terminal of the activation function circuit AFC.
  • the output terminal of the activation function circuit AFC is electrically connected to the terminal TA1 of the holding circuit KC.
  • a terminal TA2 of the holding circuit KC is electrically connected to the output terminal OUT.
  • the multiplication circuit MLT [h] uses one of the data (hereinafter sometimes referred to as weighting factors) held in the memory MW [h] (1) to the memory MW [h] (t) as a multiplier.
  • the data can be data corresponding to image data, for example.
  • the multiplier in the multiplication circuit MLT [h], that is, the memory MW [h] holding the data output from the multiplexer MUX [h] is selected by the controller CNT based on the attribute information 32.
  • attribute information 32 [i] (where i is an integer between 1 and t) is sent to the controller CNT.
  • the controller CNT can select the memory MW [h] (i).
  • the addition circuit AD is a circuit that calculates the sum of the multiplication results output from the multiplication circuits MLT [1] to MLT [s]. That is, the multiplying circuit MLT [1] to the multiplying circuit MLT [s] and the adding circuit AD constitute a product-sum operation circuit.
  • the activation function circuit AFC is a circuit that performs an operation according to a function system defined by data held in the memory MF with respect to a signal input to an input terminal, that is, a product-sum operation result.
  • a function system for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, or the like can be used.
  • the holding circuit KC acquires the calculation result output from the activation function circuit AFC from the terminal TA1, and temporarily holds the calculation result, and outputs the temporarily held calculation result to the terminal TA2.
  • the holding circuit KC can switch between the two functions described above according to the clock signal CLK input to the terminal CKT.
  • the holding circuit KC can hold the potential input from the terminal TA1, and when the pulse of the clock signal CLK is at a low level potential, the holding circuit KC. Can output the potential from the terminal TA2 to the output terminal OUT.
  • the arithmetic processing circuit 150 is a circuit that handles digital data, for example, a flip-flop circuit can be applied to the holding circuit KC.
  • a holding circuit KC shown in FIG. 13B is a sample-and-hold circuit, and includes a transistor TrA, a transistor TrB, a capacitor CA, an amplifier AMP, and a NOT circuit NL.
  • One of the source and the drain of the transistor TrA is electrically connected to the terminal TA1
  • the other of the source and the drain of the transistor TrA is electrically connected to one of the pair of electrodes of the capacitor CA
  • the gate of the transistor TrA is Are electrically connected to the terminal CKT.
  • the input terminal of the amplifier AMP is electrically connected to the other of the source and drain of the transistor TrA
  • the output terminal of the amplifier AMP is electrically connected to one of the source and drain of the transistor TrB.
  • the other of the source and the drain of the transistor TrB is electrically connected to the terminal TA2.
  • the input terminal of the NOT circuit NL is electrically connected to the terminal CKT
  • the output terminal of the NOT circuit NL is electrically connected to the gate of the transistor TrB.
  • the other of the pair of electrodes of the capacitor CA is electrically connected to the wiring GNDL.
  • a node N where the other of the source and the drain of the transistor TrA, the input terminal of the amplifier AMP, and one of the pair of electrodes of the capacitor is connected.
  • the amplifier AMP has a function of amplifying the signal input to the input terminal by a factor of 1 and outputting the amplified signal to the output terminal.
  • the wiring GNDL is a wiring that applies a reference potential.
  • the transistor TrA When the pulse of the clock signal CLK input to the terminal CKT is at a high level potential, the transistor TrA is turned on and the transistor TrB is turned off. At this time, the signal input from the terminal TA1 is input to the amplifier AMP via the transistor TrA. Therefore, the amplifier AMP amplifies the signal and outputs the amplified signal from the output terminal of the amplifier AMP. Note that since the transistor TrB is non-conductive, the amplified signal is not output from the terminal TA2.
  • the potential of the node N is held by the capacitive element CA. At this time, the potential of the node N becomes the potential of the signal input from the terminal TA1.
  • the transistor TrA When the pulse of the clock signal CLK input to the terminal CKT is at a low level potential, the transistor TrA is turned off and the transistor TrB is turned on. Since the transistor TrA is in a non-conductive state, the potential of the node N does not change.
  • the amplifier AMP outputs the potential of the node N to one of the source and drain of the transistor TrB. Since the transistor TrB is in a conductive state, the potential of the node N, that is, the potential of the signal input from the terminal TA1 when the pulse of the clock signal CLK is at a high level potential is output from the terminal TA2.
  • the transistor TrA and / or the transistor TrB is preferably an OS transistor.
  • the OS transistor preferably uses a metal oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin) and zinc in a channel formation region.
  • the holding circuit KC of the product-sum operation circuit 150 included in the semiconductor device of one embodiment of the present invention is not limited to the above structure. Depending on the case or the situation, the configuration of the holding circuit KC can be changed as appropriate.
  • the memory MW [1] to memory MW [s] and the memory MF included in the arithmetic processing circuit 150 and the memory MS that sets the states of the programmable switches PSW1 to PSW3 described later are different from each other by a driving circuit.
  • the writing may be performed. That is, it is possible to repeatedly update the data in the memories MW [1] to MW [s] and the memory MF of the product-sum operation circuit 150 without updating the data in the memory MS. This enables efficient learning in the neural network.
  • one programmable logic element has been described as having a single arithmetic processing circuit 150.
  • one product-sum arithmetic circuit includes a plurality of programmable logic elements and a programmable switch that connects the programmable logic elements. It is also possible to configure.
  • the controller CNT and the multiplexers MUX1 [1] to MUX1 [s] are omitted, and the product arithmetic circuit MAC has a single memory MW.
  • the arithmetic processing circuit included in the image recognition circuit PR can be obtained.
  • one memory MW is electrically connected to the first input terminal of one multiplication circuit MLT.
  • FIG. 14A illustrates a connection example of the wiring Q [j], the programmable switch PSW1, the programmable switch PSW2, and the programmable logic element PLE [j] in the NN circuit 100
  • FIG. 2 shows a configuration example of the switch circuit SWC.
  • the wiring Q [j] includes the wirings q [1] to q [s].
  • the first terminals of the programmable logic element PLE [j] are the input terminals In [1] to In [s] of the arithmetic processing circuit 150 described with reference to FIG. Yes. That is, in FIG. 14A, the wiring q [h] is electrically connected to the input terminal In [h].
  • the wirings q [1] to q [s] are electrically connected to the wiring “0” via the programmable switch PSW1.
  • the wiring “0” is a wiring for supplying a signal having a value of 0 (the signal potential is a reference potential).
  • the programmable switch PSW1 and the programmable switch PSW2 have a switch circuit SWC.
  • a configuration example of the switch circuit SWC included in the auto encoder 20 is shown in FIG.
  • the switch circuit SWC includes a switch SW, a controller CNT, memories MS (1) to MS (t), and a multiplexer MUX2.
  • t can be an integer greater than or equal to n. That is, the switch circuit SW includes more memories MS than the number of types of attribute information 32 that can be output by the image recognition circuit PR described above.
  • t can be set to a smaller integer. That is, the number of memories MS included in one switch circuit SWC can be made smaller than the number of types of attribute information 32 that can be output by the image recognition circuit PR described above.
  • the first terminal of the switch SW is electrically connected to the wiring q [h], and the second terminal of the switch SW is electrically connected to the wiring X.
  • the wiring X is any one of the wiring “0”, the wirings L [1] to L [l], and the wirings P [1] to P [m].
  • the attribute information 32 is input to the controller CNT.
  • the controller CNT is electrically connected to the selection signal input terminal of the multiplex MUX2.
  • the memories MS (1) to MS (t) are electrically connected to the input terminal of the multiplexer MUX2.
  • the switch SW determines a conductive state or a non-conductive state according to data held in one of the memories MS (1) to MS (t). Data to be output to the switch SW is selected by the controller CNT based on the attribute information 32. That is, one of the memories MS (1) to MS (t) is selected by the controller CNT based on the attribute information 32.
  • attribute information 32 [i] (where i is an integer between 1 and t) is sent to the controller CNT.
  • the controller CNT can select the memory MS (i).
  • Each of the programmable switch PSW1 and the programmable switch PSW2 illustrated in FIG. 14A is turned on and off by data held in one of the memories MS (1) to MS (t).
  • the wiring “0”, the wirings L [1] to L [l], and the wirings P [1] to P [m] are stored in the memory MS (1) to the memory MS (t).
  • each of the input terminals In [1] to In [s] can be controlled.
  • the switch circuit SWC that connects some of the terminals to the wiring “0” is turned on. .
  • the multiplier circuits corresponding to the some terminals can reduce power consumption by power gating.
  • a switch using MEMS (micro electro mechanical system) technology such as a transistor, a diode, or a digital micromirror device (DMD) can be applied. it can.
  • MEMS micro electro mechanical system
  • the switch SW may be a logic circuit that combines transistors. In the case where the switch SW is a single transistor, it is preferable to use an OS transistor having characteristics of extremely low off-state current.
  • one switch circuit SWC includes one memory MS, whereby the switch included in the image recognition circuit PR. It can be a circuit.
  • FIG. 14C illustrates a connection example of the wiring R [k], the programmable switch PSW3, the programmable logic element PLE [j], and the output terminals PDR [1] to PDR [v] in the NN circuit 100. Show.
  • the wiring R [k] includes the wirings r [1] to r [c].
  • the second terminals of the programmable logic element PLE [j] are represented as terminals O [1] to O [e] (here, e is an integer of 1 or more). Show. That is, in FIG. 14C, the wiring r [k] is electrically connected to the terminal O [k]. Note that in FIG. 14C, a plurality of second terminals are illustrated, but a single terminal may be used.
  • the programmable switch PSW3 has a switch circuit SWC. That is, similarly to the programmable switch PSW1 and the programmable switch PSW2, the conduction state and the non-conduction state of the switch SW included in the switch circuit SWC are determined by data held in one of the memories MS (1) to MS (t). can do. Therefore, it is possible to control the presence / absence of connection between each of the terminals O [1] to O [e] and each of the output terminals PDR [1] to PDR [v] according to the data in the memory MS. it can.
  • SRAM and MRAM can be applied to the above-described memory MS, memory MW, and memory MF.
  • a memory device using an OS transistor referred to as an OS memory in this specification and the like
  • OS memory a memory device using an OS transistor
  • a low power consumption neural network can be configured with a small number of elements.
  • FIG. 15 shows a configuration example in which the NN circuit 100A is applied as the NN circuit 100 to the encoder AIE, and the NN circuit 100B is applied as the NN circuit 100 to the decoder AID.
  • the NN circuit 100A and the NN circuit 100B are electrically connected.
  • FIG. 15 also shows an image processing circuit PP1 and an image processing circuit PP2.
  • the encoder AIE has the number of neurons included in the intermediate layer ML2 [2] and the intermediate layer ML2 [3] illustrated in FIG. 7 as the input layer IL2, the intermediate layer ML2 [1], the intermediate layer ML2 [4], and the output.
  • the layer OL2 is configured to be smaller than the number of neurons.
  • the NN circuit 100A includes an input terminal PDL [1] to an input terminal PDL [L] (where L is an integer of 1 or more), an output terminal PDR [1] to an output terminal PDR [V] ( NN circuit 100B includes an input terminal PDL [1] to input terminal PDL [V] and an output terminal PDR [1] to output terminal.
  • PDR [L] the plurality of programmable logic elements PLE included in each of the NN circuit 100 ⁇ / b> A and the NN circuit 100 ⁇ / b> B are described as a programmable logic element unit PLES ⁇ b> 1 and a programmable logic element unit PLES ⁇ b> 2.
  • the auto encoder 20 can be configured by applying the NN circuit 100 to each of the encoder AIE and the decoder AID.
  • the image data 31 sent from the image processing circuit PP1 can be converted into compressed image data 33, which is image data from which features have been extracted, by the NN circuit 100A.
  • the compressed image data 33 can be restored to the original image data 31 by the NN circuit 100B, and the restored image data 31 can be transmitted to the image processing circuit PP2 included in the display device 14.
  • the numbers of the input terminal PDL of the NN circuit 100A and the output terminal PDR of the NN circuit 100B are described as being the same, but depending on circumstances, depending on the situation or as necessary
  • the number of input terminals PDL of the NN circuit 100A and the number of output terminals PDR of the NN circuit 100B may be different from each other.
  • FIG. 16 shows the wirings electrically connected to the product operation circuit MAC [i] and the controller CNT, and the product operation circuit MAC [i] and the controller CNT.
  • the product operation circuit MAC [i] includes memories MW [i] (1) to MW [i] (t).
  • a configuration example of the memory MW [i] (g) (g is an integer of 1 to t) will be described.
  • the memory MW [i] (g) includes a transistor Tr1 (g), a transistor Tr2 (g), a transistor Tr3 (g), and a capacitor C1 (g).
  • One of the source and the drain of the transistor Tr1 (g) is electrically connected to the gate of the transistor Tr2 (g) and one of the pair of electrodes of the capacitor C1 (g).
  • the other of the source and the drain of the transistor Tr1 (g) is electrically connected to the wiring WD.
  • a gate of the transistor Tr1 (g) is electrically connected to the wiring WW (g).
  • One of the source and the drain of the transistor Tr2 (g) is electrically connected to one of the source and the drain of the transistor Tr3 (g).
  • the other of the source and the drain of the transistor Tr2 (g) is electrically connected to the wiring VSSL.
  • the other of the source and the drain of the transistor Tr3 (g) is electrically connected to the wiring RD.
  • a gate of the transistor Tr3 (g) is electrically connected to the wiring SE (t).
  • the other of the pair of electrodes of the capacitor C1 (g) is electrically connected to the wiring RW.
  • the other of the source and the drain of the transistors Tr1 (1) to Tr1 (t) can be electrically connected by one wiring WD.
  • the other of the source and the drain of the transistors Tr3 (1) to Tr3 (t) can be electrically connected by one wiring RD.
  • a node to which the other of the source and the drain of the transistor Tr1 (g), the gate of the transistor Tr2 (g), and one of the pair of electrodes of the capacitor C1 (g) is connected is referred to as a node N1 (g).
  • a low potential can be applied to the wiring VSSL.
  • the low potential for example, a ground potential can be used.
  • Data serving as a weighting coefficient is supplied to the memory MW [i] (1) to the memory MW [i] (t) via the wiring WD. Further, the conduction state of the transistor Tr1 (g) is controlled by the potential of the wiring WW (g). When data serving as a weighting coefficient output from the wiring WD is written to the memory MW [i] (g), the transistor Tr1 (g) is turned on. On the other hand, when data serving as a weighting coefficient output from the wiring WD is not written in the memory MW [i] (g), the transistor Tr1 (g) is turned off. When the transistor Tr1 (g) is turned off, data serving as a weighting coefficient corresponding to the attribute information 32 [g] can be held in the memory MW [i] (g).
  • data written in the memory MW [i] (g) is held as a charge in the node N1 (g).
  • MAC [i] performs learning, and the weighting coefficient obtained as a result of learning can be held in the memory MW [i] (1) to the memory [i] (t).
  • the transistors Tr1 (1) to Tr1 (t) and the transistors Tr2 (1) to Tr2 (t) are preferably OS transistors. Further, the channel formation regions of the transistors Tr1 (1) to Tr1 (t) and the transistors Tr2 (1) to Tr2 (t) are metal oxides containing at least one of indium, element M, and zinc. It is more preferable.
  • the transistors Tr1 (1) to Tr1 (t) and the transistors Tr2 (1) to Tr2 (t) are used.
  • To transistors Tr2 (t) can be suppressed. Accordingly, leakage of the charge held in the nodes N1 (1) to N1 (t) to the wiring WD when the transistors Tr1 (1) to Tr1 (t) are in a non-conductive state is extremely reduced. Therefore, a product-sum operation circuit with high calculation accuracy can be provided.
  • the frequency of the refresh operation to the nodes N1 (1) to N1 (t) can be reduced, the power consumption of the semiconductor device can be reduced.
  • transistors Tr2 (1) to Tr2 (t) transistors including silicon in a semiconductor layer (hereinafter referred to as Si transistors) may be used.
  • Si transistors silicon in a semiconductor layer
  • hydrogenated amorphous silicon is preferably used as the silicon because it can be formed over a large substrate with high yield.
  • OS transistors may be used as the transistors Tr3 (1) to Tr3 (t). Accordingly, all transistors provided in the product arithmetic circuit MAC [i] can be OS transistors, and the manufacturing process of the semiconductor device can be shortened. In other words, since the production time of the semiconductor device can be reduced, the number of production per certain time can be increased. Note that the transistors Tr1 (1) to Tr1 (t), the transistors Tr2 (1) to Tr2 (t), and the transistors Tr3 (1) to Tr3 (t) may all be Si transistors.
  • Data such as image data is supplied to the memory MW [i] (1) to the memory MW [i] (t) via the wiring RW.
  • the other potential of the pair of electrodes of the capacitors C1 (1) to C1 (t) is , Depending on the supplied data. Accordingly, the potentials of the nodes N1 (1) to N1 (t) change due to capacitive coupling caused by the capacitances of the capacitive elements C1 (1) to C1 (t).
  • the potentials of the nodes N1 (1) to N1 (t) are potentials corresponding to data such as image data and data serving as a weighting factor. That is, the memory cells MW [i] (1) to MW [i] (t) hold data corresponding to data such as image data and data serving as weighting factors.
  • first data data supplied from the wiring WD to the memories MW [i] (1) to MW [i] (t)
  • first data that is, for example, data serving as a weighting factor can be referred to as first data.
  • second data data supplied from the wiring RW to the memories MW [i] (1) to MW [i] (t)
  • second data data supplied from the wiring RW to the memories MW [i] (1) to MW [i] (t)
  • second data data supplied from the wiring RW to the memories MW [i] (1) to MW [i] (t)
  • second data data supplied from the wiring RW to the memories MW [i] (1) to MW [i] (t)
  • second data data supplied from the wiring RW to the memories MW [i] (1) to MW [i] (t)
  • third data data corresponding to the first data and the second data
  • the third data can be data corresponding to the product of the first data and the second data, for example.
  • the third data is output to the outside of the product operation circuit MAC [i] via the wiring RD.
  • the controller CNT has a function of controlling the conduction state of the transistor Tr3 (g) by controlling the potential of the wiring SE (g) based on the attribute information 32. For example, when the attribute information 32 [g] is input to the controller CNT and the transistors Tr3 (1) to Tr3 (t) are n-channel transistors, a high potential is applied to the wiring SE (g). A low potential is applied to the other wirings SE. Thereby, the third data can be read from the memory MW [i] (g) in which the weighting coefficient corresponding to the attribute information 32 [g] is held.
  • FIG. 17 shows the product operation circuit MAC [i] and the controller CNT, and the wiring electrically connected to the product operation circuit MAC [i] and the controller CNT, and shows a configuration different from FIG. .
  • FIG. 17 shows the case where the product operation circuit MAC [i] has the memory MW [i] (1) and the memory MW [i] (2), but the product operation circuit MAC [i] You may have three or more [i].
  • the 17 has a memory MW [i] (1), a memory MW [i] (2), a transistor Tr4, and a capacitor C2. It can be said that the transistor Tr4 and the capacitor C2 are shared by the memory MW [i] (1) and the memory MW [i] (2).
  • the product operation circuit MAC [i] may include three or more memories MW [i]. In this case, the transistor Tr4 and the capacitor C2 can be shared by the three or more memories MW [i].
  • the memory MW [i] (1) includes a transistor Tr1 (1), a transistor Tr2 (1), and a capacitor C1 (1).
  • the memory MW [i] (2) includes a transistor Tr1 (2), a transistor Tr2 (2), and a capacitor C1 (2).
  • One of the source and the drain of the transistor Tr1 (1) is electrically connected to the gate of the transistor Tr2 (1) and one of the pair of electrodes of the capacitor C1 (1).
  • One of the source and the drain of the transistor Tr1 (2) is electrically connected to the gate of the transistor Tr2 (2) and one of the pair of electrodes of the capacitor C1 (2).
  • the other of the source and the drain of the transistor Tr1 (1) and the other of the source and the drain of the transistor Tr1 (2) are electrically connected to the wiring WD.
  • the gate of the transistor Tr1 (1) is electrically connected to the wiring WW (1).
  • a gate of the transistor Tr1 (2) is electrically connected to the wiring WW (2).
  • One of the source and the drain of the transistor Tr2 (1) is electrically connected to one of the source and the drain of the transistor Tr2 (2), the gate of the transistor Tr4, and one of the pair of electrodes of the capacitor C2.
  • the other of the source and the drain of the transistor Tr2 (1) and the other of the source and the drain of the transistor Tr2 (2) are electrically connected to the wiring VRSL.
  • a high potential or a low potential can be applied to the wiring VRSL.
  • One of the source and the drain of the transistor Tr4 is electrically connected to the wiring RD.
  • the other of the source and the drain of the transistor Tr4 is electrically connected to the wiring VSSL.
  • the other of the pair of electrodes of the capacitor C1 (1) is electrically connected to the wiring SE (1).
  • the other of the pair of electrodes of the capacitor C1 (2) is electrically connected to the wiring SE (2).
  • the other of the pair of electrodes of the capacitor C2 is electrically connected to the wiring RW.
  • a node to which one of the source or the drain of the transistor Tr1 (1), the gate of the transistor Tr2 (1), and one of the pair of electrodes of the capacitor C1 (1) is connected is referred to as a node N1 (1).
  • a node to which one of the source or the drain of the transistor Tr1 (2), the gate of the transistor Tr2 (2), and one of the pair of electrodes of the capacitor C1 (2) is connected is referred to as a node N1 (2).
  • a node to which one of the source or drain of the transistor Tr2 (1), one of the source or drain of the transistor Tr2 (2), the gate of the transistor Tr4, and one of the pair of electrodes of the capacitor C2 is connected is referred to as a node N2.
  • the transistor Tr4 is preferably an OS transistor similarly to the transistor Tr1 (1), the transistor Tr1 (2), the transistor Tr2 (1), and the transistor Tr2 (2). Accordingly, when the transistor Tr4 is in a non-conductive state, the charge held at the node N2 can be prevented from leaking from the gate of the transistor Tr4, so that a product-sum operation circuit with high calculation accuracy can be provided. it can. In addition, since the frequency of the refresh operation to the node N2 can be reduced, the power consumption of the semiconductor device can be reduced.
  • FIG. 18 is a timing chart illustrating an example of an operation method when the semiconductor device having the product operation circuit MAC [i] having the configuration illustrated in FIG. 17 performs learning. Specifically, as the weighting factor, the write data in the memory MW [i] (1) the potential V 11 included in the product computation circuit MAC [i], the memory MW [i] (2) The data of the potential V 12 Indicates the case of writing.
  • FIG. 18 illustrates a wiring WD, a wiring WW (1), a wiring WW (2), a wiring RW, a wiring SE (1), a wiring SE (2), a wiring VRSL, a node N1 (1), a node N1 (2), and The potential of the node N2 is shown.
  • the potential VSS is a low potential
  • the potential VDD is a high potential
  • the potential VH is higher than the potential VDD.
  • the potentials of the wiring WD, the wiring WW (1), the wiring WW (2), the wiring RW, the wiring VRSL, the node N1 (1), the node N1 (2), and the node N2 are set to a low potential.
  • the potentials of the wiring SE (1) and the wiring SE (2) are set high.
  • the potential of the wiring WD, and the potential V 11 is a potential corresponding to data held in the memory MW [i] (1). Further, after the potential of the wiring WD and the potential V 11, the potential of the wiring WW (1) to a high potential. Thus, the transistor Tr1 (1) is turned on, and the potential of the node N1 (1) becomes the potential V 11 or a potential corresponding to the potential V 11 . As a result, data serving as a weighting coefficient is written in the memory MW [i] (1).
  • the potential V 11 for example potential VSS or more, and may be less potential VDD.
  • FIG. 18 shows a case where the potential of the node N1 (1) becomes V 11.
  • the potential of the wiring WW (1) is set to a low potential. Accordingly, the potential of the node N1 (1) is held, and the data written in the memory MW [i] (1) is held. In addition, after the potential of the wiring WW (1) is set low, the potential of the wiring WD is set low.
  • the potential of the wiring WD, and memory MW [i] potential V 12 is a potential corresponding to data held in (2). Further, after the potential of the wiring WD and the potential V 12, the potential of the wiring WW (2) a high potential. Thus, the transistor Tr1 (2) is turned on, and the potential of the node N1 (2) becomes the potential V 12 or a potential corresponding to the potential V 12 . As a result, data serving as a weighting factor is written in the memory MW [i] (2). Note that the potential V 12, for example potential VSS or more, and may be less potential VDD. Further, FIG. 18 shows a case where the potential of the node N1 (2) is V 12.
  • the potential of the wiring WW (2) is set to a low potential. Accordingly, the potential of the node N1 (2) is held, and the data written in the memory MW [i] (2) is held. Further, after the potential of the wiring WW (2) is set to a low potential, the potential of the wiring WD is set to a low potential.
  • the potential of the wiring SE (1) and the potential of the wiring SE (2) are set low. Since the other potential of the pair of electrodes of the capacitor C1 (1) is decreased, the potential of the node N1 (1) is decreased. In addition, since the other potential of the pair of electrodes of the capacitor C1 (2) is decreased, the potential of the node N1 (2) is decreased.
  • the decrease in the potential of the node N1 (1) is calculated by capacitive coupling caused by the capacitance of the capacitor C1 (1), the gate capacitance of the transistor Tr2 (1), the parasitic capacitance, and the like.
  • the decrease in the potential of the node N1 (2) is calculated by capacitive coupling caused by the capacitance of the capacitor C1 (2), the gate capacitance of the transistor Tr2 (2), the parasitic capacitance, and the like.
  • the description is made on the assumption that the decrease in the potential of the wiring SE (1) is equal to the decrease in the potential of the node N1 (1) in order to avoid complicated description. This corresponds to the capacitive coupling coefficient being 1 at the node N1 (1).
  • description is made assuming that the decrease in potential of the wiring SE (2) is equal to the decrease in potential of the node N1 (2). This corresponds to the capacitive coupling coefficient being 1 at the node N1 (2).
  • the potential of the node N1 (1) and the potential of the node N1 (2) are, for example, equal to or lower than the potential VSS. Specifically, when the potential of the node N1 (1) when the potential of the wiring SE (1) is a high potential is the potential V 11, the wiring SE (1) potential and the low potential node N1 (1) becomes V 11 + VSS ⁇ VDD. The potential when the potential of the node N1 (2) when the potential of the wiring SE (2) is a high potential is the potential V 12, when the potential of the wiring SE (2) and a low potential node N1 (2) becomes V 12 + VSS ⁇ VDD. Thus, the transistor Tr2 (1) and the transistor Tr2 (2) are turned off.
  • the above is an example of the operation method when the product arithmetic circuit MAC [i] having the configuration shown in FIG. 17 performs learning.
  • FIG. 19 illustrates an example of an operation method of the product operation circuit MAC [i] after the product operation circuit MAC [i] having the configuration illustrated in FIG. 17 performs learning using the method illustrated in FIG. 18 to acquire the first data. It is a timing chart which shows. Specifically, it is a timing chart showing an example of an operation of inputting second data such as image data to the product operation circuit MAC [i] and outputting third data.
  • FIG. 19 similarly to FIG. 18, the wiring WD, the wiring WW (1), the wiring WW (2), the wiring RW, the wiring SE (1), the wiring SE (2), the wiring VRSL, the node N1 (1), and the node N1 (2) and the potential of the node N2 are shown.
  • the potentials of the wiring WD, the wiring WW (1), the wiring WW (2), the wiring RW, the wiring SE (1), the wiring SE (2), and the node N2 are set to a low potential.
  • the potential of the wiring VRSL is set to a high potential. Note that the potential of the node N1 (1) and the potential of the node N1 (2) are the same as the potential after the time T04 illustrated in FIG. 18, for example, the potential VSS or lower.
  • Times T10 to T13 indicate the case where the data held in the memory MW [i] (1) is used as the first data, for example, the case where the attribute information 32 [1] is input to the controller CNT.
  • the data of the potential V 21 is input to the product operation circuit MAC [i] as the second data.
  • the potential V 21 is a potential corresponding to the second data. Since the other potential of the pair of electrodes of the capacitive element C2 changes, the potential of the node N2 changes due to capacitive coupling caused by the capacitance of the capacitive element C2, and the like.
  • FIG. 19 when the potential of the node N2 is V 21, i.e. capacitive coupling coefficients of the node N2 shows the case 1.
  • the potential of the wiring SE (1) is set to a high potential. Since the other potential of the pair of electrodes of the capacitor C1 (1) increases, the potential of the node N1 (1) increases due to capacitive coupling caused by the capacitance of the capacitor C1 (1) and the like. Specifically, it is the same potential as the potential after time T04 shown in FIG. 18, that is, the potential V 11 or a potential corresponding to the potential V 11 . In FIG 19, illustrates a case where the potential of the node N1 (1) becomes V 11.
  • a potential V 31 is a potential corresponding to the potential V 11 and the potential V 21.
  • the third data is read from the wiring RD.
  • the current I flowing through the wiring RD when the third data is read can be expressed by the following equation when the transistor Tr4 operates in the saturation region.
  • k is a constant determined by the channel length, channel width, mobility, capacitance of the gate insulating film, and the like of the transistor Tr4.
  • the threshold voltage of the transistor Tr4 is 0V.
  • the third data can be data corresponding to the product of the first data and the second data.
  • the offset correction can be performed by a circuit not shown in FIG.
  • the threshold voltage is not 0 V
  • the current value depending on the threshold voltage can be canceled by the offset correction.
  • the potential of the wiring SE (1) is set to the potential VH, that is, a potential higher than the potential VDD.
  • the potential of the node N1 (1) rises and becomes, for example, a potential equal to or higher than the potential VDD. Therefore, regardless of the magnitude of the potential V 11, the transistor Tr2 (1) is made conductive.
  • the potential of the wiring RW and the potential of the wiring VRSL are set low. Thus, the potential of the node N2 is reset and becomes a low potential.
  • the potential of the wiring SE (1) is set to a low potential. Accordingly, the potential of the node N1 (1) becomes, for example, the potential at the time T10 to the time T11, for example, the potential VSS or less. Thus, the transistor Tr2 (1) is turned off. After that, the potential of the wiring VRSL is set to a high potential.
  • Times T20 to T23 indicate a case where the data held in the memory MW [i] (2) is used as the first data, for example, when the attribute information 32 [2] is input to the controller CNT.
  • the second data inputs the data of the potential V 22 to the product operation circuit MAC [i].
  • Potential V 22 for example potential VSS or more and the less potential VDD.
  • the potential V 22 is a potential corresponding to the second data. Since the other potential of the pair of electrodes of the capacitive element C2 changes, the potential of the node N2 changes due to capacitive coupling caused by the capacitance of the capacitive element C2, and the like.
  • the potential of the wiring SE (2) is set to a high potential. Since the other potential of the pair of electrodes of the capacitor C1 (2) is increased, the potential of the node N1 (2) is increased by capacitive coupling caused by the capacitance of the capacitor C1 (2) and the like. Specifically, it becomes the same potential as the potential after time T04 shown in FIG. 18, that is, the potential V 12 or the potential corresponding to the potential V 12 . In FIG 19, illustrates a case where the potential of the node N1 (2) is V 12.
  • the third data is read from the wiring RD.
  • the third data can be data corresponding to the product of the first data and the second data.
  • the potential of the wiring SE (2) is set higher than the potential VH, that is, the potential VDD.
  • the potential of the node N1 (2) rises and becomes, for example, a potential equal to or higher than the potential VDD. Therefore, regardless of the magnitude of the potential V 12, the transistor Tr2 (2) is conductive.
  • the potential of the wiring RW and the potential of the wiring VRSL are set low. Thus, the potential of the node N2 is reset and becomes a low potential.
  • the potential of the wiring SE (2) is set to a low potential. Accordingly, the potential of the node N1 (2) becomes, for example, the potential at the time T10 to the time T11, for example, the potential VSS or less. Accordingly, the transistor Tr2 (2) is turned off. After that, the potential of the wiring VRSL is set to a high potential.
  • the above is an example of the operation method of the product operation circuit MAC [i] after the product operation circuit MAC [i] having the configuration illustrated in FIG. 17 performs learning by the method illustrated in FIG. 18 and acquires the first data. .
  • This embodiment mode can be combined with any of the other embodiment modes as appropriate.
  • FIG. 20 illustrates an example of a cross-sectional structure of the display device 1400.
  • a transmissive liquid crystal element 1420 is applied as a display element is shown.
  • the substrate 1412 side is the display surface side.
  • the display device 1400 has a structure in which a liquid crystal 1422 is sandwiched between a substrate 1411 and a substrate 1412.
  • the liquid crystal element 1420 includes a conductive layer 1421 provided on the substrate 1411 side, a conductive layer 1423 provided on the substrate 1412 side, and a liquid crystal 1422 sandwiched therebetween.
  • an alignment film 1424 a is provided between the liquid crystal 1422 and the conductive layer 1421
  • an alignment film 1424 b is provided between the liquid crystal 1422 and the conductive layer 1423.
  • the conductive layer 1421 functions as a pixel electrode.
  • the conductive layer 1423 functions as a common electrode or the like.
  • each of the conductive layers 1421 and 1423 has a function of transmitting visible light. Therefore, the liquid crystal element 1420 is a transmissive liquid crystal element.
  • a colored layer 1441 and a light shielding layer 1442 are provided on the surface of the substrate 1412 on the substrate 1411 side.
  • An insulating layer 1426 is provided to cover the coloring layer 1441 and the light-blocking layer 1442, and a conductive layer 1423 is provided to cover the insulating layer 1426.
  • the colored layer 1441 is provided in a region overlapping with the conductive layer 1421.
  • the light-blocking layer 1442 is provided to cover the transistor 1430 and the connection portion 1438.
  • a polarizing plate 1439a is disposed outside the substrate 1411, and a polarizing plate 1439b is disposed outside the substrate 1412. Further, a backlight unit 1490 is provided outside the polarizing plate 1439a.
  • the substrate 1412 side is the display surface side.
  • a transistor 1430, a capacitor 1460, and the like are provided over the substrate 1411.
  • the transistor 1430 functions as a pixel selection transistor.
  • the transistor 1430 is connected to the liquid crystal element 1420 through the connection portion 1438.
  • a transistor 1430 shown in FIG. 20 is a so-called bottom-gate / channel-etched transistor.
  • the transistor 1430 includes a conductive layer 1431 functioning as a gate electrode, an insulating layer 1434 functioning as a gate insulating layer, a semiconductor layer 1432, and a pair of conductive layers 1433a and 1433b functioning as a source electrode and a drain electrode.
  • a portion of the semiconductor layer 1432 which overlaps with the conductive layer 1431 functions as a channel formation region.
  • the semiconductor layer 1432 is connected to the conductive layers 1433a and 1433b.
  • the capacitor element 1460 includes a conductive layer 1431a, an insulating layer 1434, and a conductive layer 1433b.
  • An insulating layer 1482 and an insulating layer 1481 are stacked so as to cover the transistor 1430 and the like.
  • a conductive layer 1421 functioning as a pixel electrode is provided over the insulating layer 1481.
  • the conductive layer 1421 and the conductive layer 1433b are electrically connected through openings provided in the insulating layer 1481 and the insulating layer 1482.
  • the insulating layer 1481 preferably has a function as a planarization layer.
  • the insulating layer 1482 preferably has a function as a protective film which suppresses diffusion of impurities or the like into the transistor 1430 and the like.
  • an inorganic insulating material can be used for the insulating layer 1482 and an organic insulating material can be used for the insulating layer 1481.
  • FIG. 21 illustrates an example in which the colored layer 1441 is provided on the substrate 1411 side. Accordingly, the configuration on the substrate 1412 side can be simplified.
  • the insulating layer 1481 may not be provided.
  • FIG. 22 is a schematic cross-sectional view of a display device having a liquid crystal element to which an FFS (Fringe Field Switching) mode is applied.
  • FFS Frringe Field Switching
  • the liquid crystal element 1420 includes a conductive layer 1421 that functions as a pixel electrode, and a conductive layer 1423 that overlaps with the conductive layer 1421 with the insulating layer 1483 interposed therebetween.
  • the conductive layer 1423 has a slit-like or comb-like upper surface shape.
  • a capacitor is formed in a portion where the conductive layer 1421 and the conductive layer 1423 overlap with each other, and this can be used as the capacitor 1460. Therefore, since the area occupied by the pixels can be reduced, a high-definition display device can be realized. In addition, the aperture ratio can be improved.
  • the conductive layer 1423 functioning as a common electrode is positioned on the liquid crystal 1422 side, but the conductive layer 1421 functioning as a pixel electrode is positioned on the liquid crystal 1422 side as shown in FIG. Good. At this time, the conductive layer 1421 has a slit-like or comb-like top shape.
  • the manufacturing cost can be reduced as the photolithography process in the manufacturing process is smaller, that is, as the number of photomasks is smaller.
  • a formation process of the conductive layer 1431 and the like, a formation process of the semiconductor layer 1432, a formation process of the conductive layer 1433 a and the like, a formation process of the opening serving as the connection portion 1438, And the conductive layer 1421 can be manufactured through a total of five photolithography steps. That is, a backplane substrate can be manufactured using five photomasks.
  • a backplane substrate can be manufactured using five photomasks.
  • a total of four photomasks can be reduced compared to the case where they are formed by a photolithography method.
  • a semiconductor containing silicon can be used for a semiconductor layer 1432 of a transistor described below.
  • the semiconductor containing silicon hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like can be used, for example.
  • it is preferable to use hydrogenated amorphous silicon because it can be formed over a large substrate with high yield.
  • the display device of one embodiment of the present invention can perform favorable display even with a transistor to which amorphous silicon with relatively low field-effect mobility is applied.
  • the transistor illustrated in FIG. 24A includes a pair of impurity semiconductor layers 1435 functioning as a source region and a drain region.
  • the impurity semiconductor layer 1435 is provided between the semiconductor layer 1432 and the conductive layer 1433a and between the semiconductor layer 1432 and the conductive layer 1433b.
  • the semiconductor layer 1432 and the impurity semiconductor layer 1435 are provided in contact with each other, and the impurity semiconductor layer 1435 and the conductive layer 1433a or the conductive layer 1433b are provided in contact with each other.
  • the impurity semiconductor film included in the impurity semiconductor layer 1435 is formed using a semiconductor to which an impurity element imparting one conductivity type is added.
  • a semiconductor to which an impurity element imparting one conductivity type is added includes, for example, silicon to which P or As is added.
  • B can be added as the impurity element imparting one conductivity type, but the transistor is preferably n-type.
  • the impurity semiconductor layer may be formed using an amorphous semiconductor or a crystalline semiconductor such as a microcrystalline semiconductor.
  • the transistor illustrated in FIG. 24B includes a semiconductor layer 1437 between the semiconductor layer 1432 and the impurity semiconductor layer 1435.
  • the semiconductor layer 1437 may be formed using a semiconductor film similar to the semiconductor layer 1432.
  • the semiconductor layer 1437 can function as an etching stopper for preventing the semiconductor layer 1432 from being lost by etching when the impurity semiconductor layer 1435 is etched. Note that although FIG. 24B illustrates an example in which the semiconductor layer 1437 is separated to the left and right, part of the semiconductor layer 1437 may cover a channel formation region of the semiconductor layer 1432.
  • the semiconductor layer 1437 may contain a lower concentration of impurities than the impurity semiconductor layer 1435. Accordingly, the semiconductor layer 1437 can function as an LDD (Lightly Doped Drain) region, and hot carrier deterioration when the transistor is driven can be suppressed.
  • LDD Lightly Doped Drain
  • an insulating layer 1484 is provided over a channel formation region of the semiconductor layer 1432.
  • the insulating layer 1484 functions as an etching stopper when the impurity semiconductor layer 1435 is etched.
  • the transistor illustrated in FIG. 24D includes a semiconductor layer 1432p instead of the semiconductor layer 1432.
  • the semiconductor layer 1432p includes a semiconductor film with high crystallinity.
  • the semiconductor layer 1432p includes a polycrystalline semiconductor or a single crystal semiconductor.
  • the transistor illustrated in FIG. 24E includes a semiconductor layer 1432p in a channel formation region of the semiconductor layer 1432.
  • the transistor illustrated in FIG. 24E can be formed by being locally crystallized by irradiating a semiconductor film serving as the semiconductor layer 1432 with a laser beam or the like. Thereby, a transistor with high field effect mobility can be realized.
  • the transistor illustrated in FIG. 24F includes a crystalline semiconductor layer 1432p in a channel formation region of the semiconductor layer 1432 of the transistor illustrated in FIG.
  • the transistor illustrated in FIG. 24G includes a crystalline semiconductor layer 1432p in a channel formation region of the semiconductor layer 1432 of the transistor illustrated in FIG.
  • substrate As the substrate included in the display device, a material having a flat surface can be used. A substrate that extracts light from the display element is formed using a material that transmits the light. For example, materials such as glass, quartz, ceramic, sapphire, and organic resin can be used.
  • the display panel can be reduced in weight and thickness.
  • a flexible display panel can be realized by using a flexible substrate.
  • glass that is thin enough to be flexible can be used for the substrate.
  • a composite material in which glass and a resin material are bonded to each other with an adhesive layer may be used.
  • the transistor includes a conductive layer that functions as a gate electrode, a semiconductor layer, a conductive layer that functions as a source electrode, a conductive layer that functions as a drain electrode, and an insulating layer that functions as a gate insulating layer.
  • the structure of the transistor included in the display device of one embodiment of the present invention there is no particular limitation on the structure of the transistor included in the display device of one embodiment of the present invention.
  • a planar transistor, a staggered transistor, or an inverted staggered transistor may be used.
  • a top-gate or bottom-gate transistor structure may be employed.
  • gate electrodes may be provided above and below the channel.
  • crystallinity of the semiconductor material used for the transistor there is no particular limitation on the crystallinity of the semiconductor material used for the transistor, and either an amorphous semiconductor or a semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor partially including a crystal region) is used. May be used. It is preferable to use a crystalline semiconductor because deterioration of transistor characteristics can be suppressed.
  • silicon can be used for the semiconductor in which the channel of the transistor is formed.
  • silicon it is particularly preferable to use amorphous silicon.
  • amorphous silicon By using amorphous silicon, a transistor can be formed over a large substrate with high yield, and the mass productivity is excellent.
  • silicon having crystallinity such as microcrystalline silicon, polycrystalline silicon, or single crystal silicon can be used.
  • polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and higher reliability than amorphous silicon.
  • the bottom-gate transistor exemplified in this embodiment is preferable because the number of manufacturing steps can be reduced.
  • amorphous silicon can be used at a lower temperature than polycrystalline silicon, it is possible to use a material having low heat resistance as a material for wiring, electrodes, and substrates below the semiconductor layer. Can widen the choice of materials. For example, a glass substrate having a very large area can be suitably used.
  • a top-gate transistor is preferable because an impurity region can be easily formed in a self-aligning manner and variation in characteristics can be reduced. In this case, it may be particularly suitable when polycrystalline silicon, single crystal silicon, or the like is used.
  • Conductive layer In addition to the gate, source, and drain of a transistor, materials that can be used for conductive layers such as various wirings and electrodes constituting a display device include aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, A metal such as tantalum or tungsten, or an alloy containing this as a main component can be used. A film containing any of these materials can be used as a single layer or a stacked structure.
  • Two-layer structure to stack, two-layer structure to stack copper film on titanium film, two-layer structure to stack copper film on tungsten film, titanium film or titanium nitride film, and aluminum film or copper film on top of it A three-layer structure for forming a titanium film or a titanium nitride film thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film stacked thereon, and a molybdenum film or a There is a three-layer structure for forming a molybdenum nitride film.
  • an oxide such as indium oxide, tin oxide, or zinc oxide may be used. Further, it is
  • a light-transmitting conductive material that can be used for conductive layers such as various wirings and electrodes constituting a display device includes indium oxide, indium tin oxide, A conductive oxide such as indium zinc oxide, zinc oxide, zinc oxide to which gallium is added, or graphene can be used.
  • a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or an alloy material containing the metal material can be used.
  • a nitride (eg, titanium nitride) of the metal material may be used.
  • a metal material or an alloy material (or a nitride thereof) it may be thin enough to have a light-transmitting property.
  • a stacked film of the above materials can be used as a conductive layer.
  • a laminated film of an alloy of silver and magnesium and indium tin oxide because the conductivity can be increased.
  • conductive layers such as various wirings and electrodes constituting the display device and conductive layers (conductive layers functioning as pixel electrodes and common electrodes) included in the display element.
  • Insulating materials that can be used for each insulating layer include, for example, resins such as acrylic and epoxy, resins having a siloxane bond such as silicone, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, and the like Inorganic insulating materials can also be used.
  • the low water-permeable insulating film examples include a film containing nitrogen and silicon such as a silicon nitride film and a silicon nitride oxide film, and a film containing nitrogen and aluminum such as an aluminum nitride film.
  • a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like may be used.
  • liquid crystal element for example, a liquid crystal element to which a vertical alignment (VA: Vertical Alignment) mode is applied can be used.
  • VA Vertical Alignment
  • MVA Multi-Domain Vertical Alignment
  • PVA Power Planed Vertical Alignment
  • ASV Advanced Super View
  • liquid crystal elements to which various modes are applied can be used as the liquid crystal elements.
  • TN Transmission Nematic
  • IPS In-Plane-Switching
  • FFS Ringe Field Switching
  • ASM Analy Symmetrical Aligned Micro-cell
  • the liquid crystal element is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal.
  • the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field).
  • a thermotropic liquid crystal a low molecular liquid crystal
  • a polymer liquid crystal a polymer dispersed liquid crystal
  • PNLC polymer network type liquid crystal
  • Ferroelectric liquid crystals antiferroelectric liquid crystals, and the like can be used.
  • These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.
  • liquid crystal material either a positive type liquid crystal or a negative type liquid crystal may be used, and an optimal liquid crystal material may be used according to the mode and design to be applied.
  • an alignment film can be provided to control the alignment of the liquid crystal.
  • liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used.
  • the blue phase is one of the liquid crystal phases.
  • a liquid crystal composition mixed with several percent by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range.
  • a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and optical isotropy.
  • a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependency. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. .
  • liquid crystal element there are a transmissive liquid crystal element, a reflective liquid crystal element, a transflective liquid crystal element, and the like.
  • a transmissive liquid crystal element can be particularly preferably used.
  • a backlight is provided outside the polarizing plate.
  • the backlight may be a direct type backlight or an edge light type backlight. It is preferable to use a direct-type backlight including an LED (Light Emitting Diode) because local dimming is facilitated and contrast can be increased.
  • An edge light type backlight is preferably used because the thickness of the module including the backlight can be reduced.
  • see-through display can be performed by turning off the edge-light type backlight.
  • Examples of materials that can be used for the colored layer include metal materials, resin materials, resin materials containing pigments or dyes, and the like.
  • the material that can be used for the light-shielding layer include carbon black, titanium black, metal, metal oxide, and composite oxide containing a solid solution of a plurality of metal oxides.
  • the light shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal.
  • a stacked film of a film containing a material for the colored layer can be used for the light shielding layer.
  • a stacked structure of a film including a material used for a colored layer that transmits light of a certain color and a film including a material used for a colored layer that transmits light of another color can be used. It is preferable to use a common material for the coloring layer and the light-shielding layer because the apparatus can be shared and the process can be simplified.
  • a display device using a liquid crystal element as a display element is described in this embodiment mode, a light-emitting element can also be used as a display element.
  • This embodiment mode can be combined with any of the other embodiment modes as appropriate.
  • a polycrystalline silicon layer In order to form a polycrystalline silicon layer with good crystallinity, it is preferable to provide an amorphous silicon layer on a substrate and crystallize the amorphous silicon layer by irradiating it with laser light.
  • a polycrystalline silicon layer can be formed in a desired region on the substrate by using a laser beam as a linear beam and moving the substrate while irradiating the amorphous silicon layer with the linear beam.
  • the method using a linear beam has a relatively good throughput.
  • a laser beam is irradiated a plurality of times while moving relatively to a certain region, variations in crystallinity are likely to occur due to fluctuations in the output of the laser beam and changes in the beam profile resulting therefrom.
  • a semiconductor layer crystallized by the above method is used for a transistor included in a pixel of a display device, a random stripe pattern due to variation in crystallinity may be seen when an image is displayed.
  • the length of the linear beam is ideally longer than the length of one side of the substrate, but the length of the linear beam is limited by the output of the laser oscillator and the configuration of the optical system. Therefore, in the processing of a large substrate, it is realistic to irradiate the laser by folding the substrate surface. For this reason, a region where laser light is overlapped and irradiated is generated. Since the crystallinity of the region is easily different from the crystallinity of other regions, display unevenness may occur in the region.
  • the amorphous silicon layer formed on the substrate may be locally irradiated with laser to be crystallized. With local laser irradiation, it is easy to form a polycrystalline silicon layer with little variation in crystallinity.
  • FIG. 25A is a diagram for explaining a method of locally irradiating an amorphous silicon layer formed on a substrate with laser.
  • Laser light 626 emitted from the optical system unit 621 is reflected by the mirror 622 and enters the microlens array 623.
  • the microlens array 623 condenses the laser light 626 to form a plurality of laser beams 627.
  • the substrate 630 on which the amorphous silicon layer 640 is formed is fixed to the stage 615.
  • a plurality of polycrystalline silicon layers 641 can be formed at the same time.
  • each microlens included in the microlens array 623 is provided in accordance with the pixel pitch of the display device. Alternatively, it may be provided at intervals of an integer multiple of the pixel pitch. In either case, a polycrystalline silicon layer can be formed in a region corresponding to all pixels by repeating laser irradiation and movement of the stage 615 in the X or Y direction.
  • the microlens array 623 has microlenses of I rows and J columns (I and J are natural numbers) at a pixel pitch, first, laser light is irradiated at a predetermined start position, and a polycrystalline silicon layer of I rows and J columns Can be formed. Then, it is moved by a distance of J columns in the row direction and irradiated with laser light, and further, a polycrystalline silicon layer 641 of M rows and N columns is formed, thereby forming a polycrystalline silicon layer 641 of I rows and 2J columns. be able to. By repeating this process, a plurality of polycrystalline silicon layers 641 can be formed in a desired region. In the case of performing the laser irradiation process by turning back, the laser irradiation is performed by moving the distance by J columns in the row direction, and the movement of the distance by I rows in the column direction and the laser light irradiation are repeated.
  • a polycrystalline silicon layer can be formed at a pixel pitch even by a method of performing laser irradiation while moving the stage 615 in one direction.
  • the size of the laser beam 627 can be, for example, an area that includes the entire semiconductor layer of one transistor. Alternatively, the area can be such that the entire channel region of one transistor is included. Alternatively, the area can be such that part of the channel region of one transistor is included. These may be used properly according to the electrical characteristics of the required transistors.
  • the laser beam 627 can have an area enough to include the entire semiconductor layer of each transistor in one pixel.
  • the laser beam 627 may have an area enough to include the entire semiconductor layer of the transistor included in the plurality of pixels.
  • a mask 624 may be provided between the mirror 622 and the microlens array 623.
  • the mask 624 is provided with a plurality of openings corresponding to each microlens. The shape of the opening can be reflected in the shape of the laser beam 627.
  • a circular opening as shown in FIG. 26A
  • a circular laser beam 627 can be obtained.
  • a rectangular laser beam 627 can be obtained.
  • the mask 624 is effective, for example, when it is desired to crystallize only the channel region of the transistor. Note that the mask 624 may be provided between the optical system unit 621 and the mirror 622 as shown in FIG.
  • FIG. 25B is a perspective view illustrating a main configuration of a laser crystallization apparatus that can be used in the local laser irradiation process described above.
  • the laser crystallization apparatus includes a moving mechanism 612, a moving mechanism 613, and a stage 615 that are components of the XY stage. Further, a laser oscillator 620 for shaping the laser beam 627, an optical system unit 621, a mirror 622, and a microlens array 623 are provided.
  • the moving mechanism 612 and the moving mechanism 613 have a function of reciprocating linear motion in the horizontal direction.
  • a mechanism for supplying power to the moving mechanism 612 and the moving mechanism 613 for example, a ball screw mechanism 616 driven by a motor can be used. Since the moving directions of the moving mechanism 612 and the moving mechanism 613 intersect perpendicularly, the stage 615 fixed to the moving mechanism 613 can be freely moved in the X direction and the Y direction.
  • the stage 615 has a fixing mechanism such as a vacuum suction mechanism, and can fix the substrate 630 and the like. Moreover, the stage 615 may have a heating mechanism as needed. Although not shown, the stage 615 includes a pusher pin and its vertical mechanism, and the substrate 630 and the like can be moved up and down when the substrate 630 and the like are carried in and out.
  • a fixing mechanism such as a vacuum suction mechanism
  • the stage 615 may have a heating mechanism as needed.
  • the stage 615 includes a pusher pin and its vertical mechanism, and the substrate 630 and the like can be moved up and down when the substrate 630 and the like are carried in and out.
  • the laser oscillator 620 is only required to output light having a wavelength and intensity suitable for the purpose of processing, and is preferably a pulse laser, but may be a CW laser.
  • a pulse laser that can emit ultraviolet light with a wavelength of 351 to 353 nm (XeF), 308 nm (XeCl), or the like can be used.
  • XeF ultraviolet light
  • XeCl 308 nm
  • a double wave (515 nm, 532 nm, etc.) or a triple wave (343 nm, 355 nm, etc.) of a solid laser (YAG laser, fiber laser, etc.) may be used.
  • a plurality of laser oscillators 620 may be provided.
  • the optical system unit 621 includes, for example, a mirror, a beam expander, a beam homogenizer, and the like, and can extend the laser light 625 output from the laser oscillator 620 while uniformizing the in-plane distribution of energy.
  • the mirror 622 for example, a dielectric multilayer mirror can be used, and the mirror 622 is installed so that the incident angle of the laser beam is about 45 °.
  • the microlens array 623 can have a shape in which a plurality of convex lenses are provided on the upper surface or upper and lower surfaces of a quartz plate.
  • This embodiment mode can be combined with any of the other embodiment modes as appropriate.
  • FIG. 27A is a top view of a semiconductor device including a transistor 200.
  • FIG. FIG. 27B is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 27A and is a cross-sectional view in the channel length direction of the transistor 200.
  • FIG. 27C is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG. 27A and is a step view in the channel width direction of the transistor 200.
  • some elements are omitted for clarity.
  • the transistor 200 includes an insulator 224 disposed over a substrate (not shown), a metal oxide 406a disposed over the insulator 224, A metal oxide 406b disposed in contact with at least a portion of the upper surface of the metal oxide 406a, an insulator 412 disposed over the metal oxide 406b, and a conductor 404a disposed over the insulator 412; A conductor 404b disposed on the conductor 404a; an insulator 419 disposed on the conductor 404b; and an insulator 412, the conductor 404a, the conductor 404b, and a side surface of the insulator 419.
  • an insulator 225 which is in contact with the upper surface of the metal oxide 406b and in contact with a side surface of the insulator 418.
  • the top surface of the insulator 418 is preferably substantially coincident with the top surface of the insulator 419.
  • the insulator 225 is preferably provided to cover the insulator 419, the conductor 404, the insulator 418, and the metal oxide 406.
  • the metal oxide 406a and the metal oxide 406b may be collectively referred to as a metal oxide 406.
  • the transistor 200 has a structure in which the metal oxide 406a and the metal oxide 406b are stacked, the present invention is not limited to this. For example, only the metal oxide 406b may be provided.
  • the conductor 404a and the conductor 404b may be collectively referred to as the conductor 404.
  • the transistor 200 has a structure in which the conductor 404a and the conductor 404b are stacked, the present invention is not limited to this. For example, only the conductor 404b may be provided.
  • a conductor 440a is formed in contact with the inner wall of the opening of the insulator 384, and a conductor 440b is further formed inside.
  • the heights of the upper surfaces of the conductors 440a and 440b and the height of the upper surface of the insulator 384 can be approximately the same.
  • the transistor 200 has a structure in which the conductor 440a and the conductor 440b are stacked, the present invention is not limited to this. For example, only the conductor 440b may be provided.
  • a conductor 310a is formed in contact with the inner walls of the openings of the insulator 214 and the insulator 216, and a conductor 310b is formed further inside.
  • the conductor 310a is preferably in contact with the conductor 440b.
  • the heights of the upper surfaces of the conductors 310a and 310b and the height of the upper surface of the insulator 216 can be made substantially the same.
  • the transistor 200 has a structure in which the conductor 310a and the conductor 310b are stacked, the present invention is not limited to this. For example, only the conductor 310b may be provided.
  • the conductor 404 can function as a top gate, and the conductor 310 can function as a back gate.
  • the potential of the back gate may be the same as that of the top gate, or may be a ground potential or an arbitrary potential. Further, the threshold voltage of the transistor can be changed by changing the potential of the back gate independently without interlocking with the top gate.
  • the conductor 440 extends in the channel width direction like the conductor 404, and functions as a wiring for applying a potential to the conductor 310, that is, the back gate.
  • the conductor 310 is stacked over the conductor 440 functioning as a wiring for the back gate, and the conductor 310 embedded in the insulator 214 and the insulator 216 is provided, so that insulation is provided between the conductor 440 and the conductor 404.
  • the body 214, the insulator 216, and the like are provided, so that the parasitic capacitance between the conductor 440 and the conductor 404 can be reduced and the withstand voltage can be increased.
  • the switching speed of the transistor can be improved and a transistor having high frequency characteristics can be obtained. Further, by increasing the withstand voltage between the conductor 440 and the conductor 404, the reliability of the transistor 200 can be improved. Therefore, it is preferable to increase the thickness of the insulator 214 and the insulator 216. Note that the extending direction of the conductor 440 is not limited thereto, and the conductor 440 may be extended in the channel length direction of the transistor 200, for example.
  • the conductor 310a and the conductor 440a are preferably formed using a conductive material having a function of suppressing the transmission of impurities such as water or hydrogen (difficult to transmit).
  • a conductive material having a function of suppressing the transmission of impurities such as water or hydrogen (difficult to transmit).
  • impurities such as water or hydrogen (difficult to transmit).
  • tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, and a single layer or a stacked layer may be used. Thereby, it is possible to prevent impurities such as hydrogen and water from diffusing from the lower layer to the upper layer through the conductor 440 and the conductor 310.
  • the conductor 310a and the conductor 440a are a hydrogen atom, a hydrogen molecule, a water molecule, an oxygen atom, an oxygen molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2, etc.), a copper atom, or the like. It is preferable to have a function of suppressing the permeation of at least one of these impurities or oxygen (for example, oxygen atoms, oxygen molecules, etc.). The same applies to the case where a conductive material having a function of suppressing the permeation of impurities is described below. When the conductor 310a and the conductor 440a have a function of suppressing permeation of oxygen, the conductor 310b and the conductor 440b can be prevented from being oxidized and decreasing in conductivity.
  • the conductive material 310b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 310b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • the conductor 440b functions as a wiring, it is preferable to use a conductor having higher conductivity than the conductor 310b.
  • a conductor having higher conductivity for example, a conductive material mainly containing copper or aluminum can be used.
  • the conductor 440b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • the insulator 214 can function as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor from below.
  • the insulator 214 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen.
  • silicon nitride or the like is preferably used as the insulator 214.
  • impurities such as hydrogen and water can be prevented from diffusing into the upper layer than the insulator 214.
  • the insulator 214 suppresses at least one permeation of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2, and the like) and a copper atom. It preferably has a function. The same applies to the case where an insulating material having a function of suppressing the permeation of impurities is described below.
  • the insulator 214 is preferably formed using an insulating material having a function of suppressing transmission of oxygen (for example, oxygen atoms or oxygen molecules). Thereby, downward diffusion of oxygen contained in the insulator 224 and the like can be suppressed.
  • oxygen for example, oxygen atoms or oxygen molecules
  • the insulator 214 can be provided between the conductor 440 and the conductor 310.
  • a metal that easily diffuses, such as copper is used for the conductor 440b, diffusion of the metal into a layer above the insulator 214 can be prevented by providing silicon insulator or the like as the insulator 214.
  • the insulator 222 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, and for example, aluminum oxide or hafnium oxide is preferably used. Accordingly, impurities such as hydrogen and water from a lower layer than the insulator 222 can be prevented from diffusing from the insulator 222 to an upper layer. Furthermore, downward diffusion of oxygen contained in the insulator 224 and the like can be suppressed.
  • the concentration of impurities such as water, hydrogen, or nitrogen oxide in the insulator 224 is preferably reduced.
  • the amount of hydrogen desorbed from the insulator 224 is determined by the desorption amount in terms of hydrogen molecules in a temperature desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)) in the range of 50 ° C. to 500 ° C. It may be 2 ⁇ 10 15 molecules / cm 2 or less, preferably 1 ⁇ 10 15 molecules / cm 2 or less, more preferably 5 ⁇ 10 14 molecules / cm 2 or less in terms of the area of the body 224.
  • TDS Temperaturetroscopy
  • the insulator 224 is preferably formed using an insulator from which oxygen is released by heating.
  • the insulator 412 can function as a first gate insulating film, and the insulator 220, the insulator 222, and the insulator 224 can function as a second gate insulating film.
  • the transistor 200 shows a structure in which the insulator 220, the insulator 222, and the insulator 224 are stacked, the present invention is not limited to this. For example, any two layers of the insulator 220, the insulator 222, and the insulator 224 may be stacked, or any one of the layers may be used.
  • the metal oxide 406 is preferably a metal oxide that functions as an oxide semiconductor.
  • the metal oxide it is preferable to use one having an energy gap of 2 eV or more, preferably 2.5 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.
  • a transistor using a metal oxide has extremely small leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. Further, since the metal oxide can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device.
  • the metal oxide 406 preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. One or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.
  • the metal oxide 406 is an In-M-Zn oxide containing indium, the element M, and zinc is considered.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.
  • the element M may be a combination of a plurality of the aforementioned elements.
  • metal oxides containing nitrogen may be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • the atomic ratio of the element M in the constituent element is larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the metal oxide 406b.
  • the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the metal oxide 406b.
  • the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the metal oxide 406a.
  • the energy at the lower end of the conduction band of the metal oxide 406a is higher than the energy at the lower end of the conduction band in the region where the energy at the lower end of the conduction band of the metal oxide 406b is low. It is preferable to become.
  • the electron affinity of the metal oxide 406a is preferably smaller than the electron affinity in a region where the energy at the lower end of the conduction band of the metal oxide 406b is low.
  • the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined.
  • the density of defect states in the mixed layer formed at the interface between the metal oxide 406a and the metal oxide 406b is preferably lowered.
  • the metal oxide 406a and the metal oxide 406b have a common element other than oxygen (main component), a mixed layer with a low defect level density can be formed.
  • the metal oxide 406b is an In—Ga—Zn oxide
  • an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the metal oxide 406a.
  • the main path of carriers is a narrow gap portion formed in the metal oxide 406b. Since the defect level density at the interface between the metal oxide 406a and the metal oxide 406b can be reduced, the influence on carrier conduction due to interface scattering is small, and a high on-state current can be obtained.
  • the metal oxide 406 includes a region 426a, a region 426b, and a region 426c. As shown in FIG. 27B, the region 426a is sandwiched between the region 426b and the region 426c.
  • the region 426b and the region 426c are regions whose resistance is reduced by the formation of the insulator 225, and are regions having higher conductivity than the region 426a.
  • the region 426b and the region 426c are added with an impurity element such as hydrogen or nitrogen contained in the film formation atmosphere of the insulator 225.
  • an impurity element such as hydrogen or nitrogen contained in the film formation atmosphere of the insulator 225.
  • the concentration of at least one of hydrogen and nitrogen is higher in the region 426b and the region 426c than in the region 426a.
  • the concentration of hydrogen or nitrogen may be measured using secondary ion mass spectrometry (SIMS) or the like.
  • SIMS secondary ion mass spectrometry
  • the concentration of hydrogen or nitrogen in the region 426a is, for example, the vicinity of the center of the region overlapping the insulator 412 of the metal oxide 406b (for example, the distance from both side surfaces in the channel length direction of the insulator 412 of the metal oxide 406b). What is necessary is just to measure the hydrogen or nitrogen concentration of the substantially equal portion.
  • the resistance of the regions 426b and 426c is reduced by adding an element that forms oxygen vacancies or an element that combines with oxygen vacancies.
  • elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases.
  • rare gas elements include helium, neon, argon, krypton, and xenon.
  • the region 426b and the region 426c may include one or more of the above elements.
  • the atomic ratio of In to the element M is preferably approximately the same as the atomic ratio of In to the element M in the metal oxide 406b.
  • the atomic ratio of In to the element M in the regions 426b and 426c is preferably larger than the atomic ratio of In to the element M in the region 426a.
  • the metal oxide 406 can have high carrier density and low resistance by increasing the indium content.
  • the metal oxide 406b is reduced and the electric resistance of the metal oxide 406b is increased, the metal oxide is oxidized in the region 426b and the region 426c.
  • the resistance of the material 406a is sufficiently low, and the region 426b and the region 426c of the metal oxide 406 can function as a source region and a drain region.
  • FIG. 28A shows an enlarged view of the vicinity of the region 426a shown in FIG.
  • the region 426b and the region 426c are formed in a region overlapping with at least the insulator 225 of the metal oxide 406.
  • one of the region 426b and the region 426c of the metal oxide 406b can function as a source region, and the other can function as a drain region.
  • the region 426a of the metal oxide 406b can function as a channel formation region.
  • the region 426a, the region 426b, and the region 426c are formed in the metal oxide 406b and the metal oxide 406a. These regions are at least a metal oxide. What is necessary is just to form in 406b.
  • the boundary between the region 426a and the region 426b and the boundary between the region 426a and the region 426c are displayed substantially perpendicular to the upper surface of the metal oxide 406. It is not limited to this.
  • the region 426b and the region 426c may protrude to the conductor 404 side near the surface of the metal oxide 406b and recede to the insulator 225 side near the lower surface of the metal oxide 406a.
  • the region 426b and the region 426c overlap with regions where the metal oxide 406 is in contact with the insulator 225 and regions near both ends of the insulator 418 and the insulator 412. It is formed. At this time, a portion of the region 426b and the region 426c overlapping with the conductor 404 functions as a so-called overlap region (also referred to as a Lov region). With the structure having the Lov region, a high-resistance region is not formed between the channel formation region of the metal oxide 406 and the source and drain regions, so that the on-state current and mobility of the transistor can be increased. .
  • the semiconductor device described in this embodiment is not limited to this.
  • the region 426b and the region 426c may be formed in a region overlapping with the insulator 225 and the insulator 418 of the metal oxide 406.
  • the structure illustrated in FIG. 28B is a structure in which the width of the conductor 404 in the channel length direction and the width of the region 426a are approximately the same.
  • a high-resistance region is not formed between the source region and the drain region, so that the on-state current of the transistor can be increased.
  • the source region and the drain region do not overlap with the gate in the channel length direction, so that formation of unnecessary capacitance can be suppressed.
  • the insulator 412 is preferably disposed in contact with the upper surface of the metal oxide 406b.
  • the insulator 412 is preferably formed using an insulator from which oxygen is released by heating. By providing such an insulator 412 in contact with the upper surface of the metal oxide 406b, oxygen can be effectively supplied to the metal oxide 406b.
  • the concentration of impurities such as water or hydrogen in the insulator 412 is preferably reduced.
  • the thickness of the insulator 412 is preferably greater than or equal to 1 nm and less than or equal to 20 nm, and may be, for example, about 1 nm.
  • the insulator 412 preferably contains oxygen.
  • the amount of desorption of oxygen molecules per area of the insulator 412 is within the range of the surface temperature of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. 1 ⁇ 10 14 molecules / cm 2 or more, preferably 2 ⁇ 10 14 molecules / cm 2 or more, more preferably 4 ⁇ 10 14 molecules / cm 2 or more.
  • the insulator 412, the conductor 404, and the insulator 419 have a region overlapping with the metal oxide 406b.
  • the side surfaces of the insulator 412, the conductor 404a, the conductor 404b, and the insulator 419 are preferably substantially matched.
  • a conductive oxide As the conductor 404a.
  • a metal oxide that can be used as the metal oxide 406a or the metal oxide 406b can be used.
  • oxygen can be added to the insulator 412 and oxygen can be supplied to the metal oxide 406b. Accordingly, oxygen vacancies in the region 426a of the metal oxide 406 can be reduced.
  • the conductor 404b for example, a metal such as tungsten can be used.
  • a conductor that can improve conductivity of the conductor 404a by adding an impurity such as nitrogen to the conductor 404a may be used as the conductor 404b.
  • the conductor 404b is preferably formed using titanium nitride or the like.
  • the conductor 404b may have a structure in which a metal nitride such as titanium nitride and a metal such as tungsten are stacked thereover.
  • the conductor 404 having the function of a gate electrode is provided so as to cover the upper surface in the vicinity of the region 426a and the side surface in the channel width direction of the metal oxide 406b with the insulator 412 interposed therebetween. Therefore, the upper surface of the metal oxide 406b in the vicinity of the region 426a and the side surface in the channel width direction can be electrically surrounded by the electric field of the conductor 404 functioning as a gate electrode.
  • a structure of a transistor that electrically surrounds a channel formation region with an electric field of the conductor 404 is referred to as a surrounded channel (s-channel) structure.
  • a channel can be formed on the upper surface in the vicinity of the region 426a of the metal oxide 406b and the side surface in the channel width direction, a large current can flow between the source and the drain, and the current (on-current) during conduction can be reduced. Can be bigger.
  • the upper surface of the metal oxide 406b in the vicinity of the region 426a and the side surface in the channel width direction are surrounded by the electric field of the conductor 404, leakage current (off-state current) during non-conduction can be reduced.
  • an insulator 419 is disposed over the conductor 404b.
  • the side surfaces of the insulator 419, the conductor 404a, the conductor 404b, and the insulator 412 are preferably substantially matched.
  • the insulator 419 is preferably formed using an atomic layer deposition (ALD) method.
  • ALD atomic layer deposition
  • the insulator 419 can be formed with a thickness of about 1 nm to 20 nm, preferably about 5 nm to 10 nm.
  • the insulator 419 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, such as aluminum oxide or hafnium oxide. It is preferable to use it.
  • the top surface and the side surface of the conductor 404 can be covered with the insulator 419 and the insulator 418 which have a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • impurities such as water or hydrogen can be prevented from entering the metal oxide 406 through the conductor 404.
  • the insulator 418 and the insulator 419 have a function as a gate cap for protecting the gate.
  • the insulator 418 is provided in contact with the side surfaces of the insulator 412, the conductor 404, and the insulator 419.
  • the top surface of the insulator 418 is preferably substantially coincident with the top surface of the insulator 419.
  • the insulator 418 is preferably formed using an ALD method. Accordingly, the insulator 418 can be formed with a thickness of about 1 nm to 20 nm, preferably about 1 nm to 3 nm, for example, 1 nm.
  • the region 426b and the region 426c of the metal oxide 406 are formed using the impurity element added in the formation of the insulator 225.
  • an impurity element contained in the source region or the drain region may diffuse and the source region and the drain region may be electrically connected.
  • the insulator 418 by forming the insulator 418, the distance between the regions in contact with the insulator 225 of the metal oxide 406 can be increased; It is possible to prevent the drain region from being electrically conducted.
  • the film thickness is made to be approximately equal to or smaller than the miniaturized channel length, the distance between the source region and the drain region is increased more than necessary, and the resistance is increased. I can make a mistake.
  • the insulator 418 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, and for example, aluminum oxide or hafnium oxide is preferably used. Thereby, oxygen in the insulator 412 can be prevented from diffusing outside. In addition, entry of impurities such as hydrogen and water into the metal oxide 406 from an end portion of the insulator 412 can be suppressed.
  • the insulator 418 is formed using an ALD method, and then anisotropically etched, so that the insulating film 418 is in contact with the side surfaces of the insulator 412, the conductor 404, and the insulator 419. It is preferable to leave it as it is. Thereby, an insulator with a thin film thickness can be easily formed as described above. At this time, by providing the insulator 419 over the conductor 404, the insulator 412 and the conductor 404 of the insulator 418 can be removed even if the insulator 419 is partially removed by the anisotropic etching. The portion in contact with can be sufficiently left.
  • the insulator 225 is provided so as to cover the insulator 419, the insulator 418, the metal oxide 406, and the insulator 224.
  • the insulator 225 is provided in contact with upper surfaces of the insulator 419 and the insulator 418 and in contact with a side surface of the insulator 418.
  • the insulator 225 is formed by adding an impurity such as hydrogen or nitrogen to the metal oxide 406 to form the region 426b and the region 426c. Therefore, the insulator 225 preferably includes at least one of hydrogen and nitrogen.
  • the insulator 225 is preferably provided in contact with the side surface of the metal oxide 406b and the side surface of the metal oxide 406a in addition to the upper surface of the metal oxide 406b. Accordingly, in the region 426b and the region 426c, the resistance can be reduced to the side surface of the metal oxide 406b and the side surface of the metal oxide 406a.
  • the insulator 225 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • the insulator 225 is preferably formed using silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like.
  • oxygen can penetrate through the insulator 225 and oxygen can be supplied to oxygen vacancies in the region 426b and the region 426c, so that a decrease in carrier density can be prevented.
  • the insulator 280 preferably has reduced concentration of impurities such as water or hydrogen in the film.
  • the conductor 450a and the conductor 451a, and the conductor 450b and the conductor 451b are disposed in the openings formed in the insulator 280 and the insulator 225.
  • the conductor 450a and the conductor 451a, and the conductor 450b and the conductor 451b are preferably provided to face each other with the conductor 404 interposed therebetween.
  • a conductor 450a is formed in contact with the inner walls of the openings of the insulator 280 and the insulator 225, and a conductor 451a is further formed inside.
  • a region 426b of the metal oxide 406 is located at least at a part of the bottom of the opening, and the conductor 450a is in contact with the region 426b.
  • a conductor 450b is formed in contact with the inner walls of the openings of the insulator 280 and the insulator 225, and a conductor 451b is formed further inside.
  • a region 426c of the metal oxide 406 is located at least at a part of the bottom of the opening, and the conductor 450b is in contact with the region 426c.
  • FIG. 29A shows a cross-sectional view of the portion indicated by the one-dot chain line of A5-A6 in FIG. Note that FIG. 29A illustrates a cross-sectional view of the conductor 450b and the conductor 451b, but the structures of the conductor 450a and the conductor 451a are the same.
  • the conductor 450b is preferably in contact with at least the upper surface of the metal oxide 406 and further in contact with the side surface of the metal oxide 406.
  • the conductor 450b is preferably in contact with the A5 side surface and / or the A6 side surface of the metal oxide 406 in the channel width direction.
  • the conductor 450b may be in contact with the side surface of the metal oxide 406 on the A2 side in the channel length direction.
  • the conductor 450b is in contact with the side surface of the metal oxide 406 in addition to the upper surface of the metal oxide 406, so that the upper area of the contact portion between the conductor 450b and the metal oxide 406 is not increased.
  • the contact area of the contact portion can be increased, and the contact resistance between the conductor 450b and the metal oxide 406 can be reduced.
  • the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor. Note that the same applies to the conductor 450a and the conductor 451a.
  • the conductor 450a is in contact with the region 426b functioning as one of the source region and the drain region of the transistor 200
  • the conductor 450b is in contact with the region 426c functioning as the other of the source region and the drain region of the transistor 200.
  • the conductor 450a and the conductor 451a can function as one of a source electrode and a drain electrode
  • the conductor 450b and the conductor 451b can function as the other of the source electrode and the drain electrode.
  • the contact resistance between the conductor 450a and the region 426b and the contact resistance between the conductor 450b and the region 426c can be reduced, and the on-state current of the transistor 200 can be increased.
  • the conductor 450a and the conductor 450b are preferably formed using a conductive material having a function of suppressing permeation of impurities such as water or hydrogen.
  • a conductive material having a function of suppressing permeation of impurities such as water or hydrogen.
  • impurities such as water or hydrogen.
  • tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used, and a single layer or a stacked layer may be used.
  • impurities such as hydrogen and water from an upper layer than the insulator 280 can be prevented from entering the metal oxide 406 through the conductors 451a and 451b.
  • the conductor 451a and the conductor 451b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • the conductor 450a and the conductor 450b are in contact with both the metal oxide 406a and the metal oxide 406b, but the invention is not limited thereto. It may be configured to contact only the object 406b.
  • the heights of the upper surfaces of the conductor 450a, the conductor 451a, the conductor 450b, and the conductor 451b can be approximately the same.
  • the transistor 200 a structure in which the conductor 450a and the conductor 451a are stacked and the conductor 450b and the conductor 451b are stacked is described; however, the present invention is not limited thereto. For example, only the conductor 451a and the conductor 451b may be provided.
  • the insulator 224 is the bottom of the opening in which the conductor 450b (conductor 450a) is provided; however, this embodiment is not limited thereto. is not. As illustrated in FIG. 29B, the insulator 222 may be a bottom portion of an opening in which the conductor 450a and the conductor 450b are provided. In FIG. 29A, the conductor 450b (conductor 450a) is in contact with the insulator 224, the metal oxide 406a, the metal oxide 406b, the insulator 225, and the insulator 280. In the case shown in FIG.
  • the conductor 450b (conductor 450a) is in contact with the insulator 222, the insulator 224, the metal oxide 406a, the metal oxide 406b, the insulator 225, and the insulator 280.
  • a substrate over which the transistor 200 is formed for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • there is a semiconductor substrate having an insulator region inside the semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductor substrate examples include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride, a substrate having a metal oxide, or the like can be given.
  • a substrate in which a conductor or a semiconductor is provided on an insulator substrate a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like.
  • a substrate in which an element is provided may be used.
  • the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
  • a flexible substrate may be used as the substrate.
  • a method for providing a transistor over a flexible substrate there is a method in which after a transistor is formed over a non-flexible substrate, the transistor is peeled off and transferred to a substrate which is a flexible substrate.
  • a separation layer is preferably provided between the non-flexible substrate and the transistor.
  • the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape.
  • the substrate has a region having a thickness of, for example, 5 ⁇ m to 700 ⁇ m, preferably 10 ⁇ m to 500 ⁇ m, more preferably 15 ⁇ m to 300 ⁇ m.
  • a semiconductor device including a transistor can be reduced in weight.
  • by thinning the substrate there is a case where it has elasticity even when glass or the like is used, and there is a case where it returns to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.
  • the substrate that is a flexible substrate for example, a metal, an alloy, a resin, glass, or a fiber thereof can be used.
  • a substrate that is a flexible substrate is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed.
  • the substrate which is a flexible substrate for example, a material having a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 / K or less may be used.
  • the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
  • aramid has a low coefficient of linear expansion, it is suitable as a substrate that is a flexible substrate.
  • Insulator examples include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.
  • the electrical characteristics of the transistor can be stabilized by surrounding the transistor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used as the insulator 222 and the insulator 214.
  • Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium.
  • An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
  • the insulator 222 and the insulator 214 include a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, and nitride. Silicon oxide, silicon nitride, or the like may be used. Note that the insulator 222 and the insulator 214 preferably include aluminum oxide, hafnium oxide, or the like.
  • Examples of the insulator 384, the insulator 216, the insulator 220, the insulator 224, and the insulator 412 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, An insulator containing yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
  • the insulator 384, the insulator 216, the insulator 220, the insulator 224, and the insulator 412 preferably include silicon oxide, silicon oxynitride, or silicon nitride.
  • the insulator 220, the insulator 222, the insulator 224, and / or the insulator 412 preferably includes an insulator having a high relative dielectric constant.
  • the insulator 220, the insulator 222, the insulator 224, and / or the insulator 412 include gallium oxide, hafnium oxide, zirconium oxide, an oxide including aluminum and hafnium, an oxynitride including aluminum and hafnium, silicon, and It is preferable to include an oxide containing hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.
  • the insulator 220, the insulator 222, the insulator 224, and / or the insulator 412 preferably has a stacked structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having high thermal stability and high relative dielectric constant can be obtained by combining with an insulator having high relative dielectric constant. For example, in the insulator 224 and the insulator 412, by using aluminum oxide, gallium oxide, or hafnium in contact with the metal oxide 406, silicon contained in silicon oxide or silicon oxynitride is mixed into the metal oxide 406. Can be suppressed.
  • a trap center is formed at the interface.
  • the trap center can change the threshold voltage of the transistor in the positive direction by capturing electrons.
  • the insulator 384, the insulator 216, and the insulator 280 preferably have an insulator with a low relative dielectric constant.
  • the insulator 384, the insulator 216, and the insulator 280 were doped with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon, and nitrogen. It is preferable to have silicon oxide, silicon oxide having holes, resin, or the like.
  • the insulator 384, the insulator 216, and the insulator 280 are added with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon, and nitrogen added. It is preferable to have a stacked structure of silicon oxide or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used.
  • the insulator 418 and the insulator 419 include metal oxides such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, and silicon nitride oxide Alternatively, silicon nitride or the like may be used.
  • Conductor As the conductor 404a, the conductor 404b, the conductor 310a, the conductor 310b, the conductor 450a, the conductor 450b, the conductor 451a, and the conductor 451b, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, A material containing one or more metal elements selected from titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor having high electrical conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a conductive material containing a metal element contained in a metal oxide applicable to the metal oxide 406 and oxygen is used. May be.
  • the above-described conductive material containing a metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • hydrogen contained in the metal oxide 406 can be captured by using such a material.
  • hydrogen mixed from an outer insulator or the like may be captured.
  • a plurality of conductive layers formed of the above materials may be stacked.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed.
  • a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are used as a gate electrode is preferably used.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • Metal oxide applicable to metal oxide 406 >> The metal oxide 406 according to the present invention will be described below.
  • the metal oxide 406 a metal oxide that functions as an oxide semiconductor is preferably used.
  • the metal oxide 406 preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. One or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.
  • the metal oxide 406 includes indium, the element M, and zinc is considered.
  • the terms of the atomic ratio of indium, element M, and zinc included in the metal oxide 406 are [In], [M], and [Zn].
  • FIGS. 30 (A), 30 (B), and 30 (C) a preferable range of the atomic ratio of indium, element M, and zinc included in the metal oxide 406 will be described with reference to FIGS. 30 (A), 30 (B), and 30 (C). Note that the atomic ratio of oxygen is not described in FIGS. 30A, 30B, and 30C.
  • the terms of the atomic ratio of indium, element M, and zinc included in the metal oxide 406 are [In], [M], and [Zn].
  • [In]: [M]: [Zn] (1 + ⁇ ): (1- ⁇ ): number of atoms of 4
  • a line to be a ratio and a line to have an atomic ratio of [In]: [M]: [Zn] (1 + ⁇ ) :( 1 ⁇ ): 5.
  • multiple phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.).
  • two phases of a spinel crystal structure and a layered crystal structure tend to coexist.
  • two phases of a bixbite type crystal structure and a layered crystal structure tend to coexist.
  • a crystal grain boundary may be formed between different crystal structures.
  • 30A illustrates an example of a preferable range of the atomic ratio of indium, element M, and zinc included in the metal oxide 406.
  • the metal oxide can increase the carrier mobility (electron mobility) of the metal oxide by increasing the content of indium. Therefore, a metal oxide having a high indium content has higher carrier mobility than a metal oxide having a low indium content.
  • the metal oxide used for the metal oxide 406b preferably has a high carrier mobility and an atomic ratio shown by region A in FIG.
  • the metal oxide used for the metal oxide 406a preferably has an atomic ratio represented by a region C in FIG.
  • region B shown in FIG. 30B an excellent metal oxide with high carrier mobility and high reliability can be obtained in region A.
  • the metal oxide 406 it is preferable to use a target including a polycrystalline In-M-Zn oxide as a sputtering target.
  • the atomic ratio of the metal oxide film to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target.
  • the properties of metal oxides are not uniquely determined by the atomic ratio. Even if the atomic ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. For example, when the metal oxide 406 is formed using a sputtering apparatus, a film having an atomic ratio that deviates from the atomic ratio of the target is formed. Further, depending on the substrate temperature during film formation, [Zn] of the film may be smaller than [Zn] of the target. Therefore, the illustrated region is a region that exhibits an atomic ratio in which the metal oxide tends to have specific characteristics, and the boundaries of the regions A to C are not strict.
  • CAAC c-axis aligned crystal
  • CAC Cloud-Aligned Composite
  • CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and the whole material has a function as a semiconductor.
  • the conductive function is a function of flowing electrons (or holes) serving as carriers
  • the insulating function is an electron serving as carriers. It is a function that does not flow.
  • a function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.
  • CAC-OS or CAC-metal oxide has a conductive region and an insulating region.
  • the conductive region has the above-described conductive function
  • the insulating region has the above-described insulating function.
  • the conductive region and the insulating region may be separated at the nanoparticle level.
  • the conductive region and the insulating region may be unevenly distributed in the material, respectively.
  • the conductive region may be observed with the periphery blurred and connected in a cloud shape.
  • the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
  • CAC-OS or CAC-metal oxide is composed of components having different band gaps.
  • CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region.
  • the carrier when the carrier flows, the carrier mainly flows in the component having the narrow gap.
  • the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
  • CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor).
  • OS amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
  • the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and has a strain.
  • the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.
  • Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. Further, in some cases, the strain may have a lattice arrangement such as a pentagon and a heptagon. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction, the bond distance between atoms changes due to substitution of metal elements, and the like. This is probably because of this.
  • the CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked.
  • In layer a layer containing indium and oxygen
  • M, Zn elements M, zinc, and oxygen
  • indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.
  • CAAC-OS is an oxide semiconductor with high crystallinity.
  • CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs.
  • the crystallinity of an oxide semiconductor may be decreased due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (oxygen vacancies or the like). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.
  • Nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.
  • the a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.
  • Oxide semiconductors have various structures and have different characteristics.
  • the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • a transistor with high field-effect mobility can be realized by using the above metal oxide for a transistor.
  • a highly reliable transistor can be realized.
  • the carrier density in the region 426a of the metal oxide 406b is preferably low.
  • the impurity concentration in the metal oxide may be lowered and the defect level density may be lowered.
  • a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic.
  • the carrier density in the region 426a of the metal oxide 406b is less than 8 ⁇ 10 11 / cm 3 , preferably less than 1 ⁇ 10 11 / cm 3 , more preferably less than 1 ⁇ 10 10 / cm 3 , and 1 ⁇ 10 What is necessary is just to be more than -9 / cm ⁇ 3 >.
  • the trap level density may also be low.
  • the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
  • the concentration of silicon or carbon (concentration obtained by SIMS) in the region 426a of the metal oxide 406b is set to 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the metal oxide contains an alkali metal or an alkaline earth metal
  • a defect level is formed and carriers may be generated. Accordingly, a transistor including a metal oxide containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the region 426a of the metal oxide 406b.
  • the concentration of the alkali metal or alkaline earth metal in the region 426a of the metal oxide 406b obtained by SIMS is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the region 426a of the metal oxide 406b is less than 5 ⁇ 10 19 atoms / cm 3 in SIMS.
  • it is 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less, and even more preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated.
  • a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor in which a large amount of hydrogen is contained in the region 426a of the metal oxide 406b is likely to be normally on. For this reason, hydrogen in the region 426a of the metal oxide 406b is preferably reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • Transistor 201 Next, as a structural example different from the transistor 200, the transistor 201 will be described in detail.
  • FIG. 31A is a top view of a semiconductor device including a transistor 201.
  • FIG. FIG. 31B is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 31A and also a cross-sectional view in the channel length direction of the transistor 201.
  • FIG. 31C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 31A and also a cross-sectional view in the channel width direction of the transistor 201.
  • some elements are omitted for clarity.
  • the same reference numerals are used for the same components as the transistor 200.
  • the transistor 201 includes an insulator 224 disposed over a substrate (not shown), a metal oxide 406a disposed over the insulator 224, Metal oxide 406b disposed in contact with at least part of the upper surface of metal oxide 406a, conductor 452a and conductor 452b disposed in contact with at least part of the upper surface of metal oxide 406b, and metal oxide A metal oxide 406c which is in contact with at least part of the upper surface of 406b and is disposed over the conductor 452a and the conductor 452b; an insulator 413 which is disposed over the metal oxide 406c;
  • the conductor 405a is disposed, the conductor 405b disposed on the conductor 405a, and the insulator 420 disposed on the conductor 405b.
  • the conductor 405 (the conductor 405a and the conductor 405b) can function as a top gate, and the conductor 310 can function as a back gate.
  • the potential of the back gate may be the same as that of the top gate, or may be a ground potential or an arbitrary potential. Further, the threshold voltage of the transistor can be changed by changing the potential of the back gate independently without interlocking with the top gate.
  • the conductor 405a can be provided using a material similar to that of the conductor 404a in FIG.
  • the conductor 405b can be provided using a material similar to that of the conductor 404b in FIG.
  • the conductor 452a functions as one of a source electrode and a drain electrode
  • the conductor 452b functions as the other of the source electrode and the drain electrode.
  • a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same as a main component can be used.
  • a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same as a main component can be used.
  • a single layer structure is shown in the figure, a stacked structure of two or more layers may be used.
  • a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.
  • the channel is preferably formed in the metal oxide 406b. Therefore, the metal oxide 406c is preferably formed using a material having a relatively higher insulating property than the metal oxide 406b. The metal oxide 406c may be formed using a material similar to that of the metal oxide 406a.
  • the transistor 201 can be a buried-channel transistor by providing the metal oxide 406c. Further, oxidation of end portions of the conductor 452a and the conductor 452b can be prevented. In addition, leakage current between the conductor 405 and the conductor 452a (or the conductor 405 and the conductor 452b) can be prevented. Note that the metal oxide 406c may be omitted depending on circumstances.
  • the insulator 420 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used. Use it.
  • the transistor 201 can prevent the conductor 405 from being oxidized by providing the insulator 420.
  • impurities such as water or hydrogen can be prevented from entering the metal oxide 406.
  • the transistor 201 can have a larger contact area between the metal oxide 406b and the electrode (source electrode or drain electrode) than the transistor 200. Further, the step of manufacturing the region 426b and the region 426c illustrated in FIG. 27 is not necessary. Thus, the transistor 201 can have higher on-state current than the transistor 200. In addition, the manufacturing process can be simplified.
  • the description of the transistor 200 may be referred to.
  • This embodiment mode can be combined with any of the other embodiment modes as appropriate.
  • FIG. 32A illustrates a pixel circuit to which a liquid crystal element is applied as a display element.
  • the pixel circuit 306 includes a display element 301, a transistor M1, and a capacitor Cs LC . Note that the first terminal of the display element 301 corresponds to a pixel electrode, and the second terminal of the display element 301 corresponds to a common electrode.
  • FIG. 32A illustrates a signal line SL and a gate line GL that are electrically connected to the pixel circuit 306.
  • One of the source and the drain of the transistor M1 is electrically connected to the first terminal of the display element 301, the other of the source and the drain of the transistor M1 is electrically connected to the signal line SL, and the gate of the transistor M1 is a gate. It is electrically connected to the line GL.
  • the first terminal of the capacitive element Cs LC is electrically connected to the first terminal of the transistor M1.
  • a second terminal of the display element 301 is electrically connected to a wiring for driving the display element 301 and supplying a common potential.
  • the second terminal of the capacitive element Cs LC is electrically connected to a wiring that supplies a reference potential.
  • an OS transistor as the transistor M1.
  • OS transistor oxide semiconductor
  • the OS transistor has a very low leakage current (off-state current) in a non-conduction state, electric charge can be held in the pixel electrode of the liquid crystal element by making the OS transistor non-conduction.
  • a display device including the pixel circuit 306 can be made faster than a normal frame frequency (typically 60 Hz to 240 Hz) by using a characteristic of an OS transistor that has a very low off-state current in a non-conduction state. It can be driven at a low frame frequency.
  • a normal operation mode typically 60 Hz to 240 Hz
  • IDS idling stop
  • the idling stop (IDS) driving mode refers to a driving method in which rewriting of image data is stopped after execution of image data writing processing. Once the image data is written and then the interval until the next image data is written is extended, the power consumption required for writing the image data during that time can be reduced.
  • the idling stop (IDS) drive mode can be set to a frame frequency about 1/100 to 1/10 of the normal operation mode, for example.
  • 32B and 32C are timing charts for explaining the normal drive mode and the idling stop (IDS) drive mode, respectively.
  • FIG. 32B is a timing chart showing waveforms of signals supplied to the signal line SL and the gate line GL in the normal drive mode.
  • the normal drive mode In the normal drive mode, it operates at a normal frame frequency (for example, 60 Hz).
  • FIG. 32B illustrates a period from T 1 to T 3 . Giving a scanning signal to the gate line GL in each frame period, it performs an operation to write data D 1 from the signal line SL. This operation is the same even when the same data D 1 is written in the periods T 1 to T 3 or when different data is written.
  • FIG. 32C is a timing chart showing waveforms of signals supplied to the signal line SL and the gate line GL in the idling stop (IDS) driving mode.
  • the idling stop (IDS) drive operates at a low frame frequency (for example, 1 Hz). Represents one frame period in the period T 1, representing the period T W a write period of data therein, the data retention period in the period T RET.
  • Idling stop (IDS) drive mode it provides a scan signal to the gate line GL in a period T W, write data D 1 of the signal line SL, and a gate line GL is fixed to the low level of the voltage in the period T RET, transistor performs an operation of holding temporarily the data D 1 is written M1 as a non-conductive state.
  • the number of times image data is written to the pixel circuit 306 can be reduced as compared with the normal driving mode, so that power consumption can be reduced.
  • FIG. 32D illustrates a pixel circuit to which an organic EL element is applied as a display element.
  • the pixel circuit 307 includes a display element 302, a transistor M2, a transistor M3, and a capacitor Cs EL .
  • FIG. 32D illustrates a signal line DL, a gate line GL2, and a current supply line AL that are electrically connected to the pixel circuit 307.
  • an OS transistor is preferably used like the transistor M1. Since the OS transistor has a very low leakage current (off-state current) in the non-conduction state, the charge charged in the capacitor Cs EL can be held by making the OS transistor non-conduction. That is, the gate-drain voltage of the transistor M3 can be kept constant, and the light emission intensity of the display element 302 can be made constant.
  • the idling stop (IDS) drive of the display element 302 applies a scanning signal to the gate line GL2 and writes data from the signal line DL. Later, by fixing the gate line GL2 to a low level voltage, the transistor M2 is turned off to hold the data once written.
  • the idling stop (IDS) drive mode can be performed in the pixel circuit 307 as well as in the pixel circuit 306. Therefore, compared with the normal driving mode, the number of times image data is written to the pixel circuit 307 can be reduced, so that power consumption can be reduced.
  • IDS idling stop
  • the transistor M3 is preferably formed using the same material as the transistor M2. By using the same material structure for the transistor M3 and the transistor M2, the manufacturing process of the pixel circuit 307 can be shortened.
  • the materials applicable to the semiconductor layers of the transistors M1, M2, and M3 preferably include an amorphous semiconductor, particularly hydrogenated amorphous silicon (a-Si: H), other than the metal oxide. Since a transistor using an amorphous semiconductor can easily cope with an increase in the area of a substrate, for example, when manufacturing a large-screen display device compatible with 2K, 4K, 8K broadcasting, etc., a manufacturing process Can be simplified.
  • a-Si: H hydrogenated amorphous silicon
  • This embodiment mode can be combined with any of the other embodiment modes as appropriate.
  • FIG. 33A is a perspective view showing a television device.
  • a television device includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, and a sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation). Number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell, or infrared) Etc.
  • the television device can incorporate a display portion 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.
  • FIG. 33B shows an example of a digital signage (digital signage) that can be attached to a wall.
  • FIG. 33B illustrates a state where the electronic signboard 6200 is attached to the wall 6201.
  • FIG. 33C illustrates a tablet information terminal, which includes a housing 5221, a display portion 5222, operation buttons 5223, and a speaker 5224.
  • a display device to which a function as a position input device is added may be used for the display portion 5222.
  • the function as a position input device can be added by providing a touch panel on the display device.
  • the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.
  • the operation button 5223 can include any one of a power switch for starting the information terminal, a button for operating an application of the information terminal, a volume adjustment button, a switch for turning on or off the display unit 5222, and the like.
  • the number of operation buttons 5223 is four, but the number and arrangement of operation buttons included in the information terminal are not limited thereto.
  • the information terminal illustrated in FIG. 33C may have a camera.
  • the information terminal illustrated in FIG. 33C may have a structure including a flashlight or a light-emitting device for illumination.
  • the information terminal illustrated in FIG. 33C includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism) inside the housing 5221. , Temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell, infrared, etc. .
  • the direction of the information terminal shown in FIG. 33C (which direction the information terminal is oriented with respect to the vertical direction) is determined. It can be determined and the screen display of the display unit 5222 can be automatically switched according to the orientation of the information terminal.
  • the semiconductor device of one embodiment of the present invention to the information terminal illustrated in FIG. 33C, the circuit configuration of the information terminal can be simplified.
  • a display element a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. I can do it.
  • a display element, a display device, a light emitting element, or a light emitting device includes, for example, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED chip (a white LED chip, a red LED chip, Green LED chip, blue LED chip, etc.), transistor (transistor that emits light in response to current), plasma display panel (PDP), electron-emitting device, display device using carbon nanotube, liquid crystal device, electronic ink, electrowetting device , Electrophoretic element, display element using MEMS (micro electro mechanical system) (for example, grating light valve (GLV), digital micromirror device (DMD), DMS (digital micro shutter), MIRASO (Registered trademark), IMOD (interferometric modulation) element, shutter-type MEMS display element, optical interference-type MEMS display element, piezoelectric ceramic display, etc.), or quantum dots .
  • the display element, the display device, the light-emitting element, or the light-emitting device may include a display medium whose contrast, luminance, reflectance, transmittance, and the like are changed by an electric or magnetic action.
  • An example of a display device using an EL element is an EL display.
  • As an example of a display device using an electron-emitting device there is a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), or the like.
  • a display device using a liquid crystal element there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) or the like.
  • a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper.
  • An example of a display device using a quantum dot for each pixel is a quantum dot display. Note that the quantum dots may be provided not in the display element but in part of the backlight. By using quantum dots, display with high color purity can be performed.
  • part or all of the pixel electrodes may have a function as a reflective electrode.
  • part or all of the pixel electrode may have aluminum, silver, or the like.
  • a storage circuit such as an SRAM can be provided under the reflective electrode.
  • power consumption can be further reduced.
  • Graphene or graphite may be a multilayer film in which a plurality of layers are stacked.
  • a nitride semiconductor for example, an n-type GaN semiconductor layer having a crystal, or the like can be easily formed thereon. Furthermore, a p-type GaN semiconductor layer having a crystal or the like can be provided thereon to form an LED chip.
  • an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor layer having a crystal.
  • the GaN semiconductor layer of the LED chip may be formed by MOCVD. However, by providing graphene, the GaN semiconductor layer of the LED chip can be formed by a sputtering method.
  • a space in which the display element is sealed (for example, an element substrate on which the display element is arranged, and an element substrate facing the element substrate)
  • a desiccant may be disposed between the opposite substrate).
  • This embodiment mode can be combined with any of the other embodiment modes as appropriate.

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Abstract

Le but de la présente invention est de fournir un système de diffusion comprenant un autocodeur pour lequel la dimensionnalité ou la quantité de couches intermédiaires est faible, et de fournir un dispositif à semi-conducteur ayant une configuration de circuit simple. L'invention concerne un système de diffusion ayant un dispositif de transmission et un dispositif de réception, le dispositif de transmission comprenant un premier circuit et un codeur, et le dispositif de réception comprenant un décodeur. Le codeur et le décodeur constituent un autocodeur. Le premier circuit et le codeur ont une fonction permettant de recevoir des premières données d'image. Le premier circuit a une fonction permettant d'extraire des caractéristiques des premières données d'image et de générer ainsi des informations d'attribut représentatives d'attributs des premières données d'image. Le codeur a une fonction permettant d'extraire des caractéristiques des premières données d'image sur la base des informations d'attribut et de générer ainsi des secondes données d'image obtenues par la compression des premières données d'image. Le décodeur a une fonction permettant de décompresser les secondes données d'image et de restaurer celles-ci en premières données d'image sur la base des informations d'attribut.
PCT/IB2018/051209 2017-03-09 2018-02-27 Dispositif à semi-conducteur et système de diffusion Ceased WO2018163011A1 (fr)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020064557A (ja) * 2018-10-19 2020-04-23 キヤノン株式会社 画像処理装置、画像処理システム、撮像装置、画像処理方法、および、プログラム
JP2020109897A (ja) * 2018-12-28 2020-07-16 株式会社ドワンゴ 画像送受信システム、データ送受信システム、送受信方法、コンピュータ・プログラム、画像送信システム、画像受信装置、送信システム、受信装置
JP2022522685A (ja) * 2019-03-15 2022-04-20 ドルビー・インターナショナル・アーベー ニューラルネットワークを更新するための方法および装置
WO2023181525A1 (fr) * 2022-03-23 2023-09-28 株式会社Ｓｃｒｅｅｎホールディングス Dispositif d'apprentissage, dispositif de traitement d'informations, dispositif de traitement de substrat, système de traitement de substrat, procédé d'apprentissage et procédé de détermination de conditions de traitement
JPWO2024084660A1 (fr) * 2022-10-20 2024-04-25

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS644186A (en) * 1987-06-25 1989-01-09 Nec Corp Encoding method for image signal
JPH02141087A (ja) * 1988-11-21 1990-05-30 Tokyo Electric Power Co Inc:The 動画像圧縮伝送・蓄積方式
JPH02234573A (ja) * 1989-03-08 1990-09-17 Graphics Commun Technol:Kk ニューラルネットを用いた符号化伝送方法およびその装置
JPH08221993A (ja) * 1994-03-25 1996-08-30 Seiko Instr Inc 半導体集積回路装置、その製造方法及びその駆動方法
JP2002288625A (ja) * 2001-03-28 2002-10-04 Mitsubishi Heavy Ind Ltd 多目的最適化方法、プログラムおよびプラン立案装置
JP2010267705A (ja) * 2009-05-13 2010-11-25 Panasonic Corp 半導体メモリセルおよびその製造方法
JP2012161063A (ja) * 2011-01-12 2012-08-23 Kddi Corp 動画像符号化装置、動画像復号装置、動画像符号化方法、動画像復号方法、およびプログラム
JP2016004549A (ja) * 2014-06-19 2016-01-12 ヤフー株式会社 特定装置、特定方法及び特定プログラム
JP2016033806A (ja) * 2014-05-15 2016-03-10 株式会社リコー 画像処理装置、画像処理方法及びプログラム
WO2016199330A1 (fr) * 2015-06-12 2016-12-15 パナソニックＩｐマネジメント株式会社 Procédé de codage d'image, procédé de décodage d'image, dispositif de codage d'image et dispositif de décodage d'image
JP2016225613A (ja) * 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の駆動方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5982297B2 (ja) 2013-02-18 2016-08-31 日本電信電話株式会社 音声認識装置、音響モデル学習装置、その方法及びプログラム
US10545526B2 (en) 2015-06-25 2020-01-28 Semiconductor Energy Laboratory Co., Ltd. Circuit, driving method thereof, and semiconductor device

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS644186A (en) * 1987-06-25 1989-01-09 Nec Corp Encoding method for image signal
JPH02141087A (ja) * 1988-11-21 1990-05-30 Tokyo Electric Power Co Inc:The 動画像圧縮伝送・蓄積方式
JPH02234573A (ja) * 1989-03-08 1990-09-17 Graphics Commun Technol:Kk ニューラルネットを用いた符号化伝送方法およびその装置
JPH08221993A (ja) * 1994-03-25 1996-08-30 Seiko Instr Inc 半導体集積回路装置、その製造方法及びその駆動方法
JP2002288625A (ja) * 2001-03-28 2002-10-04 Mitsubishi Heavy Ind Ltd 多目的最適化方法、プログラムおよびプラン立案装置
JP2010267705A (ja) * 2009-05-13 2010-11-25 Panasonic Corp 半導体メモリセルおよびその製造方法
JP2012161063A (ja) * 2011-01-12 2012-08-23 Kddi Corp 動画像符号化装置、動画像復号装置、動画像符号化方法、動画像復号方法、およびプログラム
JP2016033806A (ja) * 2014-05-15 2016-03-10 株式会社リコー 画像処理装置、画像処理方法及びプログラム
JP2016004549A (ja) * 2014-06-19 2016-01-12 ヤフー株式会社 特定装置、特定方法及び特定プログラム
JP2016225613A (ja) * 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の駆動方法
WO2016199330A1 (fr) * 2015-06-12 2016-12-15 パナソニックＩｐマネジメント株式会社 Procédé de codage d'image, procédé de décodage d'image, dispositif de codage d'image et dispositif de décodage d'image

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YAMASHITA: "Deep learning learn from illustracion", KODANHA LTD, 10 February 2017 (2017-02-10) *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020064557A (ja) * 2018-10-19 2020-04-23 キヤノン株式会社 画像処理装置、画像処理システム、撮像装置、画像処理方法、および、プログラム
JP2020109897A (ja) * 2018-12-28 2020-07-16 株式会社ドワンゴ 画像送受信システム、データ送受信システム、送受信方法、コンピュータ・プログラム、画像送信システム、画像受信装置、送信システム、受信装置
JP2022522685A (ja) * 2019-03-15 2022-04-20 ドルビー・インターナショナル・アーベー ニューラルネットワークを更新するための方法および装置
JP7196331B2 (ja) 2019-03-15 2022-12-26 ドルビー・インターナショナル・アーベー ニューラルネットワークを更新するための方法および装置
US12400113B2 (en) 2019-03-15 2025-08-26 Dolby International Ab Method and apparatus for updating a neural network
WO2023181525A1 (fr) * 2022-03-23 2023-09-28 株式会社Ｓｃｒｅｅｎホールディングス Dispositif d'apprentissage, dispositif de traitement d'informations, dispositif de traitement de substrat, système de traitement de substrat, procédé d'apprentissage et procédé de détermination de conditions de traitement
JP2023141070A (ja) * 2022-03-23 2023-10-05 株式会社Ｓｃｒｅｅｎホールディングス 学習装置、情報処理装置、基板処理装置、基板処理システム、学習方法および処理条件決定方法
JP7761515B2 (ja) 2022-03-23 2025-10-28 株式会社Ｓｃｒｅｅｎホールディングス 学習装置、情報処理装置、基板処理装置、基板処理システム、学習方法および処理条件決定方法
JPWO2024084660A1 (fr) * 2022-10-20 2024-04-25
WO2024084660A1 (fr) * 2022-10-20 2024-04-25 日本電気株式会社 Dispositif de codage d'image, dispositif de décodage d'image, système de traitement des images, dispositif d'apprentissage de modèle, procédé de codage d'image, procédé de décodage d'image et support d'enregistrement lisible par ordinateur

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