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WO2018145515A1 - 薄膜晶体管及其制作方法、显示基板和显示装置 - Google Patents

薄膜晶体管及其制作方法、显示基板和显示装置 Download PDF

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WO2018145515A1
WO2018145515A1 PCT/CN2017/115887 CN2017115887W WO2018145515A1 WO 2018145515 A1 WO2018145515 A1 WO 2018145515A1 CN 2017115887 W CN2017115887 W CN 2017115887W WO 2018145515 A1 WO2018145515 A1 WO 2018145515A1
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layer
insulating layer
thin film
film transistor
amorphous silicon
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English (en)
French (fr)
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李小龙
李栋
张慧娟
刘政
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0227—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using structural arrangements to control crystal growth, e.g. placement of grain filters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0229—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials characterised by control of the annealing or irradiation parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/87—Arrangements for heating or cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a thin film transistor and a method of fabricating the same, a display substrate, and a display device.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • AMOLED drives a organic light-emitting layer to emit light through a Drive Thin Film Transistor (DTFT).
  • DTFT Drive Thin Film Transistor
  • low-temperature polysilicon is generally used to fabricate an active layer of a DTFT.
  • the threshold voltage of the thin film transistor is unstable and the carrier mobility is poor due to the existence of a large number of grain boundary defect states, and when the size of the thin film transistor is reduced, the problem of threshold voltage instability becomes more complicated. serious.
  • the uniformity of low-temperature polysilicon film is generally improved by ELA (excimer laser annealing) and CW solid-state laser two-step processing, but this increases the cost and process complexity, which is not suitable for practical applications.
  • the present disclosure provides, in an aspect, a method of fabricating a thin film transistor including a gate, a source, a drain, and an active layer, and the step of forming the active layer includes:
  • the pattern of the amorphous silicon layer is processed by a laser annealing process to form the active layer composed of polysilicon.
  • the pattern forming the insulating layer comprises:
  • the layer of insulating material is patterned to form a pattern of the insulating layer.
  • the pattern of forming an amorphous silicon layer on the pattern of the insulating layer comprises:
  • first end portion and the second end portion both extend beyond the insulating layer.
  • the length of the excess portion ranges from 1 to 1.5 [mu]m when the first end portion is outside the insulating layer.
  • the length of the excess portion ranges from 1 to 1.5 ⁇ m when the second end portion is outside the insulating layer.
  • the heat insulating layer has an elongated shape, the heat insulating layer has the same extending direction as the amorphous silicon layer, and the insulating layer has a width perpendicular to the extending direction greater than the middle portion. In a width perpendicular to the direction of extension.
  • the width of the insulating layer in a direction perpendicular to the extending direction is 1-2 ⁇ m larger than a width of the intermediate portion in a direction perpendicular to the extending direction.
  • the buffer material is SiNx, and the buffer material has a thickness ranging from 50 to 100 nm.
  • the insulating material is SiO 2 and the insulating material has a thickness ranging from 250 to 350 nm.
  • the laser annealing process the energy range of the laser is 350mJ / cm 2 -450mJ / cm 2 , the irradiation time of the laser range 7-8 minutes.
  • Another aspect of the present disclosure also provides a thin film transistor fabricated by the above-described fabrication method, the thin film transistor including an active layer composed of polysilicon on an insulating layer, the active layer including an insulating layer The upper part and the part beyond the insulation layer.
  • Still another aspect of the present disclosure also provides a display substrate including the thin film transistor as described above.
  • Yet another aspect of the present disclosure also provides a display device including the display substrate as described above.
  • FIG. 1 is a schematic cross-sectional view showing an active layer of a low-temperature polysilicon thin film transistor in the prior art
  • FIG. 2 is a schematic view showing a buffer layer and an insulating layer formed on a base substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic view of patterning an insulating layer according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic view of depositing an amorphous silicon layer according to an embodiment of the present disclosure
  • FIG. 5 is a schematic view of patterning an amorphous silicon layer according to an embodiment of the present disclosure
  • FIG. 6 is a schematic view showing excimer laser annealing of an amorphous silicon layer according to an embodiment of the present disclosure
  • FIG. 7 is a schematic plan view of an active layer of a thin film transistor of an embodiment of the present disclosure.
  • Reference numerals 1 base substrate 2 buffer layer 3 active layer 4 buffer layer 5 heat insulating layer 6 amorphous silicon layer 7 active layer.
  • a buffer layer 2 is usually formed on the base substrate 1, and an active layer 3 composed of a low temperature polysilicon film is formed on the buffer layer 2. Due to the large number of grain boundary defect states of the low-temperature polysilicon film, the threshold voltage of the thin film transistor is unstable and the carrier mobility is not good, and when the size of the thin film transistor is reduced, the problem of unstable threshold voltage becomes more serious. . At present, the uniformity of low-temperature polysilicon film is generally improved by ELA and CW solid-state laser two-step processing, but this increases the cost and process complexity, which is not conducive to practical applications.
  • embodiments of the present disclosure provide a thin film transistor, a manufacturing method thereof, a display substrate, and a display device, which are capable of preparing a polysilicon active layer having a large crystal grain size and uniformity at a low cost, and further The carrier mobility and threshold voltage stability of the thin film transistor are improved.
  • the embodiment provides a method for fabricating a thin film transistor including a gate, a source, a drain, and an active layer.
  • the step of forming the active layer includes:
  • the pattern of the amorphous silicon layer is processed by a laser annealing process to form the active layer composed of polysilicon.
  • the pattern of the amorphous silicon layer includes a first portion on the insulating layer and a second portion outside the insulating layer, and after the laser annealing of the amorphous silicon layer, the second portion outside the insulating layer is cooled.
  • the first part will be nucleated sooner, and the first part will be cooled more slowly, which will make the amorphous silicon layer grow crystal grains along the second part to the first part, so that the grain growth direction can be controlled and the polysilicon can be improved. Uniformity; and since the first part is formed on the insulating layer, the first part will be cooled more slowly due to the presence of the insulating layer, and the formed crystal grains will be larger, so that the grain size can be prepared at a lower cost.
  • a large and uniform polysilicon active layer improves the carrier mobility and threshold voltage stability of the thin film transistor.
  • the first portion of the amorphous silicon layer on the insulating layer is in contact with the insulating layer and is in the insulating layer
  • the orthographic projection of the first portion on the substrate substrate falls within the orthographic projection of the insulating layer on the substrate, and the orthographic projection of the second portion on the substrate is located
  • the insulating layer is outside the orthographic projection on the substrate.
  • the insulating layer is generally made of an inorganic material having a relatively slow cooling rate, and the cooling rate of the insulating layer is smaller than the cooling rate of the substrate, so that the temperature of the amorphous silicon layer formed on the insulating layer after laser annealing of the amorphous silicon layer is performed. The descent will be slower.
  • a buffer layer is further disposed between the heat insulating layer and the base substrate, specifically, a step of forming a pattern of the heat insulating layer include:
  • the layer of insulating material is patterned to form a pattern of the insulating layer.
  • the buffer material and the heat insulating material are made of different inorganic materials. Since the buffer layer also has a certain heat insulating effect, if the buffer layer is relatively thick, since the second portion is located on the buffer layer, the first part and the second part are cooled. The difference between the cooling rates will be relatively small. Therefore, it is necessary to set the buffer layer to be relatively thin, and the heat insulating layer is set to be relatively thick, so that the difference between the cooling rates of the first portion and the second portion at the time of cooling can be made relatively large.
  • the buffer material may be SiNx, the thickness ranges from 50 to 100 nm, the insulating material may be SiO 2 , and the thickness ranges from 250 to 350 nm.
  • the step of forming a pattern of the amorphous silicon layer on the pattern of the insulating layer comprises:
  • the above-mentioned strip shape means that the shape of the amorphous silicon layer is substantially smaller than the length.
  • the pattern of the amorphous silicon layer may be a linear shape, a wavy line shape, a bow shape or the like, which is not limited herein.
  • the pattern of the amorphous silicon layer may also include a plurality of ends, not limited to two ends, but in order to control the growth direction of the crystal grains and improve the uniformity of the polysilicon, the end of the pattern of the amorphous layer is not excessive. .
  • the pattern of the amorphous silicon layer includes two ends.
  • At least one of the first end portion and the second end portion of the pattern of the amorphous silicon layer is outside the insulating layer, so that after the laser annealing of the amorphous silicon layer, the cooling of the end beyond the insulating layer is faster. Nucleation, the other part of the cooling is slower than the slower nucleus, which enables the amorphous silicon layer to grow crystal grains along the end from the end beyond the insulating layer to the middle portion, thereby controlling the growth direction of the crystal grains.
  • the uniformity of the polysilicon is improved; and since the intermediate portion is formed on the insulating layer, the intermediate portion and/or the end portion on the insulating layer may be cooled relatively slowly due to the presence of the insulating layer, and the formed crystal grains may be relatively large.
  • the first end and the second end both extend beyond the insulating layer.
  • crystal grains can be simultaneously grown in a direction from the first end portion to the intermediate portion and in a direction from the second end portion to the intermediate portion, thereby increasing the speed of growing the crystal grains, so that the heat is maintained.
  • the growth of the crystal grains is completed before the layer is cooled, and the size of the formed crystal grains is increased.
  • the pattern of the amorphous silicon layer has a portion beyond the insulating layer
  • the pattern of the amorphous silicon layer is not too long to be designed beyond the length of the insulating layer portion, because the portion of the amorphous silicon layer beyond the insulating layer is only for control.
  • the growth direction of the grains, and the portion is located outside the insulating layer, the cooling is relatively slow, and the formed crystal grains are relatively small, specifically, when the first end portion is outside the insulating layer, the excess portion
  • the length ranges from 1 to 1.5 ⁇ m; when the second end is outside the insulating layer, the length of the excess portion ranges from 1 to 1.5 ⁇ m.
  • the heat insulating layer may also be elongated, matching the shape of the pattern of the amorphous silicon layer, the insulating layer and the amorphous silicon layer extending in the same direction, and the insulating layer is perpendicular to the The width in the extending direction is larger than the width of the intermediate portion in the direction perpendicular to the extending direction, so that the portion of the amorphous silicon layer except the end portion is located on the insulating layer.
  • the width of the heat insulating layer does not need to be set too large, and the heat insulating layer
  • the width in the direction perpendicular to the extending direction may be 1-2 ⁇ m larger than the width of the intermediate portion in the direction perpendicular to the extending direction.
  • the shape of the insulating layer does not necessarily need to match the pattern of the amorphous silicon layer, and the insulating layer may also have other shapes such as a circle or a square, as long as the first portion of the pattern of the amorphous silicon layer is located on the insulating layer, The two parts can be outside the insulation layer.
  • the energy range of the laser is 350mJ / cm 2 -450mJ / cm 2 , the irradiation time of the laser range 7-8 minutes.
  • the laser annealing process can also adopt other process parameters, and the above parameters are not limited.
  • Step 1 as shown in Figure 2, a substrate 1 is provided, a buffer layer 4 and a thermal insulation layer 5 are formed on the substrate 1;
  • the base substrate 1 may be a glass substrate or a quartz substrate. Specifically, after the substrate substrate 1 is cleaned, a buffer layer 4 having a thickness ranging from 50 to 100 nm may be deposited on the base substrate 1 by a plasma enhanced chemical vapor deposition (PECVD) method, and the buffer layer 4 may cover the entire liner.
  • PECVD plasma enhanced chemical vapor deposition
  • the base substrate 1 can prevent the impurity ions in the base substrate 1 from escaping and affect the performance of the thin film transistor.
  • the buffer layer 4 can be an oxide, a nitride or an oxynitride compound, and specifically, SiNx can be used.
  • the insulating layer 5 having a thickness ranging from 250 to 350 nm may be deposited on the buffer layer 4 by a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the insulating layer 5 may be an oxide, a nitride or an oxynitride compound, specifically SiO 2 .
  • Step 2 as shown in FIG. 3, patterning the heat insulating layer 5 to form a pattern of the heat insulating layer 5;
  • a layer of photoresist is coated on the insulating layer 5, and the photoresist is exposed by using a mask to form a photoresist unretained region and a photoresist remaining region.
  • the photoresist retention area corresponds to the area of the pattern of the thermal insulation layer 5, and the photoresist unretained area corresponds to the area other than the above-mentioned pattern; the development process, the photoresist in the unretained area of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the remaining area remains unchanged; the insulating layer 5 of the unretained area of the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the insulating layer 5.
  • the pattern of the heat insulating layer 5 is substantially elongated, and includes a first line segment, a second line segment, a third line segment, a fourth line segment, and a fifth line segment that are sequentially connected end to end, and the first line.
  • the segment is perpendicular to the second segment, the second segment is perpendicular to the third segment, the third segment is perpendicular to the fourth segment, and the fourth segment is perpendicular to the fifth segment.
  • Step 3 depositing an amorphous silicon layer 6 on the substrate 1 on which the step 2 is completed;
  • A-Si having a thickness ranging from 40 to 50 nm may be deposited on the base substrate 1 as the amorphous silicon layer 6 by a plasma enhanced chemical vapor deposition (PECVD) method, and a dehydrogenation process may be performed in an OVEN (high temperature annealing) furnace.
  • PECVD plasma enhanced chemical vapor deposition
  • Step 4 as shown in FIG. 5, patterning the amorphous silicon layer 6 to form an amorphous silicon layer 6.
  • a layer of photoresist is coated on the amorphous silicon layer 6, and the photoresist is exposed by using a mask to form a photoresist unretained region and a photoresist remaining region.
  • the photoresist retention area corresponds to the area where the pattern of the amorphous silicon layer 6 is located, and the photoresist unretained area corresponds to the area other than the above-mentioned pattern; the development process, the photoresist in the unretained area of the photoresist is completely removed, and the light is completely removed.
  • the thickness of the photoresist in the glue-retained region remains unchanged; the amorphous silicon layer 6 in the unretained region of the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the amorphous silicon layer 6.
  • the amorphous silicon layer 6 has a substantially elongated shape including a first end portion and a second end portion of the two ends between the first end portion and the second end portion.
  • the intermediate portion is located on the heat insulating layer, and the first end portion and the second end portion both extend beyond the heat insulating layer, and the length S of the excess portion is 1-1.5 ⁇ m.
  • the width of the insulating layer 5 in the direction perpendicular to the extending direction exceeds the width of the intermediate portion of the amorphous silicon layer 6 in the direction perpendicular to the extending direction, and the width D of the excess portion is 1-2 ⁇ m.
  • Step 5 the pattern of the amorphous silicon layer 6 is processed by an ELA process to obtain an active layer 7.
  • the conversion of amorphous silicon to polycrystalline silicon is completed by an excimer laser annealing process, the energy of the laser is in the range of 350 mJ/cm 2 to 450 mJ/cm 2 , and the irradiation time of the laser is in the range of 7-8 minutes.
  • the first end portion and the second end portion of the amorphous silicon layer 6 outside the insulating layer 5 are cooled relatively quickly, and the intermediate portion is cooled more slowly.
  • a core which enables the amorphous silicon layer to grow crystal grains in a direction from the first end portion to the intermediate portion and the second end portion to the intermediate portion, thereby controlling the growth direction of the crystal grains and improving the uniformity of the polysilicon;
  • the portion is formed on the heat insulating layer 5. Due to the presence of the heat insulating layer 5, the middle portion is cooled relatively slowly, and the formed crystal grains are also relatively large, so that the grain size can be prepared at a relatively low cost and the uniformity is good.
  • the polysilicon active layer further increases the carrier mobility and threshold voltage stability of the thin film transistor.
  • the active layer of the thin film transistor can be fabricated, and then the gate insulating layer, the gate electrode, the intermediate insulating layer, the source and the drain of the thin film transistor can be fabricated by a conventional process to obtain a thin film transistor.
  • the present embodiment provides a thin film transistor which is fabricated by the above-described fabrication method.
  • the thin film transistor includes an active layer composed of polysilicon on an insulating layer, and the active layer includes a portion on the insulating layer. And beyond the insulation layer.
  • the pattern of the amorphous silicon layer includes a first portion on the insulating layer and beyond the insulating layer
  • the pattern of the amorphous silicon layer is processed.
  • the second part of the cooling outside the insulating layer is cooled faster.
  • the first part of the cooling is slower than the slower nucleus, which enables the amorphous silicon layer to grow crystal grains in the direction from the second portion to the first portion, thereby controlling the growth direction of the crystal grains and improving the uniformity of the polycrystalline silicon;
  • the first part is formed on the thermal insulation layer.
  • the polysilicon active layer further increases the carrier mobility and threshold voltage stability of the thin film transistor.
  • This embodiment provides a display substrate including the thin film transistor as described above. Since the carrier mobility of the thin film transistor is high and the threshold voltage is relatively stable, the performance of the display substrate of the present embodiment is relatively reliable as compared with the conventional display substrate.
  • This embodiment also provides a display device including the display substrate as described above.
  • the display device may be any product or component having a display function such as a display panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the display device also includes a flexible circuit board, a printed circuit board, and a backplane.

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  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

一种薄膜晶体管及其制作方法、显示基板和显示装置，属于显示技术领域。所述薄膜晶体管包括栅极、源极、漏极和有源层（7），形成所述有源层（7）的步骤包括：形成保温层（5）的图形；在所述保温层（5）上形成非晶硅层（6）的图形，所述非晶硅层（6）的图形包括位于所述保温层（5）上的第一部分和超出所述保温层（5）之外的第二部分；利用激光退火工艺对所述非晶硅层（6）的图形进行处理使得所述非晶硅层（6）沿从所述第二部分到所述第一部分的方向生长晶粒，形成由多晶硅组成的所述有源层（7）。藉此，以较低的成本制备晶粒尺寸较大且均匀性较好的多晶硅有源层（7），进而提高薄膜晶体管的载流子迁移率和阈值电压的稳定性。

Description

薄膜晶体管及其制作方法、显示基板和显示装置
相关申请的交叉引用
本申请主张于2017年2月9日提交的中国专利申请No.201710071073.3的优先权，其全部内容通过引用结合于此。
技术领域
本公开涉及显示技术领域，特别是指一种薄膜晶体管及其制作方法、显示基板和显示装置。
背景技术
有源矩阵有机发光二极管面板(Active Matrix Organic Light Emitting Diode，AMOLED)具有能耗低、生产成本低、视角宽、响应速度快等优点，因此AMOLED已经逐渐取代传统的液晶显示器。
目前AMOLED是通过驱动晶体管(Drive Thin Film Transistor，DTFT)来驱动有机发光层进行发光，为了使得DTFT具有较高的载流子迁移率，一般采用低温多晶硅来制作DTFT的有源层。
低温多晶硅薄膜中由于晶粒间界缺陷态的大量存在导致薄膜晶体管的阈值电压不稳定和载流子迁移率不佳，并且当薄膜晶体管尺寸缩小时，阈值电压不稳定的问题将变得更为严重。目前，一般采用ELA(准分子激光退火)和CW固态激光两步处理的方法使低温多晶硅薄膜的均匀性得到改善，但是这样增加了成本和工艺的复杂度，不利于实际应用。
发明内容
为解决上述技术问题，本公开的实施例提供技术方案如下：
本公开在一方面提供一种薄膜晶体管的制作方法，所述薄膜晶体管包括栅极、源极、漏极和有源层，形成所述有源层的步骤包括：
形成保温层的图形；
在所述保温层上形成非晶硅层的图形，所述非晶硅层的图形包括位于所述保温层上的第一部分和超出所述保温层之外的第二部分；以及
利用激光退火工艺对所述非晶硅层的图形进行处理，形成由多晶硅组成的所述有源层。
在一实施例中，所述形成保温层的图形包括：
提供一衬底基板；
在所述衬底基板上沉积一层缓冲材料和一层保温材料，所述缓冲材料的厚度小于所述保温材料的厚度；以及
对该层保温材料进行构图，形成所述保温层的图形。
在一实施例中，所述在所述保温层的图形上形成非晶硅层的图形包括：
在形成有所述保温层的图形的衬底基板上沉积一层非晶硅材料；以及
对该层非晶硅材料进行构图，形成所述非晶硅层的图形，所述非晶硅层为长条形，包括相对的第一端部、第二端部、位于所述第一端部和所述第二端部之间的中间部，所述中间部位于所述保温层上，所述第一端部和所述第二端部中的至少一个超出所述保温层之外。
在一实施例中，，所述第一端部和所述第二端部均超出所述保温层之外。
在一实施例中，，在所述第一端部超出所述保温层之外时，超出部分的长度范围为1-1.5μm。
在一实施例中，在所述第二端部超出所述保温层之外时，超出部分的长度范围为1-1.5μm。
在一实施例中，所述保温层为长条形，所述保温层与所述非晶硅层的延伸方向相同，所述保温层在垂直于所述延伸方向上的宽度大于所述中间部在垂直于所述延伸方向上的宽度。
在一实施例中，所述保温层在垂直于所述延伸方向上的宽度比所述中间部在垂直于所述延伸方向上的宽度大1-2μm。
在一实施例中，所述缓冲材料为SiNx，缓冲材料的厚度范围为50-100nm。
在一实施例中，所述保温材料为SiO2，保温材料的厚度范围为250-350nm。
在一实施例中，在激光退火工艺中，激光的能量范围为350mJ/cm2-450mJ/cm2，激光的照射时间范围为7-8分钟。
本公开另一方面还提供了一种薄膜晶体管，为采用如上所述的制作方法制作得到，所述薄膜晶体管包括位于保温层上由多晶硅组成的有源层，所述有源层包括位于保温层上的部分和超出所述保温层之外的部分。
本公开再一方面还提供了一种显示基板，包括如上所述的薄膜晶体管。
本公开又一方面还提供了一种显示装置，包括如上所述的显示基板。
附图说明
图1为现有技术中低温多晶硅薄膜晶体管的有源层的截面示意图；
图2为本公开实施例在衬底基板上形成缓冲层和保温层的示意图；
图3为本公开实施例对保温层进行构图的示意图；
图4为本公开实施例沉积非晶硅层的示意图；
图5为本公开实施例对非晶硅层进行构图的示意图；
图6为本公开实施例对非晶硅层进行准分子激光退火的示意图；
图7为本公开实施例薄膜晶体管的有源层的平面示意图。
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另 一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
附图标记：1衬底基板  2缓冲层  3有源层  4缓冲层  5保温层  6非晶硅层  7有源层。
如图1所示，低温多晶硅基板中通常是在衬底基板1上形成缓冲层2，并在缓冲层2上形成由低温多晶硅薄膜组成的有源层3。由于低温多晶硅薄膜晶粒间界缺陷态的大量存在导致薄膜晶体管的阈值电压不稳定和载流子迁移率不佳，并且当薄膜晶体管尺寸缩小时，阈值电压不稳定的问题将变得更为严重。目前，一般采用ELA和CW固态激光两步处理的方法使低温多晶硅薄膜的均匀性得到改善，但是这样增加了成本和工艺的复杂度，不利于实际应用
为了解决上述问题，本公开的实施例提供一种薄膜晶体管及其制作方法、显示基板和显示装置，能够以较低的成本制备晶粒尺寸较大且均匀性较好的多晶硅有源层，进而提高薄膜晶体管的载流子迁移率和阈值电压的稳定性。
本实施例提供一种薄膜晶体管的制作方法，所述薄膜晶体管包括栅极、源极、漏极和有源层，形成所述有源层的步骤包括：
形成保温层的图形；
在所述保温层上形成非晶硅层的图形，所述非晶硅层的图形包括位于所述保温层上的第一部分和超出所述保温层之外的第二部分；
利用激光退火工艺对所述非晶硅层的图形进行处理，形成由多晶硅组成的所述有源层。
本实施例中，非晶硅层的图形包括位于保温层上的第一部分和超出保温层之外的第二部分，在对非晶硅层激光退火后，超出保温层外的第二部分冷却的比较快会首先形核，第一部分冷却的比较慢会较慢形核，这样能够使得非晶硅层沿第二部分到第一部分的方向生长晶粒，从而可以控制晶粒的生长方向，提高多晶硅的均匀性；并且由于第一部分是形成在保温层上，由于保温层的存在，第一部分会冷却的比较慢，形成的晶粒也会比较大，从而能够以较低的成本制备晶粒尺寸较大且均匀性较好的多晶硅有源层，进而提高薄膜晶体管的载流子迁移率和阈值电压的稳定性。
非晶硅层位于保温层上的第一部分与保温层相接触，且在保温层 和非晶硅层都形成在衬底基板上时，第一部分在衬底基板上的正投影落入保温层在衬底基板上的正投影内，第二部分在衬底基板上的正投影位于保温层在衬底基板上的正投影之外。
保温层一般采用冷却速率比较慢的无机材料制成，保温层的冷却速率小于衬底基板的冷却速率，这样在对非晶硅层激光退火后，形成在保温层上的非晶硅层的温度下降地会比较慢。
为了防止衬底基板的部分杂质离子逸出到其他膜层中，对薄膜晶体管的性能造成影响，在保温层和衬底基板之间还设置有缓冲层，具体地，形成保温层的图形的步骤包括：
提供一衬底基板；
在所述衬底基板上沉积一层缓冲材料和一层保温材料，所述缓冲材料的厚度小于所述保温材料的厚度；
对该层保温材料进行构图，形成所述保温层的图形。
缓冲材料和保温材料选用不同的无机材料，由于缓冲层也具有一定的保温效果，如果将缓冲层设置的比较厚，由于第二部分位于缓冲层上，则在冷却时第一部分和第二部分的冷却速率之间的差异会比较小，因此，需要将缓冲层设置的比较薄，保温层设置的比较厚，这样能够使得在冷却时第一部分和第二部分的冷却速率之间的差异比较大。具体地，缓冲材料可以采用SiNx，厚度范围为50-100nm，保温材料可以采用SiO2，厚度范围为250-350nm。
一具体实施方式，在所述保温层的图形上形成非晶硅层的图形的步骤包括：
在形成有所述保温层的图形的衬底基板上沉积一层非晶硅材料；
对该层非晶硅材料进行构图，形成所述非晶硅层的图形，所述非晶硅层为长条形，包括相对的第一端部、第二端部、位于所述第一端部和所述第二端部之间的中间部，所述中间部位于所述保温层上，所述第一端部和所述第二端部中的至少一个超出所述保温层之外。
上述长条形是指非晶硅层的图形的大致形状为宽度远小于长度，具体地，非晶硅层的图形可以为直线形、波浪线形、弓字形等，在此不做限定。非晶硅层的图形也可以包括有多个端部，不局限有两个端部，但为了控制晶粒的生长方向，提高多晶硅的均匀性，非晶体层的图形的端部也不宜过多。例如，非晶硅层的图形包括有两个端部。
非晶硅层的图形的第一端部和第二端部中的至少一个超出保温层之外，这样在对非晶硅层激光退火后，超出保温层外的端部冷却的比较快会首先形核，其他部分冷却的比较慢会较慢形核，这样能够使得非晶硅层沿该超出保温层之外的端部到中间部的方向生长晶粒，从而可以控制晶粒的生长方向，提高多晶硅的均匀性；并且由于中间部是形成在保温层上，由于保温层的存在，中间部和/或位于保温层上的端部会冷却的比较慢，形成的晶粒也会比较大。
在一实施例中，所述第一端部和所述第二端部均超出所述保温层之外。这样在对非晶硅层激光退火后，能够沿从第一端部到中间部的方向和沿从第二端部到中间部的方向同时生长晶粒，提高生长晶粒的速度，使得在保温层冷却之前就完成晶粒的生长，提高形成的晶粒的尺寸。
在非晶硅层的图形具有超出保温层的部分时，非晶硅层的图形超出保温层部分的长度不宜设计的过长，因为，非晶硅层的图形超出保温层的部分仅是为了控制晶粒的生长方向，并且该部分是位于保温层之外，冷却的比较慢，形成的晶粒比较小，具体地，在所述第一端部超出所述保温层之外时，超出部分的长度范围为1-1.5μm；在所述第二端部超出所述保温层之外时，超出部分的长度范围为1-1.5μm。
进一步地，所述保温层可以也为长条形，与非晶硅层的图形的形状相匹配，所述保温层与所述非晶硅层的延伸方向相同，所述保温层在垂直于所述延伸方向上的宽度大于所述中间部在垂直于所述延伸方向上的宽度，这样能够保证非晶硅层的图形除端部之外的其他部分都位于保温层上。
本实施例的技术方案中，由于只需要保证非晶硅层的图形除端部之外的其他部分都位于保温层上即可，因此，保温层的宽度也不需要设置的过大，保温层在垂直于所述延伸方向上的宽度可以比所述中间部在垂直于所述延伸方向上的宽度大1-2μm。
当然，保温层的形状并不一定需要与非晶硅层的图形相匹配，保温层还可以为圆形、方形等其他形状，只要能够保证非晶硅层的图形第一部分位于保温层上，第二部分超出保温层之外即可。
进一步地，在激光退火工艺中，激光的能量范围为350mJ/cm2-450mJ/cm2，激光的照射时间范围为7-8分钟。当然，激光 退火工艺还可以采用其它的工艺参数，并不限定采用上述参数。
下面结合附图对本实施例的薄膜晶体管的有源层的制作方法进行详细介绍：
步骤1、如图2所示，提供一衬底基板1，在衬底基板1上形成缓冲层4和保温层5；
衬底基板1可为玻璃基板或石英基板。具体地，在对衬底基板1进行清洗后，可以采用等离子体增强化学气相沉积(PECVD)方法在衬底基板1上沉积厚度范围为50～100nm的缓冲层4，缓冲层4可以覆盖整个衬底基板1，能够防止衬底基板1中的杂质离子逸出，影响薄膜晶体管的性能，缓冲层4可以选用氧化物、氮化物或者氧氮化合物，具体可以采用SiNx。
在缓冲层4上可以采用等离子体增强化学气相沉积(PECVD)方法沉积厚度范围为250-350nm的保温层5，保温层5可以采用氧化物、氮化物或者氧氮化合物，具体可以采用SiO2。
步骤2、如图3所示，对保温层5进行构图，形成保温层5的图形；
具体地，在保温层5上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域。光刻胶保留区域对应于保温层5的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的保温层5，剥离剩余的光刻胶，形成保温层5的图形。
具体地，如图7所示，保温层5的图形大致为长条形，包括首尾依次相接的第一线段、第二线段、第三线段、第四线段和第五线段，第一线段与第二线段垂直，第二线段与第三线段垂直，第三线段与第四线段垂直，第四线段与第五线段垂直。
步骤3、如图4所示，在完成步骤2的衬底基板1上沉积非晶硅层6；
可以采用等离子体增强化学气相沉积(PECVD)方法在衬底基板1上沉积厚度范围为40～50nm的a-Si作为非晶硅层6，并在OVEN(高温退火)炉中完成去氢工艺。
步骤4、如图5所示，对非晶硅层6进行构图，形成非晶硅层6的 图形；
具体地，在非晶硅层6上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域。光刻胶保留区域对应于非晶硅层6的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的非晶硅层6，剥离剩余的光刻胶，形成非晶硅层6的图形。
具体地，如图7所示，非晶硅层6的大致为长条形，包括两头的第一端部、第二端部、位于所述第一端部和所述第二端部之间的中间部，所述中间部位于所述保温层上，所述第一端部和所述第二端部均超出所述保温层之外，超出部分的长度S为1-1.5μm。保温层5在垂直于延伸方向上的宽度超出非晶硅层6的中间部在垂直于延伸方向上的宽度，超出部分的宽度D为1-2μm。
步骤5、如图6所示，利用ELA工艺对非晶硅层6的图形进行处理，得到有源层7。
利用准分子激光退火工艺完成非晶硅向多晶硅的转变，激光的能量范围为350mJ/cm2～450mJ/cm2，激光的照射时间范围为7-8分钟。
在对非晶硅层6激光退火后，非晶硅层6超出保温层5外的第一端部和第二端部冷却的比较快会首先形核，中间部冷却的比较慢会较慢形核，这样能够使得非晶硅层沿从第一端部到中间部和第二端部到中间部的方向生长晶粒，从而可以控制晶粒的生长方向，提高多晶硅的均匀性；并且由于中间部是形成在保温层5上，由于保温层5的存在，中间部会冷却的比较慢，形成的晶粒也会比较大，从而能够以较低的成本制备晶粒尺寸较大且均匀性较好的多晶硅有源层，进而提高薄膜晶体管的载流子迁移率和阈值电压的稳定性。
经过上述步骤1-5即可制作得到薄膜晶体管的有源层，之后可以采用现有工艺制作薄膜晶体管的栅绝缘层、栅极、中间绝缘层、源极和漏极，即可得到薄膜晶体管。
本实施例提供了一种薄膜晶体管，为采用如上所述的制作方法制作得到，所述薄膜晶体管包括位于保温层上由多晶硅组成的有源层，所述有源层包括位于保温层上的部分和超出所述保温层之外的部分。
由于在该薄膜晶体管有源层的形成过程中，是在保温层上形成非晶硅层的图形，所述非晶硅层的图形包括位于所述保温层上的第一部分和超出所述保温层之外的第二部分，再利用激光退火工艺对所述非晶硅层的图形进行处理，在对非晶硅层激光退火后，超出保温层外的第二部分冷却的比较快会首先形核，第一部分冷却的比较慢会较慢形核，这样能够使得非晶硅层沿第二部分到第一部分的方向生长晶粒，从而可以控制晶粒的生长方向，提高多晶硅的均匀性；并且由于第一部分是形成在保温层上，由于保温层的存在，第一部分会冷却的比较慢，形成的晶粒也会比较大，从而能够以较低的成本制备晶粒尺寸较大且均匀性较好的多晶硅有源层，进而提高薄膜晶体管的载流子迁移率和阈值电压的稳定性。
本实施例提供了一种显示基板，包括如上所述的薄膜晶体管。由于上述薄膜晶体管的载流子迁移率较高，阈值电压比较稳定，因此，与现有显示基板相比，本实施例的显示基板的性能也会比较可靠。
本实施例还提供了一种显示装置，包括如上所述的显示基板。所述显示装置可以为：显示面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。所述显示装置还包括柔性电路板、印刷电路板和背板。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
以上所述是本公开的实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (14)

  1. 一种薄膜晶体管的制作方法，所述薄膜晶体管包括栅极、源极、漏极和有源层，其中形成所述有源层的步骤包括：
    形成保温层的图形；
    在所述保温层上形成非晶硅层的图形，所述非晶硅层的图形包括位于所述保温层上的第一部分和超出所述保温层之外的第二部分；以及
    利用激光退火工艺对所述非晶硅层的图形进行处理，形成由多晶硅组成的所述有源层。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其中所述形成保温层的图形包括：
    提供一衬底基板；
    在所述衬底基板上沉积一层缓冲材料和一层保温材料，所述缓冲材料的厚度小于所述保温材料的厚度；以及
    对该层保温材料进行构图，形成所述保温层的图形。
  3. 根据权利要求2所述的薄膜晶体管的制作方法，其中所述在所述保温层的图形上形成非晶硅层的图形包括：
    在形成有所述保温层的图形的衬底基板上沉积一层非晶硅材料；以及
    对该层非晶硅材料进行构图，形成所述非晶硅层的图形，所述非晶硅层为长条形，包括相对的第一端部、第二端部、位于所述第一端部和所述第二端部之间的中间部，所述中间部位于所述保温层上，所述第一端部和所述第二端部中的至少一个超出所述保温层之外。
  4. 根据权利要求3所述的薄膜晶体管的制作方法，其中所述第一端部和所述第二端部均超出所述保温层之外。
  5. 根据权利要求3所述的薄膜晶体管的制作方法，其中在所述第一端部超出所述保温层之外时，超出部分的长度范围为1-1.5μm。
  6. 根据权利要求3所述的薄膜晶体管的制作方法，其中在所述第二端部超出所述保温层之外时，超出部分的长度范围为1-1.5μm。
  7. 根据权利要求3所述的薄膜晶体管的制作方法，其中所述保温层为长条形，所述保温层与所述非晶硅层的延伸方向相同，所述保温 层在垂直于所述延伸方向上的宽度大于所述中间部在垂直于所述延伸方向上的宽度。
  8. 根据权利要求7所述的薄膜晶体管的制作方法，其中所述保温层在垂直于所述延伸方向上的宽度比所述中间部在垂直于所述延伸方向上的宽度大1-2μm。
  9. 根据权利要求2所述的薄膜晶体管的制作方法，其中所述缓冲材料为SiNx，并且厚度范围为50-100nm。
  10. 根据权利要求2所述的薄膜晶体管的制作方法，其中所述保温材料为SiO2，并且厚度范围为250-350nm。
  11. 根据权利要求1所述的薄膜晶体管的制作方法，其中在激光退火工艺中，激光的能量范围为350mJ/cm2-450mJ/cm2，激光的照射时间范围为7-8分钟。
  12. 一种薄膜晶体管，其中为采用如权利要求1-11中任一项所述的制作方法制作得到，所述薄膜晶体管包括位于保温层上由多晶硅组成的有源层，所述有源层包括位于保温层上的部分和超出所述保温层之外的部分。
  13. 一种显示基板，包括如权利要求12所述的薄膜晶体管。
  14. 一种显示装置，包括如权利要求13所述的显示基板。
PCT/CN2017/115887 2017-02-09 2017-12-13 薄膜晶体管及其制作方法、显示基板和显示装置 Ceased WO2018145515A1 (zh)

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