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WO2018143812A1 - Dispositif à semiconducteur ayant une jonction - Google Patents

Dispositif à semiconducteur ayant une jonction Download PDF

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Publication number
WO2018143812A1
WO2018143812A1 PCT/NL2018/050080 NL2018050080W WO2018143812A1 WO 2018143812 A1 WO2018143812 A1 WO 2018143812A1 NL 2018050080 W NL2018050080 W NL 2018050080W WO 2018143812 A1 WO2018143812 A1 WO 2018143812A1
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Prior art keywords
terminal
top layer
bulk
region
semiconductor device
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English (en)
Inventor
Lis Karen Nanver
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Lisz BV
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Lisz BV
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/115—Resistive field plates, e.g. semi-insulating field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/043—Manufacture or treatment of planar diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/045—Manufacture or treatment of PN junction diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/411—PN diodes having planar bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes

Definitions

  • the various aspects and embodiments thereof relate to a semiconductor device having a junction between a first region having a first conductivity type extending from the top surface and a second region having a second conductivity type opposite to the first conductivity type extending from the top surface and adjacent to the first bulk area.
  • An ideal diode has not voltage over it in forward mode, irrespective from the current through it and transmits no current in backward mode, irrespective of the voltage applied over it.
  • virtually every semiconductor diode has a reverse breakdown voltage.
  • the breakdown voltage depends on various parameters, like the amount of defects in the current path and the doping level. At the surface, the breakdown electrical field is usually significantly lower than in the bulk.
  • a reason for this is that at a boundary of the semiconductor bulk and in particular a boundary between a monocrystalline semiconductor material and an isolation like an oxide of the semiconductor material, many defects are present, like dangling bonds and/or other defects. Defects can be a source of degradation, i.e., increase of leakage current and reduction of breakdown voltage, when the boundary is exposed to electrical stress or radiation. From that perspective, charge carrier transport at the
  • a first aspect provides a semiconductor device.
  • the device comprises a semiconductor bulk having a top surface, a first bulk region having a first conductivity type extending from the top surface and a second bulk region having a second conductivity type opposite to the first
  • the device further comprises a first terminal for providing an electrical contact to the first bulk region, a second terminal for providing an electrical contact to the second bulk region which second terminal is laterally spaced apart from the first terminal.
  • a top layer is provided, the top layer comprising at least 50% and preferably at least 99% of a group III or group V material, the layer covering at least a boundary between the first bulk region and the second bulk region.
  • the atoms of the top layer may align with silicon atoms at the top of the crystalline semiconductor bulk. This passivates bonds of the semiconductor substrate at the top, which reduces defects and with that, this increases the breakdown field strength.
  • the top layer may function as a resistive voltage divider over the junction. In this way, high field peaks are smoothened out throughout the bulk, near the junction and at the surface. Also this effect increases the breakdown field strength.
  • the second sub-region comprises third sub- regions having the same conductivity type as the second of the first bulk region and the second bulk region.
  • the third sub-regions act as guard rings for evening out any peaks in electrical field strength.
  • a first of the first bulk region and the second bulk region comprises a first sub-region having a first doping level and a second sub-region having a second doping level, the first sub-region has a higher doping level than the second sub-region; and the second sub- region is provided between the first sub-region and a second of the first bulk region and the second bulk region.
  • the top layer after deposition of the top layer, has a sheet resistance of at least 1 ⁇ /sq with a voltage of zero volts applied between the first terminal and the second terminal. This allows the top layer to function as a voltage divider which, in turn, evens out peaks in the electrical field below the top layer and at junctions in particular.
  • the surface of the bulk should be well treated and the top layer material should be deposited at a temperature that is not too high. The latter point is important, as a higher temperature may result in atoms of the top layer diffusing in the semiconductor bulk layer - which is not preferred.
  • the semiconductor device comprises a dielectric layer(-stack) provided on top of the top layer.
  • the layers on top of the top layer may be designed to block as much
  • the dielectric layer has a transparency of at least 10% for electromagnetic waves having a wavelength between 0.01 nanometres and 2000 nanometres and preferably between 100 nanometres and 400 nanometres. This embodiment allows the semiconductor device to be used as a detector of radiation.
  • the dielectric layer has a transparency of at least 10% for particles, including, but not limited to alpha particles, electrons, positrons, neutrons and protons.
  • a second aspect provides a method of manufacturing a semiconductor device according to any of the preceding claims.
  • the method comprises providing a semiconductor bulk having a top surface, introducing donor atoms in the semiconductor bulk via a first area of the top surface, introducing acceptor atoms in the semiconductor bulk via a second area of the top surface, the second area being adjacent to the first area.
  • the method further comprises providing a top layer on the top surface, the top layer comprising at least 50% and preferably 99% of a group III or group V material, the layer covering at least a boundary between the first bulk region and the second bulk region, providing a first terminal for providing an electrical contact to the first bulk region and providing a second terminal for providing an electrical contact to the second bulk region which second terminal is laterally spaced apart from the first terminal.
  • the voltage along the top layer can be modified by placing and biasing electrodes at different positions along the top layer.
  • Figure 1 A shows a symbolic representation of a diode
  • Figure 1 B shows a high level implementation of a practical surface based diode
  • Figure 2 shows a detailed view of a surface based diode
  • Figure 3 shows another detailed view of a surface based diode
  • Figure 4 shows a further detailed view of a surface based diode
  • Figure 5 shows another implementation of the surface based diode
  • Figure 6 shows a surface based diode with an isolation layer on top of it
  • Figure 7 A shows a first topology of a surface based diode
  • Figure 7 B shows a second topology of a surface based diode
  • Figure 7 C shows a third topology of a surface based diode
  • Figure 8 shows another embodiment of a diode having a junction boundary ending at a top surface of a semiconductor bulk.
  • Figure 1 A shows a symbol for a diode.
  • the diode comprises an anode 110 and a cathode 120.
  • Figure 1 B shows the diode 100 having a practical implementation, the diode 100 comprising semiconductor bulk 200 with the anode 110 and the cathode 120 provide at the top of the
  • the diode 100 comprises a semiconductor bulk 200 having a first bulk region 220 having a first conductivity type and a second bulk region 230 having a second conductivity type opposite to the first conductivity type.
  • the bulk preferably comprises a group-IV element material, comprising silicon, germanium, sihcon germanium, germanium tin, carbon or silicon carbide, another group- IV element or a combination thereof.
  • the semiconductor bulk 200 comprises a mix of group-Ill and group-V elements, of each group in substantially equal amounts.
  • the semiconductor bulk 200 may comprise boron, aluminium, gallium and/or indium as one part of the mix and nitride, phosphorus, arsenic and/or antimony as another part of the mix.
  • Nanver SBMicro2012 proc discusses experiments showing the use of Ga depositions on Si and Ge to form ideal p+n junctions on either Si or Ge single crystals, (ref: L. K. Nanver, A. Sammak, V. Mohammadi, K. R. C. Mok, L. Qi, A. Sakic, N. Golshani, J. Derakhshandeh, T. M. L. Scholtes, and W. D. de Boer, "Pure dopant deposition of B and Ga for ultrashallow junctions in Si-based devices," ECS Trans., vol. 49, no. 1, pp. 25-33, Sep. 2012).
  • N-type induced junction black Si photo-diode for UV detection discloses the use of an aluminium containing material (AI2O3) as a means of inducing a p + n junction on n-type silicon.
  • the first conductivity type is p-type.
  • the first bulk region 220 may comprise acceptor atoms and has an acceptor atom dopant level between zero and 10 21 per cubic centimetre.
  • the acceptor atoms are preferably group - III elements including, but not limited to boron, aluminium, galhum and indium, other or a combination thereof.
  • the second conductivity type is n-type.
  • the first bulk region 230 may comprise donor atoms and has a donor atom dopant level between zero and 10 21 per cubic centimetre.
  • the dopant atoms are preferably group -V elements including, but not limited to phosphorus, arsenic, antimony other or a combination thereof.
  • the dopant atoms may be introduced in the semiconductor bulk 200 by means of implantation, diffusion, deposition of group-IV material with the dopant atoms, other, or a combination thereof.
  • a dashed line is provided indicating a boundary between the first bulk region 220 and the second bulk region 230. In practice this will in most cases not be a strict boundary, but more or a boundary region, albeit a very narrow region.
  • a top layer 210 is deposited.
  • the top layer 210 preferably comprises at least 50% boron. More preferably, the top layer 210 comprises at least 75%, 80%, 90%, 95%, 99%, 99,99% and 99,99999% boron.
  • the top layer comprises another group-Ill material with the same purity level, including, but not limited to aluminium, gallium and indium.
  • the top layer 210 comprises a group -V element, including, but not limited to phosphorous, arsenic, antimony, other, or a combination thereof.
  • the top layer 210 preferably has a sheet resistance of at least 1 ⁇ /sq and more preferably at least 10 ⁇ /sq, at least 10 2 ⁇ /sq, at least 1 ⁇ /sq, or at least 1 ⁇ /sq. In the embodiments discussed below, the top layer 210 will be discussed as predominantly comprising boron, but this does not exclude other options. With such sheet resistance, the top layer 210 functions as a voltage divider, providing a more constant field strength along the top surface of the semiconductor bulk 200 compared to a case when the top layer 210 was not present.
  • contact pads are provided.
  • the anode contact pad 112 is provided on the p-type region and the cathode contact pad 120 is provided at the n-type region.
  • the contact pads preferably comprise a metal, including but not limited to tungsten, copper or aluminium, other, or a combination thereof.
  • the contact pads preferably provide an ohmic contact to the semiconductor bulk 200.
  • a silicide material (not shown) may be provided between the contact pads and the semiconductor bulk 200.
  • a layer 212 with holes as excess charge carriers is created at the surface of the semiconductor bulk 200.
  • the hole layer preferably has a sheet resistance of at least 1 k ⁇ /sq, preferably at least 10 kQ/sq, at least 30 k /sq and more preferred at least 1 ⁇ /sq.
  • the hole layer 212 will be depleted upon reverse biasing and the sheet resistance could then increase to the ⁇ /sq range. If the top layer predominantly comprises a type-V material, the surface layer 212 comprises electrons as excess charge carriers.
  • the top layer 210 and hole layer 212 provide a conductive path between the anode and the cathode.
  • an optional layer contact 132 may be provided for picking up charge flowing along the surface of the bulk, through the top layer 210 ancl/or the surface layer 212.
  • the adjacent p-type material and n-type material result in a depletion region 204, indicated by the dotted lines.
  • Figure 2 shows the depletion region 204 with the top layer 210 predominantly comprising boron.
  • FIG. 3 shows a practical embodiment of the semiconductor device according to the first aspect.
  • the diode 100 comprises a
  • semiconductor bulk 200 comprising one or more group-IV materials, preferably silicon, germanium, tin, or carbon, like silicon germanium or silicon carbide.
  • the semiconductor bulk 200 is doped with donor atoms at a doping level between 0 and 10 19 atoms per cubic centimetre.
  • a p-type doping region 240 is provided within the semiconductor bulk 200.
  • the doping level of the p-type doping region 240 is between 0 and 10 21 atoms per cubic centimetre.
  • the p-type doping region 240 is preferably between 0.1 micrometres and 10 micrometres deep, depending on required characteristics of the diode 100.
  • the doping level of the n-type doping region 240 is higher than the doping level of the semiconductor bulk 200, but this is not necessary.
  • an n-type doping region 250 is provided.
  • the distance between the p-type doping region 240 and the n-type doping region 250 depends on what voltage the diode 100 is to withstand. With a theoretical breakdown field of about 3 10 5 Volt per centimetre at a doping level of 3x 10 14 atoms per cubic centimetre, the distance between the two regions should be at least 30 micrometres to withstand a reverse voltage of 600 Volt. This distance should increase with decreasing doping level of the semiconductor bulk 200. However, as the practical breakdown field is usually significantly lower than the theoretical breakdown field, the diode 100 is preferably designed with a larger distance between the p-type doping region 240 and the n-type doping region 250.
  • the doping level of the n-type doping region 250 is between 0 and 10 21 atoms per cubic centimetre.
  • the n-type doping region 250 is preferably between 0.1 micrometres and 10 micrometres deep, depending on required characteristics of the diode 100.
  • the doping level of the n-type doping region 250 is higher than the doping level of the semiconductor bulk 200, but this is not necessary.
  • the semiconductor bulk 200 having an n-type conductivity type and the n-type doping region 250 form a region having an n-type conductivity type, with the n-type doping region 250 forming a first n-type sub-region and the semiconductor bulk 200 forming a second n-type sub -region.
  • FIG 3 also shows the top layer 210 discussed above.
  • the top layer 210 predominantly comprises boron. This results in a layer with holes as excess charge carriers being located below the top layer, at the surface of the semiconductor bulk 200.
  • the top layer 210 is contacted by an anode contact pad 112 and a cathode contact pas 122.
  • a depletion region 204 extends from the p-type doping region 240 to the n-type doping region 250. Between these regions, the bulk region is fully depleted in this embodiment, wherein the doping level of the p-type doping region 240 is one, two or more orders of magnitude higher than the doping level of the bulk. If the doping levels are of the same order, the depletion region 204 will not extend as far into the n-type region.
  • the depletion layer is at the top bound by a surface hole layer 212.
  • the surface hole layer 212 is located at the surface of the
  • the top layer 210 that induces hole layer 212 functions as a voltage divider, providing a more constant field strength along the top surface of the semiconductor bulk 200 compared to a case when the top layer 210 was not present. However, in some cases, this measure may not be sufficient for reducing local peaks of electrical field strength at the surface of the semiconductor bulk 200 in order to increase breakdown voltage of the diode 100.
  • intermediate p-type pockets are provided in the second n-type sub-region, the semiconductor bulk 200 between the p-type doping region 240 and the n-type doping region 250.
  • Figure 4 shows p-type pockets 410 extending from the top surface of the semiconductor bulk 200 between the p-type doping region 240 and the n-type doping region 250.
  • the surface hole layer 212 is also present in the device depicted by Figure 4, but it has been omitted for the sake for clarity.
  • Figure 5 shows another implementation of the diode 100. Most elements are the same as the implementation shown by Figure 3, which elements will not be specifically mentioned again. Different than depicted by Figure 3, the top layer 210 does not extend to the n-type doping region 250.
  • a layer contact 132 is provided on the top layer 210, at or nearby a boundary of the top layer 210 for separate biasing and picking up current from the top layer 210. Whereas the current through the top layer 210 will in most cases be relatively low or even negligible by virtue of the high sheet resistance of the top layer, further reduction of the reverse current has positive effects and is even preferred in certain embodiments.
  • influence of the current through the top layer is preferably reduced by means of the layer contact 132.
  • Figure 5 does show the top layer 210 in contact with the p-type doping region 240 and not in contact with the n-type doping region 250.
  • the top layer 210 is in contact with the n-type doping region 250 and not in contact with the p-type doping region 240.
  • the top layer 210 is not in contact with either one of the n-type doping region 250 and the p-type doping region 240.
  • other and optionally more electrodes are provided in contact with the top layer 210. Depending on the voltage applied to the extra electrodes, this can allow a part of the voltage drop over diode 100 to fall over an insulating region.
  • the electrode also provides a sink for any charge that may disturb any measurements.
  • preferably contacts are provided at the top layer 210 at opposite ends of the top layer 210.
  • FIG. 6 shows the diode 100 with an isolation layer 510 provided on top of the semiconductor bulk 200 and the top layer 210.
  • contact holes are provided, which are filled with metal plugs for contacting the p-type doping region 240 and the n-type doping region 250.
  • the metal plugs may comprise aluminium, tungsten, copper, other, or a combination thereof.
  • the isolating material may be polished.
  • the diode 100 may be used as a sensor for detecting radiation and measuring a radiation level.
  • radiation may be particle radiation, including, but not limited to electron, positron, proton, neutron and/or alpha particle radiation.
  • the diode 100 is suitable for detecting and measuring level of electromagnetic radiation.
  • the diode 100 is suitable for detecting and measuring radiation having wavelengths between 0.01 nanometres and 2000 nanometres. Measurement and detection of electromagnetic radiation having a wavelength between 10 nanometres and 400 nanometres is particularly preferred.
  • electromagnetic radiation covers the extreme ultraviolet, deep ultraviolet and ultraviolet spectrum. This type of radiation is used in medical imaging and wafersteppers used for manufacturing of integrated circuits, which makes the diode 100 suitable for use in such apparatus.
  • the isolation layer 510 is at least somewhat transparent to the radiation to be detected and/or of which the level is to be measured.
  • the isolation layer 510 is at least 20% transparent to the relevant radiation, in case applicable to the relevant radiation in the relevant part of the spectrum. A transparency of at least 50%, 60%, 75%, 80%, 90% or 99% is preferred as well.
  • the isolation layer may comprise S1O2, SiN x , AI2O3, AIN, Hf02, oxynitrides, other, or a combination thereof.
  • a particular material or mix of materials may be selected.
  • Figure 7 A, Figure 7 B and Figure 7 B show possible topologies for the diode 100 to be used as a radiation detector.
  • Figure 7 A shows a rectangular and in particular square top layer 210 between two elongated, preferably rectangular contacts, providing an anode 110 and a cathode 120.
  • Figure 7 B shows the anode 110 and the cathode 120 having a comb structure, with the teeth of both comb structures being interleaved.
  • the top layer 210 is provided between the teeth of the combs.
  • Figure 7 C shows a small cathode 120 within a circular anode 110.
  • the cathode 120 is
  • planar devices are presented having a junction with a boundary having a directional component substantial perpendicular to the upper surface and/or a junction at the surface.
  • charge carrier transport takes at least partially place along the upper surface.
  • Triacs and other switching devices are known that have a junction with a directional component perpendicular to the surface -so having a junction at the surface -, but not at the upper surface.
  • Figure 8 shows a diode having an anode contact 112 at the top and a cathode contact 122 at the bottom.
  • the diode 100 comprises a semiconductor bulk having a first bulk region 220 having a first conductivity type, p-type in this embodiment, and a second bulk region 230 having a second conductivity type opposite to the first conductivity type - n-type in this embodiment.
  • the edges of the bulk are bevelled.
  • the bevel structure may be achieved by mechanical means, physical etching, chemical etching - wet and/or dry, other processes or a combination thereof.
  • the majority of charge carrier transport takes place in the bulk, but a part will flow along the bevelled edges.
  • defects at the bevelled top surface of the diode 100 as depicted by Figure 8 may seriously decrease the breakdown voltage of the diode 100. This is also the case if the bevelled top surface is covered with an insulating passivation layer.
  • Such passivation layers may include charge, the amount of which may depend on an amount of stress applied. Furthermore, defects may exist, remain to exist or occur at the interface with the passivation. Application of the top layer 210 as discussed above on the surface on which a junction boundary 202 ends may reduce the amount of defects that are detrimental to the (reverse) breakdown voltage of the diode 100 as depicted by Figure 8.
  • the diode 100 can be manufactured using a combination of various process technologies. Doped or undoped monocrystalline semiconductor wafers are commercially available, with various material compositions, including sihcon, sihcon germanium, silicon carbide, germanium and a wide range of III-V mixtures, including gallium arsenide.
  • the - preferably - higher doped p-type and n-type regions may be selectively implanted. Otherwise, the higher doped p-type and n- type regions are created by etching of blanket deposited layers. The areas where the implants are not to be provided may be masked by means of a photolithographic process and covered by photoresist, another layer blocking atoms to be implanted, or a combination thereof. Alternatively or
  • a diffusion process may be used, with a gaseous, liquid or solid source of dopant atoms.
  • an implant step may be followed by a diffusion and/or annealing step at increased temperatures. This step is executed twice, once for acceptor atoms and once for donor atoms.
  • the top layer is deposited.
  • the top layer is deposited at a temperature at which the atoms of the top layer material do not diffuse into the bulk material - or only diffuse to a very low extent. Studies have shown that when using boron as a material for the top layer, the temperature is preferably kept around 400 degrees Centigrade or lower. At such
  • the top layer thus created may optionally be patterned.
  • the sheet resistance is preferably very high - in the order of 1 GQ - presence of the boron layer at locations where it is not required mostly does not raise any issues. In case this would cause any problems, patterning is preferred.
  • the isolation layer 510 and the contact pads are created.
  • metal or another highly conductive material is deposited and patterned. This is followed by deposition of the isolation layer 510, formation of contact holes in the isolation layer 510 and filling the contact holes with metal.
  • the metal deposition step prior to deposition of the isolation layer 510 is omitted.
  • a silicide may be formed at the locations where the anode and cathode terminals are provided.
  • metal is patterned while deposited on the top layer 212. This allows metal to be patterned before deposition of the isolation layer 510. Additionally or alternatively, a lift-off process can be used to deposit metal only on contacting regions. In another alternative or additional option, the metal may be removed from other regions by wet- etching to the top layer, for example as proposed by A. Sakic, et al., "High- efficiency silicon photodiode detector for sub-keV electron microscopy," IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 59, NO. 10, OCTOBER 2012, pages 2707 to 2714.
  • the invention may also be embodied with less components than provided in the embodiments described here, wherein one component carries out multiple functions.
  • the invention be embodied using more elements than depicted in the Figures, wherein functions carried out by one component in the embodiment provided are distributed over multiple components.

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Abstract

Un premier aspect de l'invention concerne un dispositif à semiconducteur. Le dispositif comprend un substrat semiconducteur ayant une surface supérieure, une première région de substrat ayant un premier type de conductivité s'étendant à partir de la surface supérieure et une seconde région de substrat ayant un second type de conductivité opposé au premier type de conductivité s'étendant à partir de la surface supérieure et adjacente à la première région de substrat. Le dispositif comprend en outre une première borne pour fournir un contact électrique à la première région de substrat, une seconde borne pour fournir un contact électrique à la seconde région de substrat, laquelle seconde borne est espacée latéralement de la première borne. Sur la surface supérieure, une couche supérieure est prévue, la couche supérieure comprenant au moins 50 % et de préférence au moins 99 % d'un matériau du groupe III ou du groupe V, la couche recouvrant au moins une limite entre la première région de substrat et la seconde région de substrat.
PCT/NL2018/050080 2017-02-06 2018-02-06 Dispositif à semiconducteur ayant une jonction Ceased WO2018143812A1 (fr)

Applications Claiming Priority (2)

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NL2018309 2017-02-06
NL2018309A NL2018309B1 (en) 2017-02-06 2017-02-06 semiconductor device having a junction

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2071411A (en) * 1980-03-07 1981-09-16 Philips Electronic Associated Passivating p-n junction devices
WO1998037584A1 (fr) * 1997-02-20 1998-08-27 The Board Of Trustees Of The University Of Illinois Dispositif transistorise de commande de puissance utilisant des nitrures du groupe iii
DE102005020091A1 (de) * 2005-04-29 2006-11-09 Infineon Technologies Austria Ag Integrierte Halbleiterbauelementeanordnung und Verfahren zu deren Herstellung
EP1903600A2 (fr) * 2006-09-20 2008-03-26 Toyota Jidosha Kabushiki Kaisha Procédé de production de semi-conducteur de type P en nitrure du groupe III et procédé pour produire une électrode pour semi-conducteur de type P en nitrure du groupe III

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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