WO2018143489A1 - Turbo code encoder and encoding method for improving error correction efficiency - Google Patents

Abstract

An improved turbo code encoding method and an encoder therefor are disclosed. The encoder in the present disclosure may comprise four delayers. Also, the encoder may determine a circulation state through pre-encoding and, based on the circulation state, generate a turbo code having a tail-biting structure. Furthermore, the encoder may comprise a switching circuit and work just like the conventional LTE turbo code encoders by turning off the switching circuit.

Description

Turbo Code Encoder and Encoding Method for Improving Error Correction Efficiency

The present invention relates to a channel coding method in a wireless communication system, and more particularly, to a turbo code encoder and an encoding method having an improved error correction efficiency.

Wireless access systems are widely deployed to provide various kinds of communication services such as voice and data. In general, a wireless access system is a multiple access system capable of supporting communication with multiple users by sharing available system resources (bandwidth, transmission power, etc.). Examples of multiple access systems include code division multiple access (CDMA) systems, frequency division multiple access (FDMA) systems, time division multiple access (TDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, and single carrier frequency (SC-FDMA). division multiple access) system.

In addition to the communication systems described above, channel codes are essentially used in broadcast systems. As an example of a general method of configuring a channel code, a transmitter may perform encoding on an input symbol by using an encoder and transmit an encoded symbol. Also, for example, the receiving end may restore the input symbol by receiving the encoded symbol and performing decoding on the received symbol. In this case, the size of the input symbol and the size of the encoded symbol may be defined differently according to the communication system. For example, in a turbo code for data information used in the Long Term Evolution (LTE) communication system of the 3rd Generation Partnership Project (3GPP), an input symbol has a maximum size of 6144 bits and a coded symbol size 18432 (6144 * 3) bits. Turbo coding in an LTE communication system may be referred to by 3GPP Technical Specification 36.212.

However, the LTE turbo code has a slight improvement in performance even if the signal to noise ratio (SNR) increases due to the structure of the code. In this regard, it may be considered to use a code having a lower error rate, but in this case, there is a problem that the complexity increases.

High error rates in communication systems can lead to unnecessary data retransmissions and channel reception failures. In addition, the code of too high complexity not only increases the load of the base station and the terminal, but may also cause transmission and reception delays. In particular, in the next generation communication system requiring faster data transmission and reception, the above-mentioned problems are required to be solved. Therefore, there is a need for a coding method having a low complexity while lowering an error rate.

In particular, the current LTE turbo code has a problem that an error floor occurs when the size of information increases. Accordingly, there is a need for a channel coding method capable of satisfying Ultra Reliable Radio (URR) and Low Latency Radio (LLR).

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for generating a turbo code having a tail duty structure while having backward compatibility with a conventional LTE turbo code. To provide.

Another object of the present invention is to provide an apparatus supporting these methods.

Technical objects to be achieved in the present invention are not limited to the above-mentioned matters, and other technical problems which are not mentioned are those skilled in the art from the embodiments of the present invention to be described below. Can be considered.

The turbo code encoding method of the present application for solving the above problems comprises the steps of pre-coding the input signal; Determining an end state based on the precoding; Determining a preset cyclic state based on the determined end state and the length of the input signal; And encoding the input signal into a turbo code having a tail-biting structure based on the determined cyclic state, wherein the encoder includes a forward path from an input terminal to an output terminal and the output terminal. A recursive path from to the input end, wherein the output end of the forward path has an exclusive OR (XOR) value of the input signal, the input signal delayed once, and the input signal delayed four times. The input terminal of the recursive path may be applied with a value obtained by XORing the input signal, the input signal delayed three times, and the input signal delayed four times.

In addition, a turbo code encoder for solving the above-described problems may include: a first node, a second node, and a third configured to output an exclusive OR (XOR) of the received signal values, respectively; A node, a fourth node, a fifth node, a sixth node, a seventh node, and an eighth node; A first delayer, a second delayer, a third delayer, and a fourth delayer, each of which is configured to delay and output the received signal once, and is sequentially connected between the first node and the fifth node. ; A first switching circuit connected between the fourth node and the fifth node; And a second switching circuit connected between the seventh node and the eighth node, wherein the first node receives an input signal and a signal from the eighth node, and supplies the second node and the first delay unit to the second node and the first delay node. Output a signal, wherein the second node is configured to receive signals from the first delayer and the first node, and output a signal to the third node, wherein the third node is configured to output the signal to the second node. And receive a signal from the third delayer and output a signal to the fourth node, the fourth node receiving the signal from the third node and passing through the first switching circuit. Receive a signal from a node and output an output signal, wherein the fifth node receives signals from the third delayer and the fourth delayer, and through the first switching circuit, the fourth node The sixth node is configured to receive signals from the second delayer and the third delayer and to output a signal to the eighth node, wherein the seventh node is configured to output the signal to the eighth node. Receive signals from the second delayer and the fourth delayer, and output a signal to the eighth node through the second switching circuit, the eighth node receiving a signal from the sixth node and And receiving a signal from the seventh node through the second switching circuit and outputting a signal to the first node.

The above-described aspects of the present invention are merely some of the preferred embodiments of the present invention, and various embodiments reflecting the technical features of the present invention will be described in detail by those skilled in the art. Based on the description, it can be derived and understood.

According to embodiments of the present invention has the following effects.

The encoder of the present invention may have backward compatibility with a conventional LTE turbo encoder.

In addition, the encoder of the present invention may perform turbo code encoding having a tail biting structure.

In addition, the encoder of the present invention may perform turbo code encoding, which may satisfy the URLLC environment.

Effects obtained in the embodiments of the present invention are not limited to the above-mentioned effects, and other effects not mentioned above are usually described in the technical field to which the present invention pertains from the description of the embodiments of the present invention. Can be clearly derived and understood by those who have That is, unintended effects of practicing the present invention may also be derived from those skilled in the art from the embodiments of the present invention.

It is included as part of the detailed description to assist in understanding the present invention, and the accompanying drawings provide various embodiments of the present invention. In addition, the accompanying drawings are used to describe embodiments of the present invention in conjunction with the detailed description.

1 illustrates an encoding process according to an example.

2 illustrates an encoding process of a transport block according to an example.

3 illustrates a Recursive Systematic Convolutional (RSC) encoder according to an example.

4 shows an LTE turbo encoder.

5 shows an example of a trellis according to an RSC encoder.

6 shows an example of a trellis structure.

7 is a block diagram of a turbo code encoder according to an embodiment.

8 is a flowchart of an encoding method according to an embodiment.

9 is a configuration diagram of a base station and a terminal according to an embodiment of the present invention.

The following techniques include code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), orthogonal frequency division multiple access (OFDMA), single carrier frequency division multiple access (SC-FDMA), and the like. It can be used in various radio access systems. CDMA may be implemented with a radio technology such as Universal Terrestrial Radio Access (UTRA) or CDMA2000. TDMA may be implemented with wireless technologies such as Global System for Mobile communications (GSM) / General Packet Radio Service (GPRS) / Enhanced Data Rates for GSM Evolution (EDGE). OFDMA may be implemented in a wireless technology such as IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802-20, Evolved UTRA (E-UTRA), or the like. UTRA is part of the Universal Mobile Telecommunications System (UMTS). 3rd Generation Partnership Project (3GPP) long term evolution (LTE) employs OFDMA in downlink and SC-FDMA in uplink as part of Evolved UMTS (E-UMTS) using E-UTRA. LTE-A (Advanced) is an evolution of 3GPP LTE.

For clarity, the following description focuses on 3GPP LTE / LTE-A, but the technical spirit of the present invention is not limited thereto. In addition, specific terms used in the following description are provided to help the understanding of the present invention, and the use of such specific terms may be changed to other forms without departing from the technical spirit of the present invention.

1 illustrates an encoding process according to an example.

The encoding process of FIG. 1 may be applied to many channel codes including a turbo code used in an LTE communication system. Hereinafter, for the convenience of description, the encoding process will be described based on terms according to standard documents of the LTE communication system.

In the example of FIG. 1, the transmitting end may generate a transport block (TB) (S101). In addition, the transmitting end adds a CRC bit for the transport block to the transport block (S102). In addition, the transmitter may generate a code block from the transport block to which the CRC bit is added (S103). For example, the transmitting end may segment the transport block into code blocks based on the input size of the encoder. In addition, the transmitter may add a CRC bit to each divided code block (S104). In this case, for example, the size of the code block and the code block CRC bits may consist of 6144 bits. The transmitter may perform encoding and modulation (S105) on each block composed of a code block and CRC bits. For example, as described above, turbo coding may be applied.

The decoding process may be performed in the reverse order of the encoding process of FIG. 1. For example, the receiver may decode each code block by using a decoder corresponding to each encoder, and finally configure one transport block to check whether the CRC passes through the transport block.

For example, the size of the input symbol may be different from the size of a transport block (TB) from the Media Access Control (MAC) layer. If the size of the transport block is larger than the maximum input symbol size of the turbo code, the transport block may be divided into a plurality of code blocks (CBs). According to the standard of the LTE communication system, the size of the code block may be the same as subtracting the Cyclic Redundancy Check (CRC) bit from 6144 bits. An input symbol of a turbo code may be defined as data comprising a code block and a CRC or data including a transport block (eg, a transport block is less than 6144 bits) and a CRC. The CRC bit is a very small value (e.g. up to 24 bits) compared to 6144 bits. Thus, in the following description, unless otherwise defined, a code block may refer to a code block itself or a CRC bit corresponding to a code block, and a transport block refers to a transport block itself or a CRC bit corresponding to a transport block. can do.

2 illustrates an encoding process of a transport block according to an example.

FIG. 2 illustrates an encoding process of the transport block 201 corresponding to the encoding process described above with reference to FIG. 1. First, a transport block CRC 202 is added to the transport block 201. The transport block CRC 202 may be used for identification of the transport block 201 in the decoding process. The transport block 201 and transport block CRC 202 are then divided into three code blocks 203. In the present exemplary embodiment, the code block 203 is divided into three code blocks, but the transport block 201 may be divided into a plurality of code blocks based on an input size of the encoder 205.

Code block CRC 204 is added to each code block 203. The code block CRC 204 may be used for identification of the code block 203 at the receiving end. Code block 203 and code block CRC 204 may be encoded via encoder 205 and modulator 206.

3 illustrates a Recursive Systematic Convolutional (RSC) encoder according to an example.

The RSC encoder 300 of FIG. 3 may be used for turbo coding. In FIG. 3, m denotes input data, C1 denotes a systematic bit string, and C2 denotes a coded bit string. Here, the RSC encoder 300 has a 1/2 code rate.

RSC encoder 300 may be configured by feeding back the encoded output to the input of a nonrecursive-non-systematic convoluational encoder. In the embodiment of FIG. 3, the encoder 300 includes two delayers 301 and 302. The values D of the delayers 301 and 302 may be determined according to a coding scheme. Delays 301 and 302 may be configured as memory or shift registers.

4 shows an LTE turbo encoder.

The coding scheme of the LTE turbo encoder 400 is a parallel concatenation with two eight-state element encoders 410 and 420 and one turbo code internal interleaver 430. Parallel Concatenated Convolutional Code (PCCC).

In FIG. 4, the turbo encoder 400 is composed of a first constituent encoder 410, a second element encoder 420, and a turbo code internal interleaver 430. The first element encoder 410 and the second element encoder 420 are eight-state element encoders. Each of the first element encoder 410 and the second element encoder 420 has a structure similar to that of the RSC encoder of FIG. 3. The first element encoder 410 and the second element encoder 420 each include three delayers 411, 412, 413, 421, 422, and 423.

In FIG. 4, D is a value determined according to a coding scheme. c _k is the input to the turbo encoder 400. The outputs from the first element encoder 410 and the second element encoder 420 are denoted as z _k and z ' _k , respectively. The value output from the turbo code internal interleaver 430 is denoted by c ' _k . In general, the delays 411, 412, 413, 421, 42, and 423 may delay the input value by one clock. However, the delays 411, 412, 413, 421, 42, 423 may be configured to delay the input value for more than one clock according to the internal setting. The delays 411, 412, 413, 421, 42, and 423 may be configured as shift registers, and may be configured to delay the input bits by a predetermined clock and then output the input bits to the next delays 411, 412, 413, 421, 42, 423. .

The turbo code internal interleaver 430 may reduce the effects of burst errors that may occur when transmitting signals over a wireless channel. For example, the turbo code internal interleaver 430 may be a Quadratic Polynomial Permutation (QPP) interleaver.

Turbo codes are high performance forward error correction (FEC) codes and are used in LTE communication systems. For example, a data block coded by turbo code may consist of three subblocks. One subblock may correspond to m-bit payload data. Another subblock may consist of n / 2 bits of parity bits for the payload, calculated using a recursive systematic convolution (RSC) code. In addition, the remaining sub-blocks may be composed of n / 2 bits of parity bits for permutation of payload data, calculated using an RSC code. For example, the above-described permutation may be performed by an interleaver. Thus, two subblocks of parity bits different from each other with the payload may be configured as one block. For example, if m is equal to n / 2, one block has a code rate of 1/3.

In the first element encoder 410, a process of reaching the input bit z _k by the input c _k may be divided into two paths. The two paths are a first path connected without input feedback from the input to the output and a second path fed back from the input to the input.

In the first path, c _k is input, input via a delay unit 411, a rough input c _k, and the retarder (411, 412, and 413), c _k is applied to the output stage. The relationship between the input end and the output end of the first path may be expressed by a polynomial. The polynomial for the first path is called a forward generator polynomial and may be expressed as g1 of the following equation.

On the other hand, in the second path, the input c _k, the retarder (411 and 412) the coarse input c _k, and the retarder (411, 412, and 413), a rough input c _k is fed back to the input end. The polynomial for the second path is called a recursive generator polynomial and can be expressed as g0 in the following equation.

In Equations 1 and 2, "+" means exclusive OR (XOR), and 1 means that the input goes through 0 delays. In addition, D ⁿ means that the input goes through n delays.

5 shows an example of a trellis according to an RSC encoder.

FIG. 5 shows the configuration of the trellis of the RSC encoder shown in FIG. In FIG. 5, S _i represents a state of the i th input data. In Fig. 5, each circle represents each node. In addition, the line between each node means a branch. The solid line refers to the branch for input value 1, and the dotted line refers to the branch for input value 0. The value on the branch is expressed as m / C1C2 (input value / systematic bit, coded bit). It may also have a state that is exponentially proportional to the number of memories of the encoder. For example, if the encoder includes a memory, 2 ^a states can be included in the trellis.

Trellis is a state machine that shows the possible state transitions of an encoder between two states. A convolutional encoder, such as an RSC encoder, may perform encoding according to a trellis diagram. Codewords encoded by the RSC encoder may be decoded according to an algorithm based on the trellis structure. For example, Viterbi or BCJR (Bahl, Cocke, Jelinek and Raviv) algorithms can be used.

6 shows an example of a trellis structure.

In FIG. 6, n represents the length of a codeword. Typically, trellis can be terminated by adding additional bits after the input sequence. In general, a sequence consisting of a sequence of zeros is called a tail bit. The tail bit terminates the trellis so that nodes in one state of the trellis have a value of zero.

In FIG. 6, the length of a codeword may be determined in consideration of the length k of input data and the length t of tail bits. For example, when the code rate is R, the length n of the codeword may have a value of (k + t) / R. In general, the length t of the tail bits can be determined as the length by which all delays (eg, memories) of the encoder can be reset. For example, the RSC encoder of FIG. 3 may use a total of 2 bits of tail bits. In addition, the turbo encoder of the LTE communication as shown in FIG. 4 may use 3 bits of tail bits.

The tail bit has a relatively short length compared to the length of the input data. As described above, since the length of the codeword is related to the length of the tail bits, code rate loss due to the tail bits may occur when the length of the codeword is limited. However, despite the code rate loss due to tail bits, trellis termination using tail bits is widely used. This is because the computational complexity is low and the error correction performance is excellent.

A puncturing code is a method of puncturing some of codewords. In the puncturing code, some codewords are not transmitted because some of the codewords are punctured. For example, puncturing codes may be used to reduce code rate loss due to the addition of tail bits. In this case, the receiving end may decode by using the trellis corresponding to the sum of the length k of the input data and the length t of the tail bit. That is, the receiver may perform decoding on the assumption that it has received a non-punctured codeword. In this case, the receiving end may assume that there is no input value for the branch from the node corresponding to the punctured bit (ie, the bit not transmitted at the transmitting end). That is, input data is assumed to be 0 or 1 with equal probability for branches of the node.

Unlike LTE turbo codes that use tail bits, double binary turbo codes have a tail biting structure. The tail biting structure is a method of terminating trellis by making the initial state and the end state of the encoder the same. That is, the trellis is terminated by forming a circulation state in which the start state and the end state are the same, and no tail bit is required. However, dual binary LTE turbo code requires pre-encoding to determine the recursive state. Therefore, a decrease in the encoding speed may occur due to the addition of the encoding process. In general, precoding can be performed in two steps. First, encoding is performed by setting the initial state to '0', and thereafter, the starting state and the last state are set to be the same according to a predetermined relationship based on the encoded last state.

Turbo code can provide error correction performance that is close to Shannon's theoretical limit while having a relatively simple structure. However, if the specific SNR is exceeded, further improvement of the decoding performance is insignificant. That is, the turbo code has an error-floor in which further error rate improvement is insignificant when a certain SNR is exceeded.

In order to solve this problem, two methods can be considered. For example, it may be considered to use code that does not generate an error-floor compared to current turbo code. Also, for example, concatenate code may be used by adding overhead to the current turbo code.

Regarding the fifth generation mobile communication technology, reliable communication is being studied. Reliable communication refers to a new communication service realized through Error Free Transmission or Service Availability for realizing a mission critical service (MCS). Reliability communications may be required in communications with Real-Time requirements, such as Machine-to-Machine (M2M) communications. In addition, with respect to medical reasons or emergencies, reliable communication may be required.

In particular, with respect to the fifth generation mobile communication technology, Ultra Reliable and Low-Latency Communication (URLLC) is being discussed. In the URLLC scenario, an error floor is required to occur at a Block Error Rate (BLER) of 10-5 or less. In this case, the error floor refers to a point where the error rate decreases in spite of an increase in information size. In the case of the LTE turbo code, as the information size increases, an error floor occurs in a BLER of 10 ⁻⁴ or less. As described above with respect to FIG. 4, the LTE turbo code consists of three memories (delays). The LTE turbo code is configured to have an error floor at the lowest BLER of polynomials that may consist of three memories. Therefore, the error floor cannot be improved without structural changes of the encoder of the LTE turbo code.

Therefore, hereinafter, a method of improving an error floor through memory expansion of an LTE turbo encoder is proposed.

7 is a block diagram of a turbo code encoder according to an embodiment.

In FIG. 7, the encoder 700 includes a first delayer 711, a second delayer 712, a third delayer 713, and a fourth delayer 714. That is, the encoder 700 may include four memories or shift registers and perform turbo code encoding. The first through eighth nodes 721, 722, 723, 724, 725, 726, 727, and 728 are configured to perform an exclusive-OR (XOR). Inputs and outputs to the nodes 721, 722, 723, 724, 725, 726, 727, and 728 are set in accordance with the direction of the arrow. In addition, the fourth node 724 and the eighth node 728 includes a switch.

As shown in FIG. 7, when changing the switch connection of the fourth node 724 and the eighth node 728, block 750 is completely isolated from the encoder 700. Except for block 750, the encoder 700 is configured to perform the same operations as the encoder of FIG. 3. That is, the encoder 700 of FIG. 7 has a form in which a block 750 including additional memory is added to the RSC encoder used in the LTE turbo encoder. Therefore, for backward compatibility with the conventional LTE turbo encoder, the switch connection of the fourth node 724 and the eighth node 728 may be changed. Operation of the LTE turbo encoder is as described above with reference to FIGS. 4 and 5.

The encoder 700 of FIG. 7 includes a first delayer 711, a second delayer 712, and a third delayer 713 sequentially connected between the first node 721 and the fifth node 725. And a fourth retarder 714.

The first node 721 receives the input signal and the signal from the eighth node 728, and outputs a signal to the second node 722 and the first delayer 711. The second node 722 receives the signals from the first delayer 711 and the first node 721, and outputs a signal to the third node 723. The third node 723 receives the signals from the second node 722 and the third delayer 713 and outputs the signals to the fourth node 724. The fourth node 724 receives a signal from the third node 723, receives a signal from the fifth node 725 through the first switching circuit, and outputs an output signal. The fifth node receives the signals from the third delayer 713 and the fourth delayer 714 and outputs the signals to the fourth node 724 via the first switching cycle. The sixth node 726 receives the signals from the second delayer 712 and the third delayer 713 and outputs the signals to the eighth node 728. In addition, the seventh node receives signals from the second delayer 712 and the fourth delayer 714, and outputs a signal to the eighth node 728 through the second switching circuit. The eighth node 728 receives a signal from the sixth node 726, receives a signal from the seventh node 727 through the second switching circuit, and outputs a signal to the first node 721. .

Each of the nodes 721, 722, 723, 724, 725, 726, 727, and 728 is configured to perform an XOR operation on the input signal and output the same. Also, the first and second switching circuits are configured to selectively disconnect the connection. For example, when the first and second switching circuits are turned off, the fourth node 724 cannot receive the signal from the fifth node 725 and the eighth node 728. Cannot receive a signal from the seventh node 7270.

Hereinafter, when the switch connection is the same as FIG. 7, the operation of the encoder 700 will be described.

Figure 7 recursively (recursive) primitive polynomial (primitive polynomial) g _new0 for the path is equal to the mathematical expression. In FIG. 7, a recursive path is formed by a path of signals applied to the first node 721.

Accordingly, in the forward path from the input terminal to the output terminal of the encoder 700, the output terminal is supplied with an XOR operation value of the input, the input delayed three times, and the input delayed four times.

In addition, the primitive polynomial g _new1 for the forward (forward) path is equal to the mathematical expression. In FIG. 7, the forward path is formed by the path of signals applied to the fourth node 724.

In FIG. 7, in the recursive path from the output end of the encoder 700 to the input end, an XOR operation value of an input, one delayed input, and four delayed inputs is applied to the input terminal. Meanwhile, in FIG. 7, the encoder 700 includes two switching circuits, but two switching circuits may be implemented as one switching circuit.

In Equations 3 and 4, “+” means exclusive OR (XOR), and 1 means that the input goes through 0 delays. In addition, D ⁿ means that the input goes through n delays.

The recursive generator polynomial of the encoder 700 of Equation 3 may be converted into a full rank transfer function. Thus, a tail biting technique may be applied to the encoder 700.

As described above, when the tail biting technique is applied, the initial state and the last state of the trellis need to be set to the same state. The encoder 700 of FIG. 7 includes four memories (delays 711, 712, 713, and 714). Thus, the encoder 700 has 24 states. As described above, in order to apply the tail biting technique, a pre-coding step may be used.

First, the length of the information bit is assumed to be K. First, pre-encoding is performed using a K bit sequence. In this case, according to the value of K mod 15, the state may be set with reference to Tables 1 and 2 below. After the pre-coding is performed, the value of the intersection of the row corresponding to the end state and the column corresponding to the value of K mod 15 indicates the same state as the start and end states. In this case, an initial value for precoding may be set to '0'.

Exit status K mod 15 One 2 3 4 5 6 7 0 0 0 0 0 0 0 0 One 8 4 2 9 12 6 11 2 9 12 6 11 5 10 13 3 One 8 4 2 9 12 6 4 2 9 12 6 11 5 10 5 10 13 14 15 7 3 One 6 11 5 10 13 14 15 7 7 3 One 8 4 2 9 12 8 4 2 9 12 6 11 5 9 12 6 11 5 10 13 14 10 13 14 15 7 3 One 8 11 5 10 13 14 15 7 3 12 6 11 5 10 13 14 15 13 14 15 7 3 One 8 4 14 15 7 3 One 8 4 2 15 7 3 One 8 4 2 9

Exit status K mod 15 8 9 10 11 12 13 14 0 0 0 0 0 0 0 0 One 5 10 13 14 15 7 3 2 14 15 7 3 One 8 4 3 11 5 10 13 14 15 7 4 13 14 15 7 3 One 8 5 8 4 2 9 12 6 11 6 3 One 8 4 2 9 12 7 6 11 5 10 13 14 15 8 10 13 14 15 7 3 One 9 15 7 3 One 8 4 2 10 4 2 9 12 6 11 5 11 One 8 4 2 9 12 6 12 7 3 One 8 4 2 9 13 2 9 12 6 11 5 10 14 9 12 6 11 5 10 13 15 12 6 11 5 10 13 14

For example, if K is 100, K mod 15 is 10. Also, for example, the end state of precoding may be assumed to be 8. In this case, referring to Table 2, a state in which the start state and the end state are the same (that is, the cyclic state) may be determined as the 14th state. In addition, encoding may be performed based on the determined cyclic state. Thus, the coded code has a tail biting structure.

Tables 1 and 2 described above do not include the case where the value of K mod 15 is zero. When K mod 15 is 0, turbo code encoding having a tail biting structure may be performed according to a method described below.

For example, the size of the information bit may be K 'and K' mod 15 may be zero. In this case, encoding may be performed based on information bits having a size of K '+ 1 bits. For example, one bit of a predetermined value may be added to the information bits of the K ′ bit. For example, the preset value may be transmitted by the transmitting end to the receiving end. Pre-coding may be performed on information bits of K ′ + 1 bits. The cyclic state may be determined in Tables 1 and 2 based on the end state of the pre-coding and the value of (K ′ + 1) mod 15.

Since the transmitting end and the receiving end know the value of the added 1 bit, the previous state can be known by using the added bit. For example, the encoder adds one preset bit to the end of the K 'bit. That is, a bit sequence of K '+ 1 bits having a predetermined 1 bit as a Least Significant Bit (LSB) may be used. The encoder performs precoding based on a bit sequence of K '+ 1 bits, and determines the cyclic state in Tables 1 and 2 described above. One bit of the preset value is used for precoding, but may not actually be transmitted to the receiving end.

In the above-described embodiments, a method of generating a code having a tail biting structure without adding tail bitting bits has been described. However, 3 bit tail bitting bits may be used as in the conventional LTE turbo code.

For example, a 3-bit tail biting bit can be used. The tail biting technique can be applied only to the added memory (fourth delay 714). In FIG. 7, the fourth delayer 714 is connected only to the third delayer 713. Therefore, when three tail bitting bits are used, such as LTE turbo coding, it may be assumed that the code input to the fourth delayer 714 has a tail biting structure. In this case, the states of the first delayer 711 and the second delayer 712 may not be considered in determining the tail biting state of the fourth delayer.

In this case, the encoder 700 may be assumed to be an encoder having two memories. In this case, the encoder 700 is considered to have four states. In this case, the recursive state may be determined according to Table 3 based on the value of K mod 3 and the end state of the pre-encoding. Where K represents the size of the information bit.

Exit status K mod 3 One 2 0 0 0 One 2 3 2 3 One 3 One 2

In addition, as described above, the size of the information bit may be K 'and K' mod 3 may be zero. In this case, encoding may be performed based on information bits having a size of K '+ 1 bits. For example, one bit of a predetermined value may be added to the information bits of the K ′ bit. For example, the preset value may be transmitted by the transmitting end to the receiving end. Pre-coding may be performed on information bits of K ′ + 1 bits. The cyclic state may be determined in Tables 1 and 2 based on the end state of the precoding and the value of (K ′ + 1) mod 3.

Since the transmitting end and the receiving end know the value of the added 1 bit, the previous state can be known by using the added bit. In addition, as described above, the added 1 bit is used in precoding, but may not actually be transmitted to the receiving end.

8 is a flowchart of an encoding method according to an embodiment.

In FIG. 8, the encoder may be the encoder 700 of FIG. 7. In the following description, the first switching circuit and the second switching circuit of the encoder 700 of FIG. 7 are all connected (that is, turned on). With both the first switching circuit and the second switching circuit disconnected (ie, turned off), the encoder can operate in the same manner as the LTE turbo encoder described above with respect to FIGS. 4 and 5. have.

First, the encoder pre-encodes an input signal to be transmitted (S801). The encoder determines an end state based on the result of the precoding (S802). In addition, the encoder determines a preset cyclic state based on the length and the end state of the input signal (S803). How to determine the cyclic state can be referred to by the description associated with Tables 1 to 3 described above. The encoder encodes an input signal into a turbo code having a tail biting structure based on the determined cyclic state (S804). In addition, although not shown in FIG. 8, the encoder may transmit an encoded codeword.

FIG. 9 is a diagram for schematically describing a configuration of devices to which the embodiments of the present invention described with reference to FIGS. 1 to 8 may be applied as an embodiment of the present invention.

Referring to FIG. 9, the base station apparatus 10 according to the present invention may include a receiving module 11, a transmitting module 12, a processor 13, a memory 14, and a plurality of antennas 15. . The transmission module 12 may transmit various signals, data, and information to an external device (eg, a terminal). The reception module 11 may receive various signals, data, and information from an external device (eg, a terminal). The receiving module 11 and the transmitting module 12 may be referred to as transceivers. The processor 13 may control the overall operation of the base station apparatus 10. The plurality of antennas 15 may be configured according to, for example, a two-dimensional antenna arrangement.

The processor 13 of the base station apparatus 10 according to an example of the present invention may be configured to receive channel state information according to examples proposed by the present invention. In addition, the processor 13 of the base station apparatus 10 performs a function of processing information received by the base station apparatus 10, information to be transmitted to the outside, and the like. And may be replaced by a component such as a buffer (not shown).

Referring to FIG. 9, the terminal device 20 according to the present invention may include a receiving module 21, a transmitting module 22, a processor 23, a memory 24, and a plurality of antennas 25. The plurality of antennas 25 refers to a terminal device that supports MIMO transmission and reception. The transmission module 22 may transmit various signals, data, and information to an external device (eg, a base station). The reception module 21 may receive various signals, data, and information from an external device (eg, a base station). The receiving module 21 and the transmitting module 22 may be referred to as transceivers. The processor 23 may control operations of the entire terminal device 20.

The processor 23 of the terminal device 20 according to an example of the present invention may be configured to transmit channel state information according to examples proposed by the present invention. In addition, the processor 23 of the terminal device 20 performs a function of processing the information received by the terminal device 20, information to be transmitted to the outside, etc., and the memory 24 stores the calculated information and the like for a predetermined time. And may be replaced by a component such as a buffer (not shown).

Specific configuration of the terminal device 10 as described above, may be implemented so that the above-described matters described in various embodiments of the present invention can be applied independently or two or more embodiments are applied at the same time, overlapping description will be described for clarity Omit.

In addition, in describing various embodiments of the present invention, a downlink transmission entity or an uplink reception entity is mainly described using a base station, and a downlink reception entity or uplink transmission entity is mainly described using a terminal as an example. However, the scope of the present invention is not limited thereto. For example, the description of the base station is a cell, an antenna port, an antenna port group, an RRH, a transmission point, a reception point, an access point, a repeater, or the like as a downlink transmission entity to a terminal or an uplink reception entity from a terminal. The same may apply if In addition, when the repeater becomes a downlink transmission entity to the terminal or an uplink reception entity from the terminal, or when the repeater becomes an uplink transmission entity to the base station or a downlink reception entity from the base station, The principles of the present invention described through various embodiments may be equally applied.

Embodiments of the present invention described above may be implemented through various means. For example, embodiments of the present invention may be implemented by hardware, firmware, software, or a combination thereof.

For implementation in hardware, a method according to embodiments of the present invention may include one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), and Programmable Logic Devices (PLDs). It may be implemented by field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, and the like.

In the case of an implementation by firmware or software, the method according to the embodiments of the present invention may be implemented in the form of a module, a procedure, or a function that performs the functions or operations described above. The software code may be stored in a memory unit and driven by a processor. The memory unit may be located inside or outside the processor, and may exchange data with the processor by various known means.

The embodiments described above are the components and features of the present invention are combined in a predetermined form. Each component or feature is to be considered optional unless stated otherwise. Each component or feature may be embodied in a form that is not combined with other components or features. It is also possible to combine some of the components and / or features to form an embodiment of the invention. The order of the operations described in the embodiments of the present invention may be changed. Some components or features of one embodiment may be included in another embodiment or may be replaced with corresponding components or features of another embodiment. It is obvious that the claims may be combined to form an embodiment by combining claims that do not have an explicit citation relationship in the claims or as new claims by post-application correction.

It is apparent to those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit and essential features of the present invention. Accordingly, the above detailed description should not be construed as limiting in all aspects and should be considered as illustrative. The scope of the invention should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the invention are included in the scope of the invention.

Embodiments of the present invention can be applied to various wireless access systems and broadcast communication systems. Examples of various radio access systems include 3rd Generation Partnership Project (3GPP), 3GPP2 and / or IEEE 802.xx (Institute of Electrical and Electronic Engineers 802) systems. Embodiments of the present invention can be applied not only to the various radio access systems, but also to all technical fields to which the various radio access systems are applied.

Claims (8)

As a turbo code encoding method of an encoder, Precoding the input signal; Determining an end state based on the precoding; Determining a preset cyclic state based on the determined end state and the length of the input signal; And Encoding the input signal into a turbo code having a tail-biting structure based on the determined cyclic state, The encoder comprises a forward path from an input to an output and a recursive path from the output to the input, The output terminal of the forward path is applied with an exclusive OR (XOR) value of the input signal, the input signal delayed once, and the input signal delayed four times. And a value obtained by XORing the input signal, the input signal delayed three times, and the input signal delayed four times is applied to the input terminal of the recursive path. The method of claim 1, The encoder comprises a switching circuit, When the switching circuit is turned off, The output terminal of the forward path is applied with an exclusive OR (XOR) value of the input signal, the input signal delayed once, and the input signal delayed three times. And a value obtained by XORing the input signal, the input signal delayed twice, and the input signal delayed three times is applied to the input terminal of the recursive path. The method of claim 1, The circulation state is determined according to the table below,

Where K is the length of the input signal. The method of claim 1, The circulation state is determined according to the table below,

Where K is the length of the input signal. The method of claim 1, The turbo code encoding method in which one delay indicates a delay of one clock. As a turbo code encoder, A first node, a second node, a third node, a fourth node, a fifth node, a sixth node, a seventh node, each configured to output an exclusive OR of the received signal values; And an eighth node; A first delayer, a second delayer, a third delayer, and a fourth delayer, each of which is configured to delay and output the received signal once, and is sequentially connected between the first node and the fifth node. ; A first switching circuit connected between the fourth node and the fifth node; And A second switching circuit connected between the seventh node and the eighth node, The first node is configured to receive an input signal and a signal from the eighth node, and output a signal to the second node and the first delayer, The second node is configured to receive signals from the first delayer and the first node and output a signal to the third node, The third node is configured to receive signals from the second node and the third delayer and output a signal to the fourth node, The fourth node is configured to receive a signal from the third node, receive a signal from the fifth node through the first switching circuit, and output an output signal, The fifth node is configured to receive signals from the third delayer and the fourth delayer, and output a signal to the fourth node through the first switching cycle, The sixth node is configured to receive signals from the second delayer and the third delayer and output a signal to the eighth node, The seventh node is configured to receive signals from the second delayer and the fourth delayer, and output a signal to the eighth node through the second switching circuit, The eighth node is configured to receive a signal from the sixth node, receive a signal from the seventh node through the second switching circuit, and output a signal to the first node. The method of claim 6, When the first switching circuit and the second switching circuit are turned on, The input signal, the input signal delayed once, and the input signal delayed four times are applied to the fourth node in a forward path from the first node to the fourth node, And the input signal, the input signal delayed three times, and the input signal delayed four times are applied to the first node in a recursive path from the fourth node to the first node. The method of claim 6, When the first switching circuit and the second switching circuit are turned off, The input signal, the input signal delayed once, and the input signal delayed three times are applied to the fourth node in a forward path from the first node to the fourth node, And said input signal, said input signal delayed twice and said input signal delayed three times are applied to said first node in a recursive path from said fourth node to said first node.

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