WO2018038598A1

WO2018038598A1 - Monolithic on-chip fine tune spiral inductor device

Info

Publication number: WO2018038598A1
Application number: PCT/MY2017/050043
Authority: WO
Inventors: Norlaili MOHD. NOH; Asrulnizam ABD MANAF; Farshad ESHGHABADI; Fatemeh BANITORFIAN; Awatif HASHIM; Mohd Tafir MUSTAFFA; Othman SIDEK; Shukri Korakkottil KUNHI MOHD; Yusman MOHD. YUSOF
Original assignee: Universiti Sains Malaysia (USM); SilTerra Malaysia Sdn Bhd
Current assignee: Universiti Sains Malaysia (USM); SilTerra Malaysia Sdn Bhd
Priority date: 2016-08-22
Filing date: 2017-07-27
Publication date: 2018-03-01
Anticipated expiration: 2019-02-22
Also published as: MY176382A

Abstract

A monolithic on-chip fine tune spiral inductor device comprises a semiconductor substrate including a plurality of metal layers; a plurality of peripheral metal grounds being formed in one of the metal layers and disposed at peripheral of the semiconductor substrate and connected to a perfect ground; a patterned metal shield formed in central portion of the semiconductor substrate on the same metal layer forming the peripheral metal grounds, wherein the patterned metal shield comprises a plurality of isolated metal slots, and the plurality of isolated metal slots are isolated from each other and switched individually or in a group; a conductive inductor loop having one or more turns overlying the patterned metal shield and being formed on a metal layer that is different from the one forming the peripheral metal grounds; and a plurality of switches electrically coupling the peripheral metal grounds to the metal slots of the patterned metal shield.

Description

MONOLITHIC ON-CHIP FINE TUNE SPIRAL INDUCTOR DEVICE

Field of the Invention [0001] The present invention relates to the technology fields of semiconductors, and more specifically to a monolithic on-chip fine tune spiral inductor device.

Background of the Invention [0002] Counteractive magnetic field induction is a technique that controls the magnetic flux of passive components such as inductors with partially or fully shielding it. A counteractive magnetic field according to Lenz's Jaw is induced by the eddy currents caused by the magnetic flux of spiral conductor when the magnetic flux enters into metal plate, hi MEMS inductors, this can be obtained by a parallel moving metal plate actuator (Sugawara et al. 2005). This increases the capacitance between the electrodes of inductors and metal shield due to permittivity variation, resulting in inductance variation.

[0003] A feiro fluid actuation was repotted to distribute the permeability over the

MEMS inductor (Assadsangabi et al. 2012). An external bias magnetic field is required to enable repelling of the fluid from the inductor. The inductance tuning range is variable depending on the technique. Using pizomagnetic core is another method in MEMS inductors to alter the inductance (Casha et al. 2008; El Bakkali et al. 2011). The central part of the PZT bridge extends or shortens depending on the sign of DC voltage (typically from 1 to 10 volts) applied to each pair of sided-electrodes. This causes a transfer of uniaxial tensile or compressive planar stress i½uax to the ferromagnetic core, whose permeability

alters as a result of magnetoelastic effect. The permeability and consequently the inductance were controlled through the magnetoelastic field. One of the earlier works was an electrically tunable RF inductor based on a planar solenoid with a thin-film ferromagnetic (FM) core (NiFe) (Vroubel et al. 2004). Variation of inductance was achieved by employing an additional DC current through the same device and thus, altering the effective permeability of the FM core caused as shift in inductance.

[0004] Nonetheless, all these works are not feasible to integrate with complementary metal oxide semiconductor (CMOS) and not suitable for mass production. Summary of the Invention [0005] The present invention provides a monolithic on-chip fine tune spiral inductor device. In one embodiment, the monolithic on-chip fine tune spiral inductor device comprises a semiconductor substrate including a plurality of metal layers; a plurality of peripheral metal grounds being formed in one of the metal layers and disposed at peripheral of the semiconductor substrate and connected to a perfect ground; a patterned metal shield formed in central portion of the semiconductor substrate on the same metal layer forming the peripheral metal grounds, wherein the patterned metal shield comprises a plurality of isolated metal slots, and the plurality of isolated metal slots are isolated from each other and switched individually or in a group; a conductive inductor loop having one or more turns overlying the patterned metal shield and being formed on a metal layer that is different from the one forming the peripheral metal grounds; and a plurality of switches electrically coupling the peripheral metal grounds to the metal slots of the patterned metal shield; thereby when the metal slots of the patterned metal shield when initially floated are switched to the peripheral metal grounds, the induced current from the conductive inductor loop is conducted to the ground

[0006] In another embodiment of the monolithic on-chip fine tune spiral inductor device, the plurality of peripheral metal grounds are AC ground plates.

[0007] In another embodiment of the monolithic on-chip fine tune spiral inductor device of claim 1, wherein the plurality of isolated metal slots are arranged in a ring below the overlying conductive turns of the conductive inductor loop, and all metal slots are orthogonal to the turns of conductive inductor loop.

[0008] In another embodiment of the monolithic on-chip fine tune spiral inductor device of claim 1, wherein the device contains at least 3 layer metals, and one of layer metals which are two or more layer beneath topmost layer metal is used to form the patterned metal shield.

[0009] In another embodiment of the monolithic on-chip fine tune spiral inductor device of claim 1, wherein the conductive inductor loop is separated from the patterned metal shield by at least one layer of dielectric material. [0010] In another embodiment of the monolithic on-chip fine tune spiral inductor device of claim 1, wherein the plurality of switches are low resistance FET switches which are controlled through their gate terminal.

[0011] In another embodiment of the monolithic on-chip fine tune spiral inductor device of claim 1, further comprising a control circuitry for controlling the plurality of switches, wherein the control circuitry comprises a plurality of comparators and a voltage divider dividing a reference voltage equally and feeding the comparators.

[0012] The objectives and advantages of the invention will become apparent from the following detailed description of preferred embodiments thereof in connection with the accompanying drawings.

Brief Description of the Drawings

[0013] Preferred embodiments according to the present invention will now be described with reference to the Figures, in which like reference numerals denote like elements.

[0014] FIG 1 shows a 2D view of an exemplary fine tune spiral inductor device in accordance with one embodiment of the present invention.

[0015] FIG 2 shows a 2D view of an exemplary fine tune spiral inductor device illustrating metal shields with switches (modeled as resistor) to the ground in accordance with one embodiment of the present invention.

[0016] FIG 3 shows a 3D view of an exemplary fine tune spiral inductor device illustrating metal shields with switches (modeled as resistor) to the ground in accordance with one embodiment of the present invention.

[0017] FIG 4 shows a Cadence Virtuoso layout of an exemplary fine tune spiral inductor device illustrating metal shields with switches to the ground in accordance with one embodiment of the present invention.

[0018] FIG 5 shows 2D views of an exemplary fine tune spiral inductor device in accordance with one embodiment of the present invention, where (a) all switches are OFF, (b) four switches make two metal plates grounded, (c) eight switches make four metal plates grounded, and (d) all 32 switches are ON that make all 16 metal plates grounded. [0019] FIG 6 shows an exemplary A-to-D comparator circuitry in accordance with one embodiment of the present invention.

[0020] FIG 7 shows the schematic of a control circuit in accordance with one embodiment of the present invention.

[0021 ] FIG 8 shows (a) the schematic of op-amp, (b) its symbol in half A/D converter circuit, and (c) & (d) the operation of the converter in accordance with one embodiment of the present invention.

[0022] FIG 9 is a graph showing the simulated result for the inductance arid Q-factor of a fine tune spiral inductor device in accordance with one embodiment of the present invention,

[0023] FIG 10 is a graph showing the correlation between the measured inductance and operating frequencies at different control voltages for a fine time spiral inductor device in accordance with one embodiment of the present invention.

[0024] FIG 11 is a graph showing the correlation between the measured quality factor and operating frequencies at different control voltages for a fine tune spiral inductor device in accordance with one embodiment of the present invention.

[0025] FIG 12 is a graph showing the correlations between the measured inductance and control voltages at the operating frequencies of 1.5GHz, 1.7GHz, 1.9GHz and 2.1GHz.

[0026] FIG 13 is a graph showing the correlation between the measured quality factor and controlled voltages at the operating frequencies of 1.5GHz, 1.7GHz and 1.9GHz.

Detailed Description of the Invention

[0027] The present invention may be understood more readily by reference to the following detailed description of certain embodiments of the invention.

[0028] Throughout this application, where publications are referenced, the disclosures of these publications are hereby incorporated by reference, in their entireties, into this application in order to more fully describe the state of ait to which this invention pertains.

[0029] The present invention provides a monolithic on-chip fine tune spiral inductor device that is suitable for mass production and integration with complementary metal oxide semiconductor (CMOS). The monolithic fine tune spiral inductor device can be used in the circuits that are used for microwave applications. In principle, the fining tuning of the inductance of the monolithic on-chip fine tune spiral inductor device of the present invention is realized by switching the metal plates of a patterned shield between a "float" state (not shorted to the ground) and a "shorted" state (one or more metal shields shorted to the ground).

[0030] For the sake of brevity, conventional techniques related to semiconductor device fabrication may not be described in detail herein. In particular, various steps in the manufacture of semiconductor based circuitry and integrated inductors are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details.

[0031] Referring now to FIGS 1-4, there is provided an exemplary monolithic on- chip fine tune spiral inductor device in accordance with one embodiment of the present invention. FIG 1 shows a 2D view of an exemplary fine tune spiral inductor in accordance with one embodiment of the present invention. FIG 2 shows a 2D view of an exemplary fine tune spiral inductor illustrating metal shields with switches (modeled as resistor) to the ground in accordance with one embodiment of the present invention. FIG 3 shows a 3D view of an exemplary fine tune spiral inductor illustrating metal shields with switches (modeled as resistor) to the ground in accordance with one embodiment of the present invention. FIG 4 shows a Cadence Virtuoso layout of an exemplary fine tune spiral inductor illustrating metal shields with switches to the ground in accordance with one embodiment of the present invention. As described in detail hereinbelow, the semiconductor substrate 101 includes the dielectric and metal layers. The peripheral metal grounds 102 are used to make the metal shields 103 under the main inductor 104 grounded from floating state using the applied switches 105. The monolithic on-chip fine tune spiral inductor device 100 is illustrated in a simplified manner, and its implementation will usually include additional elements, circuit components, conductive interconnects, conductive plugs, and other conventional features.

[0032] The monolithic on-chip fine tune spiral inductor device 100 comprises a semiconductor substrate 101, a plurality of peripheral metal grounds 102, a patterned metal shield 103, a conductive inductor loop 104, and a plurality of switches 105.

[0033] The semiconductor substrate 101 includes a plurality of metal layers that are separated by dielectric layers. [0034] The plurality of peripheral metal grounds 102 are disposed at the peripheral of the semiconductor substrate 101 in correspondence with the patterned metal shield 103. The peripheral metal grounds 102 are AC ground plates connected to a perfect ground. The peripheral metal grounds 102 are made of other metal layer than the inductor layer. The patterned metal shield 103 is initially floated and then switched to the peripheral metal grounds 102 to conduct the induced current from the conductive inductor loop 104 to the ground. This provides a control on the induced current from the conductive inductor loop 104.

[0035] The patterned metal shield 103 comprises a plurality of isolated metal slots that can be switched individually or in a group. The patterned metal shield 103 is formed in the central portion of the semiconductor substrate. The patterned metal shield 103 is made of other metal layers than the inductor layer, and is identical to the metal layer of the metal grounds. As illustrated, the plurality of isolated metal slots are arranged in a ring below the overlying conductive turns of the conductive inductor loop 104, and all metal slots are orthogonal to the turns of conductive inductor loop 104. All metal slots are isolated from each other. The number of metal slots can vary depending upon the applications. It is to be noted that the present invention can be applied in a semiconductor with at least 3 metal layers (as shown in FIG 3, the semiconductor contains 6 layer metals). The topmost metal layer is selected to achieve the highest quality factor in the process while one layer beneath is reserved for the inductor' s bridges. One of metal layers which are two or more layers beneath the topmost metal can be used for implementation of the metal shield.

[0036] The conductive inductor loop 104 has one or more turns overlying the patterned metal shield 103, where the conductive inductor loop 104 is separated from the metal shield 103 by at least one layer of dielectric material (not shown). The conductive inductor loop 104 has an input end 104(a) and output end 104(b), and is formed from a suitable material, typically a metal. In accordance with known semiconductor device fabrication processes, the material used for the conductive inductor loop 104 can, for example, be deposited and etched or polished into the desired pattern. In practice, the turns of the conductive inductor loop 104 can be formed using one or more interconnect planes. It should be appreciated that air bridges or similar routing techniques and interconnect technologies may be utilized to fabricate an integrated inductor coil with multiple turns. [0037] The conductive inductor loop 104 may be formed on or overlying a layer of dielectric material (not shown). In practice, the layer of dielectric material can be formed from one or more material commonly used as insulators in the semiconductor industry. In certain embodiments, the dielectric materials include silicon oxides, silicon nitrides, and low-permittivity organic or non-organic glasses. The layer of the dielectric material electrically insulates the conductive inductor loop 104 from the underlying metal plates 103.

[0038] The plurality of switches 105 are electrically coupled between the metal grounds 102 and the metal slots of the patterned metal shield 103, where the coupling is controlled electronically by a control circuitry as described hereinbelow. The switches (here, CMOS switches) are low resistance FET switches which are controlled through their gate terminal. To keep the switch open, 0 volt is applied so that the metal shield is kept floated and isolated from the peripheral metal grounds. To make the switches as thru, a maximum allowable voltage (here, 1.2 volts) is applied to the gate terminal so that the metal shield is connected to the peripheral metal grounds. The switches are controlled individually by an electronic or digital interface (FIG 6 to 8).

[0039] The magnetic field of the monolithic on-chip fine tune spiral inductor device can be changed by shorting the metal shield to the ground. This technique is for the first time for being used in a monolithic on-chip fine tune spiral inductor device. The suitable application is for circuits above 1 GHz of operation, i.e. all microwave applications where the self-inductance or mutual inductance variation is required, such as fine tuning of microwave oscillators.

[0040] When all metal slots of the patterned metal shield are float (not shorted to the ground), the inductor shows its minimum inductance. When all metal slots are shorted to the ground, the inductor shows its maximum inductance. The metal slots of the patterned metal shield can be shorted one by one, which provides a fine tuning range,

[0041] FIG 5 shows 2D views of an exemplary fine tune spiral inductor device in accordance with one embodiment of the present invention, where (a) all switches are OFF, (b) four switches make two metal slots grounded, (c) eight switches make four metal slots grounded, and (d) all 32 switches are ON that make all 16 metal slots grounded.

[0042] The 2D view of an exemplary fine tune spiral inductor is shown in FIG 5(a).

There are 32 switches, where each 2 of them are connected together through one of 16 metal slots of the patterned metal shield. When state 1 is selected, four switches are shorted so that two metal slots are grounded, as illustrated in FIG 5(b). When state 2 is selected, another four switches makes two more metal slots grounded, as illustrated in FIG 5(c). When state 8 is selected, all 32 switches are in ON state and all 16 metal slots of shield are grounded, as illustrated in FIG 5(d). This provides 9 states including OFF-state switches, state 1 , state 2, ... and state 8.

[0043] FIG 6 shows an exemplary A-to-D comparator circuitry in accordance with one embodiment of the present invention. The converter is combined from several comparators (here, 8 comparators) to provide the required states (here, 9 states). A voltage divider is used to divide the reference voltage Vref equally and feeds the comparators. The input analog control voltage (here, Vin) is compared with the fed reference voltages in the comparators. The comparators' output will be VDD if Vin is larger that the fed reference voltage in the comparator, otherwise the output will be zero volt. An analog-to-digital converter based on a comparison circuitry, as shown in FIG 6, is implemented so that by only one pad, the tuning range can be controlled. The control voltage, Vin, is 0 to VDD, The A-to-D converter can be neglected if a digital processor to control the switches is available. The output of the converter is fed to the corresponding switches.

[0044] As shown in FIG 6, the comparator circuit 106 comprises a voltage divider

107 for setting the reference voltage of each comparator, where the global reference voltage

108 is for voltage divider, and the comparator circuit 106 receives analog control voltage 109 as input and produce digital control voltage 110 as output.

[0045] FIG 7 shows the schematic of a control circuit in accordance with one embodiment of the present invention. FIG 7 is the schematic of the block diagram in FIG 6 in Cadence Spectre. The output of each comparator in the A-to-D converter is fed to 4 switches simultaneously. Each two switches are used to connect one floating metal slot in the metal shield 103 to the peripheral metal grounds 102. In this case, two metal slots are grounded using 4 switches as shown in FIG 5(a). 32 switches are used to short 16 metals slots to ground. To achieve finer tuning steps, the number of metal slots and switches can be increased. In FIG 7, the schematic includes a half analog-to-digital converter which converts a DC voltage of 0 to 1.2 V into a digital stream of 00000000 to 11 111111. The MSB is generated by the top most op-amp for the circuits in FIGS 6 and 7. The table of this conversion is given in Table 1.

[0046] Table 1. Different states in terms of control voltage State VCTRL (mV) (is the Vin in FIG 6 and Half A/D output

ΓΝ_Ρ in FIG 8)

0 0 - 93.75 00000000

1 93.75 - 187.5 00000001

2 187.5 - 281.25 00000011

3 281.25 - 375 0000011 1

4 375 - 468.75 00001111

5 468.75 - 562.5 0001 1111

6 562.5 - 656.25 0011111 1

7 656.25 - 750 011111 11

8 750 - 1.2V 1 111 1111

[0047] FIG 8 shows (a) the schematic of op-amp, (b) its symbol in half A/D converter circuit, (c) and (d) operation of the half A/D converter in accordance with one embodiment of the present invention. The op-amps in half A/D converter are simple single- stage amplifier with current tail which is followed by a common source stage to improve the linearity and output voltage swing properties. The comparator is formed by a differential common source amplifier with a current source tail and active load in the first stage, followed by a differential common source amplifier as the second stage with active load to enhance the linearity. The second stage increases the voltage swing significantly so that near to zero and VDD outputs can be obtained.

[0048] FIG 9 is a graph showing the simulated result of a fine tune spiral inductor in accordance with one embodiment of the present invention. This structure is simulated in Sonnet EM simulator for state 0 and state 8. The CMOS switches are modeled as resistors in Sonnet which are 1ΜΩ when OFF-state and 10 Ω when ON-state. The Sonnet model of the proposed inductor is given in FIGS 2 and 3. The simulation result is given in FIG 9. The inductance is varied from 8.85 nH to 9.44 nH at 1.6 GHz. This shows a 6.2% tuning range. The quality factor drops from 10.4 to 9.88.

[0049] FIG 10 is a graph showing the correlation between the measured inductance and operating frequencies at different control voltages for a fine tune spiral inductor in accordance with one embodiment of the present invention. The measured results of fabricated device showed correlations with the simulated ones and proves the concept of the proposed technique. The measured inductance, shown in FIG 10, shows the inductance variation for different control voltages. The inductance increases as the control voltages increase and more metal shields are grounded.

[0050] FIG 1 1 is a graph showing the correlation between the measured quality factor and operating frequencies at different control voltages for a fine tune spiral inductor in accordance with one embodiment of the present invention. As can be seen in FIG 11 , by increasing the control voltage and hence, increasing inductance, the quality factors decreases slightly which shows that the inductor performance is slightly changed,

[0051] FIG 12 is a graph showing the correlations between the measured inductance and control voltages at the operating frequencies of 1.5GHz, 1.7GHz, 1.9GHz and 2.1GHz. The tuning ratio is 6.6% at 2.1 GHz and 4% at 1.9 GHz. These results show that this technique shows large variation in electromagnetic field, and for this case study, the inductance, for higher frequencies.

[0052] FIG 13 is a graph showing the correlation between the measured quality factor and controlled voltages at the operating frequencies of 1.5GHz, 1.7GHz and 1.9GHz. As shown in FIG 13, the quality factor drop is negligible.

[0053] The present invention is able to adjust the monolithic passive components after fabrication with controlling their magnetic flux. The inventive principles can apply to any passive components specially inductors in semiconductor processes with no specific consideration. The main structure of the passive component stays untouched while a fine tuning capability is obtained.

[0054] The number of tuning steps can be increased depending on the application.

This does not affect the main performance of the structure but increase the tuning steps for more accurate adjustment.

[0055] The initial performance of the passive component is not affected when the tuning feature is added.

[0056] The tuning function can be controlled by digital or analog signals.

[0057] The tuning structure does not occupy significant additional area than the area required for the passive component.

[0058] The tuning structure can be used to compensate for any frequency shift that occurs after fabrication and to fine tune the RF circuits.

[0059] The tuning structure can also be applied to the transmission line and all RF components interacting with substrate and/or dielectrics. [0060] While the present invention has been described with reference to particular embodiments, it will be understood that the embodiments are illustrative and that the invention scope is not so limited. Alternative embodiments of the present invention will become appai'ent to those having ordinary skill in the art to which the present invention pertains. Such alternate embodiments are considered to be encompassed within the scope of the present invention. Accordingly, the scope of the present invention is defined by the appended claims and is supported by the foregoing description.

References:

Assadsangabi, B., M. S. M. Ali and K. Takahata (2012). Ferrofluid-based variable inductor. Micro Electro Mechanical Systems (MEMS), 2012 IEEE 25th International Conference on.

Casha, O., I. Grech, J. Micallef, E. Gatt, D. Morche, B. Viala, J. P. Michel, P. Vincent and E. de Foucauld (2008). Utilization of MEMS tunable inductors in the design of RF voltage- controlled oscillators, IEEE,

El Bakkali, M., F. Chan Wai Po, E. De Foucauld, B. Viala and J. P. Michel (2011).

"Design of a RF matching network based on a new tunable inductor concept."

Microelectronics journal 42(1): 233-238.

Sugawara, H„ Y. Yoshihara, K. Okada and K. Masu (2005). Reconfigurable CMOS LNA for software defined radio using vari ble inductor. Wireless Technology, 2005. The European Conference on.

Vroubel, M., Y, Zhuang, B. Rejaei and J. N. Burghartz (2004). "Integrated tunable magnetic RF inductor." Electron Device Letters. IEEE 25(12): 787-789.

Claims

What is claimed is: 1. A monolithic on-chip fine tune spiral inductor device, comprising:

a semiconductor substrate including a plurality of metal layers;

a plurality of peripheral metal grounds being formed in one of the metal layers and disposed at peripheral of the semiconductor substrate and connected to a perfect ground; a patterned metal shield formed in central portion of the semiconductor substrate on the same metal layer forming the peripheral metal grounds, wherein the patterned metal shield comprises a plurality of isolated metal slots, and the plurality of isolated metal slots are isolated from each other and switched individually or in a group;

a conductive inductor loop having one or more turns overlying the patterned metal shield and being formed on a metal layer that is different from the one forming the peripheral metal grounds; and

a plurality of switches electrically coupling the peripheral metal grounds to the metal slots of the patterned metal shield;

thereby when the metal slots of the patterned metal shield when initially floated are switched to the peripheral metal grounds, the induced current from the conductive inductor loop is conducted to the ground.

2. The monolithic on-chip fine tune spiral inductor device of claim 1, wherein the plurality of peripheral metal grounds are AC ground plates.

3. The monolithic on-chip fine tune spiral inductor device of claim 1, wherein the plurality of isolated metal slots are arranged in a ring below the overlying conductive turns of the conductive inductor loop, and all metal slots are orthogonal to the turns of conductive inductor loop.

4. The monolithic on-chip fine tune spiral inductor device of claim 1, wherein the device contains at least 3 layer metals, and one of layer metals which are two or more layer beneath topmost layer metal is used to form the patterned metal shield.

5. The monolithic on-chip fine tune spiral inductor device of claim 1, wherein the conductive inductor loop is separated from the patterned metal shield by at least one layer of dielectric material.

6. The monolithic on-chip fine tune spiral inductor device of claim 1, wherein the plurality of switches are low resistance FET switches which are controlled through their gate terminal.

7. The monolithic on-chip fine tune spiral inductor device of claim 1, further comprising a control circuitry for controlling the plurality of switches, wherein the control circuitry comprises a plurality of comparators and a voltage divider dividing a reference voltage equally and feeding the comparators.