WO2018032601A1 - Method for preparing enhanced gan-based hemt device - Google Patents

Abstract

Disclosed is a method for preparing an enhanced GaN-based HEMT, comprising: etching selected regions of an epitaxial structure of an HEMT by using an oxygen-containing etching gas, etc. to react a selected material (for example, an aluminium-containing substance) in the selected regions with the oxygen-containing substance until a corrosion-resistant substance capable of covering an etching surface is formed, thereby preventing an etching reagent from etching the epitaxial structure and achieving the automatic termination of etching and also obtaining a required HEMT device structure. By means of the present application, the precise control of an etching operation during the preparation of an HEMT device can be achieved, the electrical properties of the device can be ensured, the difficulty of preparing an enhanced HEMT by using technologies such as p-type gate technology and trench gate technology can be greatly reduced, and the repeatability, uniformity and stability of the device process can be ensured. At the same time, during the etching process, a passivation layer can also be naturally formed in situ on the etching surface, so that problems such as surface damage caused by a subsequent passivation layer deposition process can be effectively eliminated, and in turn problems such as the deterioration of the electrical properties of the materials and the device can be eliminated.

Description

Method for preparing GaN-based enhanced HEMT device Technical field

The present application relates to a method for fabricating a High Electron Mobility Transistor (HEMT), and more particularly to a method for preparing an enhanced GaN-based HEMT device.

Background technique

Compared to conventional silicon-based MOSFETs, AGaN/GaN heterojunction-based High Electron Mobility Transistors (HEMTs) have the unique advantages of low on-resistance, high breakdown voltage, and high switching frequency. As a core device in various types of power conversion systems, it has important application prospects in terms of energy saving and consumption reduction, and therefore has received great attention from academic and industrial circles. However, due to the polarization effect of the III-nitride material system, in general, the AlGaN/GaN heterojunction-based HEMTs are depleted (normally open), and this type of device is required for use in circuit-level systems. The negative polarity gate drive circuit is designed to achieve switching control of the device, which greatly increases the complexity and cost of the circuit. In addition, depletion devices have drawbacks in terms of fail-safe capabilities and cannot be truly commercialized. Therefore, implementing an enhanced (normally open) HEMT has become an urgent problem to be solved. It is one of the feasible solutions to prepare the enhanced HEMT based on the p-type gate technology. On the basis of the conventional HEMT epitaxial structure, the p-type layer is epitaxially grown on the AlGaN barrier layer (unintentionally doped n-type), so that the entire epitaxial wafer range A pn junction is formed therein, and a space charge region (mainly distributed in the barrier layer and the channel layer) effectively depletes the two-dimensional electron gas at the channel. Since the enhanced HEMT only requires the electrons under the gate to be depleted, in the subsequent chip process, the non-gate region on the epitaxial wafer needs to be etched to restore the depleted two-dimensional electron gas, as shown in FIG. Show. In addition, the preparation of the enhanced HEMT based on the trench gate technology is another relatively simple solution. On the basis of the conventional HEMT epitaxial structure, a part of the AlGaN barrier layer under the gate is etched away in the device process, and the barrier layer is formed. When thinned to a certain extent, the two-dimensional electron gas in the gate region is depleted; and the two-dimensional electron gas concentration in the region between the gate source and the gate drain is maintained at the original level, as shown in FIG.

The aforementioned p-type gate technology and trench gate technology all require selective etching, and in the etching process, the former needs to etch a large area of the non-gate, and the latter needs to etch the gate area. Conventional methods generally use high aluminum component etch stop layers (such as AlN) and GaN slow etch and control the etch depth by etch time, but still can not accurately control the etch depth, resulting in over-etching ) or under-etching occurs, which ultimately leads to poor electrical performance of the device. At the same time, a large number of surface defect states generated during the etching process will seriously affect the on-resistance, dynamic characteristics and threshold voltage stability of the device during operation. In addition, the slow etching process requires a long etching time, so the mask material requirements are also high.

Summary of the invention

The main object of the present application is to provide a method for preparing a GaN-based enhanced HEMT device to overcome the deficiencies in the prior art.

To achieve the foregoing object, the technical solution adopted by the present application includes:

Embodiments of the present application provide a method for fabricating a GaN-based enhanced HEMT, including: etching a selected region in an epitaxial structure of the HEMT with an etch reagent containing a selected substance, and etching the selected region The selected material in the predetermined region reacts with the selected material until an etching resistant material sufficient to cover the etched surface is formed, thereby preventing etching of the epitaxial structure by the etching reagent, thereby realizing etching automatically Terminate and obtain the desired HEMT device structure.

Further, the preparation method includes: performing a sufficient amount of the etching resistant material on the etched surface during etching the selected region with an etch reagent containing the selected substance Aggregation forms an in-situ passivation layer to achieve automatic termination of the etch.

Further, the preparation method includes: adjusting an etching parameter in real time according to at least an amount of a selected substance in the selected region and/or a required etching depth, the etching parameter including the etching At least one of the amount of the reagent, the content of the selected substance in the etching reagent, and the etching power to obtain the desired HEMT device structure while automatically completing the etching.

Preferably, the etching reagent is an etching gas.

Preferably, the selected substance is selected from the group consisting of oxygen-containing substances, further preferably an oxygen-containing gas, still more preferably oxygen or ozone or other oxygen-containing gas such as carbon dioxide or nitrogen oxide, and particularly preferably oxygen.

Preferably, the selected material is selected from the group consisting of Al-containing semiconductor materials.

In some embodiments, the epitaxial structure includes a heterostructure formed mainly by a first semiconductor and a second semiconductor, the second semiconductor being formed on the first semiconductor, at least when the etching is automatically terminated A groove structure corresponding to the gate electrode is formed in the second semiconductor, and a groove bottom surface of the groove structure is distributed at a set depth in the second semiconductor or between the second semiconductor and the first semiconductor. Preferably, the inner wall of the groove structure is covered with an in-situ passivation layer formed by the accumulation of the sufficient amount of etching resistant material on the etched surface.

In some embodiments, the epitaxial structure includes a first semiconductor, a second semiconductor formed on the first semiconductor, and a third semiconductor formed on the second semiconductor, wherein the first semiconductor and the second semiconductor cooperate to form a heterostructure The third semiconductor has a conductivity different from that of the second semiconductor. When the etching is automatically terminated, the third semiconductor is removed by etching except for a region corresponding to a region under the gate. Preferably, the second semiconductor is covered with an in-situ passivation layer formed by the sufficient amount of the etching resistant material to be aggregated on the etched surface.

Compared with the prior art, the GaN-based enhanced HEMT device provided by the present application is simple and easy to operate, can realize precise control of the etching process, effectively protects the electrical characteristics of the HEMT device, and has repeatability, uniformity and stability of the process. Reliable, low cost, and conducive to large-scale implementation.

DRAWINGS

FIG. 1 is a schematic diagram of a prior art fabrication of a p-type gate enhanced HEMT based on a selective etch technique.

2 is a schematic diagram of an enhanced HEMT based on trench gate technology in the prior art.

3 is an epitaxial structural diagram of an enhanced HEMT based on a p-GaN/AlGaN/GaN heterojunction in Embodiment 1 of the present application.

4 is a schematic view showing the structure of the device shown in FIG. 3 after completion of p-GaN gate etching.

FIG. 5 is a schematic structural view of the device shown in FIG. 4 after isolation of the active region is completed.

Figure 6 is a schematic view showing the structure of the device of Figure 5 after completion of gate metal deposition.

Figure 7 is a schematic view showing the structure of the device of Figure 6 after completion of deposition of a passivation layer.

FIG. 8 is a schematic structural view of the device shown in FIG. 7 after completion of passivation etching.

FIG. 9 is a schematic structural view of the device of FIG. 8 after completion of source-drain ohmic contact and source field plate preparation.

Figure 10 is a schematic view showing the structure of the device shown in Figure 9 after the fabrication of the lead electrodes.

11 is an epitaxial structural diagram of an enhanced HEMT based on a composite p-type layer in Embodiment 3 of the present application.

FIG. 12 is a structural diagram of an enhanced HEMT based on a composite p-type layer after completing a chip process in Embodiment 3 of the present application.

13 is a diagram showing an epitaxial structure of an HEMT based on an AlGaN/GaN heterojunction in Embodiment 4 of the present application.

Figure 14 is a structural view of the device of Figure 13 after completion of preparation of source and drain ohmic contacts.

Figure 15 is a structural diagram of the device of Figure 14 after isolation of the active region is completed.

Figure 16 is a structural view of the device of Figure 15 after completion of deposition of the passivation layer.

Figure 17 is a block diagram of the device of Figure 16 after completion of gate fenestration.

Figure 18 is a structural view of the device of Figure 17 after etching the trench gate.

Figure 19 is a structural view of the device of Figure 18 after completion of deposition of the gate dielectric layer.

Figure 20 is a structural view of the device of Figure 19 after completion of gate metal deposition.

Figure 21 is a structural view of the device of Figure 20 after completion of source and drain ohmic contact opening.

Figure 22 is a structural view of the device of Figure 21 after completion of fabrication of the lead electrode.

Figure 23 is a structural view of the device of Figure 13 after completion of gate recess etching.

Figure 24 is a structural view of the device of Figure 23 after completion of p-GaN regrowth.

Figure 25 is a structural diagram of the device of Figure 24 after completion of p-GaN etching in a non-gate region.

Figure 26 is a block diagram of the device of Figure 25 after completion of the entire chip fabrication process.

detailed description

As described above, in the prior art, the etching depth of the high aluminum component (such as AlN, etc.) and the slow etching of GaN and the etching depth controlled by the etching time cannot accurately control the etching depth, which is extremely easy to cause. Over-etching or under-etching (Under-etching) occurs, which eventually leads to poor electrical performance of the device. At the same time, a large number of surface defect states generated during the etching process will seriously affect the on-resistance, dynamic characteristics and threshold voltage stability of the device during operation. In addition, the slow etching process requires a long etching time, so the mask material requirements are also high.

In view of the foregoing deficiencies of the prior art, the inventors of the present invention have proposed the technical solutions of the present application through long-term research and extensive practice, which will be explained as follows.

A method for preparing a GaN-based enhanced HEMT provided by the embodiment of the present application includes: etching a selected region in an epitaxial structure of the HEMT with an etch reagent containing a selected substance, and etching the selected region The selected material reacts with the selected material until an etch-resistant material sufficient to cover the etched surface is formed, thereby preventing etching of the epitaxial structure by the etch reagent, thereby achieving automatic termination of the etch, At the same time, the desired HEMT device structure is obtained.

In some preferred embodiments, the method of preparing includes: ???said sufficient amount of etching resistant material during etching of the selected region with an etch reagent containing the selected material An in-situ passivation layer is formed on the etched surface to achieve automatic termination of the etch.

Further, the preparation method includes: adjusting an etching parameter in real time according to at least an amount of a selected substance in the selected region and/or a required etching depth, the etching parameter including at least the engraving At least one of an amount of the etching agent, a content of the selected substance in the etching reagent, and an etching power to obtain a desired HEMT device structure while achieving automatic termination of etching.

More preferably, the etching reagent is an etching gas.

More preferably, the selected substance may be selected from oxygen-containing gases such as oxygen O ₂ , ozone O ₃ , carbon dioxide CO ₂ , nitrogen oxide (NO _x ), etc., preferably oxygen.

More preferably, the etching gas contains any one or a mixture of two or more of chlorine gas, nitrogen gas, argon gas, and boron trichloride, and a mixed gas of oxygen. For example, the etching gas may be selected from the group consisting of chlorine gas, a mixed gas of oxygen and nitrogen, chlorine gas, a mixed gas of oxygen and argon, chlorine gas, boron trichloride, a mixed gas of oxygen and nitrogen, or chlorine gas, trichlorination. A mixed gas of boron, oxygen and argon, and is not limited thereto.

More preferably, the selected material is selected from the group consisting of Al-containing semiconductor materials. For example, the selected material may be at least selected from AlGaN, AlN, AlInGaN, or AlInN, and is not limited thereto.

In some preferred embodiments, the etching reaction gas containing oxygen is used to chemically react with the materials such as AlGaN, AlN, AlInGaN, and AlInN in the epitaxial structure of the HEMT to form a strong bond energy and resist etching. (Al, Ga)-O compound or the like (i.e., the aforementioned etching resistant material, preferably alumina, etc.), thereby effectively and reliably achieving the etching termination and precisely controlling the etching depth. Among them, the selective etching of the epitaxial layers of different aluminum components can be realized by controlling the flow rate of the etching mixed gas, the oxygen content, etc., and the selective etching is automatically terminated.

In some embodiments, the preparation method may further include: removing the etching resistant material covering the etched surface, or setting the etched material on the etched surface to be blunt Layer. More specifically, in this application, After removing the etching resistant material, the passivation layer is coated on the etching surface, or a passivation layer may be further disposed on the etching resistant material covering the etching surface, that is, At least one passivation layer is further coated on the in-situ passivation layer to better ensure device performance.

Further, the technical solution of the present application is not only suitable for an epitaxial structure not containing a high aluminum component etch stop layer, but also fully applicable to an epitaxial structure containing an etch stop layer such as AlN, and the etching termination effect is better. The etch stop layer may be distributed at any suitable position in the HEMT epitaxial structure, such as between the barrier layer and the channel layer, between the p-type layer and the barrier layer, and is not limited thereto.

In some more specific embodiments, the epitaxial structure includes a heterostructure formed mainly by a first semiconductor and a second semiconductor, and the second semiconductor is formed on the first semiconductor, and at least when the etching is automatically terminated, at least Forming a groove structure corresponding to the gate electrode in the second semiconductor, the groove bottom surface of the groove structure is distributed at a set depth in the second semiconductor or the second semiconductor and the first semiconductor between.

Preferably, the inner wall of the groove structure is covered with an in-situ passivation layer formed by the formation of the sufficient amount of etching resistant material on the etched surface.

Further, a third semiconductor is further formed on the second semiconductor, and the third semiconductor has the same conductivity as the second semiconductor, and when the etching is automatically terminated, a corresponding correspondence is formed in the third semiconductor and the second semiconductor. The groove structure of the gate.

In the present application, the aforementioned conductivity means that the semiconductor is n-type or p-type, and should not be understood as other meanings.

Further, an insertion layer may be disposed between the first semiconductor and the second semiconductor, the insertion layer may or may not include the selected material, and a groove bottom surface of the groove structure is distributed to the second semiconductor At the interface with the insertion layer or at a set depth within the insertion layer.

Preferably, the material of the insertion layer comprises AlN.

In some more specific embodiments, the epitaxial structure includes a first semiconductor, a second semiconductor formed on the first semiconductor, and a third semiconductor formed on the second semiconductor, wherein the first semiconductor and the second semiconductor are formed a heterostructure, the third semiconductor having a conductivity different from that of the second semiconductor, the third semiconductor excluding an area other than a region under the gate (ie, the gate region) when the etching is automatically terminated ( That is, the non-gate regions are all removed by etching.

Preferably, the second semiconductor is covered with an in-situ passivation layer formed by the sufficient amount of the etching resistant material to be aggregated on the etched surface.

In some embodiments, the preparation method may further include: first performing an gate region of the second semiconductor (barrier layer) with an etching reagent (eg, an etching gas containing no oxygen) containing no selected substance. Etching, then regrowth the third semiconductor (p-type layer), and then etching the non-gate region of the third semiconductor with an etching reagent containing a selected substance (eg, an oxygen-containing etching gas) Unless the third semiconductor of the gate region. With such an implementation, the threshold voltage and current output characteristics of the enhanced HEMT device can be further improved.

Wherein the first semiconductor and the second semiconductor have the same conductivity. For example, the first semiconductor and the second semiconductor may have the same conductivity, for example, all of which are unintentionally doped n-type.

Wherein, the third semiconductor is p-type or n-type. For example, if the HEMT is a trench gate based HEMT, the third semiconductor may be unintentionally doped n-type; if the HEMT is a p-type gate technology HEMT, the third semiconductor may be p-type.

Further, the third semiconductor includes a first material layer and a second material layer formed on the first material layer, the second material layer does not contain the selected material, and the first material layer contains Selecting a material, in the process of etching the third semiconductor by an etch reagent, sequentially adjusting the content of the selected substance in the etch reagent to sequentially realize the second material layer and the first material layer Etching until the in-situ passivation layer is formed to automatically terminate the etch. For example, if it is necessary to etch the second material layer p-GaN/first material layer p-AlGaN, two etching reagents having different oxygen contents or only one etching reagent (in which the oxygen content is adjustable) may be used. Preferably, the latter is capable of simultaneously etching the second material layer p-GaN/first material layer p-AlGaN by adjusting the oxygen content to a suitable range, but etching the second semiconductor (the first material layer is formed) On the second semiconductor).

Further, the third semiconductor includes a first material layer formed on the second semiconductor and a second material layer formed on the first material layer, the first material layer not including the selected a material, wherein the second material layer contains the selected material, and in the process of etching the third semiconductor by an etching reagent, the content of the selected substance in the etching reagent is adjusted, and the first Etching of the two material layers and the first material layer until reaching the interface of the first material layer and the second semiconductor or at a set depth within the second semiconductor, at the second semiconductor surface or the second semiconductor An in-situ passivation layer is formed therein to allow the etching to be automatically terminated.

For example, during etching, the second material layer is first etched with a first etch reagent, and then the first material layer is etched with a second etch reagent until reaching the first material layer and the second material layer. Forming an in-situ passivation layer in the second semiconductor surface or the second semiconductor to automatically terminate the etching at the interface of the semiconductor or at a set depth in the second semiconductor, the first etching reagent The selected material is not contained, and the second etching reagent contains the selected substance, or the content of the selected substance in the first etching reagent is lower than the content of the selected substance in the second etching reagent . Of course, it is also possible to use an etching reagent having an adjustable oxygen content, and by adjusting the oxygen content therein, the same effect as the foregoing scheme can be achieved.

For example, in some embodiments, it is possible to adopt a stable oxygen-containing etching method (including a flow rate of fixing an oxygen-containing etching gas) from the beginning to the end in the regulation of the introduction of the oxygen-containing gas. It is also possible to modulate the etching (first etching most of the area to be etched with an etching gas containing no oxygen, and then introducing an etching gas containing oxygen to complete the etching termination; or, it may be pulsed Etching is performed by introducing an etching gas containing oxygen to improve etching uniformity, surface flatness, and the like.

The material of the first semiconductor may include GaN, but is not limited thereto.

The material of the second semiconductor may include AlGaN, AlInN, or AlInGaN, but is not limited thereto.

Further, an etch stop layer may be disposed between the third semiconductor and the second semiconductor or between the second semiconductor and the first semiconductor, and the etch stop layer includes the selected material, and the etching is automatic Terminating at a set depth in the surface of the etch stop layer or within the etch stop layer.

Preferably, the material of the etch stop layer includes AlN, but is not limited thereto.

The material of the third semiconductor includes p-GaN, p-AlGaN, p-AlInN, p-InGaN, or p-AlInGaN, but is not limited thereto.

In some more specific embodiments, the HEMT device of the present application is a p-gate based HEMT, wherein the p-type semiconductor material is not limited to p-GaN. The present application is also applicable to enhanced HEMTs having other p-type layers, such as p-AlGaN, p-AlInN, p-InGaN, p-AlInGaN, and composite structures thereof. If the p-type cap layer contains Al, if an oxygen is introduced during the etching process, an oxide layer (Al,Ga)O _x (for example, Al ₂ O ₃ ) is generated, thereby suppressing further etching, so that p can be used. -AlGaN/p-GaN composite structure, first etching the p-type layer containing Al with an oxygen-free atmosphere, then etching the p-GaN layer by oxygen, etching the AlGaN barrier terminated under the p-GaN layer Floor.

Wherein, the material of the first material layer is selected from an Al-containing semiconductor material, preferably from p-AlGaN, p-AlInN, p-InGaN or p-AlInGaN.

The material of the second material layer is selected from a semiconductor material containing no Al, preferably p-GaN, but is not limited thereto.

The active region structure of the foregoing HEMT includes an AlGaN/AlN/GaN heterojunction, an AlInN/AlN/GaN heterojunction, or an AlInGaN/AlN/GaN heterojunction, but is not limited thereto.

Alternatively, the active region structure of the aforementioned HEMT includes a dual channel heterojunction.

The substrate material of the HEMT includes silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride or graphene, but is not limited thereto.

In some more specific embodiments, a method for preparing a GaN-based enhanced HEMT includes:

Providing an epitaxial structure of a HEMT, the epitaxial structure including a heterostructure formed mainly by a first semiconductor and a second semiconductor, the second semiconductor being formed on the first semiconductor, and the second semiconductor having a larger than the first a band gap of the semiconductor, and the second semiconductor comprises an aluminum-containing component;

Selecting a region of the second semiconductor with an etching gas containing oxygen, and forming an in-situ passivation layer on the inner wall of the recess when the recessed structure is etched in the selected region The etch is automatically terminated, and the in-situ passivation layer is mainly formed by agglomeration of an etch-resistant substance formed by the reaction of oxygen and an aluminum-containing component, the selected area corresponding to the gate, and the groove bottom surface of the groove structure is distributed in the Between the set depth in the second semiconductor or between the second semiconductor and the first semiconductor;

And, an electrode is fabricated on the epitaxial structure to obtain the HEMT.

In some more specific embodiments, a method for preparing a GaN-based enhanced HEMT includes:

Providing an epitaxial structure of the HEMT, the epitaxial structure including a heterostructure formed mainly by a first semiconductor and a second semiconductor, and a third semiconductor formed on the second semiconductor;

Making a source and a drain on the third semiconductor,

Forming a passivation layer on the third semiconductor, the source and the drain, and then opening an etching window on a region of the passivation layer corresponding to the gate;

The epitaxial structure is etched from the etch window with an etch gas containing oxygen, and in-situ passivation is formed on the inner wall of the recess when the recess structure is etched into the epitaxial structure a layer, the etching is automatically terminated, and the in-situ passivation layer is mainly formed by aggregating an etching resistant substance formed by reacting oxygen with an aluminum-containing substance distributed in the second semiconductor or between the second semiconductor and the first semiconductor, a groove bottom surface of the groove structure is distributed at a set depth in the second semiconductor or between the second semiconductor and the first semiconductor;

Forming a dielectric layer on the passivation layer and an inner wall of the groove structure,

And forming a gate on the epitaxial structure.

In this embodiment, the third semiconductor system functions as a cap layer, and the material thereof may be selected from GaN or the like.

Further, the preparation method may include:

Providing an intervening layer between the first semiconductor and the second semiconductor, the intercalation layer comprising an aluminum-containing substance;

Etching the epitaxial structure from the etching window with an etching gas containing oxygen until the groove structure is formed, the groove bottom surface of the groove structure is distributed on the surface of the insertion layer or the insertion The set depth in the layer. The oxygen content in the etching gas can also be adjusted during the etching of this embodiment.

In some more specific embodiments, a method for preparing a GaN-based enhanced HEMT includes:

Providing an epitaxial structure of the HEMT, the epitaxial structure including a heterostructure formed mainly by a first semiconductor and a second semiconductor, the second semiconductor being formed on the first semiconductor, the second semiconductor having a larger than the first semiconductor a band gap, a third semiconductor is formed on the second semiconductor, the conductivity of the third semiconductor is different from the second semiconductor, and an aluminum-containing substance or a first portion is distributed between the first semiconductor and the second semiconductor The second semiconductor comprises an aluminum-containing substance;

Etching the region outside the selected region of the third semiconductor with an etching gas containing oxygen, and between the third semiconductor and the second semiconductor or when the region outside the selected region is etched away Forming an in-situ passivation layer on the surface of the semiconductor, the etching is automatically terminated, and the in-situ passivation layer is mainly formed by aggregation of an etching resistant material formed by reacting oxygen with an aluminum-containing component, the selected region corresponding to the gate ;

And, an electrode is fabricated on the epitaxial structure to obtain the HEMT.

Further, the preparation method may further include:

Providing an etch stop layer between the second semiconductor and the third semiconductor, the etch stop layer comprising an aluminum-containing substance;

Etching the region outside the selected region of the third semiconductor from the etching window with an etching gas containing oxygen, and ending the etching when the region outside the selected region is removed by etching The in-situ passivation layer is formed on the surface of the layer (wherein the in-situ passivation layer is distributed between the third semiconductor and the second semiconductor). The oxygen content in the etching gas can also be adjusted during the etching of this embodiment.

Further, the preparation method may further include:

Making a gate on the third semiconductor,

Etching the region other than the region under the gate of the third semiconductor with an etching gas containing oxygen using the gate as a mask until the in-situ passivation layer is formed,

A source and a drain are then formed on the epitaxial structure.

Further, the preparation method may further include: after the etching is automatically terminated, forming a passivation layer on the epitaxial structure, and then performing electrode fabrication.

In the foregoing various embodiments of the present application, each of the semiconductor layers, the passivation layer, the dielectric layer, and the like in the HEMT epitaxial structure may be formed by physical or chemical methods such as PECVD, MOCVD, ALD, and the like.

In the foregoing various embodiments of the present application, the preparation process of the HEMT device further includes isolating the active region, and preparing the source, the drain, and the gate by evaporation, sputtering, or the like, and the operations may be performed. Implemented in a manner known in the art. In the foregoing various embodiments of the present application, in the formed HEMT device, the source and the drain may be connected to an epitaxial structure, such as a barrier layer (generally the aforementioned second semiconductor) or a cap layer (generally the foregoing The three semiconductors form an ohmic contact. In the foregoing various embodiments of the present application, in the formed HEMT device, the gate may be associated with an epitaxial structure, such as a barrier layer (generally the aforementioned second semiconductor), a p-type layer or a cap layer (generally the foregoing The third semiconductor) forms a Schottky contact or an ohmic contact, or a dielectric layer (such as an alumina material) may be disposed between the gate and the barrier layer, the p-type layer or the cap layer.

The material of the source, the drain, and the gate may be made of a metal material such as titanium, tungsten, nickel, gold, or the like, but is not limited thereto.

In the foregoing various embodiments of the present application, the formed HEMT device may also include or comprise a field plate structure.

In the foregoing various embodiments of the present application, the substrate material of the formed HEMT device may include silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride, graphene, or the like, and is not limited thereto.

The HEMT preparation process provided by the present application can realize self-terminating of etching, and can realize precise control of etching depth while ensuring etching without delay of high aluminum component and ensuring that the etching rate is not lowered, and the etching is ensured to the utmost extent. The two-dimensional electron gas in the region is not affected by the etching process, ensuring the electrical characteristics of the device, including output current, dynamic characteristic threshold voltage stability, etc., which greatly reduces the difficulty of implementing the enhanced HEMT by using p-gate technology and trench gate technology. Ensure the repeatability, uniformity and stability of the device process. Moreover, with the technical solution of the present application, an in-situ passivation layer can be naturally formed on the surface of the semiconductor in the etching process, and the passivation layer can play a key protective role, thereby effectively reducing the deposition process due to the subsequent passivation layer. Problems such as surface damage and the resulting deterioration in electrical properties of materials and devices (such as increased on-resistance and significant current collapse effects).

The present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

P-type layer etching: During the p-type layer etching process, oxygen can be introduced throughout the process; or oxygen can be introduced at a certain time according to actual needs. Further, the p-type layer may also be a p-AlGaN/p-GaN composite layer. Accordingly, the following Examples 1 to 3 are proposed:

Example 1

S1. MOCVD epitaxial growth of an enhanced HEMT epitaxial structure based on p-GaN/AlGaN/GaN heterojunction. Wherein, the p-type layer p-GaN has a thickness of 5 to 300 nm, the magnesium doping concentration ranges from 10 ¹⁸ to 10 ²¹ /cm ³ , and the AlGaN barrier layer has an Al composition x of 10% to 35% and a thickness of 5 ～. 25 nm; AlN insertion layer is about 1 nm; GaN channel layer is 50 to 200 nm, and the HEMT epitaxial structure is shown in FIG.

S2.p-GaN etching. Using photoresist AZ5214 as a mask, p-GaN is etched by ICP (Inductive Coupled Plasma) etching technique, and the mixed gas is chlorine gas/oxygen/nitrogen gas, chlorine gas flow rate is 10～100sccm, oxygen The flow rate is 5% to 80% of the chlorine gas flow rate, the nitrogen flow rate is 15% to 75% of the chlorine gas flow rate, the cavity pressure is 10 to 100 mTorr, the RF power is 10 to 100 W, and the ICP power is 300 to 2500 W to form an oxide layer (Al, Ga). The thickness of O _x is about 0.5 to 3 nm. As shown in Figure 4.

S3. Active area isolation. Ion implantation is carried out by N ion implantation technique, and the ion implantation energy is 150-400 KeV ion implantation, and the implantation ion dose is 10 ¹² to 10 ¹⁴ /cm ² , and the implantation depth is about 50 to 250 nm beyond the buffer layer, as shown in FIG. 5 .

S4. Gate metal deposition. The tungsten (W) metal is deposited by magnetron sputtering to a thickness of 50 to 200 nm, as shown in FIG.

S5. Passivation layer deposition. The SiN _x passivation layer is deposited by a dielectric layer deposition technique such as PECVD, ICP-CVD, or LPCVD to a thickness of 50 to 500 nm, as shown in FIG.

S6. Passivation layer etching window. The SiN _x is etched by RIE (Reactive Ion Etch) to realize ohmic contact opening, as shown in FIG.

S7. Source and drain ohmic contact, source field plate preparation. Preparation conditions: metal Ti / Al / Ni / Au, thickness of 20nm / 130nm / 50nm / 150nm, annealing conditions of 890 ° C, 30s, nitrogen atmosphere, as shown in Figure 9.

S8. Lead electrode. Preparation conditions: Metal Ni/Au, thickness 50 nm / 400 nm, as shown in FIG.

Example 2

S1. MOCVD epitaxial growth of an enhanced HEMT epitaxial structure based on p-GaN/AlGaN/GaN heterojunction. Wherein, the p-type layer p-GaN has a thickness of 5 to 300 nm, the magnesium doping concentration ranges from 10 ¹⁸ to 10 ²¹ /cm ³ , and the AlGaN barrier layer has an Al composition x of 10% to 35% and a thickness of 5 ～. 25 nm; AlN insertion layer is about 1 nm; GaN channel layer is 50 to 200 nm, and the HEMT epitaxial structure is shown in FIG.

S2.p-GaN etching. P-GaN was etched by ICP etching using photoresist AZ5214 as a mask. First, the etching gas is etched by chlorine gas/boron trichloride for rapid etching of p-GaN, the flow rate of chlorine gas is 10 to 100 sccm, the flow rate of boron trichloride is 20 to 250 sccm, the pressure of the cavity is 10 to 100 mTorr, and the RF power is 10 to 10. 100W, ICP power 300 ~ 2500 W, etching rate 80 ~ 400nm / min. Then, the etching gas is switched to chlorine gas/oxygen/nitrogen gas, and the remaining p-GaN is completely etched, the chlorine gas flow rate is 10 to 100 sccm, the oxygen flow rate is 5% to 80% of the chlorine gas flow rate, and the nitrogen gas flow rate is 15% of the chlorine gas flow rate. 75%, the cavity pressure is 10 to 100 mTorr, the RF power is 10 to 100 W, and the ICP power is 300 to 2500 W, and the oxide layer (Al, Ga) O _{x is formed to have a} thickness of about 0.5 to 3 nm.

S3 to S8: S3 to S8 in the same manner as in the first embodiment. The device after the completion of the entire chip process is shown in FIG.

Example 3

S1.MOCVD epitaxial growth of an enhanced HEMT epitaxial structure based on p-AlGaN/p-GaN/AlGaN/GaN heterojunction. Wherein, the p-type layer p-AlGaN has a thickness of 5 to 100 nm, the magnesium doping concentration ranges from 10 ¹⁸ to 10 ²¹ /cm ³ , the Al composition is 10% to 35%, and the p-type layer has a p-GaN thickness of 5 ~300nm, magnesium doping concentration range is 10 ¹⁸ ~ 10 ²¹ /cm ³ ; AlGaN barrier layer Al composition x is 10% ~ 35%, thickness is 5 ~ 25nm; AlN insertion layer is about 1nm; GaN groove The channel layer is 50-200 nm, and the HEMT epitaxial structure is shown in FIG.

S2.p-GaN etching. P-GaN was etched by ICP etching using photoresist AZ5214 as a mask. First, the etching gas is etched with chlorine gas/boron trichloride/oxygen to p-AlGaN, the chlorine gas flow rate is 10 to 100 sccm, and the boron trichloride flow rate is 20 to 250 sccm, and the oxygen flow rate is adjusted to be 0. % ~ 5%, cavity pressure 10 ~ 100mTorr, RF power 10 ~ 100W, ICP power 300 ~ 2500W, etching rate 80 ~ 400nm / min. Then, the etching gas is switched to chlorine gas/oxygen/nitrogen gas, and the remaining p-GaN is completely etched, the chlorine gas flow rate is 10 to 100 sccm, the oxygen flow rate is 5% to 80% of the chlorine gas flow rate, and the nitrogen gas flow rate is 15% of the chlorine gas flow rate. 75%, the cavity pressure is 10 to 100 mTorr, the RF power is 10 to 100 W, and the ICP power is 300 to 2500 W, and the oxide layer (Al, Ga) O _{x is formed to have a} thickness of about 0.5 to 3 nm.

S3 to S8: S3 to S8 in the same manner as in the first embodiment. The device after completing the entire chip process is shown in Figure 12.

In the present application, for the preparation of the enhanced HEMT based on the p-gate technology, the device process flow is not limited to the process flow described in the foregoing embodiments 1 to 3, and includes a gate first process (gate first). - GaN is formed by self-aligned etching), Passivation First (passivation first, etching of p-GaN, passivation layer deposition).

Trench etch: In the trench gate etch process, selective etching of epitaxial layers of different aluminum components is achieved by adjusting the oxygen content to achieve selective etch termination. Accordingly, the following embodiment 4 is proposed:

Example 4

S1.MOCVD epitaxial growth of HEMT epitaxial structures based on AlGaN/GaN heterojunctions. The AlGaN barrier layer has an Al composition content of 10% to 35%, a thickness of 10 to 35 nm, and an AlN insertion layer thickness of 1 to 2 nm. The GaN channel layer is 50 to 200 nm, and the HEMT epitaxial structure is as shown in FIG.

S2. Source and drain ohmic contact. The electron beam evaporation technique was used to prepare a metal Ti/Al/Ni/Au having a thickness of 20 nm/130 nm/50 nm/150 nm. The annealing conditions are 800 to 890 ° C, 30 to 50 s, and a nitrogen atmosphere, as shown in FIG.

S3. Active area isolation. Ion implantation is performed by N ion implantation technique, and the ion implantation energy is 150-400 KeV ion implantation, and the implantation ion dose is 10 ¹² to 10 ¹⁴ /cm ² , and the implantation depth is about 50 to 250 nm beyond the buffer layer, as shown in FIG.

S4. Passivation layer deposition. The SiN _x passivation layer is deposited by a dielectric layer deposition technique such as PECVD, ICP-CVD, LPCVD, and has a thickness of 50 to 500 nm as shown in FIG.

S5. The gate opens. The SiN _x was etched by RIE (Reactive Ion Etch) using the photoresist AZ5214 as a mask (1 to 2 μm) to realize gate opening, as shown in FIG.

S6. Etching the trench gate. On the basis of "gate opening", the photoresist AZ5214 is used as a mask, and etching is performed by ICP etching technology. Specifically, the etched mixed gas is made of chlorine gas/boron trichloride/oxygen, and the GaN cap layer and the AlGaN barrier layer are etched and etched and self-terminated in the AlN insertion layer, wherein the chlorine gas flow rate is 10 to 100 sccm, The flow rate of boron chloride is 20-250sccm, and the oxygen flow rate is adjusted to be 0%-3% of the chlorine gas flow rate, the cavity pressure is 10-100mTorr, the RF power is 50-150W, the ICP power is 300-2500W, and the etching rate is 80-400nm/ Min, the oxide layer (Al, Ga) O _{x is formed to have a} thickness of about 0.5 to 3 nm as shown in FIG.

S7. Gate dielectric layer deposition. The photoresist is removed, and the gate dielectric layer Al ₂ O _{3 is} deposited by an ALD (Atom Layer Deposition) technique to a thickness of 2 to 50 nm as shown in FIG.

S8. Gate metal deposition. Using electron beam evaporation technique, the preparation conditions were as follows: metal Ni/Au, thickness 50 nm / 250 nm, as shown in FIG.

S9. Source and drain ohmic contact open windows. Using photoresist AZ5214 as a mask (1~2μm), by plasma etching (in this embodiment, chlorine-containing plasma etching Al ₂ O ₃ , fluorine-containing plasma etching SiN _x ) The source and drain ohmic contacts open the window as shown in FIG.

S10. Lead electrode. Preparation conditions: Metal Ni/Au, thickness 50 nm / 400 nm, as shown in FIG.

In the present application, for the preparation of the enhanced HEMT based on the trench gate technology, the device process flow is not limited to the process of etching from the termination of the AlN insertion layer as described in the foregoing Embodiment 4, and may also include etching to terminate in the potential. Device process flow of barrier layer AlGaN.

The trench gate etching is combined with the p-GaN etching: first etching the barrier layer of the gate region (without oxygen), then regenerating the long p-type layer, and finally performing oxygen-containing etching on the non-gate region. The p-type layer of the non-gate region is removed to further increase the threshold voltage of the enhancement device. Accordingly, the following embodiment 5 is proposed:

Example 5

S1.MOCVD epitaxial growth of HEMT epitaxial structures based on AlGaN/GaN heterojunctions. The AlGaN barrier layer has an Al composition content of 10% to 35%, a thickness of 20 to 45 nm, and an AlN insertion layer thickness of 1 to 2 nm. The GaN channel layer is 50 to 200 nm, and the HEMT epitaxial structure is as shown in FIG.

S2. Etching the gate recess. The AlGaN barrier layer is etched by a chlorine gas/boron trichloride mixed gas, wherein the cavity pressure is 10 to 100 mTorr, the RF power is 5 to 150 W, the ICP power is 25 to 500 W, and the etching rate is 5 to 100 nm/min, leaving The gate region AlGaN barrier layer has a thickness of 2 to 16 nm as shown in FIG.

S3.p-GaN regrowth. The p-type layer p-GaN has a thickness of 5 to 300 nm, and the magnesium doping concentration ranges from 10 ¹⁸ to 10 ²¹ /cm ³ as shown in FIG.

S4. Non-gate region p-type layer etching. Using photoresist AZ5214 as a mask, p-GaN is etched by ICP etching technology. The mixed gas is chlorine/oxygen/nitrogen, the chlorine gas flow rate is 10~100sccm, and the oxygen flow rate is 5%-80% of the chlorine gas flow rate. The nitrogen flow rate is 15% to 75% of the chlorine gas flow rate, the cavity pressure is 10 to 100 mTorr, the RF power is 10 to 100 W, and the ICP power is 300 to 2500 W. The thickness of the oxide layer (Al, Ga) O _x is about 0.5 to 3 nm, as shown in the figure. 25 is shown.

S5 to S10 are the same as S3 to S8 of the first embodiment. The device after completing the entire chip fabrication process is shown in FIG.

The principles and embodiments of the present application have been described in detail in the present specification. The description of the above embodiments is only for facilitating understanding of the method of the present application and its core idea. It should be noted that those skilled in the art can make several modifications and changes to the present application without departing from the scope of the present application. These modifications and modifications are also within the scope of the appended claims.

Claims (29)

A method for fabricating a GaN-based enhanced HEMT, comprising: etching a selected region in an epitaxial structure of the HEMT with an etch reagent containing a selected substance, and constituting the selected region Selecting a material to react with the selected material until an etching resistant material sufficient to cover the etched surface is formed, thereby preventing etching of the epitaxial structure by the etching reagent, thereby achieving automatic termination of etching while obtaining The required HEMT device structure. The method according to claim 1, comprising: ???said sufficient amount of etching resistant material during etching of said selected region with an etching reagent containing said selected substance An in-situ passivation layer is formed on the etched surface to achieve automatic termination of the etch. The method according to claim 1, comprising: adjusting an etching parameter in real time according to at least an amount of selected material in said selected region and/or a desired etching depth, said etching parameter At least one of the amount of the etching reagent, the content of the selected substance in the etching reagent, and the etching power is included to obtain a desired HEMT device structure while achieving automatic termination of etching. The preparation method according to claim 1, wherein the etching reagent is an etching gas. Process according to claim 1, characterized in that the selected substance comprises an oxygen-containing substance, preferably from an oxygen-containing gas, preferably from oxygen, ozone, carbon dioxide or nitrogen oxides, preferably oxygen. The preparation method according to claim 5, wherein the etching gas contains any one or a combination of two or more of chlorine gas, nitrogen gas, argon gas, and boron trichloride, and a mixed gas of oxygen. The preparation method according to claim 6, wherein the etching gas comprises chlorine gas, a mixed gas of oxygen and nitrogen, a mixed gas of chlorine gas, oxygen gas and argon gas, chlorine gas, boron trichloride, oxygen gas and nitrogen gas. Mixed gas, or a mixture of chlorine, boron trichloride, oxygen and argon. The method according to claim 1, wherein the selected material is selected from the group consisting of Al-containing semiconductor materials; preferably from AlGaN, AlN, AlInGaN or AlInN. The method according to claim 1, further comprising: removing the etching resistant material covering the etched surface, or setting the etching resistant material covering the etched surface Passivation layer. The method according to claim 1, comprising: said epitaxial structure comprises a heterostructure formed mainly by a first semiconductor and a second semiconductor, said second semiconductor being formed on said first semiconductor When the etch is automatically terminated, at least a recess structure corresponding to the gate is formed in the second semiconductor, and a groove bottom surface of the groove structure is distributed at a set depth within the second semiconductor or the second Between the semiconductor and the first semiconductor; preferably, the inner wall of the recess structure is covered with an in-situ passivation layer formed by the sufficient amount of the etching resistant material to be aggregated on the etched surface. The method according to claim 10, further comprising: forming a third semiconductor on the second semiconductor, the third semiconductor having the same conductivity as the second semiconductor, and when the etching is automatically terminated, The groove structure corresponding to the gate electrode is formed in the third semiconductor and the second semiconductor. The method according to claim 10 or 11, further comprising: an intercalation layer further disposed between the first semiconductor and the second semiconductor, the intercalation layer containing or not containing the selected material, The groove bottom surface of the groove structure is distributed at the interface of the second semiconductor and the insertion layer or at a set depth in the insertion layer; preferably, the material of the insertion layer comprises AlN. The method according to claim 1, comprising: said epitaxial structure comprising a first semiconductor, a second semiconductor formed on the first semiconductor, and a third semiconductor formed on the second semiconductor, wherein the first semiconductor Forming a heterostructure with the second semiconductor, the third semiconductor having a different conductivity than the second semiconductor, and when the etching is automatically terminated, the third semiconductor is replaced by an area other than the area under the gate Etching removal; Preferably, the second semiconductor is covered with an in-situ passivation layer formed by the sufficient amount of the etching resistant material to be aggregated on the etched surface. The method according to claim 13, comprising: etching the gate region of the second semiconductor with an etching reagent containing no selected substance, and then regenerating the third semiconductor, and then using the selected one. The etch reagent of the material etches the non-gate region of the third semiconductor to remove the third semiconductor in the non-gate region until the etch is automatically terminated. The method according to claim 10, 11, 13, or 14, wherein the first semiconductor and the second semiconductor have the same conductivity. The method according to claim 11, 13 or 14, wherein the third semiconductor is p-type or n-type. The preparation method according to claim 13 or 14, wherein: The third semiconductor includes a first material layer and a second material layer formed on the first material layer, the second material layer not containing the selected material, and the first material layer containing the selected a material, in the process of etching the third semiconductor by an etching reagent, sequentially etching the second material layer and the first material layer by adjusting a content of the selected substance in the etching reagent, Automatically terminating the etching until the in-situ passivation layer is formed; Or the third semiconductor includes a first material layer formed on the second semiconductor and a second material layer formed on the first material layer, the first material layer not containing the selected material And the second material layer contains the selected material, and in the process of etching the third semiconductor by the etching reagent, sequentially adjusting the content of the selected substance in the etching reagent to sequentially implement the second Etching of the material layer and the first material layer until reaching the interface of the first material layer and the second semiconductor or at a set depth within the second semiconductor, within the second semiconductor surface or the second semiconductor An in-situ passivation layer is formed to allow the etch to be automatically terminated. The method according to claim 10, 11, 13, or 14, wherein the material of the first semiconductor comprises GaN. And/or, the material of the second semiconductor includes AlGaN, AlInN or AlInGaN. The preparation method according to claim 13, 14 or 16, wherein an etch stop layer is further disposed between the third semiconductor and the second semiconductor or between the second semiconductor and the first semiconductor, The etch stop layer includes the selected material, and the etching is automatically terminated at a predetermined depth in the surface of the etch stop layer or the etch stop layer; preferably, the material of the etch stop layer includes AlN. The preparation method according to claim 13, 14 or 16, wherein the material of the third semiconductor comprises p-GaN, p-AlGaN, p-AlInN, p-InGaN or p-AlInGaN. The preparation method according to claim 16, wherein the material of the first material layer is selected from an Al-containing semiconductor material, preferably from p-AlGaN, p-AlInN, p-InGaN or p-AlInGaN; and/or The material of the second material layer is selected from a semiconductor material not containing Al, preferably p-GaN. The method according to claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, or 16, wherein the active region structure of the HEMT comprises AlGaN /AlN/GaN heterojunction, AlInN/AlN/GaN heterojunction, AlInGaN/AlN/GaN heterojunction; or, the active region structure of the HEMT includes a double channel heterojunction; and/or, The substrate material of the HEMT includes silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride or graphene. A method for preparing a GaN-based enhanced HEMT, comprising: Providing an epitaxial structure of a HEMT, the epitaxial structure including a heterostructure formed mainly by a first semiconductor and a second semiconductor, the second semiconductor being formed on the first semiconductor, and the second semiconductor having a larger than the first a band gap of the semiconductor, and the second semiconductor comprises an aluminum-containing component; Selecting a region of the second semiconductor with an etching gas containing oxygen, and forming an in-situ passivation layer on the inner wall of the recess when the recessed structure is etched in the selected region The etch is automatically terminated, and the in-situ passivation layer is mainly formed by agglomeration of an etch-resistant substance formed by the reaction of oxygen and an aluminum-containing component, the selected area corresponding to the gate, and the groove bottom surface of the groove structure is distributed in the Between the set depth in the second semiconductor or between the second semiconductor and the first semiconductor; And, an electrode is fabricated on the epitaxial structure to obtain the HEMT. A method for preparing a GaN-based enhanced HEMT, comprising: Providing an epitaxial structure of the HEMT, the epitaxial structure including a heterostructure formed mainly by a first semiconductor and a second semiconductor, and a third semiconductor formed on the second semiconductor; Making a source and a drain on the third semiconductor, Forming a passivation layer on the third semiconductor, the source and the drain, and then opening an etching window on a region of the passivation layer corresponding to the gate; The epitaxial structure is etched from the etch window with an etch gas containing oxygen, and in-situ passivation is formed on the inner wall of the recess when the recess structure is etched into the epitaxial structure a layer, the etching is automatically terminated, and the in-situ passivation layer is mainly formed by the reaction of oxygen with an aluminum-containing substance distributed in the second semiconductor or between the second semiconductor and the first semiconductor Forming an etchant, the groove bottom surface of the groove structure is distributed at a set depth within the second semiconductor or between the second semiconductor and the first semiconductor; Forming a dielectric layer on the passivation layer and an inner wall of the groove structure, And forming a gate on the epitaxial structure. The preparation method according to claim 24, comprising: Providing an intervening layer between the first semiconductor and the second semiconductor, the intercalation layer comprising an aluminum-containing substance; Etching the epitaxial structure from the etching window with an etching gas containing oxygen, and adjusting or not adjusting the oxygen content in the etching gas during the etching process until the groove structure is formed The groove bottom surface of the groove structure is distributed at a set depth of the surface of the insertion layer or the insertion layer. A method for preparing a GaN-based enhanced HEMT, comprising: Providing an epitaxial structure of the HEMT, the epitaxial structure including a heterostructure formed mainly by a first semiconductor and a second semiconductor, the second semiconductor being formed on the first semiconductor, the second semiconductor having a larger than the first semiconductor a band gap, a third semiconductor is formed on the second semiconductor, the conductivity of the third semiconductor is different from the second semiconductor, and an aluminum-containing substance or a first portion is distributed between the first semiconductor and the second semiconductor The second semiconductor comprises an aluminum-containing substance; Etching the region outside the selected region of the third semiconductor with an etching gas containing oxygen, and adjusting or not adjusting the oxygen content in the etching gas during the etching process, outside the selected region When the regions are all etched away, an in-situ passivation layer is formed between the third semiconductor and the second semiconductor or the second semiconductor surface, and the etching is automatically terminated. The in-situ passivation layer is mainly composed of oxygen and aluminum. The etch-resistant substance formed by the partial reaction is aggregated, and the selected area corresponds to the gate; And, an electrode is fabricated on the epitaxial structure to obtain the HEMT. The preparation method according to claim 26, comprising: Providing an etch stop layer between the second semiconductor and the third semiconductor, the etch stop layer comprising an aluminum-containing substance; Etching the region outside the selected region of the third semiconductor from the etching window with an etching gas containing oxygen, and ending the etching when the region outside the selected region is removed by etching The in-situ passivation layer is formed on the surface of the layer. The preparation method according to claim 26, comprising: Making a gate on the third semiconductor, Etching the region other than the region under the gate of the third semiconductor with an etching gas containing oxygen using the gate as a mask until the in-situ passivation layer is formed, A source and a drain are then formed on the epitaxial structure. The preparation method according to claim 26, comprising: forming a passivation layer on the epitaxial structure after the etching is automatically terminated, and then performing electrode fabrication.

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