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WO2018014412A1 - Goa电路及液晶显示面板 - Google Patents

Goa电路及液晶显示面板 Download PDF

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Publication number
WO2018014412A1
WO2018014412A1 PCT/CN2016/096058 CN2016096058W WO2018014412A1 WO 2018014412 A1 WO2018014412 A1 WO 2018014412A1 CN 2016096058 W CN2016096058 W CN 2016096058W WO 2018014412 A1 WO2018014412 A1 WO 2018014412A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal line
goa
nmos transistor
pmos transistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/096058
Other languages
English (en)
French (fr)
Inventor
洪光辉
陈归
龚强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US15/319,755 priority Critical patent/US10446094B2/en
Publication of WO2018014412A1 publication Critical patent/WO2018014412A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present invention relates to the field of display screen driving, and in particular to a GOA circuit and a liquid crystal display panel.
  • liquid crystal display panels such as high resolution, high brightness, and high reaction rate.
  • GOA gate on The array circuit is an important circuit for driving a liquid crystal display panel in a liquid crystal display for realizing progressive driving of a gate to realize normal display of the liquid crystal display panel.
  • Array substrate test array The test circuit is a circuit for testing the electrical connection of a GOA circuit.
  • the signal lines of the GOA circuit such as STV (start signal line), U2D (forward scan signal line), D2U (reverse scan signal line) or the like is connected to the corresponding test signal line on the array substrate test circuit by wires.
  • STV start signal line
  • U2D forward scan signal line
  • D2U reverse scan signal line
  • static electricity may enter the GOA circuit through the test signal line of the array substrate test circuit, thereby causing damage to the GOA circuit, thereby affecting the normal operation of the entire liquid crystal display panel.
  • the object of the present invention is to provide a GOA circuit and a liquid crystal display panel which can effectively avoid electrostatic damage caused by a GOA circuit, and solve the problem that the existing GOA circuit and the liquid crystal display panel are liable to cause electrostatic damage, thereby affecting the normal operation of the entire liquid crystal display panel. technical problem.
  • An embodiment of the present invention provides a GOA circuit, including:
  • a GOA driver chip for generating a scan driving signal
  • a GOA driving signal line for transmitting the scan driving signal to a corresponding scan line
  • An array substrate test chip for generating an array substrate test signal
  • a GOA protection circuit disposed between the GOA driving signal line and the test signal line for preventing an electrostatic signal on the test signal line from being transmitted to the GOA driving signal line;
  • the GOA driving signal line includes but is not limited to at least one of a start signal line, a forward scan signal line, a reverse scan signal line, a clock signal line, a high level signal line, a low level signal line, and an enable signal line. ;
  • the GOA protection circuit is a transmission gate circuit or an inverter circuit.
  • the GOA protection circuit is a transmission gate circuit
  • the transmission gate circuit includes an NMOS transistor and a PMOS transistor
  • An input end of the NMOS transistor is connected to the test signal line, an output end of the NMOS transistor is connected to the GOA driving signal line, and a control end of the NMOS transistor is connected to a protection control signal source;
  • An input end of the PMOS transistor is connected to the test signal line, an output end of the PMOS transistor is connected to the GOA driving signal line, and a control end of the PMOS transistor is connected to the protection control signal source through a NOT gate.
  • the protection control signal source when the corresponding liquid crystal display panel performs screen display, the protection control signal source outputs a low level signal to block the test signal line and the GOA driving signal line;
  • the protection control signal source When the corresponding liquid crystal display panel performs the screen test, the protection control signal source outputs a high level signal to turn on the test signal line and the GOA driving signal line.
  • the GOA protection circuit is an inverter circuit
  • the inverter circuit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor;
  • An input end of the first NMOS transistor is connected to a low level source, an output end of the first NMOS transistor is connected to an input end of the second NMOS transistor, and a control end of the first NMOS transistor and a protection control signal Source connection
  • An output end of the second NMOS transistor is connected to the GOA driving signal line through a NOT gate, and a control end of the second NMOS transistor is connected to the test signal line;
  • An input end of the first PMOS transistor is connected to a high-level source, an output end of the first PMOS transistor is connected to an input end of the second PMOS transistor, and a control end of the first PMOS transistor passes through a non-gate
  • the protection control signal source is connected;
  • An output end of the second PMOS transistor is connected to the GOA driving signal line through a NOT gate, and a control end of the second PMOS transistor is connected to the test signal line.
  • the protection control signal source when the corresponding liquid crystal display panel performs screen display, the protection control signal source outputs a low level signal to block the test signal line and the GOA driving signal line;
  • the protection control signal source When the corresponding liquid crystal display panel performs the screen test, the protection control signal source outputs a high level signal to turn on the test signal line and the GOA driving signal line.
  • An embodiment of the present invention provides a GOA circuit, including:
  • a GOA driver chip for generating a scan driving signal
  • a GOA driving signal line for transmitting the scan driving signal to a corresponding scan line
  • An array substrate test chip for generating an array substrate test signal
  • a GOA protection circuit disposed between the GOA driving signal line and the test signal line for preventing an electrostatic signal on the test signal line from being transmitted to the GOA driving signal line.
  • the GOA protection circuit is a transmission gate circuit.
  • the transmission gate circuit includes an NMOS transistor and a PMOS transistor;
  • An input end of the NMOS transistor is connected to the test signal line, an output end of the NMOS transistor is connected to the GOA driving signal line, and a control end of the NMOS transistor is connected to a protection control signal source;
  • An input end of the PMOS transistor is connected to the test signal line, an output end of the PMOS transistor is connected to the GOA driving signal line, and a control end of the PMOS transistor is connected to the protection control signal source through a NOT gate.
  • the protection control signal source when the corresponding liquid crystal display panel performs screen display, the protection control signal source outputs a low level signal to block the test signal line and the GOA driving signal line;
  • the protection control signal source When the corresponding liquid crystal display panel performs the screen test, the protection control signal source outputs a high level signal to turn on the test signal line and the GOA driving signal line.
  • the GOA protection circuit is an inverter circuit.
  • the inverter circuit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor;
  • An input end of the first NMOS transistor is connected to a low level source, an output end of the first NMOS transistor is connected to an input end of the second NMOS transistor, and a control end of the first NMOS transistor and a protection control signal Source connection
  • An output end of the second NMOS transistor is connected to the GOA driving signal line through a NOT gate, and a control end of the second NMOS transistor is connected to the test signal line;
  • An input end of the first PMOS transistor is connected to a high-level source, an output end of the first PMOS transistor is connected to an input end of the second PMOS transistor, and a control end of the first PMOS transistor passes through a non-gate
  • the protection control signal source is connected;
  • An output end of the second PMOS transistor is connected to the GOA driving signal line through a NOT gate, and a control end of the second PMOS transistor is connected to the test signal line.
  • the protection control signal source when the corresponding liquid crystal display panel performs screen display, the protection control signal source outputs a low level signal to block the test signal line and the GOA driving signal line;
  • the protection control signal source When the corresponding liquid crystal display panel performs the screen test, the protection control signal source outputs a high level signal to turn on the test signal line and the GOA driving signal line.
  • the GOA driving signal line includes but is not limited to an enable signal line, a forward scan signal line, a reverse scan signal line, a clock signal line, a high level signal line, and a low level signal. At least one of a line and an enable signal line.
  • An embodiment of the present invention further provides a liquid crystal display panel including a GOA circuit, wherein the GOA circuit includes:
  • a GOA driver chip for generating a scan driving signal
  • a GOA driving signal line for transmitting the scan driving signal to a corresponding scan line
  • An array substrate test chip for generating an array substrate test signal
  • a GOA protection circuit disposed between the GOA driving signal line and the test signal line for preventing an electrostatic signal on the test signal line from being transmitted to the GOA driving signal line.
  • the GOA protection circuit is a transmission gate circuit.
  • the transfer gate circuit includes an NMOS transistor and a PMOS transistor;
  • An input end of the NMOS transistor is connected to the test signal line, an output end of the NMOS transistor is connected to the GOA driving signal line, and a control end of the NMOS transistor is connected to a protection control signal source;
  • An input end of the PMOS transistor is connected to the test signal line, an output end of the PMOS transistor is connected to the GOA driving signal line, and a control end of the PMOS transistor is connected to the protection control signal source through a NOT gate.
  • the protection control signal source when the corresponding liquid crystal display panel performs screen display, the protection control signal source outputs a low level signal to block the test signal line and the GOA driving signal line;
  • the protection control signal source When the corresponding liquid crystal display panel performs the screen test, the protection control signal source outputs a high level signal to turn on the test signal line and the GOA driving signal line.
  • the GOA protection circuit is an inverter circuit.
  • the inverter circuit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor;
  • An input end of the first NMOS transistor is connected to a low level source, an output end of the first NMOS transistor is connected to an input end of the second NMOS transistor, and a control end of the first NMOS transistor and a protection control signal Source connection
  • An output end of the second NMOS transistor is connected to the GOA driving signal line through a NOT gate, and a control end of the second NMOS transistor is connected to the test signal line;
  • An input end of the first PMOS transistor is connected to a high-level source, an output end of the first PMOS transistor is connected to an input end of the second PMOS transistor, and a control end of the first PMOS transistor passes through a non-gate
  • the protection control signal source is connected;
  • An output end of the second PMOS transistor is connected to the GOA driving signal line through a NOT gate, and a control end of the second PMOS transistor is connected to the test signal line.
  • the protection control signal source when the corresponding liquid crystal display panel performs screen display, the protection control signal source outputs a low level signal to block the test signal line and the GOA driving signal line;
  • the protection control signal source When the corresponding liquid crystal display panel performs the screen test, the protection control signal source outputs a high level signal to turn on the test signal line and the GOA driving signal line.
  • the GOA circuit and the liquid crystal display panel of the present invention can effectively prevent electrostatic damage to the GOA circuit caused by the electrostatic signal on the test signal line through the setting of the GOA protection circuit;
  • Some GOA circuits and liquid crystal display panels are prone to electrostatic damage, which affects the technical problems of the normal operation of the entire liquid crystal display panel.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a GOA circuit of the present invention.
  • FIG. 2 is a specific circuit diagram of a GOA protection circuit of a preferred embodiment of the GOA circuit of the present invention when transmitting a gate circuit;
  • FIG. 3 is a detailed circuit diagram of a preferred embodiment of the GOA circuit of the present invention when the GOA protection circuit is an inverter circuit.
  • FIG. 1 is a schematic structural diagram of a preferred embodiment of a GOA circuit according to the present invention.
  • the GOA circuit of the preferred embodiment is used to provide a scan driving signal to a corresponding liquid crystal display panel, and the GOA circuit 10 includes a GOA driving chip 11.
  • the GOA driver chip 11 is for generating a scan driving signal; the GOA driving signal line 12 is for transmitting a scan driving signal to the corresponding scan line 16; the array substrate test chip 13 is for generating an array substrate test signal; and the test signal line 14 is for using the array The substrate test signal is transmitted to the corresponding scan line 16; the GOA protection circuit 15 is disposed between the GOA drive signal line 12 and the test signal line 14 for preventing the electrostatic signal on the test signal line 14 from being transmitted to the GOA drive signal line 12.
  • the GOA driving signal line 12 includes, but is not limited to, an enable signal line STV1, a forward scan signal line U2D1, a reverse scan signal line D2U1, a clock signal line CK1, a high level signal line VGH1, a low level signal line VGL1, and One or more of the signal lines GRST1.
  • test signal line 14 includes, but is not limited to, an enable signal line STV2, a forward scan signal line U2D2, a reverse scan signal line D2U2, a clock signal line CK2, a high level signal line VGH2, a low level signal line VGL2, and enable.
  • an enable signal line STV2 a forward scan signal line U2D2, a reverse scan signal line D2U2, a clock signal line CK2, a high level signal line VGH2, a low level signal line VGL2, and enable.
  • GRST2 enable signal line
  • FIG. 2 is a specific circuit diagram of the GOA protection circuit of the preferred embodiment of the GOA circuit of the present invention when the gate circuit is transmitted.
  • 2 is a specific circuit diagram of a transmission gate circuit.
  • the transmission gate circuit includes an NMOS transistor 21 and a PMOS transistor 22.
  • the input end of the NMOS transistor 21 is connected to a test signal line, and the output end of the NMOS transistor 21 is connected to a GOA driving signal line.
  • the control end of 21 is connected to the protection control signal source ATEN1;
  • the input end of the PMOS transistor 22 is connected to the test signal line, the output end of the PMOS transistor 22 is connected to the GOA drive signal line, and the control end of the PMOS transistor 22 passes the NOT gate and the protection control signal.
  • Source ATEN1 is connected.
  • the protection control signal source ATEN1 When the GOA circuit 10 of the preferred embodiment is in operation, when the corresponding liquid crystal display panel performs screen display, the protection control signal source ATEN1 outputs a low level signal, so that the control terminal of the NMOS transistor 21 inputs a low level signal, and the NMOS transistor 21 is off. In the on state, the control terminal of the PMOS transistor 22 inputs a high level signal, the PMOS transistor 22 is also in an off state, and the test signal line is in a blocking state from the corresponding GOA driving signal line, thereby effectively avoiding electrostatic signal transmission of the test signal line. On the GOA circuit, the GOA circuit 10 is prevented from being electrostatically damaged.
  • the protection control signal source ATEN1 When the corresponding liquid crystal display panel performs the screen test using the test signal line, the protection control signal source ATEN1 outputs a high level signal, so that the control terminal of the NMOS transistor 21 inputs a high level signal, and the NMOS transistor 21 is in an on state; the PMOS transistor 22 The control terminal inputs a low level signal, the PMOS transistor 22 is also in an on state, and the test signal line is in an on state with the corresponding GOA driving signal line; thus, the GOA circuit 10 can be effectively tested using the test signal line.
  • FIG. 3 is a specific circuit diagram of a preferred embodiment of the GOA circuit of the present invention when the GOA protection circuit is an inverter circuit.
  • 3 is a specific circuit diagram of an inverter circuit including a first NMOS transistor 31, a second NMOS transistor 32, a first PMOS transistor 33, and a second PMOS transistor 34.
  • the input end of the first NMOS transistor 31 is connected to the low level source VGL, the output end of the first NMOS transistor 31 is connected to the input end of the second NMOS transistor 32, and the control end of the first NMOS transistor 31 is connected to the protection control signal source ATEN2.
  • the output end of the second NMOS transistor 32 is connected to the GOA driving signal line through the NOT gate, and the control terminal of the second NMOS transistor 32 is connected to the test signal line;
  • the input end of the first PMOS transistor 33 is connected to the high-level source VGH,
  • An output terminal of a PMOS transistor 33 is connected to an input terminal of the second PMOS transistor 34, a control terminal of the first PMOS transistor 33 is connected to the protection control signal source ATEN2 through a NOT gate, and an output terminal of the second PMOS transistor 34 is passed through a NOT gate and a GOA.
  • the driving signal line is connected, and the control terminal of the second PMOS transistor 34 is connected to the test signal line.
  • the protection control signal source ATEN2 When the GOA circuit 10 of the preferred embodiment is in operation, when the corresponding liquid crystal display panel performs screen display, the protection control signal source ATEN2 outputs a low level signal, so that the control terminal of the first NMOS transistor 31 inputs a low level signal, first The NMOS transistor 31 is in an off state, the control terminal of the first PMOS transistor 33 inputs a high level signal, and the first PMOS transistor 33 is in an off state, so that the input terminals of the second NMOS transistor 32 and the second PMOS transistor 34 have no signal. Therefore, the test signal line is in a state of being separated from the corresponding GOA driving signal line, so that the electrostatic signal of the test signal line can be effectively prevented from being transmitted to the GOA circuit, and the electrostatic damage of the GOA circuit 10 is prevented.
  • the protection control signal source ATEN2 When the corresponding liquid crystal display panel performs the screen test using the test signal line, the protection control signal source ATEN2 outputs a high level signal, so that the control terminal of the first NMOS transistor 31 inputs a high level signal, and the first NMOS transistor 31 is in an on state.
  • the control terminal of the first PMOS transistor 33 inputs a low level signal, and the first PMOS transistor 33 is in an on state, such that the second NMOS transistor 32 inputs a low level signal through the first NMOS transistor 31, and the second PMOS transistor 34 passes the A PMOS transistor 33 inputs a high level signal.
  • the GOA circuit 10 can be effectively signal tested using test signal lines.
  • the GOA circuit of the preferred embodiment can effectively prevent electrostatic damage to the GOA circuit caused by the electrostatic signal on the test signal line through the setting of the GOA protection circuit.
  • the embodiment of the invention further provides a liquid crystal display panel, which comprises a GOA circuit, a scan line, a data line and corresponding pixel units.
  • the GOA circuit includes a GOA driver chip, a GOA driver signal line, an array substrate test chip, a test signal line, and a GOA protection circuit.
  • the GOA driver chip is used to generate a scan driving signal; the GOA driving signal line is used to transmit the scan driving signal to the corresponding scan line; the array substrate test chip is used to generate the array substrate test signal; and the test signal line is used to transmit the array substrate test signal to Corresponding scan line; the GOA protection circuit is disposed between the GOA drive signal line and the test signal line for preventing the electrostatic signal on the test signal line from being transmitted to the GOA drive signal line.
  • the GOA protection circuit is a transmission gate circuit.
  • the transmission gate circuit comprises an NMOS transistor and a PMOS transistor; an input end of the NMOS transistor is connected to the test signal line, an output end of the NMOS transistor is connected to the GOA drive signal line, and a control end of the NMOS transistor is connected to the protection control signal source; the PMOS transistor The input end is connected to the test signal line, the output end of the PMOS transistor is connected to the GOA drive signal line, and the control end of the PMOS tube is connected to the protection control signal source through the non-gate.
  • the protection control signal source when the corresponding liquid crystal display panel performs screen display, the protection control signal source outputs a low level signal to block the test signal line and the GOA driving signal line; when the corresponding liquid crystal display panel performs screen test, the protection control signal source A high level signal is output to turn on the test signal line and the GOA drive signal line.
  • the GOA protection circuit is an inverter circuit.
  • the inverter circuit comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a second PMOS transistor; the first NMOS transistor input terminal is connected to the low level source, and the output end of the first NMOS transistor is The input end of the second NMOS transistor is connected, the control end of the first NMOS transistor is connected to the protection control signal source; the output end of the second NMOS transistor is connected to the GOA drive signal line through the NOT gate, and the control end and the test signal line of the second NMOS transistor Connecting; the input end of the first PMOS transistor is connected to the high-level source, the output end of the first PMOS transistor is connected to the input end of the second PMOS transistor, and the control end of the first PMOS transistor is connected to the protection control signal source through the NOT gate; The output end of the second PMOS transistor is connected to the GOA driving signal line through a NOT gate, and the control terminal of the second PMOS transistor is connected to the test signal line.
  • the protection control signal source when the corresponding liquid crystal display panel performs screen display, the protection control signal source outputs a low level signal to block the test signal line and the GOA driving signal line; when the corresponding liquid crystal display panel performs screen test, the protection control signal source A high level signal is output to turn on the test signal line and the GOA drive signal line.
  • the GOA driving signal line includes but is not limited to at least one of a start signal line, a forward scan signal line, a reverse scan signal line, a clock signal line, a high level signal line, a low level signal line, and an enable signal line. .
  • the specific working principle of the liquid crystal display panel of the present invention is the same as or similar to that described in the preferred embodiment of the GOA circuit described above. For details, refer to the related description in the preferred embodiment of the GOA circuit described above.
  • the GOA circuit and the liquid crystal display panel of the invention can effectively prevent the electrostatic signal on the test signal line from causing electrostatic damage to the GOA circuit through the setting of the GOA protection circuit; and solve the problem that the existing GOA circuit and the liquid crystal display panel are liable to cause electrostatic damage. Therefore, the technical problem of the normal operation of the entire liquid crystal display panel is affected.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种GOA电路，包括GOA驱动芯片（11）、GOA驱动信号线（12）、阵列基板测试芯片（13）、测试信号线（14）以及GOA保护电路（15）。GOA驱动芯片（11）用于生成扫描驱动信号；GOA驱动信号线（12）用于传输扫描驱动信号至相应的扫描线（16）；阵列基板测试芯片（13）用于生成阵列基板测试信号；测试信号线（14）用于将阵列基板测试信号传输至相应的扫描线（16）；GOA保护电路（15）设置在GOA驱动信号线（12）和测试信号线（14）之间。

Description

GOA电路及液晶显示面板 技术领域
本发明涉及显示屏驱动领域，特别是涉及一种GOA电路及液晶显示面板。
 背景技术
随着科技的发展，越来越多的用户使用各种各样的液晶显示面板进行工作、学习以及娱乐活动。因此用户对液晶显示面板的要求也越来越高，如高分辨率、高亮度以及高反应速率等。
GOA（gate on array）电路是一种液晶显示器中用于驱动液晶显示面板的重要电路，用于实现扫描线（gate）的逐行驱动，以实现液晶显示面板的正常显示。阵列基板测试（array test）电路是一种用于测试GOA电路的电性连接情况的电路。
在现有的液晶显示面板的设计方案中，GOA电路的信号线，如STV（启动信号线）, U2D（正向扫描信号线）, D2U（反向扫描信号线）等，与阵列基板测试电路上的对应的测试信号线通过导线连接。这样当该液晶显示面板进行正常显示或进行静电测试时，静电可能通过阵列基板测试电路的测试信号线进入到GOA电路，对GOA电路造成损伤，从而影响整个液晶显示面板的正常工作。
故，有必要提供一种GOA电路及液晶显示面板，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种可有效避免GOA电路造成静电损伤的GOA电路及液晶显示面板；以解决现有的GOA电路及液晶显示面板容易造成静电损伤，从而影响整个液晶显示面板的正常工作的技术问题。
 技术解决方案
本发明实施例提供一种GOA电路，其包括：
GOA驱动芯片，用于生成扫描驱动信号；
GOA驱动信号线，用于传输所述扫描驱动信号至相应的扫描线；
阵列基板测试芯片，用于生成阵列基板测试信号；
测试信号线，用于将所述阵列基板测试信号传输至相应的扫描线；以及
GOA保护电路，设置在所述GOA驱动信号线和所述测试信号线之间，用于防止所述测试信号线上的静电信号传输至所述GOA驱动信号线；
其中所述GOA驱动信号线包括但不限于启动信号线、正向扫描信号线、反向扫描信号线、时钟信号线、高电平信号线、低电平信号线以及使能信号线中至少一个；
所述GOA保护电路为传输门电路或反相器电路。
在本发明所述的GOA电路中，当所述GOA保护电路为传输门电路时，
所述传输门电路包括NMOS晶体管以及PMOS晶体管；
所述NMOS晶体管的输入端与所述测试信号线连接，所述NMOS晶体管的输出端与所述GOA驱动信号线连接，所述NMOS晶体管的控制端与保护控制信号源连接；
所述PMOS晶体管的输入端与所述测试信号线连接，所述PMOS晶体管的输出端与所述GOA驱动信号线连接，所述PMOS管的控制端通过非门与所述保护控制信号源连接。
在本发明所述的GOA电路中，当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
在本发明所述的GOA电路中，当所述GOA保护电路为反相器电路时，
所述反相器电路包括第一NMOS晶体管、第二NMOS晶体管、第一PMOS晶体管以及第二PMOS晶体管；
所述第一NMOS晶体管的输入端与低电平源连接，所述第一NMOS晶体管的输出端与所述第二NMOS晶体管的输入端连接，所述第一NMOS晶体管的控制端与保护控制信号源连接；
所述第二NMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二NMOS晶体管的控制端与所述测试信号线连接；
所述第一PMOS晶体管的输入端与高电平源连接，所述第一PMOS晶体管的输出端与所述第二PMOS晶体管的输入端连接，所述第一PMOS晶体管的控制端通过非门与所述保护控制信号源连接；
所述第二PMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二PMOS晶体管的控制端与所述测试信号线连接。
在本发明所述的GOA电路中，当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
本发明实施例提供一种GOA电路，其包括：
GOA驱动芯片，用于生成扫描驱动信号；
GOA驱动信号线，用于传输所述扫描驱动信号至相应的扫描线；
阵列基板测试芯片，用于生成阵列基板测试信号；
测试信号线，用于将所述阵列基板测试信号传输至相应的扫描线；以及
GOA保护电路，设置在所述GOA驱动信号线和所述测试信号线之间，用于防止所述测试信号线上的静电信号传输至所述GOA驱动信号线。
在本发明所述的GOA电路中，所述GOA保护电路为传输门电路。
在本发明所述的GOA电路中，所述传输门电路包括NMOS晶体管以及PMOS晶体管；
所述NMOS晶体管的输入端与所述测试信号线连接，所述NMOS晶体管的输出端与所述GOA驱动信号线连接，所述NMOS晶体管的控制端与保护控制信号源连接；
所述PMOS晶体管的输入端与所述测试信号线连接，所述PMOS晶体管的输出端与所述GOA驱动信号线连接，所述PMOS管的控制端通过非门与所述保护控制信号源连接。
在本发明所述的GOA电路中，当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
在本发明所述的GOA电路中，所述GOA保护电路为反相器电路。
在本发明所述的GOA电路中，所述反相器电路包括第一NMOS晶体管、第二NMOS晶体管、第一PMOS晶体管以及第二PMOS晶体管；
所述第一NMOS晶体管的输入端与低电平源连接，所述第一NMOS晶体管的输出端与所述第二NMOS晶体管的输入端连接，所述第一NMOS晶体管的控制端与保护控制信号源连接；
所述第二NMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二NMOS晶体管的控制端与所述测试信号线连接；
所述第一PMOS晶体管的输入端与高电平源连接，所述第一PMOS晶体管的输出端与所述第二PMOS晶体管的输入端连接，所述第一PMOS晶体管的控制端通过非门与所述保护控制信号源连接；
所述第二PMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二PMOS晶体管的控制端与所述测试信号线连接。
在本发明所述的GOA电路中，当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
在本发明所述的GOA电路中，所述GOA驱动信号线包括但不限于启动信号线、正向扫描信号线、反向扫描信号线、时钟信号线、高电平信号线、低电平信号线以及使能信号线中至少一个。
本发明实施例还提供一种液晶显示面板，其包括GOA电路，其中所述GOA电路包括：
GOA驱动芯片，用于生成扫描驱动信号；
GOA驱动信号线，用于传输所述扫描驱动信号至相应的扫描线；
阵列基板测试芯片，用于生成阵列基板测试信号；
测试信号线，用于将所述阵列基板测试信号传输至相应的扫描线；以及
GOA保护电路，设置在所述GOA驱动信号线和所述测试信号线之间，用于防止所述测试信号线上的静电信号传输至所述GOA驱动信号线。
在本发明所述的液晶显示面板中，所述GOA保护电路为传输门电路。
在本发明所述的液晶显示面板中，所述传输门电路包括NMOS晶体管以及PMOS晶体管；
所述NMOS晶体管的输入端与所述测试信号线连接，所述NMOS晶体管的输出端与所述GOA驱动信号线连接，所述NMOS晶体管的控制端与保护控制信号源连接；
所述PMOS晶体管的输入端与所述测试信号线连接，所述PMOS晶体管的输出端与所述GOA驱动信号线连接，所述PMOS管的控制端通过非门与所述保护控制信号源连接。
在本发明所述的液晶显示面板中，当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
在本发明所述的液晶显示面板中，所述GOA保护电路为反相器电路。
在本发明所述的液晶显示面板中，所述反相器电路包括第一NMOS晶体管、第二NMOS晶体管、第一PMOS晶体管以及第二PMOS晶体管；
所述第一NMOS晶体管的输入端与低电平源连接，所述第一NMOS晶体管的输出端与所述第二NMOS晶体管的输入端连接，所述第一NMOS晶体管的控制端与保护控制信号源连接；
所述第二NMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二NMOS晶体管的控制端与所述测试信号线连接；
所述第一PMOS晶体管的输入端与高电平源连接，所述第一PMOS晶体管的输出端与所述第二PMOS晶体管的输入端连接，所述第一PMOS晶体管的控制端通过非门与所述保护控制信号源连接；
所述第二PMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二PMOS晶体管的控制端与所述测试信号线连接。
在本发明所述的液晶显示面板中，当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
 有益效果
相较于现有的GOA电路及液晶显示面板，本发明的GOA电路及液晶显示面板通过GOA保护电路的设置，可有效的避免测试信号线上的静电信号对GOA电路造成静电损伤；解决了现有的GOA电路及液晶显示面板容易造成静电损伤，从而影响整个液晶显示面板的正常工作的技术问题。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图1为本发明的GOA电路的优选实施例的结构示意图；
图2为本发明的GOA电路的优选实施例的GOA保护电路为传输门电路时的具体电路图；
图3为本发明的GOA电路的优选实施例的GOA保护电路为反相器电路时的具体电路图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的GOA电路的优选实施例的结构示意图，本优选实施例的GOA电路用于给相应的液晶显示面板提供扫描驱动信号，该GOA电路10包括GOA驱动芯片11、GOA驱动信号线12、阵列基板测试芯片13、测试信号线14以及GOA保护电路15。
GOA驱动芯片11用于生成扫描驱动信号；GOA驱动信号线12用于传输扫描驱动信号至相应的扫描线16；阵列基板测试芯片13用于生成阵列基板测试信号；测试信号线14用于将阵列基板测试信号传输至相应的扫描线16；GOA保护电路15设置在GOA驱动信号线12和测试信号线14之间，用于防止测试信号线14上的静电信号传输至GOA驱动信号线12。
这里的GOA驱动信号线12包括但不限于启动信号线STV1、正向扫描信号线U2D1、反向扫描信号线D2U1、时钟信号线CK1、高电平信号线VGH1、低电平信号线VGL1以及使能信号线GRST1中一个或多个。
这里的测试信号线14包括但不限于启动信号线STV2、正向扫描信号线U2D2、反向扫描信号线D2U2、时钟信号线CK2、高电平信号线VGH2、低电平信号线VGL2以及使能信号线GRST2中一个或多个。
请参照图2，图2为本发明的GOA电路的优选实施例的GOA保护电路为传输门电路时的具体电路图。图2为传输门电路的具体电路图，该传输门电路包括NMOS晶体管21以及PMOS晶体管22，NMOS晶体管21的输入端与测试信号线连接，NMOS晶体管21的输出端与GOA驱动信号线连接，NMOS晶体管21的控制端与保护控制信号源ATEN1连接；PMOS晶体管22的输入端与测试信号线连接，PMOS晶体管22的输出端与GOA驱动信号线连接，PMOS管22的控制端通过非门与保护控制信号源ATEN1连接。
本优选实施例的GOA电路10工作时，当相应的液晶显示面板进行画面显示，保护控制信号源ATEN1输出低电平信号，这样NMOS晶体管21的控制端输入低电平信号，NMOS晶体管21处于断开状态，PMOS晶体管22的控制端输入高电平信号，PMOS晶体管22也处于断开状态，测试信号线与相应的GOA驱动信号线处于隔断状态，从而可以有效的避免测试信号线的静电信号传输至GOA电路上，防止GOA电路10产生静电损伤。
当相应的液晶显示面板使用测试信号线进行画面测试时，保护控制信号源ATEN1输出高电平信号，这样NMOS晶体管21的控制端输入高电平信号，NMOS晶体管21处于导通状态；PMOS晶体管22的控制端输入低电平信号，PMOS晶体管22也处于导通状态，测试信号线与相应的GOA驱动信号线处于导通状态；从而可使用测试信号线对GOA电路10进行有效的信号测试。
请参照图3，图3为本发明的GOA电路的优选实施例的GOA保护电路为反相器电路时的具体电路图。图3为反相器电路的具体电路图，该反相器电路包括第一NMOS晶体管31、第二NMOS晶体管32、第一PMOS晶体管33以及第二PMOS晶体管34。
第一NMOS晶体管31的输入端与低电平源VGL连接，第一NMOS晶体管31的输出端与第二NMOS晶体管32的输入端连接，第一NMOS晶体管31的控制端与保护控制信号源ATEN2连接；第二NMOS晶体管32的输出端通过非门与GOA驱动信号线连接，第二NMOS晶体管32的控制端与测试信号线连接；第一PMOS晶体管33的输入端与高电平源VGH连接，第一PMOS晶体管33的输出端与第二PMOS晶体管34的输入端连接，第一PMOS晶体管33的控制端通过非门与保护控制信号源ATEN2连接；第二PMOS晶体管34的输出端通过非门与GOA驱动信号线连接，第二PMOS晶体管34的控制端与测试信号线连接。
本优选实施例的GOA电路10工作时，当相应的液晶显示面板进行画面显示时，保护控制信号源ATEN2输出低电平信号，这样第一NMOS晶体管31的控制端输入低电平信号，第一NMOS晶体管31处于断开状态，第一PMOS晶体管33的控制端输入高电平信号，第一PMOS晶体管33处于断开状态，这样第二NMOS晶体管32和第二PMOS晶体管34的输入端均没有信号，因此测试信号线与相应的GOA驱动信号线处于隔断状态，从而可以有效的避免测试信号线的静电信号传输至GOA电路上，防止GOA电路10产生静电损伤。
当相应的液晶显示面板使用测试信号线进行画面测试时，保护控制信号源ATEN2输出高电平信号，这样第一NMOS晶体管31的控制端输入高电平信号，第一NMOS晶体管31处于导通状态，第一PMOS晶体管33的控制端输入低电平信号，第一PMOS晶体管33处于导通状态，这样第二NMOS晶体管32通过第一NMOS晶体管31输入低电平信号，第二PMOS晶体管34通过第一PMOS晶体管33输入高电平信号。
当测试信号线为高电平时，第二NMOS晶体管32导通，第二PMOS晶体管34断开，GOA驱动信号线输出高电平信号；当测试信号线为低电平时，第二PMOS晶体管34导通，第二NMOS晶体管32断开，GOA驱动信号线输出低电平信号。从而可使用测试信号线对GOA电路10进行有效的信号测试。
这样即完成了本优选实施例的GOA电路10的画面显示驱动以及画面测试驱动过程。
本优选实施例的GOA电路通过GOA保护电路的设置，可有效的避免测试信号线上的静电信号对GOA电路造成静电损伤。
本发明实施例还提供一种液晶显示面板，该液晶显示面板包括GOA电路、扫描线、数据线以及相应的像素单元。其中GOA电路包括GOA驱动芯片、GOA驱动信号线、阵列基板测试芯片、测试信号线以及GOA保护电路。
GOA驱动芯片用于生成扫描驱动信号；GOA驱动信号线用于传输扫描驱动信号至相应的扫描线；阵列基板测试芯片用于生成阵列基板测试信号；测试信号线用于将阵列基板测试信号传输至相应的扫描线；GOA保护电路设置在GOA驱动信号线和测试信号线之间，用于防止测试信号线上的静电信号传输至GOA驱动信号线。
优选的，GOA保护电路为传输门电路。
优选的，传输门电路包括NMOS晶体管以及PMOS晶体管；NMOS晶体管的输入端与测试信号线连接，NMOS晶体管的输出端与GOA驱动信号线连接，NMOS晶体管的控制端与保护控制信号源连接；PMOS晶体管的输入端与测试信号线连接，PMOS晶体管的输出端与GOA驱动信号线连接，PMOS管的控制端通过非门与保护控制信号源连接。
优选的，当相应的液晶显示面板进行画面显示时，保护控制信号源输出低电平信号，以隔断测试信号线与GOA驱动信号线；当相应的液晶显示面板进行画面测试时，保护控制信号源输出高电平信号，以导通测试信号线与所述GOA驱动信号线。
优选的，GOA保护电路为反相器电路。
优选的，反相器电路包括第一NMOS晶体管、第二NMOS晶体管、第一PMOS晶体管以及第二PMOS晶体管；第一NMOS晶体管输入端与低电平源连接，第一NMOS晶体管的输出端与第二NMOS晶体管的输入端连接，第一NMOS晶体管的控制端与保护控制信号源连接；第二NMOS晶体管的输出端通过非门与GOA驱动信号线连接，第二NMOS晶体管的控制端与测试信号线连接；第一PMOS晶体管的输入端与高电平源连接，第一PMOS晶体管的输出端与第二PMOS晶体管的输入端连接，第一PMOS晶体管的控制端通过非门与保护控制信号源连接；第二PMOS晶体管的输出端通过非门与GOA驱动信号线连接，第二PMOS晶体管的控制端与测试信号线连接。
优选的，当相应的液晶显示面板进行画面显示时，保护控制信号源输出低电平信号，以隔断测试信号线与GOA驱动信号线；当相应的液晶显示面板进行画面测试时，保护控制信号源输出高电平信号，以导通测试信号线与GOA驱动信号线。
优选的，GOA驱动信号线包括但不限于启动信号线、正向扫描信号线、反向扫描信号线、时钟信号线、高电平信号线、低电平信号线以及使能信号线中至少一个。
本发明的液晶显示面板的具体工作原理与上述的GOA电路的优选实施例中的描述相同或相似，具体请参见上述GOA电路的优选实施例中的相关描述。
本发明的GOA电路及液晶显示面板通过GOA保护电路的设置，可有效的避免测试信号线上的静电信号对GOA电路造成静电损伤；解决了现有的GOA电路及液晶显示面板容易造成静电损伤，从而影响整个液晶显示面板的正常工作的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种GOA电路，其包括：
    GOA驱动芯片，用于生成扫描驱动信号；
    GOA驱动信号线，用于传输所述扫描驱动信号至相应的扫描线；
    阵列基板测试芯片，用于生成阵列基板测试信号；
    测试信号线，用于将所述阵列基板测试信号传输至相应的扫描线；以及
    GOA保护电路，设置在所述GOA驱动信号线和所述测试信号线之间，用于防止所述测试信号线上的静电信号传输至所述GOA驱动信号线；
    其中所述GOA驱动信号线包括但不限于启动信号线、正向扫描信号线、反向扫描信号线、时钟信号线、高电平信号线、低电平信号线以及使能信号线中至少一个；
    所述GOA保护电路为传输门电路或反相器电路。
  2. 根据权利要求1所述的GOA电路，其中当所述GOA保护电路为传输门电路时，
    所述传输门电路包括NMOS晶体管以及PMOS晶体管；
    所述NMOS晶体管的输入端与所述测试信号线连接，所述NMOS晶体管的输出端与所述GOA驱动信号线连接，所述NMOS晶体管的控制端与保护控制信号源连接；
    所述PMOS晶体管的输入端与所述测试信号线连接，所述PMOS晶体管的输出端与所述GOA驱动信号线连接，所述PMOS管的控制端通过非门与所述保护控制信号源连接。
  3. 根据权利要求2所述的GOA电路，其中当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
    当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
  4. 根据权利要求1所述的GOA电路，其中当所述GOA保护电路为反相器电路时，
    所述反相器电路包括第一NMOS晶体管、第二NMOS晶体管、第一PMOS晶体管以及第二PMOS晶体管；
    所述第一NMOS晶体管的输入端与低电平源连接，所述第一NMOS晶体管的输出端与所述第二NMOS晶体管的输入端连接，所述第一NMOS晶体管的控制端与保护控制信号源连接；
    所述第二NMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二NMOS晶体管的控制端与所述测试信号线连接；
    所述第一PMOS晶体管的输入端与高电平源连接，所述第一PMOS晶体管的输出端与所述第二PMOS晶体管的输入端连接，所述第一PMOS晶体管的控制端通过非门与所述保护控制信号源连接；
    所述第二PMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二PMOS晶体管的控制端与所述测试信号线连接。
  5. 根据权利要求4所述的GOA电路，其中当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
    当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
  6. 一种GOA电路，其包括：
    GOA驱动芯片，用于生成扫描驱动信号；
    GOA驱动信号线，用于传输所述扫描驱动信号至相应的扫描线；
    阵列基板测试芯片，用于生成阵列基板测试信号；
    测试信号线，用于将所述阵列基板测试信号传输至相应的扫描线；以及
    GOA保护电路，设置在所述GOA驱动信号线和所述测试信号线之间，用于防止所述测试信号线上的静电信号传输至所述GOA驱动信号线。
  7. 根据权利要求6所述的GOA电路，其中所述GOA保护电路为传输门电路。
  8. 根据权利要求7所述的GOA电路，其中所述传输门电路包括NMOS晶体管以及PMOS晶体管；
    所述NMOS晶体管的输入端与所述测试信号线连接，所述NMOS晶体管的输出端与所述GOA驱动信号线连接，所述NMOS晶体管的控制端与保护控制信号源连接；
    所述PMOS晶体管的输入端与所述测试信号线连接，所述PMOS晶体管的输出端与所述GOA驱动信号线连接，所述PMOS管的控制端通过非门与所述保护控制信号源连接。
  9. 根据权利要求8所述的GOA电路，其中
    当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
    当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
  10. 根据权利要求6所述的GOA电路，其中所述GOA保护电路为反相器电路。
  11. 根据权利要求10所述的GOA电路，其中所述反相器电路包括第一NMOS晶体管、第二NMOS晶体管、第一PMOS晶体管以及第二PMOS晶体管；
    所述第一NMOS晶体管的输入端与低电平源连接，所述第一NMOS晶体管的输出端与所述第二NMOS晶体管的输入端连接，所述第一NMOS晶体管的控制端与保护控制信号源连接；
    所述第二NMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二NMOS晶体管的控制端与所述测试信号线连接；
    所述第一PMOS晶体管的输入端与高电平源连接，所述第一PMOS晶体管的输出端与所述第二PMOS晶体管的输入端连接，所述第一PMOS晶体管的控制端通过非门与所述保护控制信号源连接；
    所述第二PMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二PMOS晶体管的控制端与所述测试信号线连接。
  12. 根据权利要求11所述的GOA电路，其中
    当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
    当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
  13. 根据权利要求6所述的GOA电路，其中所述GOA驱动信号线包括但不限于启动信号线、正向扫描信号线、反向扫描信号线、时钟信号线、高电平信号线、低电平信号线以及使能信号线中至少一个。
  14. 一种液晶显示面板，其中包括GOA电路，其中所述GOA电路包括：
    GOA驱动芯片，用于生成扫描驱动信号；
    GOA驱动信号线，用于传输所述扫描驱动信号至相应的扫描线；
    阵列基板测试芯片，用于生成阵列基板测试信号；
    测试信号线，用于将所述阵列基板测试信号传输至相应的扫描线；以及
    GOA保护电路，设置在所述GOA驱动信号线和所述测试信号线之间，用于防止所述测试信号线上的静电信号传输至所述GOA驱动信号线。
  15. 根据权利要求14所述的液晶显示面板，其中所述GOA保护电路为传输门电路。
  16. 根据权利要求15所述的液晶显示面板，其中所述传输门电路包括NMOS晶体管以及PMOS晶体管；
    所述NMOS晶体管的输入端与所述测试信号线连接，所述NMOS晶体管的输出端与所述GOA驱动信号线连接，所述NMOS晶体管的控制端与保护控制信号源连接；
    所述PMOS晶体管的输入端与所述测试信号线连接，所述PMOS晶体管的输出端与所述GOA驱动信号线连接，所述PMOS管的控制端通过非门与所述保护控制信号源连接。
  17. 根据权利要求16所述的液晶显示面板，其中
    当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
    当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
  18. 根据权利要求14所述的液晶显示面板，其中所述GOA保护电路为反相器电路。
  19. 根据权利要求18所述的液晶显示面板，其中所述反相器电路包括第一NMOS晶体管、第二NMOS晶体管、第一PMOS晶体管以及第二PMOS晶体管；
    所述第一NMOS晶体管的输入端与低电平源连接，所述第一NMOS晶体管的输出端与所述第二NMOS晶体管的输入端连接，所述第一NMOS晶体管的控制端与保护控制信号源连接；
    所述第二NMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二NMOS晶体管的控制端与所述测试信号线连接；
    所述第一PMOS晶体管的输入端与高电平源连接，所述第一PMOS晶体管的输出端与所述第二PMOS晶体管的输入端连接，所述第一PMOS晶体管的控制端通过非门与所述保护控制信号源连接；
    所述第二PMOS晶体管的输出端通过非门与所述GOA驱动信号线连接，所述第二PMOS晶体管的控制端与所述测试信号线连接。
  20. 根据权利要求19所述的液晶显示面板，其中
    当相应的液晶显示面板进行画面显示时，所述保护控制信号源输出低电平信号，以隔断所述测试信号线与所述GOA驱动信号线；
    当相应的液晶显示面板进行画面测试时，所述保护控制信号源输出高电平信号，以导通所述测试信号线与所述GOA驱动信号线。
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