WO2018007062A1

WO2018007062A1 - Low-inductance power module design

Info

Publication number: WO2018007062A1
Application number: PCT/EP2017/061645
Authority: WO
Inventors: Ronald Eisele; Frank Osterwald; Ole MÜHLFELD; Holger BEER
Original assignee: Danfoss Silicon Power GmbH
Current assignee: Danfoss Silicon Power GmbH
Priority date: 2016-07-08
Filing date: 2017-05-15
Publication date: 2018-01-11
Anticipated expiration: 2019-01-08
Also published as: DE102016112602A1

Abstract

A power module (10) having at least two mutually electrically insulating layer, arranged one on top of the other, of conductor tracks (40, 60) conducting anti-parallel currents.

Description

Low-inductance power module design The invention relates to a power module.

Conventionally, power semiconductor modules form part of a power-electronic circuit that carries high currents and insulates high voltages. The electric circuit diagram is of low complexity and can therefore be represented by the layout of single-layer circuit carriers.

A ceramic circuit carrier has therefore been developed one side of which is covered by a structured copper layer that is structured corresponding to the circuit pattern. For reasons of symmetry and for the purpose of joining by soldering, the other side of the ceramic circuit carrier - is attached to a base plate by copper layer. This second copper layer is a usually non- structured and therefore does not represent any electric circuit-patterns. These circuit carriers are referred to as "Direct Copper Bonded" (DCB) carriers.

This type of DCB circuit carriers are usually connected by means of wire bonding to the outside terminals integrated into a housing framework.

As an alternative, for representing the electric circuit diagram, stamped copper foils or sheet copper are used that are insulated relative to the base plate using suitable, electrically non- conductive materials. In these cases, too, a single-layer structure is sufficient to represent the electric circuit diagram.

Since power modules are increasingly operated at higher switching frequencies, this leads to an increased importance of power modules having a low-inductance design. Single-layer circuit layouts are here at a disadvantage since current-carrying conductors arranged next to each other and in loops exhibit a high parasitic inductance.

Furthermore the outside terminals that are linked thereto are designed such that an additional parasitic inductance impedes the operation at high frequencies or the switching of the semiconductors with steep switching edges leads to considerable overvoltages. Demanding power electronic applications, i.e. automotive traction applications, require elevated DC link voltages in order to increase the output power while maintaining a given semiconductor voltage class, i.e. 650V. In contrast, parasitic inductance of the commutation loop induces transient voltage overshoots during the switching process of the semiconductors. In particular during a turn-off event, when a semiconductor switch is turned off and the current through consequently decays quickly, a positive voltage U is induced to the DC-link, given by the product of current change over time (di/dt) and parasitic inductance L:

di

U = L *—

dt

This induced voltage forces the system designer to introduce a safety margin between DC- link voltage and the rated breakdown voltage of the semiconductors. Thus, a limit to DC-link voltage or to the speed of turn-off (di/dt) is given by the parasitic inductance L.

In a molded power module, a fraction of 30-50% of the total parasitic inductance L is given by the lead frame design. A low-inductive lead frame would therefore allow a significant increase in DC-link voltage or in the switching speed (at the same time generating higher output power and higher efficiency in switching with the same silicon).

The object of the invention is therefore to create a power module that can be operated at higher switching frequencies.

This object is achieved by a power module having at least two mutually electrically insulated layers arranged one on top of the other of conductor tracks conducting anti-parallel currents.

The basic idea of the invention is to arrange, at least partially, a plurality of current-carrying, mutually insulated vertical layers in a power module in order to thereby enable a low- inductance formation of the electric circuit. In this way, conductors conducting anti-parallel currents (where currents are conducted in substantially opposite directions) can be created that exhibit a very low parasitic inductance. The principle of multi-layer conductor structures conducting anti-parallel currents can be utilised both on the substrate level and also for the outside terminals.

In addition, the use of such a multi-layer conductor can enable a low inductive power terminal connection to power modules. In particular a power terminal for the DC-link connection. A primary application for the invention herein described is the combination of laminated lead frames with molded power modules.

According to the invention, there is therefore provided the power module having at least two mutually electrically insulated layers, arranged one on top of the other, of conductor tracks conducting anti-parallel currents.

The conductor tracks are preferably formed by lead frames where lead frames may be formed as a metal structure from a flat plate of copper, copper alloy or other suitable metal, or as leads and/or other components mounted on a carrier such as a polyamide or polyimide film, as in the process known as tape- automated bonding (TAB). Such a lead frame can comprise a set of interconnected structures or a set of individual, separate structures which are brought to the substrate or baseplate during the assembly process of the power semiconductor module. Such lead frame structures may form simple interconnections between circuit elements, form the external leads of the module, or may have components such as chips, resistors, capacitors or other electronic components already mounted on them before placing on the substrate or baseplate.

The conductor tracks, for example the lead frames, in particular form mutually electrically insulated outside terminals conducting anti-parallel currents that are arranged one on top of the other outside the power module.

As an alternative, the first conductor track is the copper foil of a DCB power substrate and the second conductor track is formed from a thick- layer paste that is applied on an electrically insulating layer applied to the copper foil of the DCB power substrate. Particularly, the thick- layer paste can be a copper-containing thick-layer paste as well known from the state of art in the field of thick film technology.

It is further preferably provided that a first conductor track is arranged on a first electrically insulating layer that is arranged on a base plate. Particularly preferred there is then arranged a second conductor track on a second electrically insulating layer that is arranged on the first conductor track. The electrical insulation is preferably effected by a thermally conductive material. The electrical insulation is effected in particular by a plastic and/or a ceramic and/or by an inorganic cement material. The invention will be explained in more detail hereinbelow with reference to an exemplary embodiment of particularly preferred configuration which is shown in the accompanying drawings, in which:

Figure 1 shows a schematic side view of a first exemplary embodiment according to the invention;

Figure 2 shows a view of another embodiment of the invention comprising external terminals;

Figure 3 shows a schematic plan view of a further embodiment of the invention where the lead frames are placed in a position that is beneficial for achieving low terminal inductance;

Figure 4 shows a schematic plan view of a further embodiment of the invention where the lead frames are placed in a position that is beneficial for achieving even lower terminal inductance, and

Figure 5 shows a schematic side view of an alternative embodiment according to the invention.

The special exemplary embodiments described below describe alternative solutions that realise the inventive multiple layers of power layers. a) Multi-layer lead frame having lead frames and having an insulator

A preferred design variant consists in forming a power-electronics circuit by means of a plurality of electrically mutually insulated lead frames that carry the power components. The at least two layers of mutually insulated lead frames can be fastened to a base plate (cooling plate) for mechanically fastening and for optimum heat dissipation from the power components.

Ideally, the electrically insulating layers are formed from a material that is thermally conductive, electrically highly-insulating and at the same time adhering to the surfaces of lead frames and base plate. Such a material can be a thermally-conductively filled plastic, e.g. an epoxy compound filled with aluminium nitride (A1N) or boron (Br), that is processed as an adhesive insulation foil or as a liquid or liquefied plastic. Inorganic insulation materials such as cements are also possible.

Particularly preferably such a structure can also be used for the formation of the outside terminals, in that the at least two lead frame layers are arranged one on top of the other not only in the area of the circuit carrier such that the conductor tracks can be conducting anti- parallel currents, but can also be guided out as outside terminals arranged parallel on top of each other.

Fig. 1 represents such a structure of particularly preferably design.

Fig. 1 shows a power module 10 having a base plate 20, a first electrically insulating layer 30 arranged on the base plate 20 and, arranged thereon, a lower first lead frame 40 carrying two power semiconductors 70. On the first lead frame 40, a further electrically insulating layer 50 is arranged on which a further lead frame 60 is positioned such that (as far as possible) an anti-parallel power supply is possible. The bold arrows 201/202, 203/204 illustrate possible current paths in or out of the module and in addition these illustrated current paths show how the current flows are parallel, but in the opposite direction, thus forming the anti-parallel current flows.

The lead frame 40, 60 are preferably guided outside on both sides of the power module 10 and contacted in an exemplified manner by means of screw terminals 80, 90. As an alternative, the terminals can also be guided outside upwards in an angled-off manner and possibly outside of the power module 10. Figure 2 presents the general idea shown for two stacked lead frames 40, 60 separated by an insulating layer (not shown). Here substantially similar lead frames are used for illustration, which end in terminals suitable for guiding outside the molding of the module, and which end in terminals 80, 90 suitable for use as screw terminals. Mounting of the laminated lead frames can be done in a similar way to today's standard process where the laminated lead frame 40, 60 also holds a dam-bar 106 design, where the dam-bar sections of each of the plates of the laminated lead frame is position exactly on top of the other, i.e. with small adaptions to form the needed power terminal designs. Fig. 3 shows an embodiment of the present invention where the lead frames 40, 60 are placed in a position that is beneficial for achieving low terminal inductance. Here the lead frames are placed in a parallel orientation, so the magnetic fields of the DC current compensate each other. Only the external contact areas 80, 90 and the internal bonding areas of the lead frames 100, 101 can be placed in some distance to ensure ease of connection to the external busbar, in the case of the external contacts 80, 90 and the power tracks within the module 102, 103 in the case of the internal bonding areas 100, 101.

Fig. 4 shows another embodiment of the present invention where the lead frames 40, 60 are placed in a position that is beneficial for achieving low terminal inductance. Here again the lead frames are placed in a parallel orientation, so the magnetic fields of the DC current compensate each other, but where more advanced interconnect technologies may allow a vertical stack being connected directly with the system's DC-bus bar. Here, laminated lead frames placed on top of each other to reduce parasitic inductance with DC terminals 104 105 placed directly on top of each other. This enables a further reduction in inductance, but is more challenging to connect an external DC-busbar. b) Multi-layer lead frame having a thick-layer paste and having an insulator

A further preferred design variant consists in applying to a power-electronics circuit, by means of a DCB substrate, additional electrically conducting layers of a thick-layer paste that are electrically insulated relative to the upper DCB copper layer. The conductor tracks of the DCB copper layer and the conductor tracks of the thick-layer paste are arranged such that, like as in the previously mentioned exemplary embodiment, they make possible an anti- parallel power supply. Fig. 5 shows a power module 10, a first electrically insulating ceramic layer 30a of a DBC arranged between the upper copper layer 40a of a DBC and the lower layer and, arranged on the upper copper layer 40a of the DBC a power semiconductor 70. On the upper copper layer 40a of the DBC, a further electrically insulating layer 50a is arranged on which a further electrically conducting copper layer 60a is positioned such that (as far as possible) an anti- parallel power supply is possible. The conducting copper layer 60a may be applied as a solid metallic body or as a paste which is subsequently dried. A base plate as well as terminals are not shown.

Claims

1. A power module having at least two mutually electrically insulated layers arranged one on top of the other of conductor tracks conducting anti-parallel currents.

2. The power module according to Claim 1, characterized in that the conductor tracks are formed by lead frames.

3. The power module according to one of the preceding claims, characterized in that the conductor tracks outside of the power module form mutually electrically insulated outside terminals conducting anti-parallel currents that are arranged one on top of the other.

4. The power module according to Claim 1, characterized in that the one conductor track is the copper foil of a DCB power substrate and the second conductor track is formed from a thick-layer paste that is applied to an electrically insulating layer applied on the copper foil of the DCB power substrate.

5. The power module according to one of the preceding claims, characterized in that a first conductor track is arranged on a first electrically insulating layer that is arranged on a base plate.

6. The power module according to Claim 5, characterized in that a second conductor track is arranged on a second electrically insulating layer that is arranged on the first conductor track.

7. The power module according to one of the preceding claims, characterized in that the electric insulation is effected by a thermally conductive material. The power module according to one of the preceding claims, characterized in that the electric insulation is effected by a plastic and/or a ceramic and/or an inorganic cement material.