WO2018006686A1 - Method, apparatus and device for optimizing time synchronization between communication network devices - Google Patents

Abstract

The disclosure relates to a method, apparatus and device for optimizing time synchronization between communication network devices. The method comprises: acquiring a first message transmitted to a second device by a main control board of a first device; adding, in the first message, a first time difference compensation value for the first message to be transmitted from a line card processing chip of the first device to a line card port so as to obtain a second message; sending the second message to the second device; obtaining a third message returned by the second device after receiving the second message, wherein the third message records a time difference compensation value for the second message to be transmitted between a line card processing chip of the second device to a line card port after the second device receives the second message; adding, in the third message, a fourth time difference compensation value for the third message to be transmitted from the line card port of the first device to the line card processing chip so as to obtain a fourth message; and according to the fourth message, calculating a delay time of message transmission between the first device and the second device. The disclosure realizes precise time synchronization between communication network devices, and satisfies delay jitter requirements of the devices for time synchronization switching in a complex network environment.

Description

Method, device and device for optimizing time synchronization between communication network devices Technical field

The present disclosure relates to the field of network communication technologies, and in particular, to a method, an apparatus, and a device for optimizing time synchronization between communication network devices.

Background technique

PTP (Precision Time Protocol) is a master-slave synchronization system that uses the master-slave clock to encode time information and utilizes network symmetry and delay measurement techniques to synchronize master-slave time. During the synchronization process of the system, the master clock periodically issues the PTP time synchronization protocol and time information, and receives the timestamp information sent by the master clock port from the clock port, and the system calculates the time delay of the master-slave line and the master-slave time difference, and The time difference is used to adjust the local time so that the slave time is kept at the same frequency and phase as the master time.

Actually, when the time synchronization function is implemented, the delay may occur due to the transmission of the signal on the line, and the device may not be able to measure the delay of the line, and the delay compensation needs to be manually performed. At this point, the device needs to support the delay compensation function of various interfaces. Moreover, when there may be two time sources in the network, the device needs to support the automatic tracking of the standby time source when the primary time source fails. In addition, in the ring network or wireless mesh network Mesh network structure, the device needs to support tracking the time source from different line directions, and can automatically switch to other directions when the current tracking direction fails. For example, 16 device switching requires a phase jitter requirement of less than +/- 200 ns.

In the related art, when a PTP protocol packet of a different type of card and a different chip is processed by a different type of card, the delay of the delay compensation processing of the time information packet is affected. The delay jitter that causes the same time source to track from different line directions is very large, so the delay jitter requirement of tracking the same time source from different line directions cannot be met.

Summary of the invention

The technical problem to be solved by the present disclosure is to provide a method, a device and a device for optimizing time synchronization between communication network devices, which are used to solve the problem that the device cannot meet the delay jitter requirement of time synchronization switching in a complex networking environment in the related art. .

In order to solve the above technical problem, an embodiment of the present disclosure provides a method for optimizing time synchronization between communication network devices, which is applied to a first device, including:

And acquiring, by the first control board of the first device, a first packet that is sent to the second device, where the first packet is recorded with the first time information when the first packet is created;

Adding, in the first packet, a first time difference compensation value that is sent from the line card processing chip of the first device to the line card port, to obtain a second packet;

Sending the second packet to the second device;

Obtaining, by the second device, a third packet returned after receiving the second packet, where the third packet is recorded a second time difference compensation value and a third time difference compensation value transmitted between the line card processing chip of the second device and the line card port after the second device receives the second message;

Adding, in the third packet, a fourth time difference compensation value that is transmitted from the line card port of the first device to the line card processing chip, to obtain a fourth message;

And calculating, according to the fourth packet, a delay time for packet transmission between the first device and the second device.

The second time difference compensation value is a time difference compensation value that is transmitted from the line card port of the second device to the line card processing chip, where the second message added in the second message is sent;

The third time difference compensation value is the line card processing chip added from the second device in the response message fed back after the second control device obtains the second message by the second device. The time difference offset value transmitted to the line card port.

The first time information includes: a first timestamp of the main control board and a first physical clock frequency when the first packet for frequency synchronization is created on the main control board of the first device;

Recording, in the first packet, the second physical clock frequency of the line card processing chip when the first packet is transmitted from the main control board to the line card processing chip of the first device;

When the second packet is recorded from the line card port of the second device to the line card processing chip of the second device, the third physical clock of the line card processing chip is recorded a second timestamp and a fourth physical clock frequency of the main control board when the second message is transmitted from the line card processing chip of the second device to the main control board of the second device;

The third message is also recorded in the third time of the main control board when the main control board of the second device creates the response message generated by the second message on the main control board. And a fifth physical clock frequency; when the response message is transmitted from the main control board of the second device to the line card processing chip of the second device, the line card processes the sixth physical clock frequency of the chip;

The fourth message is further recorded when the third message is transmitted from the line card port of the first device to the line card processing chip of the first device, and the seventh physical clock of the line card processing chip a frequency; a fourth timestamp of the main control board and an eighth physical clock frequency when the fourth message is transmitted from the line card processing chip to the main control board of the first device.

The step of calculating a delay time of packet transmission between the first device and the second device according to the fourth packet includes:

Obtaining, according to the first physical clock frequency and the second physical clock frequency, the first transmission of the first packet from the main control board of the first device to the line card processing chip of the first device time;

Obtaining, according to the third physical clock frequency and the fourth physical clock frequency, the second transmission of the second packet from the line card processing chip of the second device to the main control board of the second device time;

Obtaining, according to the fifth physical clock frequency and the sixth physical clock frequency, a third transmission time of the response message transmitted from the main control board of the second device to the line card processing chip of the second device;

And obtaining, according to the seven physical clock frequencies and the eighth physical clock frequency, a fourth transmission time of the fourth packet from the line card processing chip of the first device to the main control board of the first device;

Determining, according to the first timestamp, the second timestamp, the third timestamp, the fourth timestamp, the first transmission time, the second transmission time, the third transmission time, the fourth transmission time, the first time difference compensation value, The two-time difference compensation value, the third time difference compensation value, and the fourth time difference compensation value are calculated by a preset algorithm to obtain a delay time of message transmission between the first device and the second device.

The first timestamp, the second timestamp, the third timestamp, the fourth timestamp, the first transmission time, the second transmission time, the third transmission time, the fourth transmission time, and the first time difference The step of calculating the delay time of the message transmission between the first device and the second device by using a preset algorithm includes: a compensation value, a second time difference compensation value, a third time difference compensation value, and a fourth time difference compensation value; :

According to the formula Delay=[((T ₄ -N ₄ -t ₄ )-(T ₁ +N ₁ +t ₁ ))+((T ₃ +N ₃ +t ₃ )-(T ₂ -N ₂ -t ₂ ))] ÷ 2, calculating a delay time of message transmission between the first device and the second device;

Delay represents a delay time for the message to be transmitted between the first device and the second device; T _{1 is} represented as the first timestamp; and T _{2 is} represented as the second timestamp ; T ₃ is represented as a third time stamp; T ₄ represents said fourth time stamp; N ₁ is expressed as the first transmission time; N ₂ of the second transmission time is represented; N ₃ is represented by a third transmission time; N _{4 is} represented as the fourth transmission time; t _{1 is} represented as the first time difference compensation value; t _{2 is} represented as the second time difference compensation value; t _{3 is} represented as the third time difference The compensation value; t _{4 is} expressed as the fourth time difference compensation value.

The embodiment of the present disclosure further provides an apparatus for optimizing time synchronization between communication network devices, including:

a first acquiring module, configured to acquire a first packet that is transmitted by the main control board of the first device to the second device, where the first packet is recorded with the first time information when the first packet is created;

The first processing module is configured to add, in the first packet, a first time difference compensation value that is sent from the line card processing chip of the first device to the line card port, to obtain a second message;

a sending module, configured to send the second packet to the second device;

a second acquiring module, configured to obtain a third packet that is returned after the second device receives the second packet, where the second packet records that the second device receives the second packet a second time difference compensation value and a third time difference compensation value transmitted between the line card processing chip of the second device and the line card port;

a second processing module, configured to add, in the third packet, a fourth time difference compensation value that is sent from the line card port of the first device to the line card processing chip, to obtain a fourth message;

The calculating module is configured to calculate, according to the fourth packet, a delay time for packet transmission between the first device and the second device.

The embodiment of the present disclosure further provides a first device, including: an apparatus for optimizing time synchronization between communication network devices as described in the foregoing embodiments.

The embodiment of the present disclosure further provides an optimization method for time synchronization between communication network devices, which is applied to a second device, and the method includes:

Receiving a second packet sent by the first device;

Adding, in the second packet, the second packet from the line card port of the second device to the line card processing core a second time difference compensation value of the slice, and transmitting the second message to the main control board of the second device;

Receiving, by the main control board, a response message that is fed back after the second packet;

And adding, in the response packet, a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port, to obtain a third message;

Transmitting the third packet to the first device by using a line card port of the second device.

After the first packet of the first device is recorded in the second packet, the first packet is added to the line of the first device in the first packet. The first time difference compensation value that the card processing chip transmits to the line card port.

The embodiment of the present disclosure further provides an apparatus for optimizing time synchronization between communication network devices, including:

The first receiving module is configured to receive the second packet sent by the first device;

a third processing module, configured to add, in the second packet, a second time difference compensation value that is sent from the line card port of the second device to the line card processing chip, and the second report is Transmitting to the main control board of the second device;

a second receiving module, configured to receive a response message that is received by the main control board after obtaining the second packet;

The fourth processing module is configured to add a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port in the response message, to obtain a third message;

And a transmission module, configured to transmit the third packet to the first device by using a line card port of the second device.

The embodiment of the present disclosure further provides a second device, including: an apparatus for optimizing time synchronization between communication network devices as described in the foregoing embodiments.

The embodiment of the present disclosure further provides a storage medium, configured to store program code, where the program code is used to perform an optimization method for time synchronization between communication network devices provided by any of the above embodiments.

The beneficial effects of the above technical solutions of the present disclosure are as follows:

In the above solution of the present disclosure, when the message is transmitted from the line card processing chip of the device to the line card port or from the line card port of the device to the line card processing chip, the time difference compensation value is added in the message, and the message is reduced. The delay error during transmission between communication network devices can realize accurate time synchronization between communication network devices and meet the delay jitter requirements of time synchronization switching of devices in complex networking environments.

DRAWINGS

1 is a flow chart showing the basic steps of a method for optimizing time synchronization between communication network devices according to an embodiment of the present disclosure;

2 is a schematic structural diagram of a device for optimizing time synchronization between communication network devices according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a packet sending and receiving path of a single device;

4 is a schematic diagram of a packet transmission delay between devices;

FIG. 5 is a flowchart of basic steps of a method for optimizing time synchronization between communication network devices according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of another apparatus for optimizing time synchronization between communication network devices according to an embodiment of the present disclosure;

FIG. 7 is a timing diagram of packet time delay optimization according to an embodiment of the present disclosure.

detailed description

The technical problems, the technical solutions, and the advantages of the present invention will be more clearly described in conjunction with the accompanying drawings and specific embodiments.

The present disclosure is directed to the problem that the device in the related art cannot meet the delay jitter requirement of time synchronization switching in a complex networking environment, and provides an optimization method for time synchronization between communication network devices, which reduces the transmission of packets between communication network devices. The delay error enables accurate time synchronization between communication network devices and meets the delay jitter requirements of time synchronization switching of devices in complex networking environments.

First embodiment

As shown in FIG. 1 , an embodiment of the present disclosure provides a method for optimizing time synchronization between communication network devices, including:

Step 11: Acquire a first packet that is sent by the main control board of the first device to the second device, where the first packet is recorded with the first time information when the first packet is created.

It should be noted that the central processing unit CPU on the main control board of the first device is responsible for maintaining the 1588 state machine, running the 1588 protocol and the 1588 loop algorithm, and reading the side-mounted FPGA (Field-Programmable Gate Array). ) The timestamp of the collection.

It should be noted that the timestamp is usually a sequence of characters that uniquely identifies the time of a certain moment.

Here, when the side-mounted FPGA provides a time stamp for frequency recovery, the counter is not time-stamped, and there is no requirement for the start time. That is, when the device is powered on, the default time issued by the timestamp counter can be uniformly used. When the frequency is restored, the clock provided by the timestamp counter is counted.

Here, the 1588 protocol is an accurate time synchronization protocol. Two types of packets, event packets and general messages are defined in the 1588 protocol. The event packet time concept packet is marked with an accurate timestamp when it enters and exits the device port. The PTP calculates the link delay based on the timestamp carried in the event packet. The event message contains the following four types: Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. Here, the first packet is an event packet.

The 1588 loop algorithm enables high-precision time synchronization calculations.

Step 12: Add a first time difference compensation value that is transmitted from the line card processing chip of the first device to the line card port in the first packet, to obtain a second packet.

It should be noted that the time difference compensation value described in the embodiment of the present disclosure can be obtained by manual compensation, and the time difference compensation value is added to the corresponding field of the message. Here, the manual compensation obtains the time difference compensation value, that is, the oscilloscope measures the transmission time of the message from the line card processing chip of the device to the line card port or from the line card port of the device to the line card processing chip, and the measured time is measured. A large amount of time data is averaged to obtain a time difference compensation value.

Of course, the time difference compensation value can also be obtained in real time through the PTP system.

Step 13, the second packet is sent to the second device;

It should be noted that the second message includes time information recorded in the first message. The second message is sent from the line card port of the first device to the line card port of the second device.

Step 14: Obtain a third packet returned by the second device after receiving the second packet, where the third packet records that the second device receives the second packet, where Line card processing chip and line card end of the second device a second time difference compensation value and a third time difference compensation value transmitted between the ports;

It should be noted that the third packet includes time information recorded in the first packet and the second packet.

Step 15: Add a fourth time difference compensation value that is transmitted from the line card port of the first device to the line card processing chip in the third message, to obtain a fourth message;

Here, the line card processing chip may be a PHY (Physical Layer) chip, and the PHY chip generally refers to a chip that interfaces with an external signal.

Step 16: Calculate, according to the fourth packet, a delay time for packet transmission between the first device and the second device.

It should be noted that the fourth packet includes time information in the first packet, the second packet, and the third packet.

Exemplarily, the second time difference compensation value is a time difference compensation value that is sent from the line card port of the second device to the line card processing chip, where the second message added in the second message is sent;

The third time difference compensation value is the line card processing chip added from the second device in the response message fed back after the second control device obtains the second message by the second device. The time difference offset value transmitted to the line card port.

Exemplarily, the first time information includes: a first timestamp of the main control board and a first physical clock when the first message for frequency synchronization is created on the main control board of the first device frequency.

Recording, in the first packet, the second physical clock frequency of the line card processing chip when the first packet is transmitted from the main control board to the line card processing chip of the first device;

When the second packet is recorded from the line card port of the second device to the line card processing chip of the second device, the third physical clock of the line card processing chip is recorded a second timestamp and a fourth physical clock frequency of the main control board when the second message is transmitted from the line card processing chip of the second device to the main control board of the second device;

The third message is also recorded in the third time of the main control board when the main control board of the second device creates the response message generated by the second message on the main control board. And a fifth physical clock frequency; when the response message is transmitted from the main control board of the second device to the line card processing chip of the second device, the line card processes the sixth physical clock frequency of the chip;

The fourth message is further recorded when the third message is transmitted from the line card port of the first device to the line card processing chip of the first device, and the seventh physical clock of the line card processing chip a frequency; a fourth timestamp of the main control board and an eighth physical clock frequency when the fourth message is transmitted from the line card processing chip to the main control board of the first device.

It should be noted that the timestamps on different devices are different because the default time of the device's timestamp counter is different. Therefore, the timestamps on different devices cannot be calculated. The time stamp of the same device can be calculated.

It should be noted that, during the transmission of the packet, the time information of the packet passing through the internal components of the device is filled in the corresponding field of the packet. That is, the message in the embodiment of the present disclosure may have a fixed format.

Preferably, the step 16 described in the embodiment of the present disclosure may further include:

Step 161: Obtain the first report according to the first physical clock frequency and the second physical clock frequency. Transmitting from the main control board of the first device to the first transfer time of the line card processing chip of the first device;

Here, the second physical clock frequency of the line card processing chip of the first device is subtracted from the first physical clock frequency of the main control board of the first device, and the first packet is transmitted from the main control board of the first device to The physical clock frequency difference of the line card processing chip of the first device. Here, the jitter time of each clock frequency offset is 1/125 ms, that is, the time interval of 8 ns, and the transmission time difference from the main control board to the line card processing chip is a CF domain difference, that is, the first message is from the first The first transmission time of the main control board of the device transmitted to the line card processing chip of the first device is that the first message is transmitted from the main control board of the first device to the line card processing chip of the first device The physical clock frequency difference is multiplied by the beat time of each clock offset.

Step 162: According to the third physical clock frequency and the fourth physical clock frequency, the second packet is transmitted from the line card processing chip of the second device to the main control board of the second device. Second transfer time;

It should be noted that the second transmission time is the difference between the fourth physical clock frequency of the line card processing chip of the second device minus the third physical clock frequency of the main control board of the second device multiplied by the frequency offset of each clock. The result of the beating time.

Step 163: According to the fifth physical clock frequency and the sixth physical clock frequency, obtain a third transmission of the response message from the main control board of the second device to the line card processing chip of the second device. time;

It should be noted that the third transmission time is the sixth physical clock frequency of the main control board of the second device minus the difference of the fifth physical clock frequency of the line card processing chip of the second device multiplied by the frequency offset of each clock. The result of the beating time.

Step 164: According to the seven physical clock frequencies and the eighth physical clock frequency, obtain the fourth packet from the line card processing chip of the first device to the fourth control panel of the first device. Transfer time

It should be noted that the fourth transmission time is the eighth physical clock frequency of the line card processing chip of the first device minus the difference of the seven physical clock frequencies of the main control board of the first device multiplied by the jitter of each clock frequency offset. The result of time.

Step 165: According to the first timestamp, the second timestamp, the third timestamp, the fourth timestamp, the first transmission time, the second transmission time, the third transmission time, the fourth transmission time, and the first time difference compensation The value, the second time difference compensation value, the third time difference compensation value, and the fourth time difference compensation value are calculated by a preset algorithm to obtain a delay time of message transmission between the first device and the second device.

Here, preferably, the step 165 may further include:

Step 1651,

According to the formula Delay=[((T ₄ -N ₄ -t ₄ )-(T ₁ +N ₁ +t ₁ ))+((T ₃ +N ₃ +t ₃ )-(T ₂ -N ₂ -t ₂ ))] ÷ 2, calculating a delay time of message transmission between the first device and the second device;

Delay represents a delay time for the message to be transmitted between the first device and the second device; T _{1 is} represented as the first timestamp; and T _{2 is} represented as the second timestamp ; T _{3 is} represented as the third time stamp; T _{4 is} represented as the fourth time stamp; N _{1 is} represented as the first transmission time; N _{2 is} represented as the second transmission time; N _{3 is} represented as a third transmission time; N _{4 is} represented as the fourth transmission time; t _{1 is} represented as the first time difference compensation value; t _{2 is} represented as the second time difference compensation value; t _{3 is} represented as the third time difference The compensation value; t _{4 is} expressed as the fourth time difference compensation value.

It should be noted that for the delay time of multiple devices, the above method can be used to obtain the delay between the two devices. Time, and finally do summation calculation.

The method for optimizing time synchronization between communication network devices provided by the embodiments of the present disclosure is used in a message when a message is transmitted from a line card processing chip of the device to a line card port or from a line card port of the device to a line card processing chip. The time difference compensation value is added to reduce the delay error when the message is transmitted between the communication network devices, so that accurate time synchronization between the communication network devices can be realized, and the delay jitter requirement of the time synchronization switching of the device in the complex networking environment can be met.

Second embodiment

As shown in FIG. 2, an embodiment of the present disclosure further provides an apparatus for optimizing time synchronization between communication network devices, including:

The first obtaining module 21 is configured to acquire a first packet that is sent by the main control board of the first device to the second device, where the first packet is recorded with the first time information when the first packet is created. ;

It should be noted that, as shown in FIG. 3, it is a schematic diagram of a packet transmission and reception path of a single device. The central processing unit CPU on the main control board of the first device is responsible for maintaining the 1588 state machine, running the 1588 protocol and the 1588 loop algorithm, and reading the time stamp collected by the Field-Programmable Gate Array (Field-Programmable Gate Array). .

It should be noted that the timestamp is usually a sequence of characters that uniquely identifies the time of a certain moment.

Here, when the side-mounted FPGA provides a time stamp for frequency recovery, the counter is not time-stamped, and there is no requirement for the start time. That is, when the device is powered on, the default time issued by the timestamp counter can be uniformly used. When the frequency is restored, the clock provided by the timestamp counter is counted.

Here, the 1588 protocol is an accurate time synchronization protocol. Two types of packets, event packets and general messages are defined in the 1588 protocol. The event packet time concept packet is marked with an accurate timestamp when it enters and exits the device port. The PTP calculates the link delay based on the timestamp carried in the event packet. The event message contains the following four types: Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. Here, the first packet is an event packet.

The 1588 loop algorithm enables high-precision time synchronization calculations.

The first processing module 22 is configured to add, in the first packet, a first time difference compensation value that is sent from the line card processing chip of the first device to the line card port, to obtain a second message;

It should be noted that the time difference compensation value described in the embodiment of the present disclosure can be obtained by manual compensation, and the time difference compensation value is added to the corresponding field of the message. Here, the manual compensation obtains the time difference compensation value, that is, the oscilloscope measures the transmission time of the message from the line card processing chip of the device to the line card port or from the line card port of the device to the line card processing chip, and the measured time is measured. A large amount of time data is averaged to obtain a time difference compensation value.

Of course, the time difference compensation value can also be obtained in real time through the PTP system.

The sending module 23 is configured to send the second packet to the second device;

It should be noted that the second message includes time information recorded in the first message. The second message is sent from the line card port of the first device to the line card port of the second device.

The second obtaining module 24 is configured to obtain a third packet that is returned after the second device receives the second packet, where the second packet records that the second device receives the second packet a second time difference compensation value and a third time difference compensation value transmitted between the line card processing chip of the second device and the line card port;

It should be noted that the third packet includes time information recorded in the first packet and the second packet.

The second processing module 25 is configured to add, in the third packet, a fourth time difference compensation value that is sent from the line card port of the first device to the line card processing chip, to obtain a fourth message;

Here, the line card processing chip may be a PHY (Physical Layer) chip, and the PHY chip generally refers to a chip that interfaces with an external signal.

The calculating module 26 is configured to calculate, according to the fourth packet, a delay time of message transmission between the first device and the second device.

It should be noted that the fourth packet includes time information in the first packet, the second packet, and the third packet.

Here, as shown in FIG. 4, it is a schematic diagram of packet transmission delay between devices. That is to say, the calculation module 26 calculates the single link delay time of the line card port of the first device to the line card port of the second device.

Exemplarily, the second time difference compensation value is a time difference compensation value that is sent from the line card port of the second device to the line card processing chip, where the second message added in the second message is sent;

The third time difference compensation value is the line card processing chip added from the second device in the response message fed back after the second control device obtains the second message by the second device. The time difference offset value transmitted to the line card port.

Exemplarily, the first time information includes: a first timestamp of the main control board and a first physical clock when the first message for frequency synchronization is created on the main control board of the first device frequency.

Recording, in the first packet, the second physical clock frequency of the line card processing chip when the first packet is transmitted from the main control board to the line card processing chip of the first device;

When the second packet is recorded from the line card port of the second device to the line card processing chip of the second device, the third physical clock of the line card processing chip is recorded a second timestamp and a fourth physical clock frequency of the main control board when the second message is transmitted from the line card processing chip of the second device to the main control board of the second device;

The third message is also recorded in the third time of the main control board when the main control board of the second device creates the response message generated by the second message on the main control board. And a fifth physical clock frequency; when the response message is transmitted from the main control board of the second device to the line card processing chip of the second device, the line card processes the sixth physical clock frequency of the chip;

The fourth message is further recorded when the third message is transmitted from the line card port of the first device to the line card processing chip of the first device, and the seventh physical clock of the line card processing chip a frequency; a fourth timestamp of the main control board and an eighth physical clock frequency when the fourth message is transmitted from the line card processing chip to the main control board of the first device.

It should be noted that the timestamps on different devices are different because the default time of the device's timestamp counter is different. Therefore, the timestamps on different devices cannot be calculated. The time stamp of the same device can be calculated.

It should be noted that, during the transmission of the packet, the time information of the packet passing through the internal components of the device is filled in the corresponding field of the packet. That is, the message in the embodiment of the present disclosure may have a fixed format.

For example, the calculation module 26 in the embodiment of the present disclosure may further include:

a first calculating unit, configured to obtain according to the first physical clock frequency and the second physical clock frequency Transmitting, by the first control device of the first device, a first transmission time of the line card processing chip of the first device;

Here, the second physical clock frequency of the line card processing chip of the first device is subtracted from the first physical clock frequency of the main control board of the first device, and the first packet is transmitted from the main control board of the first device to The physical clock frequency difference of the line card processing chip of the first device. Here, the jitter time of each clock frequency offset is 1/125 ms, that is, the time interval of 8 ns, and the transmission time difference from the main control board to the line card processing chip is a CF domain difference, that is, the first message is from the first The first transmission time of the main control board of the device transmitted to the line card processing chip of the first device is that the first message is transmitted from the main control board of the first device to the line card processing chip of the first device The physical clock frequency difference is multiplied by the beat time of each clock offset.

a second calculating unit, configured to transmit, according to the third physical clock frequency and the fourth physical clock frequency, the second packet from the line card processing chip of the second device to the second device The second transmission time of the main control board;

It should be noted that the second transmission time is the difference between the fourth physical clock frequency of the line card processing chip of the second device minus the third physical clock frequency of the main control board of the second device multiplied by the frequency offset of each clock. The result of the beating time.

a third calculating unit, configured to: according to the fifth physical clock frequency and the sixth physical clock frequency, obtain the line card processing chip that is sent from the main control board of the second device to the second device Third transmission time;

It should be noted that the third transmission time is the sixth physical clock frequency of the main control board of the second device minus the difference of the fifth physical clock frequency of the line card processing chip of the second device multiplied by the frequency offset of each clock. The result of the beating time.

a fourth calculating unit, configured to obtain, according to the seven physical clock frequencies and the eighth physical clock frequency, the fourth packet from the line card processing chip of the first device to the master of the first device The fourth transfer time of the board;

It should be noted that the fourth transmission time is the eighth physical clock frequency of the line card processing chip of the first device minus the difference of the seven physical clock frequencies of the main control board of the first device multiplied by the jitter of each clock frequency offset. The result of time.

a fifth calculating unit, configured to be according to the first timestamp, the second timestamp, the third timestamp, the fourth timestamp, the first transmission time, the second transmission time, the third transmission time, the fourth transmission time, a first time difference compensation value, a second time difference compensation value, a third time difference compensation value, and a fourth time difference compensation value, and calculating, by using a preset algorithm, a delay time of message transmission between the first device and the second device .

Here, the calculation unit can be used according to the formula Delay=[((T ₄ -N ₄ -t ₄ )-(T ₁ +N ₁ +t ₁ ))+((T ₃ +N ₃ +t ₃ )-((T ₃ +N ₃ +t ₃ )-( T ₂ -N ₂ -t ₂ ))]÷2, calculating a delay time for message transmission between the first device and the second device;

Delay represents a delay time for the message to be transmitted between the first device and the second device; T _{1 is} represented as the first timestamp; and T _{2 is} represented as the second timestamp ; T _{3 is} represented as the third time stamp; T _{4 is} represented as the fourth time stamp; N _{1 is} represented as the first transmission time; N _{2 is} represented as the second transmission time; N _{3 is} represented as a third transmission time; N _{4 is} represented as the fourth transmission time; t _{1 is} represented as the first time difference compensation value; t _{2 is} represented as the second time difference compensation value; t _{3 is} represented as the third time difference The compensation value; t _{4 is} expressed as the fourth time difference compensation value.

The embodiment of the present disclosure further provides a first device, which is a communication network device, and includes: an apparatus for optimizing time synchronization between communication network devices as described in the foregoing embodiments.

The device for optimizing time synchronization between communication network devices provided by the embodiments of the present disclosure is used in a message when a message is transmitted from a line card processing chip of the device to a line card port or from a line card port of the device to a line card processing chip. The time difference compensation value is added to reduce the delay error when the message is transmitted between the communication network devices, so that accurate time synchronization between the communication network devices can be realized, and the delay jitter requirement of the time synchronization switching of the device in the complex networking environment can be met.

Third embodiment

As shown in FIG. 5, an embodiment of the present disclosure further provides an optimization method for time synchronization between communication network devices, which is applied to a second device, including:

Step 31: Receive a second packet sent by the first device.

It should be noted here that the second message records the time information of the message when it is transmitted internally by the first device. For example, the first message created by the main control board of the first device is transmitted at a first time difference offset value from the line card processing chip of the first device to the line card port.

Step 32: Add, in the second packet, a second time difference compensation value that is sent from the line card port of the second device to the line card processing chip, and transmit the second message. To the main control board of the second device;

It should be noted that the time difference compensation value described in the embodiment of the present disclosure can be obtained by manual compensation, and the time difference compensation value is added to the corresponding field of the message. Here, the manual compensation obtains the time difference compensation value, that is, the oscilloscope measures the transmission time of the message from the line card processing chip of the device to the line card port or from the line card port of the device to the line card processing chip, and the measured time is measured. A large amount of time data is averaged to obtain a time difference compensation value.

Of course, the time difference compensation value can also be obtained in real time through the PTP system.

Step 33: Receive a response message that is sent back by the main control board after obtaining the second packet.

It should be noted that the response message is generated by the main control board according to the second message, and the response message includes the time information recorded in the second message.

Step 34: Add a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port in the response message, to obtain a third message.

It should be noted that the third packet includes a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port, and includes a response message. Other time information recorded in .

Step 35: The third packet is transmitted to the first device by using a line card port of the second device.

Illustratively, after the first packet of the first device is configured to create the first packet, the first packet is added to the first packet from the first device. The line card handles the first time difference offset value transmitted by the chip to the line card port.

The method for optimizing time synchronization between communication network devices provided by the embodiments of the present disclosure is used in a message when a message is transmitted from a line card processing chip of the device to a line card port or from a line card port of the device to a line card processing chip. The time difference compensation value is added to provide a calculation parameter, so that the delay error rate of the message transmitted between the communication network devices is reduced, thereby achieving accurate time synchronization between the communication network devices, and meeting the time synchronization switching of the device in a complex networking environment. Delay Jitter requirements.

Fourth embodiment

As shown in FIG. 6, the embodiment of the present disclosure further provides an apparatus for optimizing time synchronization between communication network devices, including:

The first receiving module 41 is configured to receive the second packet sent by the first device;

It should be noted here that the second message records the time information of the message when it is transmitted internally by the first device. For example, the first message created by the main control board of the first device is transmitted at a first time difference offset value from the line card processing chip of the first device to the line card port.

The third processing module 42 is configured to add, in the second packet, a second time difference compensation value that is sent from the line card port of the second device to the line card processing chip, and the second Transmitting the message to the main control board of the second device;

It should be noted that the time difference compensation value described in the embodiment of the present disclosure can be obtained by manual compensation, and the time difference compensation value is added to the corresponding field of the message. Here, the manual compensation obtains the time difference compensation value, that is, the oscilloscope measures the transmission time of the message from the line card processing chip of the device to the line card port or from the line card port of the device to the line card processing chip, and the measured time is measured. A large amount of time data is averaged to obtain a time difference compensation value.

Of course, the time difference compensation value can also be obtained in real time through the PTP system.

The second receiving module 43 is configured to receive a response message that is sent back by the main control board after obtaining the second packet;

It should be noted that the response message is generated by the main control board according to the second message, and the response message includes the time information recorded in the second message.

The fourth processing module 44 is configured to add a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port in the response message, to obtain a third message;

It should be noted that the third packet includes a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port, and includes a response message. Other time information recorded in .

The transmitting module 45 is configured to transmit the third packet to the first device by using a line card port of the second device.

Illustratively, after the first packet of the first device is configured to create the first packet, the first packet is added to the first packet from the first device. The line card handles the first time difference offset value transmitted by the chip to the line card port.

The embodiment of the present disclosure further provides a second device, which is a communication network device, and includes: an apparatus for optimizing time synchronization between communication network devices as described in the foregoing embodiment.

The device for optimizing time synchronization between communication network devices provided by the embodiments of the present disclosure is used in a message when a message is transmitted from a line card processing chip of the device to a line card port or from a line card port of the device to a line card processing chip. The time difference compensation value is added to provide a calculation parameter, so that the delay error rate of the message transmitted between the communication network devices is reduced, thereby achieving accurate time synchronization between the communication network devices, and meeting the time synchronization switching of the device in a complex networking environment. Delay jitter requirements.

Fifth embodiment

As shown in FIG. 7, the message time delay optimization map of the embodiment of the present disclosure. The following figure illustrates the flow of messages as they travel between communication network devices.

Step 101: Perform frequency synchronization on the main control board and the line card of the same device.

Here, the embodiment of the present disclosure takes the first device and the second device as an example. The first device sends the request as a delay, and the second device acts as the delay responder.

Step 102: The first packet of the first device is configured to form a first packet on the main control board, and the timestamp T1 and the first physical clock frequency of the moment are recorded in the first packet.

Here, the first packet is also a PTP packet, that is, an event packet. The first packet is configured on the 1588 related module of the main control board.

Step 103: After forwarding the first packet from the main control board to the line card processing chip, record the second physical clock frequency of the line card processing chip at the moment in the first message.

It should be noted that, in this step, the first packet is forwarded from the main control board to the line card processing chip, the line card processing chip is a line card FPGA module; and the second physical clock frequency of the line card processing chip is acquired, the line card The processing chip is a PHY chip.

Step 104: Add a first time difference compensation value t1 to the line card port after processing the first message by the line card processing chip, to obtain a second message.

Step 105: Send the second message to the second device.

It should be noted that the second packet includes time information of the first packet.

Step 106: Add a second time difference compensation value t2 that the line card processing chip receives the second message after receiving the second packet by the line card port of the second device.

Step 107: Record the third physical clock frequency of the line card processing chip at the time when the line card processing chip of the second device receives the second message.

Step 108: When the second packet is transmitted to the main control board by the line card processing chip of the second device, the second device acquires the second timestamp T2 and the fourth physical clock frequency of the main control board at the moment, and records the In the second message.

Here, for example, the second message passes through the line card FPGA module of the second device to the 1588 related module of the main control board.

Step 109: The main control board of the second device forms a response packet, and records the timestamp T3 and the fifth physical clock frequency of the main control board at the moment in the response message.

Here, for example, the 1588 related module of the main control board of the second device forms a response message according to the second message.

It should be noted that the response message includes time information recorded in the second message.

Step 110: After the response packet is forwarded from the main control board to the line card processing chip, the sixth physical clock frequency of the line card processing chip acquired at the moment is recorded in the response message.

Here, for example, the response message is forwarded from the main control board to the line card FPGA module, and the sixth physical clock frequency of the line card processing chip is obtained, and the line card processing chip is a PHY chip.

Step 111: Add a third time difference compensation to the line card port after the line card processing chip of the second device processes the response message. The value t3 gives a third message.

Step 112: Return the third message to the first device.

Here, the third message includes time information recorded in the response message.

Step 113: Add a fourth packet to the line card processing chip of the first device to receive a fourth time difference compensation value t4 of the third packet, to obtain a fourth packet.

Step 114: Record the seventh physical clock frequency of the line card processing chip at the time when the line card processing chip of the first device receives the third message.

Step 115: When the fourth packet passes the line card processing chip of the first device to the main control board, the first device acquires the fourth timestamp T4 and the eighth physical clock frequency of the main control board at the moment, and records the Four messages.

Here, the exemplary fourth message passes through the line card FPGA module of the first device to the 1588 related module of the main control board.

It should be noted that the fourth message includes the first message, the second message, and the time information recorded in the third message.

Step 116: Calculate the delay correction value.

Here, the delay correction value is the CF domain difference between the main control board and the line card processing chip plus the time difference compensation of the line card processing chip to the line card port, that is, N+t.

It should be noted that the CF domain difference between the main control board and the line card processing chip can be calculated by using the physical clock frequency recorded in the above steps. The calculation process is shown in the first embodiment, and is not described here.

Step 117: The second device calculates a delay time between the first device and the second device according to the formula, and the calculation formula is: Delay=[((T ₄ -N ₄ -t ₄ )-(T ₁ +N ₁ +t ₁ )) +((T ₃ +N ₃ +t ₃ )-(T ₂ -N ₂ -t ₂ ))]÷2.

Here, the calculated delay time is a single link delay time.

Delay represents a delay time for the message to be transmitted between the first device and the second device; T _{1 is} represented as the first timestamp; and T _{2 is} represented as the second timestamp ; T _{3 is} represented as the third time stamp; T _{4 is} represented as the fourth time stamp; N _{1 is} represented as the first transmission time; N _{2 is} represented as the second transmission time; N _{3 is} represented as said third transmission time; N ₄ is represented by said fourth transfer time; t ₁ represents a compensation value for said first time difference; t ₂ represents a compensation value for said second time difference; t ₃ represents said third time difference The compensation value; t _{4 is} expressed as the fourth time difference compensation value.

The above is a preferred embodiment of the present disclosure, and it should be noted that those skilled in the art can also make several improvements and refinements without departing from the principles of the present disclosure. It should be considered as the scope of protection of this disclosure.

Industrial applicability

The method and device for optimizing time synchronization between communication network devices provided by the embodiments of the present disclosure are reported when the message is transmitted from the line card processing chip of the device to the line card port or from the line card port of the device to the line card processing chip. In this paper, the time difference compensation value is added to reduce the delay error when the message is transmitted between communication network devices, so that accurate time synchronization between communication network devices can be realized, and the delay jitter requirement of time synchronization switching of the device in a complex networking environment can be met. .

Claims (12)

A method for optimizing time synchronization between communication network devices is applied to a first device, where the method includes: And acquiring, by the first control board of the first device, a first packet that is sent to the second device, where the first packet is recorded with the first time information when the first packet is created; Adding, in the first packet, a first time difference compensation value that is sent from the line card processing chip of the first device to the line card port, to obtain a second packet; Sending the second packet to the second device; Obtaining a third packet that is returned after the second device receives the second packet, where the third packet records that the second device receives the second packet, after the second packet a second time difference compensation value and a third time difference compensation value transmitted between the line card processing chip of the device and the line card port; Adding, in the third packet, a fourth time difference compensation value that is transmitted from the line card port of the first device to the line card processing chip, to obtain a fourth message; And calculating, according to the fourth packet, a delay time for packet transmission between the first device and the second device. The method for optimizing time synchronization between communication network devices according to claim 1, wherein the second time difference compensation value is the second message added in the second message from the second device The time difference compensation value of the line card port transmitted to the line card processing chip; The third time difference compensation value is the line card processing chip added from the second device in the response message fed back after the second control device obtains the second message by the second device. The time difference offset value transmitted to the line card port. The method for optimizing time synchronization between communication network devices according to claim 1, wherein the first time information comprises: when the first message for frequency synchronization is created on the main control board of the first device, a first timestamp of the main control board and a first physical clock frequency; Recording, in the first packet, the second physical clock frequency of the line card processing chip when the first packet is transmitted from the main control board to the line card processing chip of the first device; When the second packet is recorded from the line card port of the second device to the line card processing chip of the second device, the third physical clock of the line card processing chip is recorded a second timestamp and a fourth physical clock frequency of the main control board when the second message is transmitted from the line card processing chip of the second device to the main control board of the second device; The third message is also recorded in the third time of the main control board when the main control board of the second device creates the response message generated by the second message on the main control board. And a fifth physical clock frequency; when the response message is transmitted from the main control board of the second device to the line card processing chip of the second device, the line card processes the sixth physical clock frequency of the chip; The fourth message is further recorded when the third message is transmitted from the line card port of the first device to the line card processing chip of the first device, and the seventh physical clock of the line card processing chip Frequency; the fourth timestamp and the eighth physical clock frequency of the main control board when the fourth message is transmitted from the line card processing chip to the main control board of the first device rate. The method for optimizing the time synchronization between the communication network devices according to claim 3, wherein the calculating, according to the fourth packet, a delay time of packet transmission between the first device and the second device The steps include: Obtaining, according to the first physical clock frequency and the second physical clock frequency, the first transmission of the first packet from the main control board of the first device to the line card processing chip of the first device time; Obtaining, according to the third physical clock frequency and the fourth physical clock frequency, the second transmission of the second packet from the line card processing chip of the second device to the main control board of the second device time; Obtaining, according to the fifth physical clock frequency and the sixth physical clock frequency, a third transmission time of the response message transmitted from the main control board of the second device to the line card processing chip of the second device; And obtaining, according to the seven physical clock frequencies and the eighth physical clock frequency, a fourth transmission time of the fourth packet from the line card processing chip of the first device to the main control board of the first device; Determining, according to the first timestamp, the second timestamp, the third timestamp, the fourth timestamp, the first transmission time, the second transmission time, the third transmission time, the fourth transmission time, the first time difference compensation value, The two-time difference compensation value, the third time difference compensation value, and the fourth time difference compensation value are calculated by a preset algorithm to obtain a delay time of message transmission between the first device and the second device. The method for optimizing time synchronization between communication network devices according to claim 4, wherein said according to said first time stamp, second time stamp, third time stamp, fourth time stamp, first transmission time, The second transmission time, the third transmission time, the fourth transmission time, the first time difference compensation value, the second time difference compensation value, the third time difference compensation value, and the fourth time difference compensation value are calculated by a preset algorithm to obtain the first device and The step of delaying packet transmission between the second devices includes: According to the formula Delay=[((T ₄ -N ₄ -t ₄ )-(T ₁ +N ₁ +t ₁ ))+((T ₃ +N ₃ +t ₃ )-(T ₂ -N ₂ -t ₂ ))] ÷ 2, calculating a delay time of message transmission between the first device and the second device; Delay represents a delay time for the message to be transmitted between the first device and the second device; T _{1 is} represented as the first timestamp; and T _{2 is} represented as the second timestamp ; T _{3 is} represented as the third time stamp; T _{4 is} represented as the fourth time stamp; N _{1 is} represented as the first transmission time; N _{2 is} represented as the second transmission time; N _{3 is} represented as a third transmission time; N _{4 is} represented as the fourth transmission time; t _{1 is} represented as the first time difference compensation value; t _{2 is} represented as the second time difference compensation value; t _{3 is} represented as the third time difference The compensation value; t _{4 is} expressed as the fourth time difference compensation value. An apparatus for optimizing time synchronization between communication network devices, comprising: a first acquiring module, configured to acquire a first packet that is transmitted by the main control board of the first device to the second device, where the first packet is recorded with the first time information when the first packet is created; The first processing module is configured to add, in the first packet, a first time difference compensation value that is sent from the line card processing chip of the first device to the line card port, to obtain a second message; a sending module, configured to send the second packet to the second device; a second acquiring module, configured to obtain a third packet returned by the second device after receiving the second packet, where Recording, in the third packet, a second time difference compensation value and a third transmission between the line card processing chip of the second device and the line card port after the second device receives the second message Time difference compensation value; a second processing module, configured to add, in the third packet, a fourth time difference compensation value that is sent from the line card port of the first device to the line card processing chip, to obtain a fourth message; The calculating module is configured to calculate, according to the fourth packet, a delay time for packet transmission between the first device and the second device. A first device comprising: the apparatus for optimizing time synchronization between communication network devices according to claim 6. An optimization method for time synchronization between communication network devices is applied to a second device, where the method includes: Receiving a second packet sent by the first device; Adding, in the second packet, a second time difference compensation value that is transmitted from the line card port of the second device to the line card processing chip, and transmitting the second message to the The main control board of the second device; Receiving, by the main control board, a response message that is fed back after the second packet; And adding, in the response packet, a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port, to obtain a third message; Transmitting the third packet to the first device by using a line card port of the second device. The method for optimizing time synchronization between communication network devices according to claim 8, wherein the second message is recorded in the first message after the main control board of the first device creates the first message. The first time difference compensation value that the first message is transmitted from the line card processing chip of the first device to the line card port is added. An apparatus for optimizing time synchronization between communication network devices, comprising: The first receiving module is configured to receive the second packet sent by the first device; a third processing module, configured to add, in the second packet, a second time difference compensation value that is sent from the line card port of the second device to the line card processing chip, and the second report is Transmitting to the main control board of the second device; a second receiving module, configured to receive a response message that is received by the main control board after obtaining the second packet; The fourth processing module is configured to add a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port in the response message, to obtain a third message; And a transmission module, configured to transmit the third packet to the first device by using a line card port of the second device. A second device comprising: the apparatus for optimizing time synchronization between communication network devices according to claim 10. A storage medium arranged to store program code for performing an optimization method of time synchronization between communication network devices according to any one of claims 1 to 5 and 8 to 10.

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