WO2018004682A1

WO2018004682A1 - Schottky diodes using cmos technology

Info

Publication number: WO2018004682A1
Application number: PCT/US2016/040820
Authority: WO
Inventors: Domagoj Siprak
Original assignee: Intel IP Corp
Current assignee: Intel IP Corp
Priority date: 2016-07-01
Filing date: 2016-07-01
Publication date: 2018-01-04
Anticipated expiration: 2019-01-01

Abstract

A Schottky diode may be manufactured using complementary metal oxide semiconductor (CMOS) techniques. The Schottky diode may include a shallow trench isolation region confining/bounding the outer perimeter region of the Schottky diode, a ohmic contact patterned onto a doped implant region formed in a semiconductor substrate and a Schottky contact patterned onto the semiconductor substrate. The Schottky contact is spaced a distance from the doped implant region and a semiconductor separation region exists between the Schottky contact and the doped implant region.

Description

SCHOTTKY DIODES USING CMOS TECHNOLOGY

DOMAGOJ SlPRAK

TECHNICAL FIELD

The present disclosure relates to Schottky diodes formed using complementary metal oxide semiconductor (CMOS) technology.

BACKGROUND

Due to their favorable properties in high frequency applications, Schottky diodes have found widespread use in various radio frequency circuit applications. Despite the popularity and economic advantages of complementary metal oxide semiconductor (CMOS) silicon technology, the lossy nature of the silicon substrate has made the implementation of CMOS into full-scale microwave use relatively slow going. At higher frequencies, undesirable properties of silicon substrate begin to predominate.

Schottky diodes have multiple applications such as varactors (variable capacitance semiconductor devices), rectifiers, AC to DC converters; amplitude, power, and radiation sensors up to millimeter wavelength and terahertz (THz) frequencies; and voltage clamps (in ESD or other overvoltage protection circuits). Due to their majority carrier based transport, Schottky diodes avoid the large diffusion capacitance of PN-junction diodes, which can be beneficial as free-wheel diodes in DC to DC converters of power management units. The non-linearity of Schottky diodes permits their use in frequency multipliers used to generate millimeter wave frequencies. Compared to PN-junction diodes, Schottky diodes have several advantages, such as lower forward ON voltage, a consideration in voltage clamps, rectifiers, and AC-to-DC converters in low voltage CMOS and faster switching due to majority carrier transport avoiding a large diffusion capacitance.

BRIEF DESCRIPTION OF THE DRAWINGS

Features and advantages of various embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals designate like parts, and in which:

FIG. 1A provides a cross-sectional elevation of an illustrative Schottky diode executed using complementary metal oxide semiconductor (CMOS) technology, in accordance with at least one embodiment of the present disclosure;

FIG. IB provides a cross-sectional elevation of another illustrative Schottky diode executed using complementary metal oxide semiconductor (CMOS) technology, in accordance with at least one embodiment of the present disclosure;

FIG. 1C provides a cross-sectional elevation of another illustrative Schottky diode executed using complementary metal oxide semiconductor (CMOS) technology, in accordance with at least one embodiment of the present disclosure;

FIG. ID provides a cross-sectional elevation of another illustrative Schottky diode executed using complementary metal oxide semiconductor (CMOS) technology, in accordance with at least one embodiment of the present disclosure;

FIG. 2 provides a layout of an illustrative Schottky diode executed using CMOS technology, in accordance with at least one embodiment of the present disclosure;

FIG. 3 provides a layout of another illustrative Schottky diode executed using CMOS technology, in accordance with at least one embodiment of the present disclosure;

FIG 4 provides a graph that compares the Current/Voltage ( V) response of an illustrative Schottky diode with and without a shallow trench isolation (STI) region with the W response of a PN diode with and without an STI region, in accordance with at least one embodiment of the present disclosure;

FIG. 5 provides a logarithmic graph that compares the Current/Voltage (logl/V) response of an illustrative Schottky N-well diode and PN junction N-well diode without a shallow trench isolation (STI) region, in accordance with at least one embodiment of the present disclosure;

FIG. 6 provides a graph that compares the Capacitance/Voltage (C/V) response of an illustrative Schottky diode with and without a shallow trench isolation (STI) region with an illustrative PN diode with and without an STI region, in accordance with at least one embodiment of the present disclosure; and FIG. 7 provides a high-level block flow diagram of an illustrative method of forming a Schottky diode using CMOS technology, in accordance with at least one embodiment of the present disclosure; and

FIG. 8 provides a high-level block flow diagram of an illustrative method of forming a Schottky diode using CMOS technology, in accordance with at least one embodiment of the present disclosure.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.

DETAILED DESCRIPTION

The systems and methods disclosed herein provide Schottky diode apparatuses, systems, and methods that beneficially provide improved power efficiency and reduced losses. The apparatuses, systems, and methods disclosed herein provide a Schottky diode formed using CMOS techniques that may demonstrate a reduced series resistance which improves the quality factor ("Q") of the diode when operated as a varactor and/or increases the ON current of the diode when operated in forward bias (as a consequence of the reduced series resistance of the diode). More particularly, the introduction of newer CMOS silicides such as cobalt silicide, nickel silicide, platinum silicide, and nickel/platinum silicide beneficially permits the formation of high quality Schottky diodes in CMOS thereby leveraging the inherent advantages of the Schottky diode directly in a CMOS process, lowering the bill of material, reducing the overall cost, and reducing the system and circuit area and so allowing for a more compact system integration which improves the performance at higher frequencies. So this document specifically refers to Schottky diodes realized in CMOS silicon technologies but is not limited to it. Some features present in CMOS technology are the integration of n-type and p-type field effect transistors (FET) in the same substrate using gate stacks for controlling the current drive features of the FET. The gate stack includes a gate (i.e. gate conductor, or gate metal) disposed proximate or over a gate dielectric or gate oxide which is over a semiconductor substrate. This gate stack forms a metal oxide semiconductor system (MOS).

The gate dielectric may consist of silicon oxide or nitrided silicon oxide or a high-k material (material with a dielectric constant larger than 3.9) like hafnium oxide. The gate conductor may consist of poly silicon, silicided poly silicon, a silicide, or a metal like titanium nitride. N-type FETs (NFET) use a p-type semiconductor substrate or p-well with n- type source/drain (S/D) P/N junctions (i.e., n-doped junction in p-well) formed inside the p- well. P-type FETs (PFET) use an n-type semiconductor substrate or n-well with p-type source/drain (S/D) P/N junctions (i.e. p doped junction in n-well) formed inside the n-well. In so called triple well technology the N-FET p-well is formed inside an n-well which lies in a p-substrate. The FET can be planar or extend into 3D like a FinFET having S/D elevated above or etched out of the substrate. The semiconductor part used for FETs and Schottky diodes may be part of the bulk semiconductor/silicon substrate. FETs processed in a bulk semiconductor substrate are electrical isolated from each other by a so called shallow trench isolation (STI). The STI is a portion of semiconductor substrate which is removed, etched out, or a hole processed into the surface of the semiconductor substrate and filled with a dielectric, typically a silicon oxide for a silicon substrate, which electrically isolates the FETs from each other.

The S/D of FETs are connected to the metallization of the technology via a silicide which is formed on or within the substrate. This silicided regions are connected with help of metal contacts (e.g. tungsten) to the metallization of the technology residing above the FETs and Schottky diodes. The S/D regions can be formed inside the semiconductor substrate or be elevated even above the substrate, i.e. technology using raised S/D. The various wells are formed by very high energy (150-350 keV) implants leading to peak dopant concentrations more far away from the gate dielectric to semiconductor interface or the S/D P/N-junctions and at least below the depth/bottom of the shallow trench isolation region/hole.

Besides the P/N junctions, ohmic contact may also be formed. Such ohmic contacts feature a low resistance and a symmetrical current/voltage ( V) curve around zero volts bias like a simple resistor in contrast to the asymmetrical V curves of Schottky diodes and P/N- junctions which show forward and reverse V regions. Ohmic contacts are used to connect the wells in a low ohmic resistive way to some parts of the circuit. N-type contacts are made of n-type dopants in n-wells and p-type contacts are made of p-type dopants in p-wells or p- substrate. Typically, the bulk node of a FET is connected via a ohmic well contact. Ohmic contacts require similar dosage like P/N-junctions with a dosage of at least lxlO¹⁵ 1/cm². In embodiments of Schottky contact areas (108, 112 in Fig. 1) the implants forming PN-junction or ohmic contacts may be blocked. In general wells show a variation of dopant concentration when moving from the gate dielectric to semiconductor interface towards the inner part or backside of the semiconductor substrate. As used herein, the term "dopant" refers to any material and/or combination of materials capable of altering or changing the conductivity of a semiconductor. In general, P-type dopants may be considered to enhance the hole carrier concentration while N-type dopants may be considered to enhance the electron carrier concentration.

The semiconductor substrate may include a top portion of an around 10 μιη thick epitaxial layer of semiconductor substrate with a highly perfect crystal lattice for ultra large scaled device integration. Lightly doped drains and sources (LDD) may be used to connect the FET channel to the S/D regions. For NFET LDD is of n-type. For PFET LDD is of p- type. The LDD is a shallow low energy (5 - 30 keV) dopant implant but which can have in advanced CMOS very high implant dosage, even larger as the S/D P/N junction dose. For adjustment of the FET threshold voltage V^th dopants can be introduced into the substrate under the gate stack. There are two ways of forming V^th adjustment implants. The first method may include doping the well with a low dose (Ixl0ⁿ-lxl0¹³ 1/cm²) prior to gate conductor and S/D silicide formation (V^th adjust implant). The second may include doping the substrate thru the S/D junction area with an angled high energy implant after formation of the gate stack, the so called halo implants. The halo implants are implanted right before or right after the LDD implant using the same mask. For NFETs the Vth adjust and halo implants are of p-type. For PFETs the V^th adjust and halo implants are of n-type. In embodiments of Schottky contact areas (108, 112 in Fig. 1) the LDD and halo implants may be blocked.

More specifically, a Schottky diode formed using CMOS techniques and without a shallow trench isolation (STI) region between the Schottky contact and the ohmic contact of the Schottky diode reduces the series resistance of the diode but still enables the diode to handle high voltages. Further, the absence of the STI region within the Schottky diode reduces the non-tunable or much less tunable parasitic capacitance within the diode while advantageously providing a large tuning range for millimeter wave varactors.

The Schottky diode apparatuses, systems, and methods described herein are beneficial in devices compliant with millimeter wave based wireless communication and connectivity standards such as: 5^th generation wireless systems (5G); 802.1 lad; WiGig; next-generation 60 GHz connectivity; IEEE 802. Hay (WiGig 2); millimeter wave sensors such as millimeter wave based radar and imaging. The Schottky diode apparatuses, systems, and methods described herein may be extended to areas outside of millimeter wave applications, for example as voltage clamps in ESD protected devices, as free-wheel diodes for DC to DC converters, frequency multipliers, varactors, rectifiers, and amplitude-, power-, and radiation- sensors. As used herein, the terms "top," "bottom," "up," "down," "upward," "downward," "upwardly," "downwardly" and similar directional terms should be understood in their relative and not absolute sense. Thus, a component described as being "upwardly displaced" may be considered "laterally displaced" if the device carrying the component is rotated 90 degrees and may be considered "downwardly displaced" if the device carrying the component is inverted. Such implementations should be considered as included within the scope of the present disclosure.

A Schottky diode is provided. The Schottky diode may include a semiconductor substrate that includes a Schottky diode area, a shallow trench isolation region disposed about at least a portion of a periphery of the Schottky diode area, at least one doped implant region formed in the semiconductor substrate; at least one ohmic contact patterned onto at least a portion of the at least one doped implant region; and at least one Schottky contact patterned directly onto the semiconductor substrate and spaced apart from the at least one ohmic contact by a separation region that does not include a shallow trench isolation region.

A Schottky diode manufacturing method is also provided. The manufacturing method may use complementary metal oxide semiconductor manufacturing technique. The manufacturing method may include patterning a shallow trench isolation region about at least a portion of a periphery of a Schottky diode area on a semiconductor substrate; doping a portion of the semiconductor substrate in the Schottky diode area to provide a doped implant region; patterning an ohmic contact onto the doped implant region; and patterning at least one Schottky contact directly onto the semiconductor substrate in a location spaced apart from the doped implant region by a separation region that does not include a shallow trench isolation region.

A Schottky diode manufacturing system using complementary metal oxide semiconductor manufacturing techniques is also provided. The manufacturing system may include a means for patterning a shallow trench isolation region about at least a portion of a periphery of a Schottky diode area on a semiconductor substrate; a means for doping a portion of the semiconductor substrate in the Schottky diode area to provide a doped implant region; a means for patterning an ohmic contact onto the doped implant region; and a means for patterning at least one Schottky contact directly onto the semiconductor substrate in a location spaced apart from the doped implant region by a separation region that does not include a shallow trench isolation region.

FIG 1A provides a cross-sectional elevation of an illustrative Schottky diode 100 formed using CMOS techniques that includes separation region(s) 102 positioned between the doped substrate regions 104 proximate ohmic contacts 106 and the Schottky contact 108 and also no silicidation or silicide formation/deposition between the doped substrate regions 104 proximate the ohmic contacts 106 and the Schottky contact 108 and a shallow trench isolation (STI) region 140 disposed about at least a portion of a periphery and/or an external periphery of the Schottky diode area, in accordance with at least one embodiment of the present disclosure. FIG IB provides a cross-sectional elevation of another illustrative Schottky diode 100 formed using CMOS techniques that includes a P/N-j unction 130 positioned proximate the edge of the silicide forming the Schottky contact 108 and also no silicidation or silicide formation/deposition between the doped substrate regions 104 proximate the ohmic contacts 106 and the Schottky contact 108 and a shallow trench isolation (STI) region 140 disposed about at least a portion of a periphery and/or an external periphery of the Schottky diode area, in accordance with at least one embodiment of the present disclosure. FIG 1C provides a cross-sectional elevation of another illustrative Schottky diode 100 formed using CMOS techniques that includes separation region(s) 102 positioned between a central doped substrate region 104 proximate an ohmic contact 106 and at least one Schottky contact 108 disposed in, on, about, or around at least a portion of the ohmic contact 106 and also no silicidation or silicide formation/deposition between the doped substrate regions 104 proximate the ohmic contacts 106 and the Schottky contact 108 and a shallow trench isolation (STI) region 140 disposed about at least a portion of a periphery and/or an external periphery of the Schottky diode area 100, in accordance with at least one embodiment of the present disclosure. FIG ID provides a cross-sectional elevation of another illustrative Schottky diode 100 formed using CMOS techniques that includes a P/N- junction 130 positioned proximate the edge of the silicide forming the Schottky contact 108 with nearby separation region(s) 102 positioned between a central doped substrate region 104 proximate an ohmic contact 106 and at least one Schottky contact 108 disposed in, on, about, or around at least a portion of the ohmic contact 106 and also no silicidation or silicide formation/deposition between the doped substrate regions 104 proximate the ohmic contacts 106 and the Schottky contact 108 and a shallow trench isolation (STI) region 140 disposed about at least a portion of a periphery of the Schottky diode area 100, in accordance with at least one embodiment of the present disclosure.

In embodiments, the separation region(s) 102 may be doped differently than the bulk semiconductor substrate 110 where the field effect transistors (FETs) are formed. In some implementations, the resistive features of the bulk semiconductor substrate 110 may be altered under the Schottky contact 108 as well as some or all of the separation region(s) 102 when compared to the doped substrate regions where FETs are processed. In some instances, such modified doping may advantageously enhance the figures of merit (FOM) of the Schottky diode 100, i.e. improve the tuning range, quality factor and lead to reduced forward bias on voltage and/or resistance.

In some implementations, such Schottky diodes may be fabricated by patterning ohmic contacts 106 in, on, or about a doped n-type semiconductor region 104 within an n- type substrate 110 or n-well. In other implementations, such Schottky diodes may be fabricated by patterning ohmic contacts 106 in, on, or about a doped p-type semiconductor region 104 within an p-type substrate 110 or p-well. The Schottky contact 108 is patterned in, on, or about the n-type or p-type substrate 110. Separation region(s) 102 separate the doped semiconductor regions 104 from a Schottky area 112 proximate the Schottky contact 108.

The separation region(s) 102 may be tailored and/or configured to permit higher voltages or larger tuning range for the Schottky diode 100. In some implementations, for example, no gate conductors (i.e. , gates, gate metal, and/or gate conductor) may be disposed or otherwise patterned in some or all of the area above separation region(s) 102. Such gates may include, but are not limited to: gates, gate metal, and/or gate conductors that at least partially overlap at least a portion of the Schottky contact 108 and may at least partially overlap at least a portion of the separation region(s) 102, or overlapping separation region(s) 102 and on edge with the Schottky contact 108 or gate conductors overlapping separation region 102 and having a distance to the Schottky contact 108 of less than 100 nm. Such structures, gates, gate metal, and/or gate conductors may include, but are not limited to, an FET gate, or a filling structure consisting of the gate conductor material that planarizes the region above separation region(s) 102. Gate conductors which overlap separation region(s) 102, doped regions 104, and may be proximate the Schottky contact region 108 may reduce the breakdown voltage of the Schottky diode 100 and introduce a parasitic capacitance that detrimentally impacts the tuning range of the Schottky diode 100.

In some embodiments, gates, gate metal, and/or gate conductors may be deposited or otherwise patterned over some or all of the doped region 104 (potentially including portions of the doped region that extend above separation region(s) 102), provided a separation of at least 100 nm; at least 200 nm; or at least 300 nm is maintained between the gate metal and the silicided region forming the Schottky contact 108. In other embodiments, the region above the separation region(s) 102 and extending to the height/thickness approximately equal to the height of the contacts 120 and/or the dielectric region 122 between contacts 120 over the ohmic contacts 106 and over the silicided Schottky contact region 108 may be substantially free of any conductive material (any metal, or gate conductor, e.g., polysilicon, doped polysilicon, silicided poly silicon, doped silicided poly silicon, silicide, gate metal) thereby beneficially increasing the breakdown voltage and/or the capacitance tuning range of the Schottky diode 100. The dielectric region 122 between the contacts 120 and over regions 102, 104, 106 and 108 may include a material having a low dielectric constant, such as: equal to or less than 3.0; equal to or less than 2.5 or equal to or less than 2. In some

implementations, the dielectric region 122 between the contacts 120 and over regions 102, 104, 106 and/or 108 may include air gaps to beneficially improve the tuning range of the Schottky diode 100. In embodiments, gate conductors may be placed over the STI regions within the outer perimeter of the Schottky diode to achieve a sufficient planarization for the forming of the gates for the FETs or other devices (e.g. MOS varactors) integrated into the same technology as the Schottky diode.

In implementations, the separation region(s) 102 may include one or more P-type dopants, one or more N-type dopants, or a combination of P-type and N-type dopants. In some implementations, the separation region(s) 102 may include balanced concentrations of both P-type and N-type dopants to provide a neutral or effectively undoped region that may provide a reduced leakage current about all or a portion of the perimeter of the Schottky region. In some implementations the separation region maybe undoped.

The ohmic contacts 106 may include one or more conductive materials patterned in, on, or about a p-doped or n-doped semiconductor region 104. In embodiments, each of the ohmic contacts 106 may include one or more conductive silicides, such as titanium silicide (TiSi, TiSi₂), cobalt silicide (CoSi, CoSi₂), nickel silicide (NiSi, NiSi₂, Ni₂Si, Ni₃Si, Ni₃iSii₂), platinum silicide (PtSi), nickel-platinum silicide (NiPtSi), or combinations thereof. The ohmic contacts 106 may be deposited on the p-doped or n-doped semiconductor region 104 using any current or future developed patterning or deposition technologies. Such patterning and/or deposition technologies include, but are not limited to: lithography, photolithography, screen printing, sputtering, electroplating, chemical vapor deposition, physical vapor deposition, electroless plating, or combinations thereof. Further annealing steps may provide the forming of a silicide. In implementations, some or all of the regions 104, 106 and 108 may be elevated above the substrate (and region 102) in CMOS technologies using raised/elevated source/drain ("S/D") regions or epitaxially grown S/D semiconductor area on the semiconductor substrate. In implementations using FinFETs the S/D regions may be etched out of the substrate to allow formation of three-dimensional shaped FinFETs in a bulk substrate.

The Schottky contact 108 may include one or more conductive materials patterned directly onto the surface of the substrate 110 at a distance from the ohmic contacts 106. A Schottky area may be formed in the substrate 110 proximate at least a portion of the Schottky contact 108. In embodiments, the Schottky contact 108 may include one or more conductive silicides, such as titanium silicide (TiSi, TiSi2), cobalt silicide (CoSi, C0S12), nickel silicide (NiSi, NiSi2, INfeSi, Ni₃Si, Ni₃iSii₂), platinum silicide (PtSi), nickel-platinum silicide (NiPtSi), or combinations thereof. The Schottky contact is not formed by a material used for forming the gate conductor of FET gate stacks. In embodiments, one or more dopants may be added beneath and/or proximate the Schottky contact region 108 to improve the electrical features and/or characteristics of the Schottky diode 100. In embodiments, p-type dopants in p-well or n-type dopants in n-well located under and/or positioned proximate the Schottky contact area 108 may improve the tuning range of the Schottky diode 100 by influencing the change of space charge region with applied reverse bias of the Schottky diode 100. Such dopants may be provided at an area concentrations (or dose) of from about lxlO¹¹ 1/cm² to about lxlO¹³ 1/cm² with implant energies of from about 15 keV to about 100 keV. In some embodiments boron (B) is implanted with an energy of 15 keV up to 35 keV and a concentration/dose of 3 x 10¹² 1/cm² up to 8 x 10¹² 1/cm² into a p-well. In other embodiments Arsenic (As) is implanted with an energy of 40 keV up to 100 keV and a concentration dose of 3 x 10¹² 1/cm² up to 8 x 10¹² 1/cm² into an n-well. The depth of the dopant peak volume concentration should be equal to or less than 250 nm.

The Schottky barrier height between the silicide and the underlying semiconductor influences the Schottky diode forward on voltage. The Schottky barrier height may be altered, changed, adjusted or controlled using image force charges introduced proximate the silicide 108 to semiconductor interface 110 of the Schottky diode area 112. One or more dopants may be introduced to increase or decrease the barrier height to create image force charges in a respective depletion area of the Schottky area 112. The dopants may be implanted into the surface of the semiconductor before forming the silicide or even after silicide formation into the silicide with subsequent annealing and dopant diffusion towards the silicide 108 to semiconductor interface 110 of the Schottky area 112. In embodiments, implant energies may range from about 2 keV to about 25 keV and dosage from lxlO¹¹ 1/cm² to about lxlO¹⁵ 1/cm². In embodiments, one or more n-type dopants (e.g., As, P, Sb) may be implanted in p- type or n-type semiconductors/wells 110. In embodiments, one or more p-type dopants (e.g., B or In) may be implanted in n-type or p-type semiconductors/wells 110. The introduction of such dopants may change the Schottky barrier height through introduction of barrier height lowering or barrier height increasing image force charges in the charge depletion area of the Schottky diode area 112. In embodiments, dopants with higher mass may be preferred for the required shallow implants. In some embodiments the dopants may be implanted in the semiconductor to a depth of: about 75 nm or less; about 50 nm or less; or about 25 nm or less from the silicide 108 to semiconductor 110 interface. Dopants for modifying features of the Schottky diode may be provided via ion implantation techniques or plasma doping techniques.

The Schottky contact 108 may be deposited on a non-doped region of the substrate 110 using any current or future developed patterning or deposition technologies. Such patterning and/or deposition technologies include, but are not limited to: lithography, photolithography, screen printing, sputtering, electroplating, chemical vapor deposition, physical vapor deposition, electroless plating, or combinations thereof. Further annealing steps may provide the forming of a silicide. In embodiments, the Schottky contact 108 may have a width of: about 0.18μιη or less; about 0.3μιη or less; about 0.5 μιη or less; about 0.75μιη or less; or about Ιμιη or less. In embodiments, the Schottky contact 108 may have an area of: about Ιμιη² or less; about 0.75μιη² or less; about 0.5μιη² or less; or about 0.25μιη² or less. In embodiments, such as applications in the millimeter-wave region (e.g., from 30 GHz to 300 GHz), the Schottky contact 108 area may be reduced to beneficially improve the quality factor of the Schottky diode 100.

In embodiments, the width of the Schottky contact 108 may determine the tunable capacitance of the Schottky diode 100 (i. e. the greater the width of the Schottky contact 108, in general, the greater the tuning range of the Schottky diode 100). However, the greater the width of the Schottky contact 108 the greater the effective distributed resistance of the Schottky contact 108 towards the region 104 and region 106 which reduces the quality factor of the Schottky diode varactor.

In embodiments, the Schottky contact 108 may include a silicide or metal deposited or patterned on the semiconductor 110. In embodiments, the portion of the semiconductor 110 proximate the Schottky contact 108 may include lower doping or doping extending less inside the semiconductor 110 compared to ohmic contacts or P/N-junctions used for forming S/D junctions of FETs. The Schottky contact features an asymmetrical current/voltage ("I/V") characteristic around a zero- volt bias with a higher forward current and a lower reverse current. In embodiments, the forward ON voltage may be about 0 Volts to about 0.5 Volts but may be altered or adjusted by modifying the Schottky barrier height. At times, the Schottky diode 100 may have a lower ON voltage compared to the P/N-S/D-junctions thereby providing an advantage over the high forward ON voltage of P/N-j unctions found in advanced low supply voltage CMOS. The capacitance at reverse bias is a charge depletion capacitance and also the capacitance in forward direction is a depletion capacitance featuring no diffusion capacitance as the Schottky diode 100 is a majority carrier device compared to a P/N-junction which is a minority carrier device. The thickness of the substrate region 110 may be sufficiently thin to permit the formation of mechanically flexible substrates in the form of flexible foils but having sufficient thickness to provide large charge depletion regions under the Schottky contact area 108. In some embodiments, the bulk semiconductor substrate 110 may have a total thickness of 0.5μιη or more, Ιμιη or more, 2μιη or more, 5μιη or more, ΙΟμιη or more, 20μιη or more, 50μιη or more. In some embodiments the bulk semiconductor substrate 110 may have a total thickness of 300μιη or less, 200μιη or less, ΙΟΟμιη or less.

The shallow trench isolation area 140 may be disposed about at least a portion of a periphery, perimeter, or external boundary of the Schottky diode 100. In some

implementations the STI area 140 may be disposed about the entire periphery, perimeter, or external boundary that defines the Schottky diode 100. In some implementations, the STI area 140 may include one or more shallow trenches etched into the semiconductor substrate 110. The one or more shallow trenches may be partially filled, completely filled, or overfilled with one or more dielectric materials, such as silicon oxide, to provide an electrically isolative barrier about all or a portion of the Schottky diode 100.

FIG. 2 provides a layout of an illustrative Schottky diode 200, in accordance with at least one embodiment of the present disclosure. As depicted in FIG 2, the ohmic contact(s) 106 may be patterned and deposited on, in, or about an implant region that may be doped with a p- or n-type implant region 104 (e.g., a p-type dopant in p-substrate or p-well or an n- type dopant in n-substrate or n-well). The Schottky contact 108 may be patterned and deposited in, on, or about a region of the substrate 110 that may or may not include one or more dopants. Silicide blocking masks 202 may be used to isolate the ohmic contact(s) 106 from the Schottky contact 108 but also to create and maintain low series resistance pathways between the ohmic contact(s) 106 and the Schottky contact 108 during the manufacturing process. Dopants of the type used for the ohmic contacts can be placed also inside the area covered by the silicide blocking mask to lower the resistance between the contact(s) 106 and the Schottky contact 108. In at least some implementations, the physical configuration of the ohmic contact(s) 106 and the Schottky contact 108 may be determined, based in whole or in part on a target series resistance value between the contacts. The material of the silicide blocking (hard) mask 202 may be removed and replaced by a more suitable material to fill regions 122.

The separation regions 202 may be configured to permit higher voltages or larger tuning range for the Schottky diode 100. In some implementations, for example, no gate conductors (i.e. , gates, gate conductor, e.g. , polysilicon, doped polysilicon, silicided poly silicon, doped silicided poly silicon, silicide, gate metal) may be disposed or otherwise patterned in the area above separation region(s) 202. Such gates may include, but are not limited to: gates, gate metal, or gate conductor that at least partially overlap at least a portion of the Schottky contact 108 and may at least partially overlap at least a portion of the separation region(s) 202 and the Schottky contact area 108 or gates, gate metal, or gate conductor overlapping separation region(s) 202 and lying on edge with the Schottky contact area 108, or gate conductors overlapping separation region 102 and having a distance to the Schottky contact 108 of less than 100 nm. Such gates and/or gate structures may include, but are not limited to, an FET gate, or a filling structure consisting of the gate conductor material that planarizes the region above separation region(s) 202. Gate conductors which overlap separation region(s) 202, doped regions 104, and/or the Schottky contact region 108 may reduce the breakdown voltage of the Schottky diode 100 and introduce a parasitic capacitance that detrimentally impacts the tuning range of the Schottky diode 100.

In some embodiments, gate metal may be deposited or otherwise patterned over the doped region 104 (and potentially extending above separation region(s) 202), provided a separation of at least 100 nm; at least 200 nm; or at least 300 nm is maintained between the gate conductor and the silicided region forming the Schottky contact 108. In other embodiments, the surface of separation region(s) 202 between contacts 120 over the silicided region 106 and over the silicided region 108 may be substantially free of any conductive material (i.e. , any metal, or gate conductor, e.g., polysilicon, doped polysilicon, silicided poly silicon, doped silicided poly silicon, silicide, gate metal etc.) which would reduce the breakdown voltage or reduce the capacitance tuning range of the Schottky diode 100. The dielectric region 122 between the contacts 120 and over regions 102, 104, 106 and 108 may include a material having a low dielectric constant, such as: equal to or less than 3.0; equal to or less than 2.5, or equal to or less than 2. In some implementations, the dielectric region 122 between the contacts 120 and over regions 102, 104, 106 and/or 108 may include air gaps to beneficially improve the tuning range of the Schottky diode 100. In embodiments, gate conductors may be placed over the STI regions within the outer perimeter of the Schottky diode to achieve a sufficient planarization for the forming of the gates for the FETs or other devices (e.g. MOS varactors) integrated into the same technology as the Schottky diode.

In embodiments, the Schottky contact 108 may have a width of: about 0.18μιη or less; about 0.3μιη or less; about 0.5 μιη or less; about 0.75μιη or less; or about Ιμιη or less. In embodiments, the Schottky contact 108 may have an area of: about Ιμιη² or less; about 0.75μιη² or less; about 0.5μιη² or less; or about 0.25μιη² or less. In embodiments, such as applications in the millimeter-wave region (e.g., from 30 GHz to 300 GHz), the Schottky contact 108 area may be reduced to beneficially improve the quality factor of the Schottky diode 200.

As depicted in FIG 2, in some embodiments, the periphery, perimeter, and/or external boundary of the Schottky diode area 210 may be bounded by the shallow trench isolation (STI) area 140. In some implementations, the STI area 140 may extend about only a portion of the periphery, perimeter, and/or external boundary of the Schottky diode area 210. In addition, in embodiments, a blocking mask 212 may be disposed proximate all or a portion of the separation regions 202 between the at least one Schottky contact 108 and the ohmic contact(s) 106.

FIG. 3 provides a layout of another illustrative Schottky diode 300 having separation region(s) 102 positioned between the ohmic contact(s) 106 and the Schottky contact 108, in accordance with at least one embodiment of the present disclosure. In implementations, the implant region 104 and/or the silicide blocking mask 202 may be selected based at least in part on achieving a desired series resistance between the ohmic contact(s) 106 and the Schottky contact 108. In some instances, the ohmic contacts 106 may be disposed at a distance about all or a portion of a perimeter of the Schottky contact 108. In some instances, as depicted in FIG 3, some or all of the ohmic contacts 106 may be patterned, formed, or otherwise deposited in a manner that forms a contiguous or discontinuous ring and/or about all or a portion of the perimeter of the Schottky contact 108 and spaced a distance from the Schottky contact 108. In at least some implementations, such as depicted in FIG 3, the ohmic contacts 106 may be patterned, formed, or otherwise deposited in a generally square or rectangular configuration about or around a generally square or rectangular Schottky contact 108. In other instances, some or all of the ohmic contacts 106 may be patterned, formed, or otherwise deposited in a generally circular or oval configuration about or around a generally circular or oval Schottky contact 108. In another embodiment the position of the ohmic contact 106 may be interchanged with the position of the Schottky contact 108, i.e. a ring/circular/oval shaped Schottky contact resides nearby the shallow trench isolation (in accordance with FIG. 1C, ID) while a rectangular or squared ohmic contact is located in the center of the Schottky diode. Such an embodiment maybe allow to reduce the Schottky contact area compared to the shown embodiment in FIG. 3, as a silicide blocking mask has a minimum enclosed area which is allowed due to manufacturing reasons and which prohibits a further reduction of the Schottky contact area. A reduced Schottky contact area maybe improve the quality factor of the Schottky diode varactor.

Any number of contacts 120 may electrically conductively couple a metal layer 302 (e.g. , metal layer 1 or Ml) to the underlying ohmic contacts 106. Similarly, any number of contacts 120 may electrically conductively couple the same or a different metal layer 304 to the underlying Schottky contact 108. In embodiments, the Schottky contact 108 may have a width of: about 0.18μιη or less; about 0.3μιη or less; about 0.5 μιη or less; about 0.75μιη or less; or about Ιμιη or less. In embodiments, the Schottky contact 108 may have an area of: about Ιμιη² or less; about 0.75μιη² or less; about 0.5μιη² or less; or about 0.25μιη² or less. In embodiments, such as applications in the millimeter-wave region (e.g., from 30 GHz to 300 GHz), the Schottky contact 108 area may be reduced to beneficially improve the quality factor of the Schottky diode 200.

In another embodiment, the ohmic contacts 106 and the Schottky contact 108 depicted in FIG 3 may be reversed. In such embodiments, the Schottky contact 108 may be disposed in a ring-like configuration about one or more centrally located ohmic contacts 106. Further, as understood by one of ordinary skill in the art, other configurations (such as circular, oval, square, and triangular) are possible in addition to the generally rectangular configuration depicted in FIG 3.

FIG 4 provides a graph 400 that compares the Current/Voltage (I/V) response of an illustrative Schottky diode with and without a shallow trench isolation (STI) region with the I/V response of an illustrative PN diode with and without an STI region, in accordance with at least one embodiment of the present disclosure. The PN diode and the Schottky diode may lie or may be at least partially formed or otherwise deposited in a p-well. The illustrative Schottky diode and the illustrative PN diode with STI have an equal contact area of 19.4μιη² and the illustrative Schottky diode and the illustrative PN diode without STI have an equal contact area of 23.5μιη².

First, comparing the I/V response of the illustrative Schottky diodes with and without shallow trench isolation (STI), both illustrative Schottky diodes exhibit a forward ON voltage of approximately 0.1 Volts. However, at a forward ON bias voltage of -1 Volt, the illustrative Schottky diode without STI demonstrates a significantly higher current (57.6 niA or approx. 2.45 mA/μιη²) than the illustrative Schottky diode without STI (26.4 mA or approx. 1.36 mA/μιη²). It may be appreciated that the increase in forward ON current of the Schottky diode exceeds the increase in forward ON current for the P/N-diode due to the removal of the STI between ohmic contact region 106 and Schottky contact region 108 (or respective pn-j unction region).

Second, comparing the illustrative Schottky diodes to the illustrative PN junction diodes, the forward ON voltage of the illustrative P/N-junction diodes (approx. 0.8 V) is considerably greater than the forward ON voltage of the illustrative Schottky diodes (approx. 0.1 V). Consequently, the current capacity of the illustrative PN junction diodes is significantly compromised when compared to the current capacity of the illustrative Schottky diode: 57.6 mA or approx. 2.45 mA/μιη² for the illustrative Schottky diode without STI versus 21.7 mA or approx. 0.93 mA/μιη² for the illustrative PN junction diode without STI; 26.4 mA or approx. 1.36 mA/μιη² for the illustrative Schottky diode with STI versus 11.2 mA or approx. 0.58 mA/μιη² for the illustrative PN junction diode with STI. The illustrative Schottky diode without STI shows higher ON current at a forward bias of 1 Volt and the ON current per diode area is approximately twice as large when compared to the illustrative Schottky diode with STI. For a forward voltage of equal to less than IV the Schottky diode without STI shows higher current capability per area compared to P/N-junctions which may provide beneficial feature for voltage clamps and electrostatic discharge ("ESD") protection circuits/elements/devices in scaled CMOS technologies with supply voltages of equal to less than IV.

FIG. 5 provides a logarithmic graph 500 that compares the Current/Voltage (logl/V) response of an illustrative Schottky diode and an illustrative PN junction diode without a shallow trench isolation (STI) region, in accordance with at least one embodiment of the present disclosure. The PN diode and the Schottky diode may lie or may be at least partially formed or otherwise deposited in an n-well. Comparing the illustrative Schottky diode without STI to the illustrative PN junction diode without STI, at an equivalent current, the forward ON voltage of an illustrative Schottky diode (approx. 0.5 V) is lower than the forward ON voltage of the illustrative PN junction diode (approx. 0.8 V). Until a reverse bias of up to -IV, a similar leakage current may be observed for both the P/N-diode as well as the Schottky diode 100. FIG. 6 provides a graph that compares the Capacitance/Voltage (C/V) response of an illustrative Schottky diode with and without a shallow trench isolation (STI) region with an illustrative PN diode with and without an STI region, in accordance with at least one embodiment of the present disclosure. The PN diode and the Schottky diode may lie or may be at least partially formed or otherwise deposited in a p-well. The illustrative Schottky diode and the illustrative PN diode with STI have an equal contact area of 19.4μιη² and the illustrative Schottky diode and the illustrative PN diode without STI have an equal contact area of 23.5μιη².

First, comparing the capacitance of the illustrative Schottky diodes with and without shallow trench isolation (STI), the illustrative Schottky diode with STI demonstrates a capacitance value of approx. 65 femtoFarads (fF) at 0 Volts (3.35 fF/μιη²) and the illustrative Schottky diode without STI demonstrates a capacitance value of approximately 106 fF at 0 Volts (4.53 fF/μιη²). Comparing the capacitance of the illustrative P/N junction diodes with and without STI, the illustrative PN junction diode with STI demonstrates a capacitance of approx. 39 fF at 0 Volts (2.03 fF/μιη²) and the illustrative PN junction diode without STI demonstrates a capacitance of approx. 103 fF at 0 Volts (4.39 fF/μιη²). Beneficially, the illustrative Schottky diodes demonstrate a lower and even negative capacitance as the forward bias voltage is increased across the diode compared to the illustrative PN junction diodes which demonstrate a large positive diffusion capacitance as the forward bias voltage is increased. The Schottky diodes avoid a large diffusion capacitance at forward bias. In general, the illustrative Schottky diode without STI exhibits the highest ratio of forward bias ON current to capacitance at zero bias voltage - such performance may be advantageously employed in numerous applications, for example as voltage clamps, or electrostatic discharge ("ESD") protection for RF inputs/outputs towards an antenna requiring low input capacitance in low voltage CMOS applications. The Schottky diode 100 also demonstrates a larger tuning range (= C_max(@bias =0V) / Cmin(@reverse bias) of 106/35 ~ 3 compared to the PN-diode without STI 103/52 ~ 2. This beneficially permits the use of a smaller Schottky diode 100 when compared to a conventional P/N-diode.

FIG. 7 provides a high-level block flow diagram of an illustrative method 700 of forming a complementary metal oxide semiconductor (CMOS) Schottky diode 100, in accordance with at least one embodiment of the present disclosure. The method commences at 702.

At 704, regions in the semiconductor substrate are formed wherein the Schottky diodes will be processed. A shallow trench isolation (STI) area 140 may be disposed about at least a portion of the periphery, perimeter, or external boundary that defines the Schottky diode area 210. In some implementations, the STI area 140 may extend continuously about the periphery, perimeter, or external boundary that defines the Schottky diode area 210. Within the Schottky diode area 210, one or more Schottky diodes 100 may be connected in parallel and may be arranged according to at least one embodiment of the present disclosure. In at least some embodiments one or more gate conductors may be deposited, patterned, or otherwise formed on at least a portion of some or all of the STI area 140.

At 706, the one or more ohmic contact(s) 106 may be patterned and deposited in, on, or about a doped region 104 of the bulk semiconductor substrate 110. In some

implementations, the one or more ohmic contact(s) 106 may be patterned and deposited in, on, or about an n-doped region 104 of an n-type semiconductor substrate 110. In some implementations, the n-type semiconductor substrate 110 may include an n-type

semiconductor well formed in a p-type substrate. In other implementations, the one or more ohmic contact(s) 106 may be patterned and deposited in, on, or about a p-doped region 104 of an p-type semiconductor substrate 110. In some implementations, the p-type semiconductor substrate 110 may include an p-type semiconductor well formed in a n-type substrate or n- well (triple well concept: p-well in n-well). In embodiments, the one or more ohmic contact(s) 106 may include contacts patterned and deposited in one or more of the following silicides: a titanium silicide, a cobalt silicide, a nickel silicide, a platinum silicide, or a nickel/platinum silicide.

At 708, the one or more Schottky contacts 108 may be patterned and deposited on the semiconductor substrate 110. The one or more Schottky contacts 108 may be separated, distanced, or spaced remotely from some or all of the one or more ohmic contact(s) 106 by a separation region 102. In some implementations, the one or more Schottky contacts 108 may be spaced from the ohmic contact(s) 106 based at least in part on maintaining a defined series resistance between the one or more Schottky contacts 108 and the one or more ohmic contact(s) 106. In embodiments, the separation region 102 between the one or more Schottky contact(s) 108 and the one or more ohmic contact(s) 106 may include a doped or undoped semiconductor material. Effectively undoped regions maybe formed by

doping/implanting similar amounts of n-type and p-type dopants into the separation region 102. In embodiments, the one or more Schottky contacts 108 may include contacts patterned and deposited in one or more of the following silicides: a titanium silicide, a cobalt silicide, a nickel silicide, a platinum silicide, or a nickel/platinum silicide. For patterning the Schottky contact 108, implants for the ohmic contact region 106 as well as FET D/S pn-junctions, Halo and LDD implants maybe blocked with help of a mask from the Schottky area 112.

At 710, the silicide blocking masks may be removed from the surface of the bulk semiconductor substrate after forming, patterning, or otherwise depositing the ohmic contacts at 706 and after forming, patterning, or otherwise depositing the Schottky contact at 708. The method 700 concludes at 712.

FIG. 8 provides a high-level block flow diagram of an illustrative method 800 of forming a complementary metal oxide semiconductor (CMOS) Schottky diode 100, in accordance with at least one embodiment of the present disclosure. The method commences at 802.

At 804, before forming the Schottky contact 108 silicide, the region below the Schottky contact 108 area maybe doped with a p-type dopant in p-well or an n-type dopant in n-well to improve the tuning characteristic of a Schottky diode varactor, selecting the implant energies between 15 keV up to 100 keV and implant dosage between 1 x 10¹² 1/cm² till 1 x 10¹³ 1/cm². The method 800 concludes at 806.

Additionally, operations for the embodiments have been further described with reference to the above figures and accompanying examples. Some of the figures may include a logic flow. Although such figures presented herein may include a particular logic flow, it can be appreciated that the logic flow merely provides an example of how the general functionality described herein can be implemented. Further, the given logic flow does not necessarily have to be executed in the order presented unless otherwise indicated. In addition, the given logic flow may be implemented by a hardware element, a software element executed by a processor, or any combination thereof. The embodiments are not limited to this context.

Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents. Various features, aspects, and embodiments have been described herein. The features, aspects, and

embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and

modifications.

As described herein, various embodiments may be implemented using hardware elements, software elements, or any combination thereof. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, transmission lines, and so forth), integrated circuits, application specific integrated circuits (ASIC), wireless receivers, transmitters, transceivers, smart antenna arrays for beamforming and electronic beam steering used for wireless broadband communication or radar sensors for autonomous driving or as gesture sensors replacing a keyboard device for tactile internet experience, screening sensors for security applications, medical sensors

(cancer screening), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. The wireless receivers, transmitters or transceiver maybe connected to an antenna. Examples for the antenna may include an internal antenna, an omni- directional antenna, a monopole antenna, a dipole antenna, an end fed antenna, a circularly polarized antenna, a micro-strip antenna, a micro-strip patch antenna, an endfire antenna, a diversity antenna, a dual antenna, an antenna array for beamforming reasons or electronic beam steering functionality, and so forth. The wireless communication system may communicate media and control information in accordance with one or more protocols. A protocol may comprise a set of predefined rules or instructions to control how the nodes communicate information between each other. The protocol may be defined by one or more protocol standards as promulgated by a standards organization, such as the Internet

Engineering Task Force (IETF), International Telecommunications Union (ITU), the Institute of Electrical and Electronics Engineers (IEEE), and so forth. The Schottky diodes, circuits, systems, and methods described herein are beneficial in devices, circuits and systems compliant with millimeter wave based wireless communication and connectivity standards such as: 5^th generation wireless systems (5G); 802.1 lad, WiGig; next-generation 60 GHz connectivity; IEEE 802.11 ay (WiGig 2); millimeter wave sensors such as millimeter wave based radar and imaging. Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The following examples pertain to further embodiments. The embodiments are not limited to planar bulk CMOS integration but can include usage of bipolar or integrated bipolar + CMOS (BiCMOS) technologies. Schottky diodes may be formed as planar devices but also as 3D Fin devices (when placed in FinFET technology). Semiconductors to be used for the formation of the Schottky diode can include silicon, germanium, silicon-germanium (SiGe), GaAs, InAs, GaN, InN, A1N, InSb, and InP. In semiconductors like GaAs, InAs, GaN, InN, A1N, InSb, and InP the schottky contact maybe formed by a respective metal semiconductor alloy or a metal patterned onto the semiconductor substrate with a subsequent annealing step. In particular, the Schottky contact area 108 can be formed in SiGe, with Germanium having a higher dielectric constant compared to silicon, allowing an increased tuning range for Schottky diode varactors.

According to example 1, there is provided a Schottky diode. The Schottky diode may include a semiconductor substrate that includes a Schottky diode area, a shallow trench isolation region disposed about at least a portion of a periphery of the Schottky diode area, at least one doped implant region formed in the semiconductor substrate; at least one ohmic contact patterned onto at least a portion of the at least one doped implant region; and at least one Schottky contact patterned directly onto the semiconductor substrate and spaced apart from the at least one ohmic contact by a separation region that does not include a shallow trench isolation region.

Example 2 may include elements of example 1 where the separation region may include or may consist of a semiconductor substrate having similar concentrations of one or more p-type dopants and one or more n-type dopants to provide an effectively undoped separation region.

Example 3 may include elements of example 1 where the at least one Schottky contact may include a Schottky contact formed on/in a portion of the semiconductor substrate that includes a silicon-germanium (SiGe) alloy. Example 4 may include elements of example 1 where the semiconductor substrate may include a semiconductor substrate having a total thickness of 0.5 micrometers (μιη) or more.

Example 5 may include elements of example 1 where the semiconductor substrate may include a p-type substrate.

Example 6 may include elements of example 5 where wherein the doped implant region may include a p-doped implant having a concentration of larger than 1 x 10¹⁴ per square centimeter (1/cm²) formed in the p-type substrate.

Example 7 may include elements of example 1 where the semiconductor substrate may include a n-type substrate.

Example 8 may include elements of example 7 where the doped implant region may include a n-doped implant having a concentration of larger than 1 x 10¹⁴ per square centimeter (1/cm²) formed in the n-type substrate.

Example 9 may include elements of example 1 where a P/N-j unction region formed in the semiconductor substrate may overlap at least a portion of a perimeter of the at least one Schottky contact and at least a portion of the separation region.

Example 10 may include elements of any of examples 1 through 9 where the at least one diode electrode may include at least one ohmic contact including a silicide selected from the group of silicides including: titanium silicide; cobalt silicide; nickel silicide; platinum silicide; or nickel/platinum silicide.

Example 11 may include elements of example 10 where the at least one Schottky contact may include at least one Schottky contact including a silicide selected from the group of silicides including: titanium silicide; cobalt silicide; nickel silicide; platinum silicide; or nickel/platinum silicide.

Example 12 may include elements of example 11 where the Schottky diode may have a quality factor of at least 15 at operating frequencies of 100 GHz or more at lower frequencies with a tuning range Cmax/Cmin of at least 1.4.

Example 13 may include elements of example 1 and may additionally include one or more gate conductors disposed proximate above and overlapping the shallow trench isolation region disposed about at least a portion of the periphery of the Schottky diode area.

Example 14 may include elements of example 1 with a separation region that does not have a gate conductor above and overlapping the separation region.

Example 15 may include elements of example 1 and further comprising a dopant in the semiconductor substrate below and overlapping the Schottky contact area with an area concentration of 1 x 10¹² up to 1 x 10¹³ per square centimeter (1/cm²) and a depth of the dopant peak volume concentration of less than 250 nm.

According to example 16, there is provided a Schottky diode manufacturing method. The manufacturing method may use complementary metal oxide semiconductor

manufacturing technique. The manufacturing method may include patterning a shallow trench isolation region about at least a portion of a periphery of a Schottky diode area on a semiconductor substrate; doping a portion of the semiconductor substrate in the Schottky diode area to provide a doped implant region; patterning an ohmic contact onto the doped implant region; and patterning at least one Schottky contact directly onto the semiconductor substrate in a location spaced apart from the doped implant region by a separation region that does not include a shallow trench isolation region.

Example 17 may include elements of example 16, and may additionally include depositing a silicide blocking mask on at least a portion of a surface of the semiconductor substrate prior to patterning the ohmic contact on the implant region formed in the semiconductor substrate and patterning the at least one Schottky contact onto the

semiconductor substrate; and removing at least a portion of the silicide blocking mask from at least a portion of a surface of the semiconductor substrate subsequent to patterning the ohmic contact on the implant region formed in the semiconductor substrate and patterning the at least one Schottky contact onto the semiconductor substrate.

Example 18 may include elements of example 16 where patterning at least one

Schottky contact directly onto the semiconductor substrate in a location spaced apart from the doped implant region by a separation region may include patterning at least one Schottky contact directly onto the semiconductor substrate in a location spaced apart from the doped implant region by a separation region containing similar concentrations of one or more p-type dopants and one or more n-type dopants to provide an effectively undoped separation region.

Example 19 may include elements of example 16 where patterning at least one Schottky contact directly onto the semiconductor substrate may include patterning at least one Schottky contact onto a silicon-germanium semiconductor portion within the

semiconductor substrate.

Example 20 may include elements of example 16 where patterning an ohmic contact onto a doped implant region may include patterning the at least one ohmic contact onto a doped implant region formed in a p-type substrate.

Example 21 may include elements of example 20 where patterning the ohmic contact onto the doped implant region formed in a p-type substrate may include patterning the ohmic contact onto a p-doped implant region having a concentration of greater than 1 x 10¹⁴ per square centimeter (1/cm²) formed in the p-type substrate.

Example 22 may include elements of example 16 where patterning an ohmic contact onto a doped implant region formed in a semiconductor substrate may include patterning the ohmic contact onto a doped implant region formed in an n-type substrate.

Example 23 may include elements of example 22 where patterning the ohmic contact onto the doped implant region formed in an n-type substrate may include patterning the ohmic contact onto an n-doped implant region having a concentration of greater than 1 x 10¹⁴ per square centimeter (1/cm²) formed in the n-type substrate.

Example 24 may include elements of example 16, and may additionally include forming a P/N-junction region in the semiconductor substrate such that the P/N-junction region overlaps at least a portion of a perimeter of the at least one Schottky contact and at least a portion of the separation region.

Example 25 may include elements of any of examples 16 through 24 where patterning an ohmic contact onto a doped implant region formed in a semiconductor substrate may include patterning an ohmic contact including a silicide selected from the group of silicides including: titanium silicide, cobalt silicide; nickel silicide; platinum silicide; or

nickel/platinum silicide onto the doped implant region.

Example 26 may include elements of example 25 where patterning at least one Schottky contact directly onto the semiconductor substrate may include patterning the at least one Schottky contact including a silicide selected from the group of silicides including: titanium silicide, cobalt silicide; nickel silicide; platinum silicide; or nickel/platinum silicide directly onto the semiconductor substrate.

Example 27 may include elements of example 16 with a separation region where no gate conductor above and overlapping the separation region is patterned.

Example 28 may include elements of example 16, further comprising introducing a dopant in the semiconductor substrate below and overlapping the Schottky contact area with an area concentration of about 1 x 10¹² to about 1 x 10¹³ per square centimeter (1/cm²) and an implant energy from 15 keV up to 100 keV.

Example 29 may include elements of example 16, further blocking dopants with help of masks from the Schottky contact area.

According to example 30, there is provided a Schottky diode manufacturing system using complementary metal oxide semiconductor manufacturing techniques. The manufacturing system may include a means for patterning a shallow trench isolation region about at least a portion of a periphery of a Schottky diode area on a semiconductor substrate; a means for doping a portion of the semiconductor substrate in the Schottky diode area to provide a doped implant region; a means for patterning an ohmic contact onto the doped implant region; and a means for patterning at least one Schottky contact directly onto the semiconductor substrate in a location spaced apart from the doped implant region by a separation region that does not include a shallow trench isolation region.

Example 31 may include elements or example 30, and may additionally include a means for depositing a silicide blocking mask on at least a portion of a surface of the semiconductor substrate prior to patterning the ohmic contact on the implant region formed in the semiconductor substrate and patterning the at least one Schottky contact onto the semiconductor substrate; and a means for removing at least a portion of the silicide blocking mask from at least a portion of a surface of the semiconductor substrate subsequent to patterning the ohmic contact on the implant region formed in the semiconductor substrate and patterning the at least one Schottky contact onto the semiconductor substrate.

Example 32 may include elements of example 30 where the means for patterning at least one Schottky contact directly onto the semiconductor substrate in a location spaced apart from the doped implant region by a separation region may include a means for patterning at least one Schottky contact directly onto the semiconductor substrate in a location spaced apart from the doped implant region by a separation region containing similar concentrations of one or more p-type dopants and one or more n-type dopants to provide an effectively undoped separation region.

Example 33 may include elements of example 30 where the means for patterning at least one Schottky contact directly onto the semiconductor substrate may include a means for patterning at least one Schottky contact onto a silicon-germanium semiconductor portion within the semiconductor substrate.

Example 34 may include elements of example 30 where the means for patterning an ohmic contact onto a doped implant region may include a means for patterning the at least one ohmic contact onto a doped implant region formed in a p-type substrate.

Example 35 may include elements of example 34 where the means for patterning the ohmic contact onto the doped implant region formed in a p-type substrate may include a means for patterning the ohmic contact onto a p-doped implant region having a concentration of greater than 1 x 10¹⁴ per square centimeter (1/cm²) formed in the p-type substrate.

Example 36 may include elements of example 30 where the means for patterning an ohmic contact onto a doped implant region formed in a semiconductor substrate may include a means for patterning the ohmic contact onto a doped implant region formed in an n-type substrate.

Example 37 may include elements of example 36 where the means for patterning the ohmic contact onto the doped implant region formed in an n-type substrate may include a means for patterning the ohmic contact onto an n-doped implant region having a

concentration of greater than 1 x 10¹⁴ per square centimeter (1/cm²) formed in the n-type substrate.

Example 38 may include elements of example 30, and may additionally include a means for forming a P/N-j unction region in the semiconductor substrate such that the P/N- junction region overlaps at least a portion of a perimeter of the at least one Schottky contact and at least a portion of the separation region.

Example 39 may include elements of any of examples 30 through 38 where the means for patterning an ohmic contact onto a doped implant region formed in a semiconductor substrate may include a means for patterning an ohmic contact including a silicide selected from the group of silicides including: titanium silicide; cobalt silicide; nickel silicide;

platinum silicide; or nickel/platinum silicide onto the doped implant region.

Example 40 may include elements of example 39 where the means for patterning at least one Schottky contact directly onto the semiconductor substrate may include a means for patterning the at least one Schottky contact including a silicide selected from the group of silicides including: titanium silicide, cobalt silicide; nickel silicide; platinum silicide; or nickel/platinum silicide directly onto the semiconductor substrate.

The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents.

Claims

WHAT IS CLAIMED:

1. A Schottky diode, comprising:

a semiconductor substrate that includes a Schottky diode area;

a shallow trench isolation region disposed about at least a portion of a periphery of the

Schottky diode area;

at least one doped implant region formed in the semiconductor substrate;

at least one ohmic contact formed on at least a portion of the at least one doped implant region; and

at least one Schottky contact formed directly on the semiconductor substrate and spaced apart from the at least one ohmic contact by a separation region that does not include a shallow trench isolation region.

2. The Schottky diode of claim 1 wherein the separation region consists of the semiconductor substrate having similar concentrations of one or more p-type dopants and one or more n-type dopants to provide an effectively undoped separation region.

3. The Schottky diode of claim 1 wherein the at least one Schottky contact comprises a Schottky contact formed using a silicon-germanium (SiGe) alloy.

4. The Schottky diode of claim 1 wherein the semiconductor substrate comprises a semiconductor substrate having a total thickness of 0.5 micrometers (μιη) or more.

5. The Schottky diode of claim 1 wherein the semiconductor substrate comprises a p-type substrate.

6. The Schottky diode of claim 5 wherein the doped implant region comprises a p-doped implant having a concentration of greater than 1 x 10¹⁴ per square centimeter (1/cm²) formed in the p-type substrate.

7. The Schottky diode of claim 1 wherein the semiconductor substrate comprises a n-type substrate.

8. The Schottky diode of claim 7 wherein the doped implant region comprises a n-doped implant having a concentration of greater than 1 x 10¹⁴ per square centimeter (1/cm²) formed in the n-type substrate.

9. The Schottky diode of claim 1 wherein a P/N-j unction region formed in the semiconductor substrate overlaps at least a portion of a perimeter of the at least one Schottky contact and at least a portion of the separation region.

10. The Schottky diode of any of claims 1 through 9 wherein the at least one ohmic contact comprises a silicide selected from the group of silicides including: titanium silicide; cobalt silicide; nickel silicide; platinum silicide; or nickel/platinum silicide.

11. The Schottky diode of claim 10 wherein the at least one Schottky contact comprises a silicide selected from the group of silicides including: titanium silicide; cobalt silicide; nickel silicide; platinum silicide; or nickel/platinum silicide.

12. The Schottky diode of claim 11 wherein the Schottky diode has a quality factor of at least 15 at operating frequencies of 100 GHz or more at lower frequencies with a tuning range C_max/Cmin of at least 1.4.

13. The Schottky diode of claim 1, further comprising one or more gate conductors disposed at least partially above and at least partially overlapping the shallow trench isolation region disposed about at least a portion of the periphery of the Schottky diode area.

14. The Schottky diode of claim 1, further comprising a separation region that does not have a gate conductor above and overlapping the separation region.

15. The Schottky diode of claim 1, further comprising a dopant in the

semiconductor substrate below and overlapping the Schottky contact area with an area concentration of 1 x 10¹² up to 1 x 10¹³ per square centimeter (1/cm²) and a depth of the dopant peak volume concentration of less than 250 nm.

16. A Schottky diode manufacturing method using complementary metal oxide semiconductor manufacturing techniques, the method comprising: forming a shallow trench isolation region about at least a portion of a periphery of a Schottky diode area in a semiconductor substrate;

doping a portion of the semiconductor substrate in the Schottky diode area to provide a doped implant region;

forming an ohmic contact on the doped implant region; and

forming at least one Schottky contact directly on the semiconductor substrate in a location spaced apart from the doped implant region by a separation region that does not include a shallow trench isolation region.

17. The Schottky diode manufacturing method of claim 16, further comprising: depositing a silicide blocking mask on at least a portion of a surface of the semiconductor substrate prior to forming the ohmic contact and the at least one Schottky contact on the semiconductor substrate; and

removing at least a portion of the silicide blocking mask from at least a portion of a surface of the semiconductor substrate subsequent to forming the ohmic contact on the implant region and the at least one Schottky contact on the semiconductor substrate.

18. The Schottky diode manufacturing method of claim 16 wherein forming at least one Schottky contact directly onto the semiconductor substrate in a location spaced apart from the doped implant region by a separation region comprises:

forming at least one Schottky contact directly onto the semiconductor substrate in a location spaced apart from the doped implant region by a separation region containing similar concentrations of one or more p-type dopants and one or more n-type dopants to provide an effectively undoped separation region.

19. The Schottky diode manufacturing method of claim 16 wherein patterning at least one Schottky contact directly onto the semiconductor substrate comprises patterning at least one Schottky contact onto a silicon-germanium semiconductor portion within the semiconductor substrate.

20. The Schottky diode manufacturing method of claim 16 wherein forming an ohmic contact on a doped implant region comprises forming the at least one ohmic contact on a doped implant region formed in a p-type substrate.

21. The Schottky diode manufacturing method of claim 20 wherein forming the ohmic contact on the doped implant region formed in a p-type substrate comprises:

forming the ohmic contact on a p-doped implant region having a concentration of greater than 1 x 10¹⁴ per square centimeter (1/cm²) formed in the p-type substrate.

22. The Schottky diode manufacturing method of claim 16 wherein forming an ohmic contact on a doped implant region formed in a semiconductor substrate comprises: forming the ohmic contact on a doped implant region formed in an n-type substrate.

23. The Schottky diode manufacturing method of claim 22 wherein forming the ohmic contact on the doped implant region formed in an n-type substrate comprises:

forming the ohmic contact on an n-doped implant region having a concentration of greater than 1 x 10¹⁴ per square centimeter (1/cm²) formed in the n-type substrate.

24. The Schottky diode manufacturing method of claim 16 further comprising forming a P/N-junction region in the semiconductor substrate such that the P/N-junction region overlaps at least a portion of a perimeter of the at least one Schottky contact and at least a portion of the separation region.

25. The Schottky diode manufacturing method of any of claims 16 through 24 wherein forming an ohmic contact on a doped implant region formed in a semiconductor substrate comprises:

forming an ohmic contact including a silicide selected from the group of silicides including: titanium silicide; cobalt silicide; nickel silicide; platinum silicide; or

nickel/platinum silicide on the doped implant region.

26. The Schottky diode manufacturing method of claim 25 wherein forming at least one Schottky contact directly on the semiconductor substrate comprises:

forming the at least one Schottky contact including a silicide selected from the group of silicides including: titanium silicide, cobalt silicide; nickel silicide; platinum silicide; or nickel/platinum silicide directly on the semiconductor substrate.

27. The Schottky manufacturing method of claim 16, wherein a dopant is introduced in the semiconductor substrate below and overlapping the Schottky contact area with an area concentration of about 1 x 10¹² to about 1 x 10¹³ per square centimeter (1/cm²) and an implant energy from 15 keV up to 100 keV.

28. A Schottky diode manufacturing system using complementary metal oxide semiconductor manufacturing techniques, the system comprising:

a means for forming a shallow trench isolation region about at least a portion of a periphery of a Schottky diode area on a semiconductor substrate;

a means for doping a portion of the semiconductor substrate in the Schottky diode area to provide a doped implant region;

a means for forming an ohmic contact on the doped implant region formed in a semiconductor substrate; and

a means for forming at least one Schottky contact directly on the semiconductor substrate in a location spaced apart from the doped implant region by a separation region that does not include a shallow trench isolation region.

29. The Schottky diode manufacturing method of claim 28 wherein the means for forming at least one Schottky contact directly on the semiconductor substrate in a location spaced apart from the doped implant region by a separation region comprises:

a means for forming at least one Schottky contact directly on the semiconductor substrate in a location spaced apart from the doped implant regions by a separation region containing similar concentrations of one or more p-type dopants and one or more n-type dopants to provide an effectively undoped separation region.

30. The Schottky diode manufacturing method of claim 28 wherein the means for forming at least one Schottky contact directly on the semiconductor substrate comprises: a means for forming at least one Schottky contact directly on the semiconductor substrate on a portion of the semiconductor substrate that includes a silicon-germanium alloy.