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WO2018004659A1 - Cellule de mémoire à trois transistors avec semi-conducteurs à oxyde métallique et transistors à base de si - Google Patents

Cellule de mémoire à trois transistors avec semi-conducteurs à oxyde métallique et transistors à base de si Download PDF

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Publication number
WO2018004659A1
WO2018004659A1 PCT/US2016/040715 US2016040715W WO2018004659A1 WO 2018004659 A1 WO2018004659 A1 WO 2018004659A1 US 2016040715 W US2016040715 W US 2016040715W WO 2018004659 A1 WO2018004659 A1 WO 2018004659A1
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Prior art keywords
gate
transistor
coupled
source
metal layer
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Inventor
Van H. Le
Gilbert William DEWEY
Rafael Rios
Jack T. Kavalieros
Marko Radosavljevic
Shriram SHIVARAMAN
Mesut Meterelliyoz
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present description i s related to memory cells for semiconductors and, in particular, to three transistor memory cells using amorphous oxide semiconductors.
  • SRAM Static Random Access Memory
  • CMOS Complementary Metal Oxide Semiconductor
  • DRAM Dynamic Random Access Memory
  • 6T SRAM two transistor
  • 3T memory gain cells are normally used for DRAM (Dynamic Random Access Memory).
  • DRAM is not as fast as 6T SRAM but is less expensive and requires less power to operate.
  • a DRAM cell stores the memory state in a capacitor and so for optimum performance DRAM i s built on separate dies for which the design of the capacitor is optimized. With a separate die, the DRAM can be made using the best or lowest cost techniques available for DRAM without regard to the logic circuitry. Nevertheless, there are still high off-state leakages that limit the retention times of the corresponding memory cell. Therefore, constant refresh cycles are required to retain the state stored in the memory. The refresh cycles require power so that DRAM al so requires constant power and generates significant heat.
  • Figure I i s a circuit diagram of a three transistor memory cell according to an
  • Figure 2 is a diagram of a three transistor memory cell array according to an
  • Figure 3 is a cross-sectional side view diagram of a memory cell with a charging transistor in a metal layer above silicon logic according to an embodiment.
  • Figure 4 is a cross-sectional side view diagram of an alternative memory cell with a charging transistor and a sensing transistor in a metal layer above silicon logic according to an embodiment.
  • Figure 5 is a process flow diagram of fabricating a three transistor memory cell according to an embodiment.
  • Figure 6 i s a block diagram of a computing device incorporating a die with a memory cell array according to an embodiment.
  • a low off-state leakage write transistor such as an amorphous oxide semiconductor (AOS ) or metal oxide semiconductor, such as IGZO ( Indium Gallium Zinc Oxide), transistor may be fabricated for use in a memory cell .
  • AOS amorphous oxide semiconductor
  • IGZO Indium Gallium Zinc Oxide
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the 3T architecture has an improved reading sense margin as compared to a 2T memory cell .
  • Non-Si based transistors such as amorphous oxide semiconductors (AOS) with high mobility and low off-state leakage current are suitable for use in very high speed memory applications, such as those normal ly reserved for SRAM
  • AOS materials can be deposited in the back end layers of a silicon die stack to allow for vertical ; 3-D integration . Stacking the memory over other logic increases the scaling density of the die.
  • Embedded memory becomes increasingly important in efforts to reduce the total number of dies and also to increase speed.
  • a reduced overall memory array footprint helps reduce aerial density scaling and cost.
  • Thi s is particularly true of memory which comes in large arrays and with traditional SRAM that uses six transistors.
  • a 3-D vertical 3 1 ' memory array that can be created in the back end layers presents real benefits.
  • the described fabrication of 3T memory provides enough speed that it can replace 6T SRAM for certain on-die memory applications, thereby allowing for higher density and lower costs.
  • 3T memory cells are used in some high speed memory applications and are the prevailing circuit for DRAM as the system memory of a computing system.
  • the gate capacitance of one of the transistors is used as the storage element and the gate capacitance of the other transistor is used as the charging element.
  • an AOS device is used as the charging element.
  • the retention time of the memory cell is limited by the total leakage in the OFF state.
  • the current in the sensing transi stor varies by orders of magnitude between a "0" or OFF state and the " 1 " or ON state, providing wide read margins.
  • the read speed depends at least in part on the speed of the sensing transi stor and the pass gate transistor.
  • Figure 1 is a circuit diagram of a single 3T memory cel l 102. It has a charging transistor
  • the drain is coupled to the gate of a read or sensing transistor 06.
  • the drain of the sensing transistor is coupled to the source of a pass gate transistor 1 10.
  • the drain of the pass gate transistor is coupled to a read bit line RBL and the gate is coupled to a read word line RWL.
  • RBL read bit line
  • RWL read word line
  • the charging or write transistor may be formed with a very low off-state leakage using a metal oxide semiconductor or AOS, such as IGZQ, 1GO, and ITO, as the channel material .
  • the sense and pass gate transistors may be fabricated with a high mobility low leakage silicon MOSFET design formed in the front side layers of a silicon die.
  • the sensing transistor may al so be formed in the metal layers using a metal oxide channel . This provides for a fast and very small sense and pass gate transistor.
  • the charge may then be stored in the drain of the charging transistor very quickly for fast w rite times. No additional capacitor is required using an AOS charging transistor. The charge may be read quickly using the sense and pass gate transistors for fast read times.
  • the channel material may be IZO ( Indium Zinc Oxide, In 2 0 3 , Sii0 2 , ITO ( Indium Tin Oxide), ZnO, or other materials. While the channel is referred to as AOS, any metal oxide may be used and the oxide may be in an amorphous, crystalline, or polycrystalline state, or it may change states during use.
  • IZO Indium Zinc Oxide, In 2 0 3 , Sii0 2 , ITO ( Indium Tin Oxide), ZnO, or other materials.
  • AOS any metal oxide may be used and the oxide may be in an amorphous, crystalline, or polycrystalline state, or it may change states during use.
  • the AOS channel construction allows the charging transistors and optionally, the sensing transistors to be fabricated in metal and dielectric without doped silicon wells.
  • the source and drain of the charge transistor may be formed in one layer while the gate electrode and WWL are in another metal layer. Different metal layers may be used to suit different implementations.
  • memory cell s may be stacked over each other so that one memory cell may use metal layers M 1 -M2 and another uses M5-M6 or any other desired pattern to suit the intended memory array design .
  • Figure 2 is an e ample of a 3T memory cel l array 1 22 with rows across the horizontal di ection and columns down the vertical di ection. The rows share bit lines and the columns share word lines. Each 3T grouping provides one bit of storage as ON or OFF. Considering one of the cells 124 in position (0, 1 ) labeled as transistor A, it is shown as storing a " 1 " or ON state.
  • This state was written by activating or setting to O or high WBL I and WWLO for as long as it takes to store a sufficient charge.
  • RBL I is charged to " 1" for a p recharge phase.
  • RWLO is pulled to "0" to select cell (1,0).
  • the other RWL' s in the row remain at “ 1.”
  • the ON or " 1" state of transistor A is then sensed on RWLO through the sense transistor.
  • Figure 3 i s a cross-sectional side view diagram of a part of a row of 3T memory cel ls in a
  • the 3T memory cell is formed as embedded memory in a die that contains other logic.
  • the other logic may be for a central processor chip, a graphics processor chip, an image processing chip, a digital signal processor, or any of a variety of other types of logic and processing circuitry.
  • the die i s built on a substrate 204, such as a silicon substrate and logic circuitry 206 is formed on the front side of the substrate. This is typically referred to as FEOL ( Front End of the Line).
  • the pass gate transistor, the sensing transistor, RBL, and RWL are formed in this front side silicon logic circuitry.
  • the application of the metal layers alternating with dielectric layers i s typically referred to as the BEOL (Back End of the Line) and is used to provide connections between the logic components, such as transistors, capacitors, resistors, etc. of the FEOL.
  • the BEOL also uses vias through the di electric between metal layers to provide connections from the logic to pads for external connections.
  • the dielectric layers are sometimes referred to as ILD ( Interlayer
  • a first layer of ILD 208 over the active logic circuitry 206 to isolate and protect the circuitry.
  • a bottom metal layer 210 is applied over one or more metal and dielectric ( ILD) layers over the logic circuitry 206.
  • the bottom metal layer may be copper, aluminum, tungsten or any other suitable metal material .
  • Thi s layer may be the seventh metal layer, M7, but may be any other layer.
  • a second dielectric layer 2 12 is applied over the bottom metal layer 2 10.
  • the dielectric layers may be formed of any of a variety of different material s including Sn0 2 , ⁇ ( Indium Tin Oxide), or IZO ( Indium Zinc Oxide).
  • a second metal layer, M8, 2 14 is applied over the second dielectric 2 12. Additional dielectric and metal layers may be applied over the second metal layer 2 14. While two metal layers are sufficient to form the charging transistor of the memory cell, there may be more layers for other purposes above and below the memory cell .
  • the memory cell is formed of a sensing transistor and a pass gate transistor (not shown) coupled together within the logic circuitry of the silicon substrate and coupled to a charging transistor in the metal layers.
  • the charging transistor 220 is built in the metal layers with a via 222 between the source 224 of the charging transistor in the first metal layer through the first dielectric 208 to the transfer gate 216, that is the gate of the sensing transistor.
  • the via may connect directly to the transfer gate or be coupled to the transfer gate through other traces, components or lines in the logic circuitry.
  • a source 220 and drain 224 are formed of the metal in the bottom metal layer 208.
  • the source and drain may also serve as contacts for the RBL and RWL and connect to control circuitry and other memory cells in an array.
  • the bottom metal layer serves as connection lines and terminals for the sensing transistor 221.
  • the charging transistor 220 has a source 224 and a drain 226 in first metal layer 210 or any other metal layer depending on the particular implementation.
  • the source 224 connects to the via 222 from the gate of the sensing transistor.
  • An amorphous oxide semiconductor ( AOS) layer 230 is formed as a channel in the dielectric layer 212 and between the source and the drain. For a typical memory cell, this layer may be 6-8nm thick and is in direct electrical contact with the source and drain.
  • the AOS material is selected for low leakage so that the charge may be stored longer with less frequent refreshes.
  • One suitable material is Indium Gallium Zinc Oxide (IGZO).
  • a high K dielectric layer 232 is formed over the AOS layer. This layer may be 5-10nm thick and the thickness is selected based on a balance of leakage and electrostatics for the device.
  • a metal gate layer 234 is formed over the high K dielectric to form the gate.
  • the metal gate is covered with a protective layer 236, such as a nitride, oxynitride or doped nitride film and with the second dielectric layer 212.
  • a conductive via 238 such as a filled copper via is formed over the gate to connect to the next metal layer 214 through the dielectric layer 212 in which the gate has been formed.
  • the charging transistor stores charge in the connection 222 between the source of the charging transistor and the gate of the sensing transistor.
  • the connection is a via through the first dielectric.
  • the sensing transistor is a thick gate, low leakage transistor. This sensing transistor will be similar to other logic circuitry Si transistors except with a thicker gate oxide. The gate oxide thickness may be balanced against capacitance and response times. The thick gate is selected to reduce the gate leakage in the sensing transistor. This improves retention times and reduces power consumption.
  • the metal gate 234 above the storage node 222 is coupled through another via 238 to a connection pad 240 on the metal layer 2 14 above the gate.
  • This connection pad serves as the gate electrode for connection to the WW L.
  • the metal layer is used for routing the WWL, connecting to other memory cells and connecting to the write circuitry and controllers in the logic circuitry layer 206.
  • These control lers may be in the logic circuitry 206 below the metal layers or in another location.
  • Other vias may be used to connect other components to form the memory array. Addressing, refresh, and read circuity may be formed in the logic circuitry 206 below the memory array and be connected to the metal layers using vertical vias.
  • This AOS storage node and charging transistor cell allows for a stack able memory array in the backend for 3D vertical embedded circuit integration that is compatible with logic processes.
  • the metal gates may be formed directly over and in contact with the metal electrodes 224, 226 of the transistor below to form a direct electrical contact.
  • the dielectric may then be formed over the metal gate and the metal oxide channel over the di electric.
  • the vi as from the next layer up reach down to contact the gate channel Accordingly, the source and drain of a transi tor i s above the gate channel and connect using vias, while the gate electrode i s below the gate and is a direct connection with the lower metal layer.
  • the source in the lower metal layer of the transi stor below becomes the storage node instead of the via.
  • Thi s inverted approach may provide for a better redistribution within the metal layers than the illustrated approach.
  • Figure 4 is a cross-sectional side view diagram of a 3D vertical configuration for a memory cel l 302 in metal layers over silicon logic circuitry.
  • the 3T memory cel l i formed as embedded memory in a die that contains other logic.
  • the other logic may be for a central processor chip, a graphics processor chip, an image processing chip, a digital signal processor, or any of a variety of other types of logic and processing circuitry.
  • the die is built on a substrate 304, such as a silicon substrate and logic circuitry 306 i s formed on the front side of the substrate.
  • a bottom metal layer 308 applied over one or more metal and dielectric ( 1 LD ) layers over the logic circuitry 306.
  • the bottom metal layer may be copper, aluminum, tungsten or any other suitable metal material .
  • This layer is indicated as the second metal layer. Ml , but may be any other layer.
  • a dielectric layer 310 is applied over the bottom metal layer.
  • the dielectric may be formed of any of a variety of different materials including Sn02, ⁇ , or IZO.
  • a second metal layer, M2, 3 1 2 is applied over the first dielectric 3 10.
  • Another dielectric 1 ayer 3 14 i s applied over the second metal layer 3 1 2 and a top metal layer, M3, 3 16 is appli ed over the second dielectric.
  • the pass gate transistor (not shown) is in the silicon logic circuitry 306 and has a balanced high speed design.
  • the sensing transistor 321 and the charging transistor 33 1 are coupled together with a via 332 between the first 308 and second 312 metal layers.
  • a source 320 and drain 324 are formed of the metal in the bottom metal layer 308. The source and drain may also serv e as contacts for the RBL and RWL and connect to control circuitry and other memory cells in an array. In this way the bottom metal layer serves as connection lines and terminals for the sensing transistor 321.
  • the gate and channel of the sensing transistor are formed in the dielectric layer 310 above the first metal layer.
  • First a layer 326 of an AOS is applied.
  • This AOS layer forms a channel and is formed of a material that is suited to the metal , dielectric layer environment and that allows for fast reads and low leakage such as ITO or IGO For a typical memory cell, this layer may be 6-8nm thick and i s in direct electrical contact w ith the source and drain.
  • the first AOS lay er 326 is covered with a high K dielectric layer 328 of e.g. 5-10nm thick, which is then covered with a metal layer 330 to form a gate over the AOS channel .
  • the thickness of the dielectric may be selected based on a balance of leakage and electrostatics for the dev ice.
  • a conductive via 332 such as a filled copper via is formed over the gate to connect to the next metal layer 3 12 through the dielectric layer 3 10 in which the gate has been formed.
  • the charging transistor 33 1 has a source 334 and a drain 336 in the next or second metal layer 3 1 2.
  • the source 334 connects to the via 332 from the gate of the sen si ng transistor.
  • a second AOS layer 340 is formed as a channel in the dielectric layer 3 14 and between the source and the drain.
  • the charging transistor has an AOS layer 340 to serve as a channel, a high K dielectric layer 342 over the AOS layer and a metal layer 346 over the high K dielectric to form the gate.
  • a different AOS material may be selected such as IGZO for still lower leakage.
  • the charging transi stor stores charge in the connection 332 between the source of the charging transi stor and the gate of the sensing transi stor.
  • the connection is a via through the dielectric.
  • the metal gate 346 abov e the storage node 332 is coupled through another via 348 to a connection pad 350 on the metal layer 316 above the gate.
  • This connection pad serves as the gate electrode for connection to the WWL.
  • the metal layer i s used for routing the WWL, connecting to other memory cells, and connecting to the write circuitry and controllers. These controllers may be in the logic circuitry 306 below the metal layers or in another location.
  • Other vias 352 may be used to connect other components to form the memory array. Addressing, refresh, and read circuity may be formed in the logic circuitry 306 below the memory array and be connected to the metal layers using vertical vias 352.
  • This all AOS memory cell allows for a stackable memory array in the backend for 3D vertical embedded circuit integration that is compatible with logic processes.
  • the higher mobility AOS will al so allow for faster reading of the memory value stored in the storage node.
  • both the AOS channel 326, 340 and the high K dielectric 328, 342 wrap around the sides of the metal gate.
  • the bottom of the gate over the source and drain and the sides of the gate within the dielectric layer are covered by these two layers.
  • the films are deposited include a pre-formed trench between the source and the drain. As a result the IGZO channel is deposited without any damage to the film
  • Figure 5 is a process flow diagram for forming a 3T memory cell array with charging transistors in BEOL layers as shown in Figure 3.
  • the logic circuitry is formed on the silicon die, thi s includes the sensing transistor and the pass gate transistor for each memory cell of the array.
  • the sensing transistor and the pass gate transistor are designed for low leakage with thick gates and for fast reads.
  • the logic circuitry layer also includes the RBL, RWL, and WWL for the memory cell and the necessary circuitry to activate and drive these li nes.
  • an interlayer dielectric is applied over the logic circuitry. There may al so be other layers applied over the logic circuitry depending on the particular implementation.
  • a CMP chemical metal planarization
  • a via is formed over the gate of the sensing transistor by etching an opening into the planarized ILD and then filling the opening with copper or another suitable conductor.
  • the metal layer is then patterned and applied at 508 over the via and the rest of the dielectric to form the source and drain areas of the charging transistor.
  • the next layer of dielectric is applied over the second metal layer.
  • the metal may first be planarized and protected with a nitride etch stop layer before the next layer of ILD is applied.
  • the dielectric is etched to open areas for an AOS channel and metal gate.
  • the ILD and nitride etch stop layer are removed to expose the metal lines
  • a blanket AOS deposition is made using e.g. CVD so that the AOS is in contact with the source and drain of the charging transistor.
  • an AOS with a low off state leakage such as IGZO is chosen to reduce the refresh rate of the memory cell .
  • the AOS deposition may be done using CVD (Chemical Vapor Deposition) or in any of a variety of other ways.
  • CVD Chemical Vapor Deposition
  • a high K dielectric is appli ed using, for example, ALD (Atomic Layer Deposition) or any of a variety of other techniques.
  • a fill metal is deposited to form the gate of the charging transistor.
  • a damascene approach may be used.
  • the deposit may be only on the bottom of the opening as shown in Figure 3 or al so on the sidewalls of each previous layer.
  • the deposits are blanket layer deposition so that the AOS material is in contact with the source and the drain .
  • CMP i used again to planarize the CDN over the metal of the gate.
  • a nitride etch stop deposition is performed over the gate metal at 522 then ILD is deposited to form the level of the next metal layer.
  • the ILD is planarized and then the via to the metal gate is formed.
  • openings are etched for vias to the metal gate and to the lower metal layers for any other desired connections and at 526 these are filled with a conductor.
  • the next metal layer with a gate electrode and any other routing such as WBL are formed in the next metal layer.
  • the die is finished with routing layers, contact pads, solder ball s and any other desired components. Additional operations may al so be applied to the back side of the die, such as thinning, applying heat spreaders and other operations.
  • Figure 6 i llustrates a computing device I 1 in accordance with one implementation.
  • the computing device 1 1 houses a board 2.
  • the board 2 may include a number of components, including but not limited to a processor 4 and at least one communication chip 6.
  • the processor 4 is physically and electrically coupled to the board 2.
  • the at least one communication chip 6 i s also physically and electrically coupled to the board 2.
  • the communication chip 6 is part of the processor 4.
  • computing device 1 1 may include other components that may or may not be physically and electricall y coupled to the board 2.
  • these other components include, but are not limited to, volatile memory (e.g., DRAM ) 8, non -volatile memory (e.g., ROM) 9, flash memory (not shown), a graphics processor 1 2, a digital signal processor (not shown ), a crypto processor (not shown), a chipset 14, an antenna 16, a display 1 8 such as a touchscreen display, a touchscreen controller 20, a battery 22, an audio codec (not shown ), a video codec (not shown), a power amplifier 24, a global positioning system (GPS) device 26, a compass 28, an accelerometer (not shown), a gyroscope (not shown), a speaker 30, a camera 32, and a mass storage device (such as hard disk drive) 10, compact disk (CD) (not shown), digital versatile disk (DVD ) (not shown), and so forth).
  • volatile memory e.g., DRAM
  • the communication chip 6 enables wireless and/or wired communications for the transfer of data to and from the computing devi ce 1 1.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium . The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 6 may implement any of a number of wireless or wired standards or protocol s, including but not limited to Wi-Fi ( IEEE 802. 1 1 family), WiMAX ( IEEE 802.16 family).
  • the computing device 1 1 may include a plurality of communication chips 6.
  • a first communication chip 6 may be dedicated to shorter range wireless communications such as Wi -Fi and Bluetooth and a second
  • communication chip 6 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the integrated circuit die of the processor, memory devices, communication devices, or other components are fabricated to include three transistor memory cell s w ith an AOS as described herein.
  • the described memory cel ls may be embedded as memory for other components in a CMOS or other logic processing die or a standalone memory array may be made on its own die.
  • processor may refer to any device or portion of a device that processes electronic data from registers and/ or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the computing device I 1 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA ), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 1 1 may be any other electronic device that processes data including a wearable device.
  • Embodiments may be implemented as a part of one or more memory chips, controllers, CPUs (Central Processing Unit), microchips or integrated circuits interconnected using a motherboard, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA).
  • CPUs Central Processing Unit
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • references to “one embodiment”, “an embodiment”, “example embodiment”, “various embodiments”, etc., indicate that the embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.
  • Coupled is used to indicate that two or more elements co-operate or interact with each other, but they may or may not have intervening physical or electrical components between them .
  • Some embodiments pertain to a memory cell that includes a pass gate transistor having a source coupled to a read bit line and a gate coupled to a read word line, a sensing transistor having a source coupled to a drain of the pass gate transistor, a charging transistor having a source and a drain in a first metal layer and a gate between the source and the drain, herein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor, wherein the source of the charging transi stor is coupled to the gate of the sensing transistor, and a gate electrode in a second metal layer coupled to the gate of the charging transistor.
  • the metal oxide semiconductor is an amorphous oxide semiconductor.
  • the metal oxide semiconductor of the charging transistor is selected as a low off state leakage material.
  • the metal oxide semiconductor of the charging transistor is an indium gallium zinc oxide.
  • Further embodiments include a conductive via through the interlayer dielectric coupled to the gate of the sensing transistor and to the source of the charging transistor, the via forming a storage node of the charging transistor.
  • the gate electrode is coupled to the metal of the gate through the conductive via.
  • the first metal layer is on a semiconductor die over logic circuitry of the die and wherein the second metal layer is over the first metal layer.
  • the pass gate transistor and the sensing transistor are thick gate transistors in the logic ci rcuitry of the die having higher mobility than the charging transistor.
  • the sensing transi stor has a source and a drain in a third metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor material .
  • the metal oxide semiconductor material of the sensing transistor is an indium gallium oxide or an indium tin oxide.
  • Further embodiments include a write bit line coupled to the first metal layer and a write word line in the second metal layer.
  • Some embodiments pertain to a method that includes patterning logic ci cuitry over a silicon substrate to form a pass gate transi stor and a sensing transi stor in the silicon of the silicon substrate, applying a first interlayer dielectric (ILD) over the logic circuitry, forming a via over the gate of the sensing transistor, patterning a first metal layer to form a source and a drain of a charging transi stor over the gate of the sensing transi stor wherein the source of the charging transistor is coupled to the via, applying a second II .D over the first metal layer, depositing a low off state leakage metal oxide semiconductor material in an opening in the second ILD as charging transistor gate channel, depositing a metal over the charging transistor gate channel as a gate, forming a second via over the charging transistor gate, and patterning a third metal layer with a gate electrode coupled to the second via.
  • ILD interlayer dielectric
  • the low off state leakage metal oxide semiconductor is an indium gallium zinc oxide.
  • Some embodiments pertain to a computing system that includes a memory having instructions stored thereon, and a processor coupled to the memory to execute the instructions, the processor having silicon logic circuitry formed on a si licon substrate and embedded memory, the embedded memory having a pass gate transistor having a source coupled to a read bit line and a gate coupled to a read word line, a sensing transi stor having a source coupled to a drain of the pass gate transistor, a charging transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor, wherein the source of the charging transistor is coupled to the gate of the sensing transistor, and a gate electrode in a second metal layer coupled to the gate of the charging transi stor.
  • the metal oxide semiconductor is crystalline.
  • FIG. 1 Further embodi ments include an interlayer dielectric between the first metal layer and the gate of the sensing transistor, and a conductive via through the interlayer dielectric coupled to the gate of the sensing transistor and to the source of the charging transi stor, the via forming a storage node of the charging transistor.
  • the embedded memory comprises a plurality of sensing transistors and charging transi stors in an array coupled to a shared write bit line and a shared w rite word line.

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne une cellule de mémoire à trois transistors avec des semi-conducteurs à oxyde métallique. Dans certains exemples, la cellule de mémoire comporte un transistor à grille de passage ayant une source couplée à une ligne de bits de lecture et une grille couplée à une ligne de mots de lecture, un transistor de détection ayant une source couplée à un drain du transistor à grille de passage, un transistor de charge ayant une source et un drain dans une première couche métallique et une grille entre la source et le drain, la grille présentant un canal situé entre la source et le drain et couplé à ceux-ci, le canal étant constitué d'un semi-conducteur à oxyde métallique, la source du transistor de charge étant couplée à la grille du transistor de détection, et une électrode de grille dans une seconde couche métallique étant couplée à la grille du transistor de charge.
PCT/US2016/040715 2016-07-01 2016-07-01 Cellule de mémoire à trois transistors avec semi-conducteurs à oxyde métallique et transistors à base de si Ceased WO2018004659A1 (fr)

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WO2024093178A1 (fr) * 2022-11-01 2024-05-10 北京超弦存储器研究院 Mémoire et dispositif électronique

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WO2024093178A1 (fr) * 2022-11-01 2024-05-10 北京超弦存储器研究院 Mémoire et dispositif électronique

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