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WO2018001451A1 - Parallélisation d'un précodeur de tomlinson-harashima pour transmission mimo dans un système dsl - Google Patents

Parallélisation d'un précodeur de tomlinson-harashima pour transmission mimo dans un système dsl Download PDF

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Publication number
WO2018001451A1
WO2018001451A1 PCT/EP2016/064894 EP2016064894W WO2018001451A1 WO 2018001451 A1 WO2018001451 A1 WO 2018001451A1 EP 2016064894 W EP2016064894 W EP 2016064894W WO 2018001451 A1 WO2018001451 A1 WO 2018001451A1
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Prior art keywords
dslam
matrix
sub
signals
linear
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PCT/EP2016/064894
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English (en)
Inventor
Xiang Wang
Syed-Hassan-Raza NAQVI
Andrea MATERA
Umberto Spagnolini
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Huawei Technologies Co Ltd
Politecnico di Milano
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Huawei Technologies Co Ltd
Politecnico di Milano
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Priority to PCT/EP2016/064894 priority Critical patent/WO2018001451A1/fr
Publication of WO2018001451A1 publication Critical patent/WO2018001451A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/32—Reducing cross-talk, e.g. by compensating
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03343—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/497—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems
    • H04L25/4975—Correlative coding using Tomlinson precoding, Harashima precoding, Trellis precoding or GPRS

Definitions

  • the present invention refers to a Digital Subscriber Line Access Multiplexer, DSLAM, apparatus, a corresponding coding method for a DSLAM apparatus and a computer program adapted to perform the steps of the coding method.
  • the data rate of xDSL systems is maximized if crosstalk among the twisted pairs in the cable binder is properly cancelled.
  • the crosstalk in a cable binder is the result of inductive and capacitive coupling between the twisted pairs and it causes severe performance degradation if not handled properly.
  • the cross coupling between the lines at opposite ends of the cable binder is called Far End Crosstalk, FEXT, and limits the data rate of DSL systems. It must be properly mitigated through multi-user detection and precoding techniques in upstream and downstream transmission respectively.
  • DSL Access Multiplexer, DSLAM, devices contain a Vectoring Processor, VP that uses precoding and multiuser detection techniques to mitigate FEXT in downstream and upstream directions, respectively.
  • Vectoring as defined by the ITU-T G.993.5 standard, can greatly improve the performance of DSL networks.
  • Vectoring is mandatory to mitigate the crosstalk among the copper lines in the same vectored group, i.e., In-Domain, ID, self-FEXT, in high frequency (e.g. >50MHz) and high data rate DSL systems.
  • DSL is severely impaired by the crosstalk from other vectored groups (out- of-domain (OD) FEXT) sharing the same cable binder, if not properly accounted.
  • Cooperation among VPs is mandatory in a multi-VP-Group scenario (an implementation example would be a multi DSLAM situation, where each DSLAM implements one VP group) where multiple vectoring groups coexist in a same cable binder.
  • Dynamic Spectrum Management, DSM can cope with OD FEXT in multi vectoring group scenario.
  • DSM could be beneficial against the OD FEXT and alien-FEXT, but it requires an external processing unit that hosts complex spectrum management algorithms to balance all the lines.
  • DSM techniques may not maximize the data rate of all the lines in the cable binder, and it is even worse when FEXT channel becomes so severe to be comparable with direct channel insertion loss, IL as for high frequency band (e.g., >30MHz).
  • Centralized vectoring where a single Vectoring Processor is employed for precoding to cancel all FEXT, is a straightforward solution to any FEXT but these solutions are not feasible for larger cable binders (that carry hundreds of twisted pairs) due to processing delay in conventional Tomlinson-Harashima Precoding (THP) as it is based on sequential processing.
  • TTP Tomlinson-Harashima Precoding
  • the objective of the present invention is therefore to minimize the processing delay associated with conventional THP and provide the scalable solution through parallel THP.
  • the invention provides a DSLAM structure, a coding method for a DSLAM apparatus, and a corresponding computer program, which provide a flexible and scalable way to perform downstream FEXT- Cancellation by parallelizing the conventional THP architecture.
  • a first aspect of the present invention provides a Digital Subscriber Line Access Multiplexer, DSLAM, structure comprising at least two encoders, ECs, to encode signals into encoded signals, wherein at least one of the ECs is an independent Tomlinson-Harashima-Precoding, THP, structure comprising a feedback matrix processor and a modulo operator, and a linear precoder, LP, comprising an encoding matrix, to process said encoded signals into transmission signals to be transmitted through a multiple-input-multiple-output, MIMO, channel.
  • the MIMO channel models an ensemble of a number of physical cables.
  • said LP comprises at least two first sub-linear precoders, each one of said first sub-linear precoders corresponding to one of said ECs, respectively, and a second sub-linear precoder.
  • the second sub-linear precoder is adapted to mitigate the interference among output signals from the at least two of the said first sub-linear precoders.
  • the second sub-linear precoder is a linear precoder adapted to linearly mitigate interference between signals from the first sub-linear precoders.
  • the linear precoder is a block diagonalization processor adapted to perform block diagonalization processing on the signals from the first sub-linear precoders.
  • each of the first sub-linear precoders comprises a feed-forward matrix processor.
  • the matrix elements of the ECs and the LP are calculated based on the MIMO channel.
  • the matrix of the feedback matrix processor is an upper triangular matrix.
  • the matrix of the feedback matrix processor is a lower triangular matrix.
  • a second aspect of the present invention provides a coding method for a Digital Subscriber Line
  • DSLAM Downlink Access Multiplexer
  • structure comprising the steps of encoding, in at least two encoders, ECs, signals into encoded signals, wherein at least one of the ECs is an independent Tomlinson-Harashima-Precoding, THP, structure comprising a feedback matrix processor and a modulo operator, and processing, in a linear precoder, LP, comprising an encoding matrix, said encoded signals into transmission signals to be transmitted through a multiple-input-multiple- output, MIMO, channel.
  • THP Tomlinson-Harashima-Precoding
  • LP linear precoder
  • said LP comprises at least two first sub-linear precoders, each one of said first- sub-linear precoders corresponding to one of said ECs, respectively, and a second sub-linear precoder.
  • the second sub-linear precoder mitigates the interference among output signals from the at least two of the said first sub-linear precoders.
  • the second sub-linear precoder is a linear precoder which linearly mitigates interference between signals from the first sub-linear precoders.
  • the linear precoder is a block diagonalization processor which performs block diagonalization processing on the signals from the first sub-linear precoders.
  • each of the first sub-linear precoders comprises a feed-forward matrix processor.
  • the matrix elements of the ECs and the LP are calculated based on the MIMO channel.
  • the matrix of the feedback matrix processor is an upper triangular matrix.
  • the matrix of the feedback matrix processor is a lower triangular matrix.
  • DSLAM Digital Subscriber Line Access Multiplexer
  • a novel Distributed Block Diagonal Tomlinson-Harashima Precoding, D-BD-THP, scheme for downstream FEXT cancellation in a single- or multi- VP-Group DSL structure is established through VPs cooperation (here a single VP can be assumed in an independent DSLAM device, however a single DSLAM device can also host multiple VP modules within a single integrated circuit, or multiple integrated circuits or cards that are interconnected within the IC, or via ultra-high speed copper traces or backplane, respectively).
  • the THP structure corresponds to and implements the functionality of a VP.
  • the LP and specifically its second sub-linear precoder corresponds to and implements the functionality of the FEXT cancellation of VP-groups by a BD processor or any of the technically equivalent variants of a BD processor.
  • the present invention is focused on the parallelization of nonlinear THP processor through a predefined inter- VPs signaling. In this way also the sequential processing delay inherent to conventional serial THP is reduced due to the new parallel structure. Also, by the parallelization of the nonlinear THP processor, Legacy CPEs which support only linear Vectoring can coexist with the CPEs supporting nonlinear THP encoder in the same system, whereas the FEXT are mitigated.
  • D-BD-THP are based on Linear Precoder, LP, and THP for OD FEXT and ID self-FEXT mitigation, respectively.
  • the information exchange in D- BD-THP enables all the VPs to perform vectoring from the local vectoring engine.
  • Each VP exchanges the precoded data for its own CPEs with all the other VPs to cooperatively build the transmitted signal in such a way that both OD FEXT and ID self-FEXT are nullified or mitigated at the Customer Premises Equipments, CPEs.
  • the exchanging of precoded data has the benefit to enable each VP to encode data for the benefit of the other VPs (and in turn, of itself).
  • the present invention proposes a parallel architecture for carrying out nonlinear precoding such as THP by using an ensemble of Vector Processors, VPs, which can be arbitrarily aggregated in number depending on the number of vectored groups and on the strategy used to pair VPs to copper lines.
  • the ensemble of VPs can be arbitrarily augmented provided that a suitable signalling is deployed among the VPs using any signaling architecture (i.e., bus, star, all- to-all, etc.).
  • any signaling architecture i.e., bus, star, all- to-all, etc.
  • D-BD-THP denotes a combination of BD and THP, but it should be noted that the invention covers the implementation of other suitable LP techniques instead of BD.
  • Another part of the invention is the further degree of freedom provided by the choice of the strategy used for the pairing of the copper lines to different VPs: an example is that the groups of lines assigned to different processors minimally interfere with each other as this solution eases the inter- VP interference cancellation processing carried out by LP.
  • Fig. 1 shows a schematic block diagram of a DSLAM structure according to an embodiment of the invention
  • Fig. 2 shows a more detailed block diagram of the DSLAM structure of Fig. 1, and
  • Fig. 3 shows the schematic structure of a THP processor of the DSLAM structure of Fig.
  • Fig. 1 shows a symmetric block diagram of the DSLAM structure 1 according to the invention, which encodes incoming signals Si and Sk into transmission signals.
  • the incoming signals Si and Sk may be vector signals corresponding to one or more users.
  • the transmission signals are transmitted by means of MIMO channel 4 (which models a number of physical cables) to a number of consumer premises entities 5i, 52, 5t and 5N.
  • the DSLAM comprises, in the example shown in Fig.
  • the number of two sub-signals is only an example, and that any number of sub-signals may be grouped into a signal Si or Sk.
  • the shown and claimed DSLAM structure 1 can be implemented in different ways.
  • the DSLAM structure 1 as shown in Fig. 1 and described later on in detail, could be implemented in a single physical DSLAM device.
  • the DSLAM structure 1 could be separated into different physical entities such as circuits, or cards, or integrated circuits, or any combination, including programmable entities implementing the claimed processing steps by software.
  • the ECs 2 could be implemented in a single physical DSLAM device, and the LP 3 could be implemented in a separate physical device.
  • each DSLAM device could also be implemented into separate individual DSLAM devices, i.e. each DSLAM device then would comprise only a single EC 2.
  • Each EC 2 comprises a feedback matrix processor 8 and a modulo operator (or processor) 7, which is schematically shown in Fig. 2 and in more technical detail in Fig. 3.
  • the LP 3 comprises two or more first sub-linear precoders 8, wherein each sub-linear precoder 8 is allocated to and corresponds to one of the ECs 2, i.e. receives the encoded signals from the respectively allocated EC 2, as well as a second sub-linear precoder 12.
  • the second sub-linear precoder 12 is a linear precoder which is adapted to linearly mitigate the interference between the signals output from the various first sub-linear precoders 8.
  • Each of the first sub-linear precoders 8 comprises a feed-forward matrix processor, i.e. an entity which processes a feedforward matrix ⁇ , ⁇ , which will be explained in more detail below.
  • the feedback matrix processor 6 of each of the ECs 2 comprises a feedback matrix Bb,K, which can for example be either an upper triangular matrix, or a lower triangular matrix, or any other suitable matrix.
  • the term processor as used in the present application, is intended to define any kind of entity or structure which is adapted to perform the mathematical processing on the basis of the described matrices. It will be described in more detail below that the matrix elements of the feed-forward matrix ⁇ , ⁇ and the feedback matrix Bb,K, as well as the matrix elements of the encoding matrix of the LP 3 are calculated based on the characteristics of the MIMO channel 4.
  • the reference number 2 is used to represent the number of ECs 2i ... 2k ... 2 ⁇ .
  • the reference number 6 is used to characterise the number of feedback matrix processers 6i ... 6* ... 6 ⁇ .
  • the reference number 7 is used to characterise the modulo processers 7i ... Ik ... IK.
  • the reference number 8 is used to characterise the feed-forward matrix processors 8i ... 8A ... $ ⁇ .
  • the reference number 5 is used to characterise the various CPEs 5i ... 5t ... 5N.
  • the term encoder, EC as used in the claims as well as in the present description defines processing functionalities (i.e. the functionalities of the feedback matrix processor 6 and the modulo operator 7) which can be implemented in respective vector processors VPs, 1 l i ... 11* ...
  • the LP 3 is defined as consisting of the two or more first sub-linear precoders 8 and the second sub-linear precoder 12.
  • the second sub-linear precoder 12 is described, in the following, by means of the functionality of the BD processor 12.
  • THP is a non-linear precoding technique that compensates ID self-FEXT without uncontrollably increasing the Power Spectral Density, PSD.
  • Technical details and definitions of THP are, e.g., explained in "A multi-user Precoding Scheme achieving Crosstalk Cancellation with application to DSL Systems" by G.
  • the present invention is applicable to a Multi-VP-Group DSL structure 1 for downstream, as, e.g., shown in more detail in Fig. 2, where ⁇ Vector Groups that share the same cable binder are interfering with each other when transmitting over the CPEs 5.
  • a DSLAM comprises one EC 2 in the following example:
  • the km Vector Group serves a group composed by Nk customer premises equipments, CPEs, and their number is arbitrarily different (i.e., Ni ⁇ N2 ⁇ . . . ⁇ NK).
  • the DSLAM hosts a single VP 1 1 for ID self-FEXT cancellation using THP.
  • the compound received signal at the group of Ni CPEs 5 of km Vector Group is "y*" that is achieved when the transmitted precoded signals "x" from all the Vector Groups passes through the DSL channel H (MIMO Channel 4).
  • the VP 1 1 of each Vector Group cancels ID self-FEXT using THP.
  • the THP processing at km Vector Group is based on QR decomposition of the channel matrix "Hut”.
  • the transmitted symbol vector "x*" is obtained by mixing " with feed- forward matrix "Bp".
  • the feedforward (Bp) and feedback ('3 ⁇ 4>,*") matrices are functions of "Q" (unitary) and “R” (upper triangular/lower triangular) matrices of the feedforward matrix processors 8 and the feedback matrix processors 6, respectively, that are achieved by the QR factorization of channel matrix "Hj ⁇ ".
  • the received signal vector "y*" at the CPEs 5t to 5N of km Vector Group is then potentially heavily interfered due to the crosstalk from all the other K-l Vector Groups (i.e. OD FEXT).
  • the DSLAM processing time of one symbol is one time unit (due to back substitution processing in feedback filter '3 ⁇ 4>,/")
  • the overall processing time is 100 time units for only one transmitted symbol for each of the 100 CPEs.
  • the processing delay increases in conventional THP with the increase in number of CPEs, hence centralized vectoring using serial THP is unfeasible for the scalable solution.
  • the present invention proposes a Block Diagonalization, BD precoding scheme, the basic functionalities of which were previously proposed by Spencer et al. ("Zero-Forcing Methods for Downlink Spatial Multiplexing in Multiuser MIMO Channels", IEEE Transactions on Signal Processing, Vol. 52, No. 2, Feb. 2004) for a Multi-User, MU, wireless Multiple-Input and Multiple-Output, MIMO, systems, but which are redesigned according to the present invention for a DSL network.
  • the VP encoding and communication to each CPE in a DSL system is not a MIMO system but rather it is a multiple CPEs MISO system.
  • the block precoding in the BD processor 12 of the LP 3 is adapted to orthogonalize each transmitted signal with respect to all the receiving CPEs, and thus the signal intended for each CPE lies in the null space of all the others.
  • block diagonalization turns the compound MU-MIMO channel into a parallel of Single-User MIMO, SU-MIMO, channels.
  • the BD proposed for DSL in this disclosure turns the compound large MISO DSL system into smaller parallel MISO DSL groups where OD self-FEXT is mitigated. Once the OD self-FEXT is mitigated, non-linear precoding is used to eliminate, or mitigate, ID self-FEXT.
  • the proposed D-BD-THP scheme of the invention offers parallelization of THP that can cope with the unavoidable latency of the conventional THP.
  • a distributed precoding technique for FEXT-cancellation in downstream data transfer based on inter- VP cooperation in multi-VP-Group (or equivalently multi-VP-Group) setting is proposed.
  • the precoding scheme for multi-VP-Group/multi-user channel matrix mitigates the OD FEXT using the Block Diagonalization, BD, of the ensemble channel matrix for all Vector Groups.
  • Each VP 1 1 precodes the transmit data using local available information (portion of channel matrix and own CPE data that is available in high speed local memory) that minimizes the OD FEXT toward all the others, still maximizing the utility for itself, and stores it in the system memory that is accessible by all the VPs.
  • Conventional THP is adopted for ID self-FEXT mitigation after BD.
  • Proposed D-BD-THP precoding attains the performance of centralized THP -vectoring where one single processing unit mitigates ID and OD FEXT for all the VPs.
  • BD in the BD processor 12 is used to precode signals for OD FEXT cancellation that transforms the Multi Vector Groups MISO, MD-MISO, system (in Fig. 2) into K parallel Vector Group MISO, SD- MISO, systems. THP is then applied by the VPs 11 to each SD-MISO to compensate the ID self- FEXT.
  • the proposed D-BD-THP enables a distributed implementation of THP by inter- VPs signalling to ensure that each Vector Group can intelligently use the other Vector Groups to relay the signal for its own CPEs that nullifies toward the CPEs of the other Vector Groups.
  • the cooperation among Vector Groups for D-BD- THP is based on cross connections among all VPs of all the Vector Groups established through ultra-high speed backplane as shown in Fig. 2.
  • An implementation example of the VP 11 is shown in Fig. 3.
  • D-BD-THP scheme is outlined in Fig. 2, where the new part is the BD processor block 12 downstream of the THP processors 11.
  • This block 12 enables the exchange of signals among the VPs 11 to implement the full equivalence in parallelization.
  • the proposed scheme provides interconnections between the VPs 11 such that each VP 11 accepts some partial processed data from other VPs 11 to enable the full parallelization of the naturally serial processing.
  • the benefit is that the new block 12 can be plugged as an add-on device enabling the parallelization of a multitude of VPs 11 that, if used alone, would not mitigate the OD FEXT across cluster of lines belonging to different VPs 11.
  • Vector Group is the ensemble channel matrix that includes all the rows of block partitioned channel matrix H except the kth row belonging to the CPEs of kth Vector Group.
  • the algebraic null space analysis of the complementary channel matrix H k determines the BD precoder Mk for kth Vector Group that is obtained by the singular value decomposition, SVD, of ll k .
  • precoding matrix Mk reference number 9* for the BD at the km Vector Group is simply generated from the right singular vectors of ⁇ 3 ⁇ 4 . corresponding to the "zero" singular values.
  • the coefficients of feed-forward (Bp) and feedback (Bb,k) filters in THP can be computed by the QR factorization of the effective channel "HiMt" for ID self-FEXT mitigation at km Vector Group.
  • the effective channel in D- BD-THP at km Vector Group is "HAM*”.
  • modulo operator " ⁇ ⁇ " 7 in D-BD-THP is the same as in conventional THP.
  • the THP is split into a feedback (B fc;i ) and feed-forward (By ;i ) from the QR decomposition of the effective SD-MISO channel:
  • y A diag(R A )s A +w A .
  • each VP 11 precodes its own CPE data locally.
  • VP filters the M-QAM data symbols "s*" by its local THP block.
  • the output of THP ( s k ) is then precoded by the BD filter Mi.
  • inter- VPs signalling is performed.
  • VP at kth Vector Group forwards the row blocks ⁇ M mk s k ⁇ of its own precoded symbols to all K-l Vector Groups to cancel OD FEXT.
  • the received signal at the CPEs of kt Vector Group is thus with significantly reduced FEXT as in centralized vectoring.
  • D-BD-THP is a flexible and scalable architecture that performs downstream FEXT-cancellation by parallelizing the THP nonlinear processing.
  • the conventional multi-VP-Group system that serially performs centralized THP, we parallelize the processing onto an arbitrary number of VPs, each one performing serial THP for a subset of lines (arbitrarily selected) in parallel with the other VPs.
  • the resulting inter- VPs interference is cancelled by proper inter- VPs signalling.
  • the signal processing delay introduced by the sequential interference cancellation of conventional nonlinear precoding is reduced.
  • the plurality of non-linear precoders such as THPs can be aggregated to form a larger THP for the ensemble of CPEs, wherein each of the precoding unit can be a card, or a circuit, or an integrated circuit, or implemented over a general purpose processing unit programmable by a software code.
  • D-BD-THP Another key advantage of the proposed D-BD-THP is that it allows coexistence of legacy linearly-precoded lines with new nonlinear THP-precoded lines.
  • the legacy lines may be grouped into one or more VPs while the new THP-precoded lines may be grouped into one or more other VPs. This feature enables a service provider to smoothly upgrade from a legacy linear system to all THP-precoded system.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
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Abstract

Un multiplexeur d'accès de ligne d'abonné numérique, DSLAM, une structure (1) comprenant au moins deux codeurs, EC (2), et un précodeur linéaire, LP (3). Les EC codent des signaux en signaux codés. Au moins un des EC est une structure indépendante du précodeur Tomlinson-Harashima, THP, comprenant un processeur de matrice de rétroaction (6) et un opérateur modulo (7). Le LP (3) comprend une matrice de codage et traite les signaux codés en signaux de transmission pour une transmission par l'intermédiaire d'un canal MIMO (4) à entrées multiples et sorties multiples.
PCT/EP2016/064894 2016-06-27 2016-06-27 Parallélisation d'un précodeur de tomlinson-harashima pour transmission mimo dans un système dsl Ceased WO2018001451A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2672661A2 (fr) * 2011-05-18 2013-12-11 Huawei Technologies Co., Ltd. Procédé, système et monocarte de ligne d'abonné numérique vectorisée, dispositif de multiplexage d'accès de ligne d'abonné numérique
EP3032789A1 (fr) * 2014-12-11 2016-06-15 Alcatel Lucent Précodage non linéaire avec un mélange de lignes capables NLP et non-capables NLP

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2672661A2 (fr) * 2011-05-18 2013-12-11 Huawei Technologies Co., Ltd. Procédé, système et monocarte de ligne d'abonné numérique vectorisée, dispositif de multiplexage d'accès de ligne d'abonné numérique
EP3032789A1 (fr) * 2014-12-11 2016-06-15 Alcatel Lucent Précodage non linéaire avec un mélange de lignes capables NLP et non-capables NLP

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
G. GINIS; JOHN M. CIOFFI: "A multi-user Precoding Scheme achieving Crosstalk Cancellation with application to DSL Systems", CONFERENCE RECORD OF THE THIRTY-FOURTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTER, vol. 2, 2000, pages 1627 - 1631
HEKRDLA MIROSLAV ET AL: "Interference-sharing multi-operator cooperation for downlink precoding in cloud-RAN architecture", 2016 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS WORKSHOPS (ICC), IEEE, 23 May 2016 (2016-05-23), pages 128 - 133, XP032919854, DOI: 10.1109/ICCW.2016.7503776 *
SPENCER ET AL.: "Zero-Forcing Methods for Downlink Spatial Multiplexing in Multiuser MIMO Channels", IEEE TRANSACTIONS ON SIGNAL PROCESSING, vol. 52, no. 2, February 2004 (2004-02-01), XP011105731, DOI: doi:10.1109/TSP.2003.821107

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