WO2018001453A1

WO2018001453A1 - Linear-in-db variable gain amplifier

Info

Publication number: WO2018001453A1
Application number: PCT/EP2016/064915
Authority: WO
Inventors: Helen Waite
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-06-28
Filing date: 2016-06-28
Publication date: 2018-01-04
Anticipated expiration: 2018-12-28
Also published as: CN109417366B; CN109417366A

Abstract

A variable gain amplifier (1) is configured to amplify an input signal (I_{vga_ in}) with a variable gain, resulting in a linear-in-db output signal (I_{vga_out}). The variable gain amplifier (1) comprises a linear-in-db control current generator (2), a control voltage generator (3) and an output current regulator (4). The linear-in-db control current generator (2) is configured to generate a linear-in-db control current (I_{Iin_ in_dB}) based on a predefined gain setting. The control voltage generator (3) is configured to generate a control voltage (V_{vga_ctrl}) from the linear-in-db control current (I_{lin_ in_dB}). The output current regulator (4) is adapted to generate the linear-in-db output signal (Ivga_out) based on the input signal (I_{vga_in}) and the control voltage (V_{vga_ctrl}).

Description

LINEAR-IN-DB VARIABLE GAIN AMPLIFIER

TECHNICAL FIELD The invention relates to variable gain amplifiers, especially variable gain amplifiers which can be very accurately controlled.

BACKGROUND Achieving fine and accurate gain steps in variable gain amplifiers over a wide gain range and a wide signal bandwidth, e.g. >500MHz and at the same time assuring high linearity has proven difficult to achieve. This is especially due to the limited bandwidth of existing implementations. For 5G communications systems, signal bandwidths will be even higher than in existing 2G/3G/4G communications systems. Therefore, achieving sufficient performance over a wide bandwidth becomes significant.

These issues may be targeted as follows:

1. A closed loop or open loop approach where a resistor array is used and a resistor value is switched to set the required gain can be employed. In a closed loop approach this may be achieved by switching the input resistor or feedback resistor of a closed loop amplifier arrangement. In an open-loop approach, either a degeneration resistor or load resistor could be switched. The limitations and disadvantages of this approach are:

When many gain steps are required a large resistor switching array is necessary. This results in significant parasitic capacitance from the switches and from the layout of the resistor array. These parasitic capacitances act to limit the supported bandwidth.

For fine gain steps, it is not always easy to realize the gain steps particularly when the gain steps need to be realized in dB. Resistor arrays are more suited to using a unit resistance value due to matching considerations, and this does not lend itself to the implementation of fine step realized in dB. Also, the switch resistance contributes to the overall resistance and needs to be considered. The range of resistor values that can be used to implement the gain control is generally somewhat limited because of the loading effect of the active devices of the amplifier. Once resistor values increase and start to approach output impedance values then the accuracy of the gain step is lost. This can limit the achievable gain range using resistor arrays to vary the gain. The minimum resistance size can also be limited in this type of arrangement as the switch resistance needs to be considered.

Resistor ladder networks can be used to achieve accurate gain control, with taps from different points in the resistive ladder for the different gain steps. In this case a large array of resistors is required, and the achievable steps are set by the resistors of the resistive ladder. The limitations and disadvantages of this are:

The resistive ladder has a limited number of fixed gain steps set by the resistor values chosen.

The resistor array can become very large, the ratios depend on the required gain step, and each gain step requires additional resistors in the ladder.

The loading of the resistor array can limit the bandwidth, which can be a limiting point when bandwidth requirements are large.

A voltage mode linear in dB amplifier approach offers flexibility regarding gain steps. This makes use of the exponential relationship of a bipolar device. A linear current is used as a control current to generate a linear in dB current. This linear in dB current is then used as a bias current for a bipolar device.

The transfer function of the bipolar gain gm=(Ic/Vt) is proportional to the current (Ic) and so gain steps in dB can be obtained. The limitations and disadvantages of this are:

The linearity of the amplifier is limited by the linearity of the bipolar device. Usually linearization techniques could be applied to improve the bipolar linearity, but these result in either limited improvements in linearity, e.g. multi-tanh, or too much complexity. Some linearization approaches, such as emitter degeneration cannot be used because they destroy the linear in dB relationship required for dB gain steps. When emitter degeneration is present the gain relationship is no longer defined by Ic/Vt.

Linearity is an important parameter for a receiver path, and the linearity requirements prevent this approach from being used in many cases, since the linearity of a bipolar device without degeneration is quite limited.

SUMMARY

Accordingly, an object of the present invention is to provide an amplifier, which allows for a wide bandwidth, a high linearity, and an accurate adjustability of the gain over a large range, while only requiring a low circuit complexity.

The object is solved by the features of claim 1 for the apparatus. The dependent claims contain further developments.

According to a first aspect of the invention, a variable gain amplifier, configured to amplify an input signal with a variable gain, resulting in a linear-in-db output signal is provided. The variable gain amplifier comprises a linear-in-db control current generator, a control voltage generator and an output current regulator. The linear-in-db control current generator is configured to generate a linear-in-db control current based on a predefined gain setting. The control voltage generator is configured to generate a control voltage from the linear-in-db control current. The output current regulator is adapted to generate the linear-in-db output signal based on the input signal and the control voltage. It is thereby possible to achieve a wide bandwidth of the amplifier, an accurate gain adjustability and a high linearity.

According to a first implementation form of the first aspect, the linear-in-db control current generator is configured to generate the linear-in-db control current based on a variable gain setting current. The variable gain setting current is proportional to the predefined gain setting, the predefined gain setting being a linear gain. By this measure, it is especially easy to set the variable gain. According to a second implementation form of the first aspect or the first

implementation form, the generated linear-in-db control current is an exponential of the variable gain setting current. This also simplifies the setting of the variable gain. According to a further implementation form of the first implementation form or the second implementation form, the linear-in-db control current generator comprises a first bias current source, a first control current transistor, a second control current transistor, an operation amplifier, a first resistor, and an output current mirror. The first bias current source is connected to a first terminal of a supply voltage and to a collector of the first control current transistor, to a base of the first control current transistor, and to a first input of the operation amplifier. An emitter of the first control current transistor is connected to a second terminal of the supply voltage. The variable gain setting current is supplied between a second input of the operation amplifier and the second terminal of the supply voltage. The first resistor is connected between the second input of the operation amplifier and an output of the operation amplifier. The output of the operation amplifier is moreover connected to a base of the second control current transistor. An emitter of the second control current transistor is connected to the second terminal of the supply voltage. A collector of the second control current transistor is connected to the output current mirror. The output current mirror is furthermore connected to the first terminal of the supply voltage. The linear-in-db control current is provided at an output terminal of the output current mirror. It is thereby possible to provide the linear-in-db control current in a simple and efficient manner. According to a further implementation form of the first aspect or any of the previous implementation forms, the control voltage generator is configured to generate the control voltage as a function of the linear-in-db control current. It is thereby possible to especially easily generate the control voltage. According to a further implementation form of the first aspect or any of the previous implementation forms, the control voltage generator comprises a first differential pair, comprising a first transistor and a second transistor. The control voltage generator comprises a third transistor and a first dump path. A base of the first transistor and a collector of the first transistor are supplied with the linear-in-db control current. A collector of the second transistor is connected to the first dump path. A base of the second transistor is connected to a reference voltage. The first dump path is directly or indirectly connected to a first terminal of a supply voltage. An emitter of the first transistor is connected to an emitter of the second transistor and to a current source. The control voltage is generated at the base of the first transistor. The forming of the control voltage based on the linear-in-db control current is very simple by this construction.

According to a further implementation form of the first aspect or any of the previous implementation forms, the output current regulator is adapted to generate the linear-in- db output signal as a function of the input signal and the control voltage. This assures a high linearity of the output signal.

According to a further implementation form of the first aspect or any of the previous implementation forms, the output current regulator comprises a second differential pair, comprising a fourth transistor and a fifth transistor. The output current regulator moreover comprises a sixth transistor, a second dump path and a first load element. The second dump path and the first load element are connected to a first terminal of the supply voltage. The first load element is connected to a collector of the fourth transistor and to a first output terminal. A base of the fourth transistor is connected to the control voltage. A collector of the fifth transistor is connected to the second dump path. The base of the fifth transistor is connected to a reference voltage. An emitter of the fourth transistor and an emitter of the fifth transistor are connected together and to a mirrored copy of the input signal. The linear-in-db output signal is provided at the first output terminal. This assures a simple generation of the linear-in-db output signal.

According to a first implementation form of the previous implementation form, the output current regulator is configured to provide the linear-in-db output signal at the first output terminal.

Advantageously, the output current regulator is configured to provide the linear-in-db output signal as a linear-in-db output current at the first output terminal. Advantageously, the linear-in-db output signal is a linear in dB output current in the collector of the fourth transistor, but if the load is a resistor then this linear-in-dB output current will flow in the output load to generate a linear in dB output voltage. So depending on the configuration at the output terminal, the signal is either a current or voltage. In an implementation with a load resistor it would be voltage, but if the resistor was removed then the output terminal would be directly the collector of the fourth transistor and it would be a current. A further processing of this output signal is thereby facilitated. According to a further implementation form of the first aspect or any of the previous implementation forms, the input signal is a differential signal and the linear-in-db output signal is a differential signal. The processing of differential signals is thereby possible. According to a first implementation form of the previous implementation form, the input signal is a differential signal comprising a first input signal and a second input signal. The linear-in-db output signal also is a differential signal. The output current regulator comprises a third differential pair comprising a seventh transistor and an eighth transistor. The output current regulator comprises a third dump path and a second load element. The third dump path and the second load element are connected to the first terminal of the supply voltage. The second load element is connected to a collector of the seventh transistor and to a second output terminal. A base of the seventh transistor is connected to the control voltage. A collector of the eighth transistor is connected to the third dump path. A base of the eighth transistor is connected to the reference voltage. An emitter of the seventh transistor and an emitter of the eighth transistor are connected together and to a mirrored copy of the first input signal or the second input signal. The linear-in-db output signal is provided at the first output terminal and the second output terminal. A very simple generation of the differential output signal is thereby achieved.

According to a further implementation form of the previous four implementation forms, the variable gain amplifier comprises an input signal converter, configured to generate an input current signal derived from the input signal. The input signal converter is configured to provide the input current signal to the base of a sixth transistor, if the input signal is not a differential signal. The input signal converter is configured to provide the input current signal to the base of the sixth transistor and the base of the ninth transistor if the input signal is a differential signal. By this alternative construction, it is possible to directly handle radio frequency input signals.

It is important to note that the signal referred to as input current signal derived from the input signal refers to a signal provided to the base of the respective transistor, allowing for a mirroring of the input signal by the respective transistor. According to a final implementation form of the previous implementation form, the sixth transistor and the ninth transistor are connected to a DC bias circuit. This facilitates the construction of the previously shown implementation form and allows for an especially simple circuit design. Generally, it has to be noted that all arrangements, devices, elements, units and means and so forth described in the present application could be implemented by software or hardware elements or any kind of combination thereof. Furthermore, the devices may be processors or may comprise processors, wherein the functions of the elements, units and means described in the present applications may be implemented in one or more processors. All steps which are performed by the various entities described in the present application as well as the functionality described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if in the following description or specific embodiments, a specific functionality or step to be performed by a general entity is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respect of software or hardware elements, or any kind of combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is in the following explained in detail in relation to embodiments of the invention in reference to the enclosed drawings, in which: FIG. 1 shows a first embodiment of the variable gain amplifier of the first aspect of the invention;

FIG. 2 shows a detail of a second embodiment of the variable gain amplifier of the first aspect of the invention;

FIG. 3 shows a third embodiment of the variable gain amplifier of the first aspect of the invention;

FIG. 4 shows a fourth embodiment of the variable gain amplifier of the first aspect of the invention; and

FIG. 5 shows a fifth embodiment of the variable gain amplifier of the first aspect of the invention.

DESCRIPTION OF THE EMBODIMENTS

First we demonstrate the general construction and function of the variable gain amplifier of the first aspect along FIG. 1. With regard to FIG. 2 - 5, details of the construction and the function are described. Similar entities and reference numbers in different figures have been partially omitted.

In general, the presented amplifier makes use of a linear in dB current together with the concept of current steering of a linear in dB current in a current mode configuration to achieve accurate gain steps and high levels of linearity. The limitations of prior art that are removed: a. Complexity: The circuit achieves gain steps directly in the signal path without adding significant complexity in the signal path, the current that is used for setting the gain steps is outside the signal path, and the gain steps can be very small, e.g. below ldB, accurate, and cover a wide range due to the linear in dB relationship. b. Bandwidth limitations: The circuit operates in current mode in the signal path, using current steering to achieve the gain steps, so the loading and impact on bandwidth is very low. c. Linearity: The circuit operates in current mode to achieve the gain steps, and current mode is much more linear than voltage mode. This removes the constraint of the bipolar device transfer function when used as a voltage amplifier with a linear in dB current, in common emitter configuration. d. Gain step size and number of gain steps: The number of gain steps and the size of gain steps do not impact complexity or performance. Continuous gain control is possible, as are very fine gain steps as small as O.ldB.

The implementation makes use of a linear in dB current generator, which outputs an exponential current that is controlled by a linear control current. This exponential current is used to set up a current steering arrangement to achieve the gain control. The resulting gain control can be very fine, down to sub-ldB. The circuit does not add significant complexity in the signal path, simply a current steering device. The loading of this arrangement is low and so wide bandwidths can be achieved. The solution is suitable for an RF VGA, or an analog baseband VGA that needs to support very wide bandwidth signals, e.g. up to lGHz.

In FIG. 1, a first embodiment of the variable gain amplifier 1 of the first aspect of the invention is shown. The variable gain amplifier 1 comprises a linear-in-db control current generator 2, which is connected to a control voltage generator 3, which in turn is connected to an output current regulator 4. The linear-in-db control current generator 2 is provided with a variable gain setting current Ictri, which sets a variable gain of the variable gain amplifier 1. From this variable gain setting current Ictri, the linear-in-db control current generator 2 generates a linear-in-db control current Iiin in dB, which is provided to the control voltage generator 3. The predefined gain setting defines the gain to be obtained from the variable gain amplifier. The control voltage generator 3 generates a control voltage Vvga ctri and provides it to the output current regulator 4. The output current regulator 4 is moreover provided with an input signal I_vga in. The output current regulator 4 generates an output signal I_vga out by amplifying the input signal I_vga in using the variable gain set by the control voltage Vvga ctri.

Especially, it has to be noted, that the implementation advantageously uses a current steering achieved through current steering a proportion of the input current via a differential pair circuit implementation.

Regarding the details of the construction and the function, it is referred to FIG. 2 - FIG. 5.

In FIG. 2, a detail of the embodiment shown in FIG. 1 is shown. Especially, in FIG. 2, the linear-in-db control current generator 2 is shown in detail. The linear-in-db control current generator 2 comprises a first bias current source 20, a first control current transistor 21, a second control current transistor 25, an operation amplifier 23, a first resistor 24 and an output current mirror 26.

The first bias current source 20 is connected to a first terminal 70 of a supply voltage and to a collector of the first control current transistor 21. Moreover, it is connected to a base of the first control current transistor 21 and to a first input of the operation amplifier 23. Especially, the collector and base of the first control current transistor 21 are diode-connected.

Especially, it has to be noted that advantageously, the first control current transistor 21 and the second control current transistor 25 are both bipolar transistors, enabling the generation of the exponential current.

An emitter of the first control current transistor 21 is connected to a second terminal 71 of the supply voltage. The variable gain setting current Ictri is supplied between a second input of the operation amplifier 23 and a second terminal of the supply voltage. The first resistor 24 is connected between the second input of the operation amplifier 23 and an output of the operation amplifier 23. The output of the operation amplifier 23 is connected to a base of the second control current transistor 25. An emitter of the second control current transistor 25 is connected to the second terminal 71 of the supply voltage. A collector of the second control current transistor 25 is connected to the output current mirror 26. The output current mirror 26 is connected to the first terminal 70 of the supply voltage. The linear-in-db control current Ii in in dB IS provided at an output terminal of the output current mirror 26. The output current mirror 26 comprises a first mirror transistor 27 and a second mirror transistor 28. The mirror transistors 27, 28 are either bipolar or MOS devices.

Also alternative current source arrangements can be used.

In the following, the detailed function including the underlying mathematics of the linear-in-db control current generator 2 are shown.

The current 12 is generated by the linear in dB control current generator 2, where:

12 = (A2/A1) * II * exp (Rl * Vt).

Ictri in dB is simply a mirrored copy of 12. For a given gain step in dB, AGdB, the necessary variable gain setting current Ictri step can be calculated as:

AICTRL = AGdB/20 *Vt/Rl *2,303 where 2,303 is the factor for converting between loglO and In.

The Ictri current is varied in a linear manner to generate the linear in dB output current

Below an analysis showing the derivation of the linear in dB current relationships is shown:

Equation for npn device Ql is:

11 = Al *Is*exp (Vlp/Vt) so Vlp = Vt In (Il/(Al *Is)).

Equation for npn device Q2 is:

12 = A2*Is*exp (V2/Vt).

The op-amp input V In is a virtual ground assuming A is large so Vlp = Vln => V2 = Vlp + Rl *Ictri

=> V2 = [Vt In (I1/(A1 *Is)) + Rl * i].

Recall 12 = A2*Is*exp (V2/Vt).

So substituting V2 to obtain 12:

12 = A2*Is*exp ([Vt In (I1/(A1 *Is)) + Rl * |/Vt)

= A2*Is* exp (In (Il/(Al *Is)) * exp(Rl * Vt)

= (A2*Is*Il)/(Al *Is) * exp(Rl *Ictri/Vt)

12 = (A2/A1) * exp (Rl * Vt)

12 provides a linear in dB output current when Ictri is controlled with linear steps due to the exponential nature of the relationship.

Now considering two current settings for Ictri of la and lb to give a gain step AGdB:

AGdB = 20*log (Ib/Ia)

AGdB = 20*log (K * exp (Rl *Ib/Vt)/ K * exp (Rl *Ia/Vt)) AGdB = 20*log exp [Rl/Vt * (Ib-Ia)] AGdB =20*log exp [RIM * (AW)].

Therefore,

Alctri = (AGdB / 20) * (Vt / Rl) * 2,303.

In FIG. 3, a detailed embodiment of the variable gain amplifier of the first aspect of the invention is shown. The variable gain amplifier la comprises a linear-in-db current generator 2, a control voltage generator 3 and an output current regulator 4, which are connected as shown in FIG. 1. The linear-in-db current generator 2 is for example constructed as shown in FIG. 2.

The linear-in-db current generator 2, the control voltage generator 3 and the output current regulator 4 each are connected to a first terminal 70 of a supply voltage and to a second terminal 71 of the supply voltage, which is put into practice here as a mass connection. The control voltage generator 3 comprises a first differential pair, which in turn comprises a first transistor 32 and a second transistor 33. The first transistor 32 is diode-connected, meaning that the collector and base of the first transistor 32 are connected. Moreover, this connection is supplied with the linear-in-db control current llin in dB by the linear-in-db current generator 2.

Moreover, the control voltage generator 3 comprises a dump path 30, which consists of a dump resistor 31 and the second transistor 33. The dump resistor 31 is connected to the first terminal 70 of the supply voltage and to the collector of the second transistor 33. The base of the second transistor 33 is supplied with a reference voltage Vref. The emitter of the second transistor is connected to the emitter of the first transistor and to a collector of a further transistor 35. The emitter of the transistor 35 is connected to the second terminal 71 of the supply voltage. The control voltage Vvga ctri is generated at the collector and base of the first transistor 32 and provided to the output current regulator 4. Through the sixth transistor 35, a mirrored copy of an input reference signal I_vga __ref is driven.

The control voltage Vvga ctri generated is governed by the relationship of a bipolar device where:

Ic = Is * exp(eVbe/kT).

This means that the transistors 32 and 33 are bipolar transistors. As the arrangement is such that a differential pair 32, 33 is used where the other side of the differential pair is set to a reference voltage Vref. The bipolar transistor collector/base voltage Vvga ctri will be set depending on the proportion of the current provided by the linear-in-db control current Ii in in dB compared to the total current flowing in both branches of the differential pair 32, 33, and depending also on the reference voltage Vref on the other side of the bipolar transistor, according to the physical relationships of the current flow in bipolar type devices as specified above.

The output current regulator 4 comprises a second differential pair, consisting of a fourth transistor 43 and a fifth transistor 44. Moreover, the output current regulator 4 comprises a further transistor 45, a second dump path 40, which consists of a second dump resistor 42 and the fourth transistor 44 and a load element, for example a load resistor 41. It is not a requirement that the load element is a load resistor, it could also be a further current mirror if the output is kept in "current mode".

The second dump path 40 and the load element are connected to the first terminal 70 of the supply voltage. The load element 41 is connected to a collector of the fourth transistor 43 and to a first output terminal. In the case the load element is a resistor, the current I_vga out flows in the load resistor and thereby generates a voltage in the output terminal. The output current I_vga out flows through the collector of the fourth transistor 43. A base of the fourth transistor is connected to the control voltage Vvga ctri provided by the control voltage generator 3. A collector of the fifth transistor 44 is connected to the second dump path 40, especially to the second dump resistor 42. The base of the fifth transistor is connected to the reference voltage Vref. The emitter of the fourth transistor and the emitter of the fifth transistor are both connected together and to a mirrored copy of the input signal I_vga in, which is provided by the sixth transistor 45.

The first dump path 40 may be connected directly or through other components to the first terminal of the fifth transistor 44.

Advantageously, the transistors 43 and 44 are bipolar transistors.

The input reference signal I_vga _ref is provided by a current source 52, which is connected to transistor 51 , especially to the collector of the transistor 51. The transistor 51 is diode-connected. Also, the base of the transistor 51 is connected to the base of the transistor 35, to advantageously create a current mirror structure. The emitter of the transistor 51 is connected to the second terminal 71 of the supply voltage. Therefore, a current source is provided by transistor 35 as a mirror current of the current provided by the current source 52. The base of the ninth transistor 45 is connected to the base of a further transistor 61, which is also diode-connected to the collector of the transistor 61, to advantageously create a current mirror structure. This connection is moreover connected with an input current source, which provides the input signal I_vga in. The emitter of the transistor 61 is connected to the second terminal 71 of the supply voltage.

It has to be noted that the first terminal 70 of the supply voltage and the second terminal 71 of the supply voltage can be positive and negative terminals of the supply voltage. Alternatively, the first terminal 70 or the second terminal 71 can be a positive or negative terminal, while the respective other terminal 70, 71 can be a mass connection. The second terminal 71 does not have to be a mass connection, as depicted.

The general idea is that a linear in dB current Iim in dB provided by the linear in dB current generator 2 is forced into one side of a differential pair, especially into the first transistor 32, which is diode connected to create the control voltage Vvga ctri. The control voltage Vvga ctri is applied to the VGA current mirror, especially to the output current regulator 4, where current steering will force the output current I_vga out to be linear in dB. The unused part of the VGA current is dumped into the dump path, especially into the dump resistor 42. Especially, the resulting VGA output current can be converted into the voltage domain by the load element 41.

In the previously described FIG. 3, a single-ended implementation is described. With the presented approach, though, also a differential implementation is possible. This is shown in FIG. 4.

In FIG. 4, a variable gain amplifier lb is shown. The linear-in-db current generator 2 and the control voltage generator 3 are identical to the implementation shown in FIG. 3. Here, though, the output current regulator 4 comprises a first differential pair consisting of the transistors 43 a and 44a and a second differential pair consisting of the transistors 43b and 44b. The transistor 43 a is connected to a first load element 41a with its collector. The transistor 43b is connected to a second load element 41b with its collector. The load elements 41a and 41b are connected to the first terminal 70 of the supply voltage. The base of the transistor 43a and the base of the transistor 43b are both connected to the control voltage Vvga ctri. The output current regulator 4 moreover comprises a first dump path 40a and a second dump path 40b. The first dump path 40a comprises a dump resistor 42a, which is connected to the collector of the transistor 44a. The second dump path 40b comprises a second dump resistor 42b, which is connected to the collector of the transistor 44b. The emitters of the transistors 43 a and 43b are connected together and to the collector of a transistor 45 a, which corresponds to the transistor 45 of FIG. 3. The emitters of the transistors 43b and 44b are also connected together and connected to the collector of a transistor 45b, which also corresponds to the transistor 45 of FIG. 3. The base of the transistor 45a is connected to the base of a transistor 61a, which is diode-configured and connected to a current source 62a. The base of the transistor 45b is connected to the base of a transistor 61b, which is diode-configured and connected to a current source 62b. The input signal is a differential input signal and comprises the partial signals Ivgajnp and Ivga , which are provided by the current source 62a and 62b. Therefore, the configuration drives mirrored copies of the currents Ivgajnp and Ivga through the transistors 45 a, 45b.

Apart from the above-described details, the construction of the variable gain amplifier lb corresponds to the construction of the variable gain amplifier la of FIG. 3. Also, the presented approach can also be applied to an RF implementation. This is illustrated in FIG. 5. Here, the variable gain amplifier lc is also constructed in a somewhat similar manner to the variable gain amplifier la of FIG. 3. The linear-in-db current generator 2 and the control voltage generator 3 are constructed as shown in FIG. 3. Also, the output current regulator 4 is mainly constructed as the output current regulator 4 of FIG. 3. The key difference here, though, is that the transistors 35 and 45 are connected to a DC bias circuit 80 resulting in bias currents being driven through the transistors 35 and 45. Especially, the base of the transistor 35 is connected to the base and collector of a transistor 85, which is connected to a current source 82.

Moreover, the base of the transistor 45 is connected to a resistor 85, which is connected to a further resistor 84, which is connected to the base of a transistor 81. The resistor 85 is moreover connected to the collector of the transistor 81. The collector of the transistor 81 is moreover connected to a current source 83. The emitter of the transistor 81 is connected to the second terminal 71 of the voltage supply. Moreover, the base of the transistor 45 is connected to a coupling capacitor 86, which is connected to an RF input terminal 87, which is supplied with the RF input signal RFIN. The RF load 41 may be an integrated resonant LC load or a transmission line.

Especially, an application to low noise amplifiers is possible.

The invention is not limited to the examples. The characteristics of the exemplary embodiments can be used in any advantageous combination.

The invention has been described in conjunction with various embodiments herein. However, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word

"comprising " does not exclude other elements or steps and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in usually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. A computer program may be

stored/distributed on a suitable medium, such as an optical storage medium or a solid- state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the internet or other wired or wireless communication systems.

Claims

1. A variable gain amplifier (1, la, lb, lc), configured to amplify an input signal (Ivga in) with a variable gain, resulting in a linear-in-db output signal (I_vga out), comprising a linear-in-db control current generator (2), a control voltage generator (3) and an output current regulator (4),

wherein the linear-in-db control current generator (2) is configured to generate a linear-in-db control current (Iiin in dB) based on a predefined gain setting,

wherein the control voltage generator (3) is configured to generate a control voltage (Vvga ctri) from the linear-in-db control current (Iiin in dB), and

wherein the output current regulator (4) is adapted to generate the linear-in-db output signal (I_vga out) based on the input signal and the control voltage (Vv_ga ctri).

2. The variable gain amplifier (1, la, lb, lc) according to claim 1,

wherein the linear-in-db control current generator (2) is configured to generate the linear-in-db control current (Iiin in dB) based on a variable gain setting current (Ictri), and wherein the variable gain setting current (Ictri) is proportional to the predefined gain setting, the predefined gain setting being a linear gain.

3. The variable gain amplifier (1, la, lb, lc) according to claim 1 or 2,

wherein the generated linear-in-db control current (Iiin j_n dB) is an exponential of the variable gain setting current (Ictri).

4. The variable gain amplifier (1, la, lb, lc) according to claim 2 or 3,

wherein the linear-in-db control current generator (2) comprises a first bias current source (20), a first control current transistor (21), a second control current transistor (25), an operation amplifier (23), a first resistor (24), and an output current mirror (26), wherein the first bias current source (20) is connected to a first terminal of a supply voltage and to a collector of the first control current transistor (21), to a base of the first control current transistor (20), and to a first input of the operation amplifier (23), wherein an emitter of the first control current transistor (21) is connected to a second terminal of the supply voltage,

wherein the variable gain setting current (Ictri) is supplied between a second input of the operation amplifier (23) and the second terminal of the supply voltage, wherein the first resistor (24) is connected between the second input of the operation amplifier (23) and an output of the operation amplifier (23),

wherein the output of the operation amplifier (23) is connected to a base of the second control current transistor (25),

wherein an emitter of the second control current transistor (25) is connected to the second terminal of the supply voltage,

wherein a collector of the second control current transistor (25) is connected to the output current mirror (26),

wherein the output current mirror (26) is connected to the first terminal of the supply voltage, and

wherein the linear-in-db control current (Iiin in dB) is provided at an output terminal of the output current mirror (26).

5. The variable gain amplifier (1 , la, lb, lc) according to any of claims 1 to 4, wherein the control voltage generator (3) is configured to generate the control voltage (Vvga ctri) as a function of the linear-in-db control current (Iiin in dB).

6. The variable gain amplifier (1 , la, lb, lc) according to any of claims 1 to 5, wherein the control voltage generator (3) comprises a first differential pair, comprising a first transistor (32) and a second transistor (33),

wherein the control voltage generator (3) comprises a third transistor (35) and a first dump path (30),

wherein a base of the first transistor (32) and a collector of the first transistor (32) are supplied with the linear-in-db control current (Iiin j_n dB),

wherein a collector of the second transistor (33) is connected to the first dump path (30),

wherein a base of the second transistor (33) is connected to a reference voltage (Vref), wherein the first dump path (30) is directly or indirectly connected to a first terminal of a supply voltage (70),

wherein an emitter of the first transistor (32) is connected to an emitter of the second transistor (33) and to a current source (50), and

wherein the control voltage (Vvga ctri) is generated at the base of the first transistor (32).

7. The variable gain amplifier (1 , la, lb, lc) according to any of claims 1 to 6, wherein the output current regulator (4) is adapted to generate the linear-in-db output signal (I_vga out) as a function of the input signal (Ivgajn) and the control voltage

8. The variable gain amplifier (1, la, lb, lc) according to any of claims 1 to 7, wherein the output current regulator (4) comprises a second differential pair, comprising a fourth transistor (43, 43a) and a fifth transistor (44, 44a),

wherein the output current regulator (4) comprises a sixth transistor (45), a second dump path (40), and a first load element (41),

wherein the second dump path (40) and the first load element (41) are connected to a first terminal of a supply voltage (70),

wherein the first load element (41) is connected to a collector of the fourth transistor (43) and to a first output terminal,

wherein a base of the fourth transistor (43) is connected to the control voltage wherein a collector of the fifth transistor (44) is connected to the second dump path (40),

wherein the base of the fifth transistor (44) is connected to a reference voltage (Vref), wherein an emitter of the fourth transistor (43) and an emitter of the fifth transistor (44) are connected together and to a mirrored copy of the input signal (Ivga in, 45), and wherein the linear-in-db output signal (I_vga out) is provided at the first output terminal.

9. The variable gain amplifier (1, la, lb, lc) according to claim 8,

wherein output current regulator (4) is configured to provide the linear-in-db output signal (I_vga out) as a linear-in-db output current at the first output terminal.

10. The variable gain amplifier (1, la, lb, lc) according to any of claims 1 to 9, wherein the input signal (I_vga jn_P, Ivga inn) is a differential signal, and

wherein the linear-in-db output signal (I_vga outp, Ivga outn ) is a differential signal.

11. The variable gain amplifier (1, la, lb, lc) according to claim 10,

wherein the input signal (I_vga jn_P, Ivga inn) is a differential signal comprising a first input signal (Ivgajnp) and a second input signal (Ivga inn),

wherein the linear-in-db output signal (I_vga outp, Ivga outn ) is a differential signal, wherein the output current regulator (4) comprises a third differential pair, comprising a seventh transistor (43b) and an eighth transistor (44b),

wherein the output current regulator (4) comprises, a third dump path (40b), and a second load element (41b),

wherein the third dump path (40b) and the second load element (41b) are connected to the first terminal of the supply voltage (70),

wherein the second load element (40b) is connected to a collector of the seventh transistor (43b) and to a second output terminal,

wherein a base of the seventh transistor (43b) is connected to the control voltage (Vref), wherein a collector of the eighth transistor (44b) is connected to the third dump path (40b),

wherein a base of the eighth transistor (44b) is connected to the reference voltage wherein an emitter of the seventh transistor (43b) and an emitter of the eighth transistor (44b) are connected together and to a mirrored copy of the first input signal (Ivga jnp) or the second input signal (I_vga jnn), and

wherein the linear-in-db output signal (I_vga outp, Ivga outn ) is provided at the first output terminal and the second output terminal.

12. The variable gain amplifier (1, la, lb, lc) according to any of claims 8 to 11, wherein the variable gain amplifier (la, lb, lc) comprises an input signal converter, configured to generate an input current signal derived from the input signal (Ivga in,

wherein the input signal converter is configured to provide the input current signal to the base of the sixth transistor (45), if the input is not a differential signal, and wherein the input signal converter is configured to provide the input current signal to the base of the sixth transistor (45a) and the base of the ninth transistor (45b), if the input is a differential signal (I_vga inn, Ivgajnp).

13. The variable gain amplifier (1, la, lb, lc) according to claim 12,

wherein the sixth transistor (45, 45a) and the ninth transistor (45b) are connected to a DC bias circuit (60, 80).