WO2018000765A1 - Co-processor, data reading method, processor system and storage medium - Google Patents

Abstract

A co-processor (10). The co-processor (10) comprises: a read circuit (101) configured to receive a transport instruction sent by a space needing to be read; determining a transport channel needing to execute a transport task according to the transport instruction; transporting data of the space needing to be read to a closely coupled memory of a main processor via the transport channel; and when the transport task is completed, sending a reading notification to the main processor, so that the main processor reads the data of the space needing to be read. Further disclosed are a data reading method, a processor system and a storage medium.

Description

Coprocessor, data reading method, processor system and storage medium Technical field

The present invention relates to wireless communication technologies, and in particular, to a coprocessor, a data reading method, a processor system, and a storage medium.

Background technique

In the system-on-chip (SOC) architecture of multi-mode mobile phone chips, the processor's efficient access to external registers and peripheral space for operations can greatly improve overall architecture performance. The processor's access to the physical layer includes frequent configuration of a large number of physical layer registers, the physical layer hardware will process the data according to the configuration, and then the processor will re-read the data in the physical layer, regenerate the new configuration based on the data, and then again The physical layer registers are configured, and the process loops in sequence to complete the interaction between the processor and the physical layer. Therefore, in the entire SOC architecture, processor access to the physical layer's register space and data space performance is the key to the overall architecture performance. However, if the processor accesses the external registers and the peripheral space is slow, the timing will be tight, the physical layer process will be abnormal, and during the interaction between the processor and the physical layer, if the interaction time is too long, it will also cause processing. The power consumption of the device is increased.

Summary of the invention

To solve the above technical problem, embodiments of the present invention are expected to provide a coprocessor, a data reading method, a processor system, and a storage medium, which can improve performance of a processor accessing an external register or a peripheral space, and save time for a physical layer process. Improve the performance of the physical layer.

The technical solution of the present invention is implemented as follows:

In a first aspect, a coprocessor is provided, the coprocessor comprising:

a read circuit configured to receive a transport instruction sent by the read space; according to the transport instruction, Determining a handling lane that needs to perform a handling task; transferring data of the space to be read to the tightly coupled memory of the main processor through the handling lane; and sending a read notification to the main processor when the handling task is completed So that the main processor reads the data of the space to be read.

In the above solution, the handling instruction includes information about the space to be read, and the coprocessor further includes:

a storage area configured to store correspondence between information of each register and peripheral space and a channel;

The read circuit is configured to use, as the transport channel, a channel corresponding to the information determining the space to be read according to the correspondence.

In the above solution, the coprocessor further includes:

a write circuit configured to receive a write request and write data sent by the processor, the write request is for requesting writing the write data to a write space; sending a write response to the processor; A write space sends the write request and the write data.

In the above solution, the buffer depth of the write circuit and the buffer depth of the read circuit are preset.

In a second aspect, a data reading method is provided, the method comprising:

Receiving a handling instruction sent by the space to be read;

Determining, according to the transport instruction, a transport lane that needs to perform a transport task;

Carrying data of the space to be read into the main processor through the transport channel;

When the handling task is completed, a read notification is sent to the main processor, so that the main processor reads the data of the space to be read.

In the above solution, the handling instruction includes information about the space to be read, and the method further includes:

Set the correspondence between the information of each register and peripheral space and the channel;

The determining, according to the carrying instruction, the carrying lane that needs to perform a carrying task includes:

According to the correspondence, a channel corresponding to the information of the space to be read is determined as the transport channel.

In the above solution, the method further includes:

Receiving a write request and write data sent by the processor, where the write request is used to request to write the write data into a write space;

Sending a write response to the processor;

Transmitting the write request and the write data to the space to be written.

In a third aspect, a coprocessor is provided, the coprocessor comprising:

a receiving module configured to receive a transport instruction sent by the read space;

a determining module configured to determine a handling lane that needs to perform a handling task according to the handling instruction;

a handling module configured to carry data of the space to be read into a tightly coupled memory of the main processor through the handling channel;

And a sending module configured to send a read notification to the main processor when the carrying task is completed, so that the main processor reads the data of the space to be read.

In a fourth aspect, a processor system is provided, comprising:

Main processor and coprocessor;

The coprocessor is configured to receive a transport instruction sent by the read space; determine, according to the transport instruction, a transport channel that needs to perform a transport task; and carry the data of the space to be read to the main processor through the transport channel In the tightly coupled memory; when the handling task is completed, a read notification is sent to the main processor, so that the main processor reads the data of the space to be read.

The embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the data reading method.

The embodiment provides a coprocessor, a data reading method, a processor system, and a storage medium. The coprocessor includes: a read circuit configured to receive a transport instruction to be sent in a read space; determine, according to the transport instruction, a transport path that needs to perform a transport task; and carry the data of the space to be read through the transport channel Going to the tightly coupled memory of the main processor; sending a read notification to the main processor when the transfer task is completed; the main processor being configured to receive the read notification and read the read space The data. Thus, by utilizing the coupling of the main processor's tightly coupled memory and the processor, the main processor can directly read the data of the space to be read stored on the tightly coupled memory of the main processor, which greatly saves the processor reading the external The time in the register or peripheral space improves the performance of the processor reading external space, saving time for the physical layer and optimizing the physical layer flow.

DRAWINGS

1 is a schematic structural diagram 1 of a coprocessor according to an embodiment of the present invention;

2 is a schematic structural diagram 2 of a coprocessor according to an embodiment of the present invention;

3 is a schematic structural diagram of a processor provided by the prior art;

4 is a flowchart of a data reading method according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram 3 of a coprocessor according to an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a coprocessor according to an embodiment of the present invention.

FIG. 7 is a schematic structural diagram 1 of a processor according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram 2 of a processor according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings.

Embodiment 1

This embodiment provides a coprocessor 10. As shown in FIG. 1, the coprocessor 10 includes:

The read circuit 101 is configured to receive a transport instruction sent by the read space; according to the transport instruction, Determining a handling lane that needs to perform a handling task; transferring data of the space to be read to the tightly coupled memory of the main processor through the handling lane; and sending a read notification to the main processor when the handling task is completed So that the main processor reads the data of the space to be read.

Here, the read circuit 101 sets an unlimited number of parallel channels, each channel having a unique fixed identification.

The tightly coupled memory of the main processor is configured to store data of the space to be read.

The tightly coupled memory of the main processor includes: a primary storage space and a secondary storage space; wherein the primary storage space has a higher handling priority than the secondary storage space.

In this way, by utilizing the coupling of the main processor's tightly coupled memory and the processor, the main processor can directly read the data of the space to be read stored on the tightly coupled memory of the main processor, which greatly saves the processor reading. Taking the time of the external register or peripheral space improves the performance of the processor to read the external space, saves time for the physical layer, and optimizes the physical layer flow.

Further, as shown in FIG. 2, the transport instruction includes information about the space to be read, and the coprocessor 10 further includes:

The storage area 102 is configured to store a correspondence between information of each register and a peripheral space and a channel;

The read circuit 101 is specifically configured to: according to the correspondence, a channel corresponding to the information determining the space to be read is used as the transport channel.

In this embodiment, information is needed to read a register or a peripheral space, the information includes an address interval of a register or a peripheral space, a resource amount, etc., and then the coprocessor reads directly according to the information without any other components. The register or peripheral space is taken, and the read data is written into the primary storage space or the secondary storage space of the main processor allocated in advance, where the primary and secondary storage spaces are tightly coupled with the primary processor. of. In the storage system, the performance of accessing the primary storage space is the highest, and the performance of accessing the secondary storage space is second. When the processor really needs to read the data of these registers or peripheral space, it can directly access the level that has been written. Storage or secondary storage interval. This greatly saves the processor's time to read external registers or peripheral space, improves the performance of the processor to read the external space, saves time for the physical layer, optimizes the physical layer flow, and at the same time, needs to process the read The data does not need to wait for the processor to save power. And the reading device can set a parallel channel without limiting the number to solve the problem of process parallelism.

Further, as shown in FIG. 2, the coprocessor 10 further includes:

Write circuit 103, configured to receive a write request and write data sent by the processor, the write request is for requesting writing the write data to a write-only space; sending a write response to the processor; A write space is required to transmit the write request and the write data.

Further, the buffer depth of the write circuit and the buffer depth of the read circuit are preset.

As shown in Figure 3, the normal SOC architecture, the main processor externally integrates the L2 cache tightly coupled memory, the L2 cache outside the integrated matrix bridge, the external registers or peripheral space is integrated on the matrix bridge slave. In general, external registers and peripheral space are not cacheable to the processor, but the processor can only access external registers and peripheral space through the L2 cache to read and write. Therefore, in this architecture, the requirements of the bus capability and the performance of the processor access input/output (I/O) are very high.

The coprocessor provided in this embodiment can avoid reading or writing to an external register or a peripheral space through the second level cache, and directly writes to the external register or the external space by the coprocessor configuration. Improves the processor's ability to read external space, saves time for the physical layer, and optimizes physical layer processes.

Embodiment 2

The embodiment of the invention provides a data reading method, which is applied to a coprocessor as shown in FIG. 4, and the method includes:

Step 201: Receive a transport instruction sent by the read space.

Step 202: Determine a transport channel that needs to perform a transport task according to the transport instruction.

Step 203: Carry the data of the space to be read into the tightly coupled memory of the main processor through the transport channel.

Step 204: When the handling task is completed, send a read notification to the main processor, so that the main processor reads the data of the space to be read.

In this way, by utilizing the coupling of the main processor's tightly coupled memory and the processor, the main processor can directly read the data of the space to be read stored on the tightly coupled memory of the main processor, which greatly saves the processor reading. Taking the time of the external register or peripheral space improves the performance of the processor to read the external space, saves time for the physical layer, and optimizes the physical layer flow.

Further, the transport instruction includes information about the space to be read, and the method further includes: setting a correspondence between information of each register and the peripheral space and the channel;

Correspondingly, step 202 may specifically include:

According to the correspondence, a channel corresponding to the information of the space to be read is determined as the transport channel.

Further, the method further includes:

Receiving a write request and write data sent by the processor, the write request is for requesting writing the write data to a write space; sending a write response to the processor; and sending the write to the space to be written Write request and the write data.

Embodiment 3

The embodiment of the present invention provides a coprocessor 30. As shown in FIG. 5, the coprocessor 30 includes:

The receiving module 301 is configured to receive a transport instruction sent by the read space.

The determination module 302 determines a transportation lane that needs to perform a transportation task according to the transportation instruction.

The transport module 303 transports the data of the space to be read to the tightly coupled memory of the main processor through the transport path.

The sending module 304 sends a read notification to the main processor when the handling task is completed, so that the main The processor reads the data of the space to be read.

In this way, by utilizing the coupling of the main processor's tightly coupled memory and the processor, the main processor can directly read the data of the space to be read stored on the tightly coupled memory of the main processor, which greatly saves the processor reading. Taking the time of the external register or peripheral space improves the performance of the processor to read the external space, saves time for the physical layer, and optimizes the physical layer flow.

Further, as shown in FIG. 6, the transport instruction includes information about the space to be read, and the coprocessor 30 further includes: a setting module 305 configured to set a correspondence between the information of each register and the peripheral space and the channel;

Correspondingly, the determining module 302 is specifically configured as:

According to the correspondence, a channel corresponding to the information of the space to be read is determined as the transport channel.

Further, the determining module 302 is specifically configured to:

Receiving a write request and write data sent by the processor, the write request is for requesting writing the write data to a write space; sending a write response to the processor; and sending the write to the space to be written Write request and the write data.

The embodiment of the invention provides a processor system 40, as shown in FIG. 7, comprising:

Coprocessor 10 and main processor 20.

The coprocessor 10 is configured to: receive a transport instruction to be sent in the read space; determine, according to the transport command, a transport channel that needs to perform a transport task; and carry the data of the space to be read to the main through the transport channel a tightly coupled memory of the processor; when the handling task is completed, sending a read notification to the main processor;

The main processor 20 is configured to receive the read notification and read data of the space to be read.

In the embodiment of the present invention, the processor system formed by the main processor plus the coprocessor, the coprocessor-assisted read and write operations are all performed by the coprocessor separately, and the operation data is stored in the coprocessor. When the main processor needs data, it needs to be retrieved from the coprocessor's memory, and the main processor accesses the coprocessor's memory with a delay, which leads to a decrease in performance, and only when the main processor needs to read and write peripheral space. When you are working. As shown in FIG. 8, the circuit provided by the present embodiment effectively utilizes the feature of the host processor to efficiently access the tightly coupled memory, and breaks the conventional method of directly accessing the peripheral space by the host processor or the coprocessor, and the software analyzes in advance. The peripheral data required by the processor is combined with software and hardware to acquire peripheral data in advance, improving the performance of the processor to read and write peripheral space. Also, the read circuit device and the write circuit device can be flexibly used. This architecture provides the flexibility to increase processor access to external registers and peripheral space. Provides higher performance guarantees for the processor to interact with the physical layer.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The device is implemented in a flow chart A function specified in a block or blocks of a process or multiple processes and/or block diagrams.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Claims (10)

A coprocessor, the coprocessor comprising: a read circuit configured to receive a transfer command; determine, according to the transfer command, a transfer path that needs to perform a transfer task; and through the transfer path, carry the data of the read space to a tightly coupled memory of the main processor; When the handling task is completed, a read notification is sent to the main processor, so that the main processor reads the data of the space to be read. The coprocessor according to claim 1, wherein the handling instruction includes information of the space to be read, and the coprocessor further comprises: a storage area configured to store correspondence between information of each register and peripheral space and a channel; The read circuit is configured to use, as the transport channel, a channel corresponding to the information determining the space to be read according to the correspondence. The coprocessor of claim 1 or 2, wherein the coprocessor further comprises: a write circuit configured to receive a write request and write data sent by the processor, the write request is for requesting writing the write data to a write space; sending a write response to the processor; A write space sends the write request and the write data. The coprocessor according to claim 3, wherein a buffer depth of said write circuit and a buffer depth of said read circuit are preset. A data reading method, the method comprising: Receiving a handling instruction sent by the space to be read; Determining, according to the transport instruction, a transport lane that needs to perform a transport task; Carrying data of the space to be read into the main processor through the transport channel; When the handling task is completed, a read notification is sent to the main processor, so that the main processor reads the data of the space to be read. The method of claim 5 wherein said handling instructions comprise said reading empty Information, the method further includes: Set the correspondence between the information of each register and peripheral space and the channel; The determining, according to the carrying instruction, the carrying lane that needs to perform a carrying task includes: According to the correspondence, a channel corresponding to the information of the space to be read is determined as the transport channel. The method of claim 6 wherein the method further comprises: Receiving a write request and write data sent by the processor, where the write request is used to request to write the write data into a write space; Sending a write response to the processor; Transmitting the write request and the write data to the space to be written. A coprocessor, the coprocessor comprising: a receiving module configured to receive a transport instruction sent by the read space; a determining module configured to determine a handling lane that needs to perform a handling task according to the handling instruction; a handling module configured to carry data of the space to be read into a tightly coupled memory of the main processor through the handling channel; And a sending module configured to send a read notification to the main processor when the carrying task is completed, so that the main processor reads the data of the space to be read. A processor system comprising: Main processor and coprocessor; The coprocessor is configured to receive a transport instruction sent by the read space; determine, according to the transport instruction, a transport channel that needs to perform a transport task; and carry the data of the space to be read to the main processing through the transport channel In the tightly coupled memory of the device; when the handling task is completed, sending a read notification to the main processor; The main processor is configured to receive the read notification and read the number of spaces to be read according to. A computer storage medium having stored therein computer executable instructions for performing the data reading method of any one of claims 5 to 7.

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