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WO2018076682A1 - Procédé et appareil de commande de séquence temporelle d'interface parallèle - Google Patents

Procédé et appareil de commande de séquence temporelle d'interface parallèle Download PDF

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Publication number
WO2018076682A1
WO2018076682A1 PCT/CN2017/085924 CN2017085924W WO2018076682A1 WO 2018076682 A1 WO2018076682 A1 WO 2018076682A1 CN 2017085924 W CN2017085924 W CN 2017085924W WO 2018076682 A1 WO2018076682 A1 WO 2018076682A1
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Prior art keywords
module
rate
data communication
adaptive
mclk
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PCT/CN2017/085924
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Chinese (zh)
Inventor
徐超
周畅
龚晓亮
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/1469—Two-way operation using the same type of signal, i.e. duplex using time-sharing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex

Definitions

  • the present invention relates to the field of communications, and in particular, to a parallel interface timing control method and apparatus.
  • JESD207 is a radio front-end (Base-to-Plane Integrated Circuit) (RF-based front end integrated circuit (RFIC)).
  • RFIC radio front end-Baseband Digital Parallel
  • RBDP radio front end-Baseband Digital Parallel
  • TDD Time Division Duplex
  • FDD Frequency Division Duplex
  • Figure 1 shows JESD207 data.
  • DIQ[11:0] and DIQ[9:0] signals are data bidirectional transmission buses that support transmission in 12-bit and 10-bit data formats, respectively, and can be selected as needed. All data are double data rate (DDR, Double) Data Rate).
  • the JESD207 data interface has the characteristics of less occupied pin resources, low interface rate, and low design difficulty.
  • the FCLK can be regarded as the MCLK homologous clock for the BBIC interface level, the frequency of the clock can be ignored, and only the received MCLK is performed. After the delay, the output can be, but for the latter stage of the BBIC interface, the MCLK clock cycle information is still needed to understand the data communication rate. Therefore, the data communication rate matched with the latter circuit of the BBIC interface is provided to ensure that the data between the RFIC and the BBIC can be correctly transmitted and received. Therefore, when it is necessary to replace different RFICs when testing, it is necessary to meet the requirements of each RFIC.
  • the interface rate is configured to bring inconvenience in testing.
  • embodiments of the present invention are expected to provide a parallel interface timing control method and apparatus, and implement parallel interface rate adaptive configuration.
  • an embodiment of the present invention provides a parallel interface timing control apparatus, where the parallel interface timing control apparatus includes: a register configuration module, a rate adaptation module, an interface timing control module, and a data and timing processing module, where
  • the register configuration module is configured to acquire configuration information of the system
  • the rate adaptation module is configured to generate an updated data communication rate and an adaptive flag by using period information of the MCLK sent by the peer end when detecting that the first configuration information in the register configuration module is valid, and the updating Data communication rate and adaptive flag are sent to the register configuration module;
  • the register configuration module is further configured to configure a current data communication rate according to the adaptive flag
  • the interface timing control module is configured to generate an interface timing according to the second configuration information and the MCLK information in the register configuration module;
  • the data and timing processing module is configured to transmit data according to the interface timing, and process data according to the number of channels in the register configuration module and the current data communication rate.
  • an embodiment of the present invention provides a parallel interface timing control method, where the method is used for a parallel interface timing control apparatus, where the parallel interface timing control apparatus includes: a register configuration module, a rate adaptation module, and an interface timing control Module and data and timing processing module, The method includes:
  • the register configuration module acquires configuration information of the system
  • the rate adaptation module When the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module generates an updated data communication rate and an adaptive flag by using period information of the MCLK sent by the peer, and Transmitting the updated data communication rate and the adaptive flag to the register configuration module;
  • the register configuration module configures a current data communication rate according to the adaptive flag
  • the interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module;
  • the data and timing processing module transmits data according to the interface timing, and processes data according to the number of channels in the register configuration module and the current data communication rate.
  • Embodiments of the present invention provide a parallel interface timing control method and apparatus, the method is used for a parallel interface timing control apparatus, and the parallel interface timing control apparatus includes: a register configuration module, a rate adaptation module, an interface timing control module, and a data and timing processing module, the method comprising: the register configuration module acquiring configuration information of the system; and when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module Generating an updated data communication rate and an adaptive flag by using the period information of the MCLK sent by the opposite end, and transmitting the updated data communication rate and the adaptive flag to the register configuration module; the register configuration module is configured according to the adaptive flag Configuring a current data communication rate; the interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module; the data and timing processing module transmits data according to the interface timing, according to the Register configuration module current data pass Data processing rate, enabling parallel interface rate adaptation configuration.
  • Figure 1 is a JESD207 data interface connection diagram
  • FIG. 2 is a schematic diagram of communication interaction between a parallel interface timing control apparatus and a radio frequency front-end integrated circuit according to an embodiment of the present invention
  • FIG. 3 is a timing diagram of data transmission start of JESD 207 according to an embodiment of the present invention.
  • FIG. 4 is a timing diagram of data transmission end of JESD 207 according to an embodiment of the present invention.
  • FIG. 5 is a timing diagram of data reception start of JESD 207 according to an embodiment of the present invention.
  • FIG. 6 is a timing diagram of data reception end of JESD 207 according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a parallel interface timing control circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a structural block diagram of a parallel interface timing control apparatus according to an embodiment of the present invention.
  • FIG. 9 is a structural block diagram of a rate adaptation module according to an embodiment of the present invention.
  • FIG. 10 is a flowchart of a parallel interface timing control method according to an embodiment of the present invention.
  • FIG. 11 is a flowchart of generating an updated data communication rate by an adaptive module according to an embodiment of the present invention.
  • FIG. 12 is a flowchart of processing data by a data and timing processing module according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a communication interaction between a parallel interface timing control device and an RFIC according to an embodiment of the present invention. It can be understood that the schematic diagram is only used to explain the technical solution of the embodiment of the present invention, and is not intended to be The embodiment of the invention is arbitrarily limited.
  • the parallel interface timing control device is located on the BBIC side, and the parallel interface timing control device corresponds to the RBDP related circuit in the BBIC of FIG.
  • Figures 3 and 4 show the timing of the JESD 207 data transmission operation
  • Figures 5 and 6 show the timing of the JESD 207 data reception operation.
  • the indication, TXNRX signal to indicate the direction of data transmission high level indicates transmission, low level indicates low reception, and for transmitting data, RFIC uses FCLK for sampling.
  • BBIC uses MCLK for sampling.
  • an embodiment of the present invention provides a parallel interface timing control method, the parallel interface timing control method is used for a parallel interface timing control device, and FIG. 7 is a schematic structural diagram of a parallel interface timing control circuit, which is implemented by the present invention.
  • the register configuration module acquires configuration information of the system; when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module sends the MCLK period through the peer end.
  • the interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module; the data and timing processing module transmits data according to the interface timing, and configures a current data communication rate of the module according to the register. Processing data to achieve parallel connection Rate adaptation configuration.
  • the parallel interface timing control apparatus 80 includes: a register configuration module 801, a rate adaptation module 802, and an interface timing control module. 803 and data and timing processing module 804, wherein
  • the register configuration module 801 is configured to acquire configuration information of the system
  • the rate adaptation module 802 is configured to generate an updated data communication rate and an adaptive flag by using period information of the MCLK sent by the peer end when detecting that the first configuration information in the register configuration module is valid, and The updated data communication rate and the adaptive flag are sent to the register configuration module;
  • the register configuration module 801 is further configured to configure a current data communication rate according to the adaptive flag
  • the interface timing control module 803 is configured to perform a second according to the register configuration module Configuration information and MCLK information generation interface timing;
  • the data and timing processing module 804 is configured to transmit data according to the interface timing, and process data according to the number of channels in the register configuration module and the current data communication rate.
  • the configuration information includes: interface module enable, channel number, default data communication rate, TDD mode subframe type, adaptive function enable, adaptive successful detection times, and adaptive failure detection times. ;
  • the adaptive function is enabled to correspond to the first configuration information, where the first configuration information is effective to enable the adaptive function in the register configuration module to be valid, for example, the adaptive function is enabled when the high level is enabled; and the TDD mode is used. Corresponding to the second configuration information.
  • the period information of the MCLK sent by the opposite end refers to the period information of the MCLK sent by the RFIC;
  • the adaptive flag includes an adaptive success flag and an adaptive failure flag.
  • the block diagram of the rate adaptation module 802 is as shown in FIG. 9.
  • the rate adaptation module 802 includes: an MCLK period detection sub-module 8021, an MCLK clock stability detection sub-module 8022, a rate adaptive failure detection sub-module 8023, and Rate adaptive information update submodule 8024;
  • the MCLK period detecting sub-module 8021 is configured to acquire the period information of the MCLK through the working clock, and send the period information of the MCLK to the MCLK clock stability detecting sub-module 8022 and the rate adaptive information updating sub-module 8024 in real time;
  • the working clock is not less than 2 times the MCLK clock frequency and is an integer multiple of the MCLK clock frequency;
  • the MCLK clock stability detection sub-module 8022 is configured to trigger the rate adaptive information update sub-module 8024 to generate an updated data communication rate when detecting that the number of consecutive times of the MCLK periodic information coincides with the preset adaptive success value. Sended to the register configuration module 801;
  • rate adaptive information update sub-module 8024 configured to turn off the adaptive function when the number of times of inconsistency of the periodic information of the MCLK that is detected twice consecutive times satisfies the value of the adaptive failure. Yes; among them,
  • the MCLK clock stability detection submodule 8022 is configured to
  • the internal clock stabilization counter When the period information of the MCLK consecutively detected is the same, the internal clock stabilization counter performs an accumulation count to obtain a first accumulated count value; and, when the first accumulated count value reaches a pre-configured adaptive success value, Generating a rate adaptive success flag; and transmitting the rate adaptive success flag to the rate adaptive information update sub-module 8024 and the register configuration module 801.
  • the rate adaptive information update sub-module 8024 is configured to convert the period information of the MCLK into a data communication rate when the rate adaptive success flag is detected; and to use the data communication rate converted by the period information of the MCLK as the updated data.
  • the communication rate is sent to the register configuration module 801.
  • the MCLK clock stability detection sub-module 8022 and the rate adaptive information update sub-module 8024 are configured to implement an updated data communication rate, and send the information to the The process of register configuration module 801.
  • the MCLK clock stability detection sub-module 8022 is further configured to trigger the rate adaptive information update sub-module 8024 to turn off the adaptive function when detecting that the number of times of the inconsistency of the periodic information of the MCLKs of the two consecutive times meets the adaptive failure value;
  • the MCLK clock stability detection sub-module 8022 is further configured to
  • the internal clock stabilization counter When detecting that the period information of the MCLK consecutive times is inconsistent, the internal clock stabilization counter performs an accumulation count clearing to generate an MCLK change flag; and, the MCLK change flag is sent to the rate adaptive failure detection submodule 8023.
  • the rate adaptive fail detection sub-module 8023 is configured to, when detecting the MCLK change flag, perform an accumulative counting operation on the internal clock change counter to obtain a second accumulated count value; and, when the second accumulated count value Upon reaching the pre-configured adaptive failure value, a rate adaptive failure flag is generated; and the rate adaptive failure flag is sent to the rate adaptive information update sub-module 8024 and the register configuration module 801.
  • the rate adaptive information update sub-module 8024 is further configured to turn off the rate adaptation function when the rate adaptation failure flag is detected.
  • the MCLK clock stability detection sub-module 8022, the rate adaptive failure detection sub-module 8023, and the rate adaptive information update sub-module 8024 are configured to implement the shutdown. The process of adapting to functions.
  • the register configuration module 801 is further configured to: configure a current data communication rate according to the adaptive success flag as the updated data communication rate; configure a current data communication rate according to the adaptive failure flag to be configured to be sent by the system to the register Configure the module's default data communication rate.
  • the communication type includes: uplink communication and downlink communication;
  • the interface timing refers to an interface timing that meets the requirements of the JESD207 protocol
  • the interface timing control module 803 is configured to
  • the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, configured to generate an interface timing corresponding to the uplink data communication;
  • the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, configured to generate an interface timing corresponding to the downlink data communication, and generate the same FCLK timing as the MCLK timing according to the MCLK information delay .
  • the data and timing processing module 804 is configured to receive uplink data transmitted by the interface timing control module 803 according to an interface timing corresponding to the uplink data communication when the data communication type is uplink data communication, according to the register configuration module 801. The number of channels in the current data communication rate and the current data communication rate are sent to the BBIC's subsequent stage circuit;
  • the interface timing control module 803 sends data to the data and timing processing module 804, that the interface timing control module 803 corresponds to TXNRX, ENABLE timing signals, and MCLK timing according to uplink data communication.
  • the interface timing control module 803 receives data of the DDR sent by the peer end through the DIQ interface, the interface timing control module 803 converting the data of the DDR
  • the data for the single data rate (SDR) is sent to the data and timing processing module 804 for data processing, and the data and timing processing module 804 finally corresponds to the TXNRX, ENABLE timing signal and MCLK timing according to the uplink data communication.
  • the processed SDR data is sent to the BBIC's subsequent stage circuit;
  • the data communication type is downlink data communication
  • receiving downlink data transmitted by the BBIC subsequent circuit according to the interface timing corresponding to the downlink data communication, according to the number of channels in the register configuration module 801 and the current data communication rate.
  • the downlink data is sent to the interface timing control module 803;
  • the data sent by the subsequent circuit of the BBIC to the data and timing processing module 804 is SDR data
  • the subsequent circuit of the BBIC corresponds to the TXNRX and ENABLE timings according to the downlink data communication.
  • the signal and MCLK timings send SDR data to the data and timing processing module 804, and the data of the SDR processed by the data and timing processing module 804 is finally converted to DDR data by the interface timing control module 803.
  • the data of the DDR is sent by the interface timing control module 803 to the opposite end according to the downlink data communication corresponding TXNRX, ENABLE timing signal and FCLK through the DIQ interface.
  • the present embodiment also uses the rate adaptation module 802 to generate a rate adaptive fail flag off rate adaptation function for the problem that the MCLK frequent jitter causes frequent update of the data communication rate information.
  • the rate adaptation module 802 uses the rate adaptation module 802 to generate a rate adaptive fail flag off rate adaptation function for the problem that the MCLK frequent jitter causes frequent update of the data communication rate information.
  • a rate adaptive invalidation flag is generated and sent to the register configuration module 801.
  • the rate adaptive information update sub-module 8024 detects the rate adaptive invalidation flag and then turns off the rate adaptation function.
  • the embodiment provides a parallel interface timing control device
  • the register configuration module 801 is configured to acquire configuration information of the system
  • the rate adaptation module 802 is configured to detect the first configuration in the register configuration module.
  • the register configuration module 801 is configured to configure a current data communication rate according to the adaptive flag
  • the interface timing control module 803 is configured to be configured according to the register Second configuration information and MCLK information generation interface timing
  • the data and timing processing module 804 is configured to transmit data according to the interface timing, process data according to a current data communication rate of the register configuration module, thereby implementing a parallel interface rate Adaptive configuration.
  • a parallel interface timing control method according to an embodiment of the present invention is shown.
  • the method periodically detects the period information of the MCLK clock of the host RFIC and combines the channel configuration information to obtain the slave BBIC and the host.
  • the communication rate of the RFIC thus, the interface of the slave sends the timing signal required by the host RFIC at the detected rate to complete the communication between the two devices; since the periodic detection is performed, when the host RFIC clock MCLK changes, the communication is changed. Rate to ensure normal communication between the two devices.
  • the method is used for a parallel interface timing control device, and the parallel interface timing control device comprises: a register configuration module, a rate adaptation module, an interface timing control module, and a data and timing processing module, the method comprising:
  • the register configuration module acquires configuration information of the system
  • the rate adaptation module When the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module generates an updated data communication rate and an adaptive flag by using period information of the MCLK sent by the peer end, And transmitting the updated data communication rate and the adaptive flag to the register configuration module;
  • the register configuration module configures a current data communication rate according to the adaptive flag.
  • the interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module.
  • the data and timing processing module transmits data according to the interface timing, and processes data according to the number of channels in the register configuration module and the current data communication rate.
  • the configuration information includes: interface module enable, number of channels, default Data communication rate, TDD mode subframe type, adaptive function enable, adaptive successful detection times, adaptive failure detection times;
  • the adaptive function is enabled to correspond to the first configuration information, where the first configuration information is effective to enable the adaptive function in the register configuration module to be valid, for example, the adaptive function is enabled when the high level is enabled; and the TDD mode is used. Corresponding to the second configuration information.
  • the rate adaptation module includes: an MCLK period detection submodule, an MCLK clock stability detection submodule, a rate adaptive failure detection submodule, and a rate adaptive information update submodule;
  • the period information of the MCLK sent by the peer end refers to the period information of the MCLK sent by the RFIC;
  • the adaptive flag includes an adaptive success flag and an adaptive failure flag.
  • FIG. 11 is a flowchart of the adaptive module generating an updated data communication rate.
  • the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module passes The period information of the MCLK sent by the terminal generates an updated data communication rate and an adaptive flag, and sends the updated data communication rate and the adaptive flag to the register configuration module, including:
  • the rate adaptation module acquires period information of the MCLK by using an operating clock; the working clock is not less than twice the MCLK clock frequency and is an integer multiple of the MCLK clock frequency;
  • step S10022 When the rate adaptation module detects that the number of coincidences of the periodic information of the two consecutive MCLKs meets the preset adaptive success value, step S10023 to step S10027 are performed; when the MCLK clock stability detection submodule detects two consecutive When the number of times of inconsistency of the periodicity information of the MCLK meets the adaptive failure value, step S10028 to step S100212 are performed;
  • the clock stabilization counter inside the rate adaptation module performs an accumulation count, and the rate adaptation module obtains a first accumulated count value
  • the rate adaptation module sends the rate adaptive success flag to the registration Device configuration module
  • the rate adaptation module sends a data communication rate of the cycle information conversion of the MCLK to the register configuration module as an updated data communication rate.
  • step S10023 to step S10027 when the rate adaptation module detects that the number of coincidences of the periodic information of the two consecutive times of MCLK meets the preset adaptive success value, an updated data communication rate is generated and sent to the The implementation process of the register configuration module.
  • S10028 The clock stabilization counter inside the rate adaptation module performs an accumulation count clearing, and the rate adaptation module generates an MCLK change flag.
  • the rate adaptation module generates a rate adaptation failure flag when the second accumulated count value reaches a pre-configured adaptive failure value of the rate adaptation module;
  • the rate adaptation module sends the rate adaptation failure flag to the register configuration module.
  • step S10028 to step S100212 is an implementation process for turning off the adaptive function when the rate adaptation module detects that the number of times of coincidence of the periodic information of the MCLKs that are consecutive two times satisfies the adaptive failure value.
  • the register configuration module configures a current data communication rate according to the adaptive flag, including:
  • the register configuration module configures a current data communication rate as the updated data communication rate according to an adaptive success flag
  • the register configuration module configures a current data communication rate according to an adaptive failure flag to configure a default data communication rate that the system sends to the register configuration module.
  • the communication type includes: uplink communication and downlink communication;
  • the interface timing refers to an interface timing that meets the requirements of the JESD207 protocol
  • the interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module, including:
  • the interface timing control module When the data communication type in the TDD mode subframe type in the register configuration module is uplink data communication, the interface timing control module generates an interface timing corresponding to the uplink data communication;
  • the interface timing control module When the data communication type in the TDD mode subframe type in the register configuration module is downlink data communication, the interface timing control module generates an interface timing corresponding to the downlink data communication, and the interface timing control module according to the MCLK information The delay generates the same FCLK timing as the MCLK timing.
  • the data includes uplink receiving data and downlink sending data
  • FIG. 12 is a flowchart of processing data by the data and timing processing module, the data and timing processing module transmits data according to the interface timing, and processes according to the number of channels in the register configuration module and the current data communication rate.
  • Data including:
  • the data and timing processing module receives uplink data transmitted by the interface timing control module according to an interface timing corresponding to the uplink data communication, where the data and timing processing module is configured according to the register Configuring the number of channels in the module and the current data communication rate to send the uplink data to the subsequent circuit of the BBIC;
  • the data and timing processing module receives downlink data transmitted by the BBIC subsequent circuit according to an interface timing corresponding to the downlink data communication, where the data and timing processing module is configured according to the register The number of channels in the module and the current data communication rate send the downlink data to the interface timing control module.
  • the interface timing control module For step S10051, the interface timing control module
  • the data sent to the data and the timing processing module means that the interface timing control module receives the data of the DDR sent by the opposite end through the DIQ interface according to the uplink data communication corresponding to the TXNRX, the ENABLE timing signal and the MCLK timing, and the interface timing control module Data for converting DDR data into SDR is sent to the data and timing processing module for data processing, and the data and timing processing module finally responds to the TXNRX, ENABLE timing signal and MCLK sequence processed SDR data according to the uplink data communication.
  • the data sent by the subsequent circuit of the BBIC to the data and the timing processing module is data of the SDR
  • the subsequent circuit of the BBIC corresponds to the TXNRX according to the downlink data communication.
  • the ENDR timing signal and the MCLK timing send the SDR data to the data and timing processing module, and the data of the SDR processed by the data and the timing processing module is finally converted into the data of the DDR by the interface timing control module,
  • the data of the DDR is sent to the opposite end by the interface timing control module through the DIQ interface according to the downlink data communication corresponding to the TXNRX, ENABLE timing signal and FCLK.
  • the rate adaptation module generates a rate adaptive failure flag off rate adaptation function for the problem that the MCLK frequent jitter causes the data communication rate information to be frequently updated.
  • a rate adaptive fail flag is generated and sent to the register configuration module and the rate adaptation.
  • the information update sub-module, the rate adaptive information update sub-module detects the rate adaptive invalidation flag and then turns off the rate adaptation function.
  • the embodiment provides a parallel interface timing control method
  • the register configuration module acquires configuration information of the system, and when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate is self-determined.
  • the adaptation module generates an updated data communication rate and an adaptive flag by using the period information of the MCLK sent by the peer end, and sends the updated data communication rate and the adaptive flag to the register configuration module, where the register configuration module is configured according to the Adapting the flag to configure a current data communication rate, the interface timing control module according to the registration
  • the second configuration information in the configuration module selects a timing signal required for the communication type and the communication type, the data and timing processing module transmits data according to the interface timing, and processes data according to the current data communication rate of the register configuration module.
  • embodiments of the present invention can provide a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.
  • These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computing and readable memory produce an article of manufacture comprising the instruction device.
  • the instruction means implements the functions specified in one or more blocks of the flow or processes and/or block diagrams in the flowchart.
  • These computer program instructions can also be loaded on a computer or other programmable processing device such that instructions executed on a computer or other programmable device are provided for implementation in a flow or a block diagram of a flow or a block diagram or The steps of the function specified in multiple boxes.
  • the register configuration module acquires configuration information of the system; when the rate adaptation module detects that the first configuration information in the register configuration module is valid, the rate adaptation module sends the information through the peer end.
  • the cycle information of the MCLK generates an updated data communication rate and an adaptive flag, and sends the updated data communication rate and the adaptive flag to the register configuration module;
  • the register configuration module configures the current data communication according to the adaptive flag Rate;
  • the interface timing control module generates an interface timing according to the second configuration information and the MCLK information in the register configuration module;
  • the data and timing processing module transmits data according to the interface timing, according to the register configuration module current
  • the data communication rate processes the data to enable parallel interface rate adaptive configuration.

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Abstract

La présente invention concerne, selon des modes de réalisation, un procédé et un appareil de commande de séquence temporelle d'interface parallèle, l'appareil de commande de séquence temporelle d'interface parallèle consistant : en un module de configuration de registre, en un module d'adaptation de débit, en un module de commande de séquence temporelle d'interface et en un module de traitement de données et de séquence temporelle, destinés à mettre en œuvre une configuration adaptative du débit d'interface parallèle.
PCT/CN2017/085924 2016-10-28 2017-05-25 Procédé et appareil de commande de séquence temporelle d'interface parallèle Ceased WO2018076682A1 (fr)

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Application Number Priority Date Filing Date Title
CN201610962540.7 2016-10-28
CN201610962540.7A CN108011703B (zh) 2016-10-28 2016-10-28 一种并行接口时序控制方法和装置

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