WO2018074228A1 - Semiconductor device, and production method therefor - Google Patents

Abstract

This semiconductor device is provided with: a semiconductor substrate (10) provided with a diode-forming region (Di); a first-conductivity-type upper diffusion region (20, 50, 70) which is formed in the surface layer of a main surface (10a) of the semiconductor substrate, and in the diode-forming region; and a second-conductivity-type lower diffusion region (30, 60, 80) which is formed in a deeper position than the upper diffusion region with respect to the main surface in the depth direction of the semiconductor substrate, and which has a higher impurity concentration than the semiconductor substrate. Furthermore, the lower diffusion region forms a PN junction surface (S) with the upper diffusion region at a position deeper than the main surface, and is provided with a maximum point (P, P1, P2) which indicates the maximum concentration in an impurity concentration profile of the lower diffusion region in the diode-forming region.

Description

Semiconductor device and manufacturing method thereof Cross-reference of related applications

This application is based on Japanese Patent Application No. 2016-204668 filed on October 18, 2016 and Japanese Patent Application No. 2017-76087 filed on April 6, 2017. The description of is incorporated.

The present disclosure relates to a semiconductor device including a Zener diode and a manufacturing method thereof.

A constant voltage power supply using a Zener diode is known. A constant voltage power supply is also used for a battery monitoring IC mounted on a vehicle, but high-precision voltage control is required to supply power to the IC.

Conventionally, in a PN junction between an N conductivity type epitaxial layer and a P conductivity type diffusion layer, the Zener voltage is uniquely determined depending on the concentration of both. On the other hand, in the semiconductor device disclosed in Patent Document 1, the first diffusion region and the second diffusion region are provided in the semiconductor substrate, and the impurity concentration of the two diffusion regions related to the PN junction is arbitrarily controlled. Made possible. The desired Zener characteristic can be obtained by controlling the impurity concentration of the diffusion region.

JP 2010-239015 A

By the way, it is known that the Zener voltage varies over time due to breakdown. This characteristic variation is presumed to occur when hot carriers generated by the breakdown phenomenon are trapped by surface defects of the semiconductor substrate.

In the semiconductor device described in Patent Document 1, the breakdown voltage due to the overlap is reduced at the junction due to the overlap between the first diffusion region and the second diffusion region. And it is said that yielding occurs in the part corresponding to this overlap. In such a configuration, the portion corresponding to the overlap is an area existing three-dimensionally, and the yield phenomenon occurs somewhere in the three-dimensional area, but the position is indefinite. That is, the exact position at which yield occurs cannot be controlled.

The occurrence of hot carriers and the state of traps on the surface defects of the hot carriers differ depending on the position where breakdown occurs, so the occurrence position of breakdown is uncertain because it causes the amount of variation in Zener voltage over time to increase. Become. Then, a change in Zener voltage with time may hinder high-accuracy voltage control.

Therefore, an object of the present disclosure is to provide a semiconductor device capable of suppressing a change in Zener voltage and a method for manufacturing the semiconductor device.

A semiconductor device according to a first aspect of the present disclosure includes a semiconductor substrate having a diode formation region, an upper diffusion region of a first conductivity type formed in a surface layer of a main surface of the semiconductor substrate in the diode formation region, and a depth of the semiconductor substrate. A lower diffusion region of a second conductivity type formed at a position deeper than the upper diffusion region with respect to the main surface in the vertical direction, and the lower diffusion region is a PN junction with the upper diffusion region at a position deeper than the main surface And has a local maximum point indicating the local maximum in the impurity concentration profile of the lower diffusion region in the diode formation region.

According to this, since the electric field can be increased at the maximum point of the impurity concentration in the lower diffusion region, the breakdown phenomenon can be easily generated at the maximum point. The designer can arbitrarily determine the impurity concentration of the lower diffusion region and its peak position, and can control the position where the breakdown phenomenon occurs. That is, the variation factor of the Zener voltage can be suppressed to the minimum.

Further, since the PN junction surface between the upper diffusion region and the lower diffusion region is formed at a position deeper than the main surface of the semiconductor substrate, it is trapped by surface defects existing on the main surface when hot carriers are generated. Probability can be reduced. That is, the fluctuation amount of the Zener voltage can be reduced.

Thus, according to this semiconductor device, it is possible to suppress the fluctuation factor of the Zener voltage and to suppress the characteristic fluctuation amount at the breakdown.

The method for manufacturing a semiconductor device according to the second aspect of the present disclosure is such that a semiconductor substrate is prepared, impurities are implanted into a surface layer of the main surface of the semiconductor substrate, and a rotationally symmetric shape is obtained when the main surface is viewed from the front. Forming the second conductivity type lower implant region, forming the lower implant region, diffusing the lower implant region by annealing, and after diffusing by annealing the lower implant region, the surface layer on the main surface of the semiconductor substrate An upper implantation region of the first conductivity type is formed at a position shallower to the main surface than the lower implantation region so as to have a rotationally symmetric shape concentric with the lower implantation region, After forming, the lower implantation region is diffused by annealing to form the lower diffusion region, and the upper implantation region is diffused to form the upper diffusion region.

According to this, since the local maximum point where the impurity concentration becomes maximum can be formed on the rotational symmetry axis of the lower implantation region, the variation factor of the Zener voltage can be suppressed to the minimum.

Further, a semiconductor device according to the third aspect of the present disclosure includes a second conductivity type semiconductor substrate having a diode formation region, and a first conductivity type upper diffusion formed in a surface layer of a main surface of the semiconductor substrate in the diode formation region. A second conductivity type lower diffusion region formed at a position deeper than the upper diffusion region with respect to the main surface in the depth direction of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate; and a diode formation region A second conductivity type counter electrode region formed on a surface layer of the main surface and having an impurity concentration higher than that of the semiconductor substrate, and further, a surface layer of the main surface between the upper diffusion region and the counter electrode region In the region, an inter-electrode region of the second conductivity type having an impurity concentration higher than that of the semiconductor substrate is formed.

According to this, when a breakdown occurs, it is possible to suppress the intrusion of a depletion layer that progresses to the main surface layer between the upper diffusion region and the counter electrode region, and it is possible to suppress an increase in electrical resistance in the current path. Therefore, fluctuations in the Zener voltage can be suppressed.

Furthermore, the method for manufacturing a semiconductor device according to the fourth aspect of the present disclosure includes preparing a second conductivity type semiconductor substrate, implanting impurities into the surface layer of the main surface of the semiconductor substrate, and having an impurity concentration higher than that of the semiconductor substrate. Forming a raised second conductivity type lower implantation region; forming a lower implantation region; diffusing the lower implantation region by annealing; and diffusing by annealing of the lower implantation region; Impurities are implanted into the surface layer to form an upper implantation region of the first conductivity type at a position shallower than the main surface of the lower implantation region. After forming the upper implantation region, the lower implantation region is diffused by annealing. Forming the lower diffusion region, diffusing the upper implantation region to form the upper diffusion region, and in addition, injecting impurities into the surface layer of the semiconductor substrate at a position separated from the lower implantation region. Forming a second conductivity type counter-electrode injection region, forming an inter-electrode region having a higher impurity concentration than the semiconductor substrate in a surface layer of the semiconductor substrate between the counter-electrode injection region and the lower injection region, Is provided.

According to this, when a breakdown occurs, it is possible to suppress the intrusion of a depletion layer that progresses to the main surface layer between the upper diffusion region and the counter electrode region, and it is possible to suppress an increase in electrical resistance in the current path. Therefore, fluctuations in the Zener voltage can be suppressed.

The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawing
FIG. 1 is a diagram illustrating a cross section and an upper surface of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing a process of preparing a semiconductor substrate, FIG. 3 is a cross-sectional view showing a process of forming the lower implantation region, FIG. 4 is a cross-sectional view showing the first annealing step, FIG. 5 is a cross-sectional view showing a process of forming the upper implantation region, FIG. 6 is a cross-sectional view showing the second annealing step, FIG. 7 is a diagram showing a three-dimensional profile of impurity concentration. FIG. 8 is a diagram showing the change over time in the amount of fluctuation of the Zener voltage. FIG. 9 is a cross-sectional view of the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing a process of forming the lower implantation region, FIG. 11 is a cross-sectional view showing the first annealing step, FIG. 12 is a cross-sectional view showing the process of forming the upper implantation region, FIG. 13 is a cross-sectional view of the semiconductor device according to the third embodiment. FIG. 14 is a cross-sectional view showing a process of forming a lower injection region and a counter electrode injection region, FIG. 15 is a cross-sectional view showing the first annealing step, FIG. 16 is a cross-sectional view showing a process of forming the upper injection region and the interelectrode injection region, FIG. 17 is a cross-sectional view of the semiconductor device according to the fourth embodiment.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same reference numerals are given to the same or equivalent parts.

(First embodiment)
First, a schematic configuration of the semiconductor device according to the present embodiment will be described with reference to FIG.

This semiconductor device includes a Zener diode as an element, and is introduced into a power supply circuit, for example, and functions as a constant voltage power supply.

As shown in FIG. 1, the semiconductor device 100 includes a semiconductor substrate 10, an upper diffusion region 20, a lower diffusion region 30, and a silicide block layer 40.

The semiconductor substrate 10 is a part of an N conductivity type semiconductor wafer, and in particular, FIG. 1 shows a part of the main surface 10a side. The semiconductor substrate 10 has a diode formation region Di. In the diode formation region Di, a PN junction diode is formed as an element by forming an upper diffusion region 20 and a lower diffusion region 30 described later. The P diffusion type upper diffusion region 20 functions as an anode, and the N conductivity type semiconductor substrate 10 functions as a cathode. In this embodiment, the N conductivity type corresponds to the second conductivity type, and the P conductivity type corresponds to the first conductivity type.

The upper diffusion region 20 is a P conductivity type semiconductor region. The upper diffusion region 20 is formed in the surface layer on the main surface 10 a side of the semiconductor substrate 10 so as to be exposed on the main surface 10 a of the semiconductor substrate 10. As shown in FIG. 1, the upper diffusion region 20 is formed to be rotationally symmetric with respect to an axis A orthogonal to the main surface 10a. In particular, the upper diffusion region 20 in the present embodiment is formed in a substantially perfect circle shape centered on a point passing through the axis A when the main surface 10a is viewed from the front. And the cross-sectional shape which passes along the axis | shaft A of the upper diffusion area | region 20 has a structure which became depressed so that the axis | shaft A vicinity might be shown in FIG. That is, it is formed in a disk shape with a recessed center. As will be described later, the axis A in this embodiment coincides with the symmetry axis. Note that the upper diffusion region 20 in the present embodiment is a substantially perfect circle when the main surface 10a is viewed from the front, and has a shape like a so-called rotating body, but does not necessarily need to be a rotating body. For example, the shape may be n times symmetrical when the main surface 10a is viewed from the front. Specifically, an ellipse, a capsule shape (2-fold symmetry), an equilateral triangle (3-fold symmetry), a square (4-fold symmetry), or the like may be employed.

The lower diffusion region 30 is an N conductivity type semiconductor region. The lower diffusion region 30 is formed so as to cover the upper diffusion region 20. Similarly to the upper diffusion region 20, the lower diffusion region 30 is also rotationally symmetric with respect to the axis A. In particular, the lower diffusion region 30 in the present embodiment has an axis when the main surface 10a is viewed from the front. It is formed in a substantially perfect circle shape centered on a point passing through A. Also for the lower diffusion region 30, the shape of the main surface 10 a when viewed from the front is not limited to a perfect circle, but may be formed to be n times symmetrical.

Since the lower diffusion region 30 is formed adjacent to the upper diffusion region 20, a PN junction surface S is formed between the lower diffusion region 30 of N conductivity type and the upper diffusion region of P conductivity type. Yes. As described above, since the upper diffusion region 20 has a concave shape on the opposite surface that is not exposed to the main surface 10a, the PN junction surface S also has the same shape. That is, the PN junction surface S has a concave shape when the upper diffusion region 20 is mainly used.

Note that the lower diffusion region 30 in the present embodiment completely covers the upper diffusion region 20, and a part thereof is exposed to the main surface 10a. That is, when the main surface 10a is viewed from the front, the lower diffusion region 30 is exposed to the main surface 10a in a region beyond the outer edge of the upper diffusion region 20 with respect to the formation center. In other words, when the main surface 10a is viewed from the front, the upper diffusion region 20, the lower diffusion region 30, and the N-conductivity type semiconductor region of the semiconductor substrate 10 are arranged in this order around the point where the axis A intersects the main surface 10a. It is formed in a concentric circle.

As described above, in this semiconductor device 100, the P conductivity type semiconductor region of the upper diffusion region 20 and the lower diffusion region 30 and the N conductivity type semiconductor region of the semiconductor substrate 10 form a PN junction to form a diode. . The P diffusion type upper diffusion region 20 functions as an anode, and the N conductivity type semiconductor substrate 10 functions as a cathode.

The silicide block layer 40 is an insulating film, and is formed of, for example, SiO ₂ in this embodiment. The silicide block layer 40 is formed in an annular shape around the point where the axis A and the main surface 10a intersect. In the semiconductor device 100 according to the present embodiment, the upper diffusion region 20 and the lower diffusion region 30 are exposed on the main surface 10a, and the semiconductor region of the semiconductor substrate 10 is exposed outside thereof. The silicide block layer 40 is formed so as to cover the surface from the outer edge of the upper diffusion region 20 through the lower diffusion region 30 to the semiconductor region of the semiconductor substrate 10. That is, it is formed so as to straddle the PN junction line L1 between the P conductivity type upper diffusion region 20 and the N conductivity type semiconductor region exposed on the main surface 10a and the boundary line L2 between the lower diffusion region 30 and the semiconductor substrate 10. ing.

The silicide block layer 40 functions as an electrode for the anode and the cathode. For example, when a silicide electrode containing cobalt is stacked on the main surface 10a, the silicide block layer 40 and the N diffusion type P diffusion region 20 are formed. It is formed for the purpose of maintaining electrical insulation between the lower diffusion region 30 and the semiconductor substrate 10.

Next, a method for manufacturing the semiconductor device 100 will be described with reference to FIGS. 2 to 6 and FIG.

First, as shown in FIG. 2, a semiconductor substrate 10 having N conductivity type is prepared.

Thereafter, a photoresist (not shown) cut into a perfect circle having a diameter of R is laminated on the main surface 10a, and phosphorus or arsenic is ion-implanted. The ion implantation is performed with the same energy on the one surface 10a, and the implantation depth is made substantially constant. As a result, as shown in FIG. 3, an N conductivity type lower implantation region 31 having a diameter R is formed. That is, a disk-shaped N conductivity type region having the axis A as the rotational symmetry axis is formed. The lower implantation region 31 is a region before being diffused by annealing, and becomes the lower diffusion region 30 after two annealing steps described later.

After the formation of the lower implantation region 31, the photoresist (not shown) is removed and a first annealing process is performed. By the annealing process, impurities forming the lower implantation region 31 diffuse in the semiconductor substrate 10 as shown in FIG. In the first annealing step, the impurity region 32 in which the lower implantation region 31 is thermally diffused does not diffuse as much as the lower diffusion region 30 shown in FIG.

After the first annealing step, a photoresist (not shown) having the same center as that of the lower implantation region 31 and having a smaller diameter than the impurity region 32 shown in FIG. And boron is ion-implanted. The ion implantation is performed with the same energy on the one surface 10a, and the implantation depth is made substantially constant. As a result, as shown in FIG. 5, a P conductivity type upper implantation region 21 surrounded by the impurity region 32 is formed. That is, a disk-shaped P conductivity type region having the axis A as a rotationally symmetric axis is formed. The upper implantation region 21 is a region before being diffused by annealing, and becomes the upper diffusion region 20 after the second annealing step described later.

After the formation of the upper implantation region 21, the photoresist (not shown) is removed and a second annealing step is performed. By the second annealing step, the upper implantation region 21 is thermally diffused as shown in FIG. 6, and the impurity region 32 in which the lower implantation region 31 is diffused to some extent is further thermally diffused. After performing the second annealing step, the upper implantation region 21 diffuses to a region corresponding to the upper diffusion region 20, and the lower implantation region 31 diffuses to a region corresponding to the lower diffusion region 30.

It should be noted that the formation depth of the lower diffusion region 30 after thermal diffusion is preferably designed to be substantially the same as the ion implantation diameter R of the lower implantation region 31. Parameters for the annealing temperature, ion implantation energy, and impurity concentration may be determined by making the process common with other elements formed on the semiconductor substrate 10, and it may be difficult to change the values. For this reason, if the formation depth of the lower diffusion region 30 is designed to be substantially the same as the ion implantation diameter R of the lower implantation region 31, the formation radius of the lower implantation region 31 is set to be the same as that of the assumed lower diffusion region 30. It means to match the formation depth.

Incidentally, before the second annealing step is performed, the impurity concentration of the impurity region 32 caused by the lower implantation region 31 has a peak at a position on the axis A and deeper than the upper implantation region 21. For this reason, when the upper implantation region 21 is thermally diffused through the second annealing step, the conductivity type is unlikely to be reversed in the vicinity of the center of the disk-shaped upper implantation region 21. Thus, after performing the second annealing step, as shown in FIG. 6, the cross-sectional shape passing through the axis A of the upper diffusion region 20 becomes a structure that is recessed toward the vicinity of the axis A as shown in FIG. 1. Yes. That is, the upper diffusion region 20 is formed in a disk shape with a recessed center. That is, the PN junction surface S between the upper diffusion region 20 and the lower diffusion region 30 has a concave shape when the upper diffusion region 20 is mainly used.

Note that the contour lines shown in the lower diffusion region 30 in FIG. 6 indicate the contour lines of the impurity concentration, and that the peak of the impurity concentration in the lower diffusion region 30 is located below the dent in the upper diffusion region 20. Show.

After the second annealing step, as shown in FIG. 1, the PN junction line L1 between the P conductivity type upper diffusion region 20 and the N conductivity type semiconductor region exposed on the main surface 10a, and the lower diffusion region 30 and the semiconductor The silicide block layer 40 is formed so as to straddle the boundary line L2 with the substrate 10.

The semiconductor device 100 can be manufactured by a manufacturing method including the above steps.

Next, functions and effects of the semiconductor device 100 and the manufacturing method thereof in the present embodiment will be described.

In the semiconductor device 100 shown in FIGS. 1 and 6, since the upper diffusion region 20 and the lower diffusion region 30 are formed in substantially rotational symmetry with respect to the axis A, the respective impurity profiles are also substantially rotationally symmetric with respect to the axis A. It becomes. The inventor simulated a specific impurity profile using a computer. The simulation results are shown in FIG.

As shown in FIG. 7, the lower diffusion region 30 formed in the diode formation region Di has a maximum point P at which the impurity concentration is maximum. In this embodiment, in particular, there is only one maximum point P in the lower diffusion region 30. The maximum point P in the present embodiment is on the axis A and is located below the PN junction surface S.

In general, in a PN junction Zener diode, when a reverse bias is applied, an electric field is increased between portions with high impurity concentrations in an N conductivity type region and a P conductivity type region, and a breakdown phenomenon is likely to occur. In the semiconductor device 100 according to the present embodiment, the high impurity concentration portion of the lower diffusion region 30 exhibiting N conductivity is not three-dimensionally distributed as in the prior art, but is defined as zero dimension (point). Therefore, it is possible to identify the portion where the yield phenomenon occurs as a point. That is, the yielding phenomenon in the semiconductor device 100 can be fixed at a substantially predetermined position (maximum point P).

The cause of increasing the amount of fluctuation of the Zener voltage over time is presumed to be that the generation of the breakdown phenomenon is indefinite because the generation source of the breakdown phenomenon is distributed three-dimensionally. In the semiconductor device 100, the occurrence position of the breakdown phenomenon can be determined as a point. According to this, as compared with the conventional configuration in which the breakdown phenomenon occurs three-dimensionally, the generation position of the breakdown phenomenon can be limited. As shown in FIG. It can be suppressed compared to. For example, when a Zener diode included in the semiconductor device 100 is used as a constant voltage power source, the output voltage can be controlled with high accuracy regardless of the passage of time.

Further, the semiconductor device 100 according to the present embodiment has a concave structure in which the PN junction surface S is recessed when the upper diffusion region 20 is mainly used. In particular, in this embodiment, the structure is recessed near the axis A. According to this, as shown in FIG. 7, it is possible to easily form an impurity distribution having a peak in the lower diffusion region 30 at the lower portion of the recessed portion of the upper diffusion region 20. In other words, the maximum impurity concentration can be easily formed in a dot shape.

Further, in the semiconductor device 100 according to the present embodiment, the upper diffusion region 20 and the lower diffusion region 30 have a rotationally symmetric shape, particularly a perfect circle shape, when the one surface 10a is viewed from the front. According to this, the maximum of the impurity concentration in the lower diffusion region 30 can be on the rotational symmetry axis (axis A in the present embodiment), and the maximum of the impurity concentration can be easily formed in a dot shape.

In addition, in the manufacturing process of the semiconductor device 100 according to the present embodiment, the formation diameter R of the lower implantation region 31 that is a precursor region of the lower diffusion region 30 is substantially the same as the assumed formation depth of the lower diffusion region 30. To do. According to this, the maximum of the impurity concentration in the lower diffusion region 30 can be easily formed in a dot shape. For example, when the formation diameter R of the lower implantation region 31 is larger than the assumed formation depth of the lower diffusion region 30, the maximum impurity concentration is distributed one-dimensionally or two-dimensionally extending in the direction along the main surface 10a. Cheap. Alternatively, when the formation diameter R of the lower implantation region 31 is smaller than the assumed formation depth of the lower diffusion region 30, the maximum impurity concentration is distributed one-dimensionally or two-dimensionally extending in the depth direction of the semiconductor substrate 10. It's easy to do. On the other hand, when the formation diameter R of the lower implantation region 31 is substantially the same as the assumed formation depth of the lower diffusion region 30, the maximum impurity concentration in the lower diffusion region 30 can be easily formed in a dot shape.

Further, the semiconductor device 100 according to the present embodiment ion-implants impurities with a uniform depth in the manufacturing process, particularly in the formation of the upper implantation region 21. According to this, in the second annealing step, the conductivity type is easily reversed at the portion where the impurity concentration in the impurity region 32 which is the precursor region of the lower diffusion region 30 is low, and the concave structure of the PN junction surface S can be easily formed. it can. That is, as described above, the maximum impurity concentration of the lower diffusion region 30 can be easily formed in a dot shape.

Furthermore, in the semiconductor device 100 according to the present embodiment, the lower diffusion region 30 is formed so as to cover the upper diffusion region 20, and is exposed to the main surface 10a. According to this, in the surface layer of the main surface 10a, the depletion layer formed between the P conductivity type upper diffusion region 20 and the N conductivity type region extends in the direction along the main surface 10a. 30 can be suppressed as compared with a configuration in which the main surface is not exposed. Thereby, it is possible to suppress trapping of hot carriers at a level caused by surface defects existing in the vicinity of the main surface 10a, and it is possible to suppress an amount of fluctuation of the Zener voltage with time.

Incidentally, the semiconductor device 100 according to the present embodiment includes the silicide block layer 40 on the main surface 10a. According to this, when the silicide electrode is stacked on the main surface 10a, the silicide is formed between the P diffusion type upper diffusion region 20 and the N conductivity type lower diffusion region 30 or the semiconductor substrate 10. It is possible to prevent electrical continuity due to. For this purpose, the silicide block layer 40 is formed so as to straddle the PN junction line L1 between the upper diffusion region 20 and the lower diffusion region 30 when the lower diffusion region 30 is exposed to the main surface 10a. At the same time, it should be formed so as to straddle the boundary line L <b> 2 between the lower diffusion region 30 and the semiconductor region in the semiconductor substrate 10. Further, when the lower diffusion region 30 is not exposed to the main surface 10 a, it should be formed so as to straddle the boundary line between the upper diffusion region 20 and the semiconductor region in the semiconductor substrate 10.

(Second Embodiment)
In the first embodiment, when the upper diffusion region 20 is mainly used, the PN junction surface S between the upper diffusion region 20 and the lower diffusion region 30 is a concave surface, but a convex surface may be used.

The semiconductor device 110 in this embodiment includes an upper diffusion region 50 and a lower diffusion region 60 having shapes different from those in the first embodiment, as shown in FIG. The semiconductor device 110 has a convex surface portion C that becomes a convex surface in the cross section of the PN junction surface S. Also in the semiconductor device 110, the shape of the upper diffusion region 50 and the lower diffusion region 60 when viewed from the main surface 10a is a perfect circle, and an axis B passing through the center of the perfect circle and orthogonal to the main surface 10a is an axis of symmetry. A rotating body is formed. The concave portion C has a convex vertex on the axis B.

In this embodiment, the impurity concentration of the lower diffusion region 60 has a peak in the vicinity of the lower portion of the concave surface portion formed outside the convex surface portion C of the PN junction surface S. That is, the cross section shown in FIG. 9 has the maximum point of impurity concentration at the points indicated by points P1 and P2. Actually, since the upper diffusion region 50 and the lower diffusion region 60 are disk-shaped, the maximum points P1 and P2 are also part of a circle having the axis B as the symmetry axis. That is, as for the maximum points of the impurity concentration of the lower diffusion region 60 in the present embodiment, a plurality of maximum points are distributed around the axis B in a one-dimensional manner (specifically, in a circular shape).

Thus, by making the PN junction surface S convex, the maximum points of the impurity concentration of the lower diffusion region 60 can be distributed one-dimensionally. Similar to the first embodiment, since the maximum point of the impurity concentration is effective as the occurrence position of the breakdown phenomenon, the occurrence position of the breakdown phenomenon can be defined as a line in the semiconductor device 110. According to this, as compared with the conventional configuration in which the breakdown phenomenon occurs three-dimensionally, the generation position of the breakdown phenomenon can be limited, and the variation of the Zener voltage with time can be suppressed. For example, when a Zener diode included in the semiconductor device 110 is employed as a constant voltage power source, the output voltage can be controlled with high accuracy regardless of the passage of time.

Hereinafter, a method for manufacturing the semiconductor device 110 will be briefly described.

First, as in the first embodiment, a semiconductor substrate 10 is prepared as shown in FIG.

Next, as shown in FIG. 10, phosphorus or arsenic is ion-implanted to form a lower implantation region 61. The lower injection region 61 is formed in a rotationally symmetric shape with the axis B as the axis of symmetry. In particular, in the present embodiment, it is formed in an annular shape. The lower injection region 31 in the first embodiment is a perfect circle when viewed from the main surface 10a, but the lower injection region 61 in the present embodiment is an annular shape in which the vicinity of the center is hollowed out. Since FIG. 10 is a cross-sectional view, the two lower injection regions 61 are illustrated as being separated from each other, but are actually continuous in the front-rear direction of the paper. The lower implantation region 61 is a region that becomes the lower diffusion region 60 by two thermal diffusions in a later process.

Next, the first annealing step is performed. As a result, as shown in FIG. 11, the lower implantation region 61 is thermally diffused to form an N conductivity type impurity region 62. Since the lower implantation region 61 before the annealing step is annular, the impurity concentration structure in the impurity region 62 after the thermal diffusion is a substantially torus structure in which the higher concentration portion is distributed in a circle having the axis B as the symmetry axis. ing.

Next, as shown in FIG. 12, boron is ion-implanted to form an upper implantation region 51. The upper implantation region 51 is formed so as to be included in the impurity region 62. Specifically, the upper implantation region 51 is formed on the upper portion of the impurity region 61 that is the precursor region of the lower diffusion region 60 where the concentration reaches a peak. That is, the upper injection region 51 is formed in a rotationally symmetric shape with the axis B as the axis of symmetry. In particular, in the present embodiment, the upper injection region 51 is formed in an annular shape. The upper injection region 21 in the first embodiment is a perfect circle when viewed from the main surface 10a, but the upper injection region 51 in the present embodiment has an annular shape in which the vicinity of the center is hollowed out. Since FIG. 12 is a cross-sectional view, the two upper injection regions 51 are illustrated so as to be separated from each other, but are actually continuous in the front-rear direction of the drawing. The upper implantation region 51 is a region that becomes the upper diffusion region 50 by two thermal diffusions in a later step.

Next, a second annealing step is performed. As a result, as shown in FIG. 9, the upper implantation region 51 is thermally diffused, and the impurity region 62 in which the lower implantation region 61 is diffused to some extent is further thermally diffused. The upper implantation region 51 after the second annealing step is diffused to a region corresponding to the upper diffusion region 50, and the lower implantation region 61 is diffused to a region corresponding to the lower diffusion region 60.

At this time, the torus shape of the impurity concentration distribution of the impurity region 62 which is a precursor region of the lower diffusion region 60 is substantially maintained, and the maximum impurity concentration of the lower diffusion region 60 is configured in the circular shape as described above. Become. The silicide block layer 40 is formed so as to straddle the PN junction line between the P conductivity type upper diffusion region 50 exposed on the main surface 10a and the N conductivity type semiconductor region, and the boundary line between the lower diffusion region 60 and the semiconductor substrate 10. To do.

As described above, the semiconductor device 110 in which the PN junction surface S is a convex surface can be manufactured.

(Third embodiment)
In the configuration having the lower diffusion regions 30 and 60 exemplified in the first embodiment and the second embodiment, the depletion layer when the breakdown occurs is the lower diffusion regions 30 and 60 in the surface layer of the semiconductor substrate 10. May extend to a wide area outside. This is presumed to be caused by surface traps in the surface layer of the semiconductor device 10, and an increase in the electrical resistance of the current path between the upper diffusion regions 20 and 50 as the anode and the cathode occurs. This increase in electrical resistance may cause a change in Zener voltage with time.

Therefore, as shown in FIG. 13, the semiconductor device 120 according to the present embodiment has a cathode whose impurity concentration is higher than that of the semiconductor substrate 10 in the diode formation region Di in addition to the upper diffusion region 70 and the lower diffusion region 80. A region 90 and an inter-electrode region 91 formed between the upper diffusion region 70 functioning as an anode and the cathode region 90 are provided. The cathode region 90 corresponds to a counter electrode region.

The upper diffusion region 70 and the lower diffusion region 80 in the present embodiment are formed in the same manner as the upper diffusion region 20 and the lower diffusion region 30 in the first embodiment, respectively. That is, the upper diffusion region 70 is a P conductivity type semiconductor region formed so as to be exposed on the main surface 10 a, and the lower diffusion region 80 is formed so as to cover the upper diffusion region 70 in the semiconductor substrate 10. This is an N conductivity type semiconductor region. Although a detailed structure has been described in the first embodiment, it will be omitted. However, in this embodiment as well, the PN junction surface S between the upper diffusion region 70 and the lower diffusion region 80 has a concave shape, and the breakpoint is almost the same. It is structurally controlled to be formed as a point (0 dimension).

The cathode region 90 which is a counter electrode region is an N conductivity type semiconductor region having a concentration higher than that of the semiconductor substrate 10 and is an annular region concentric with the upper diffusion region 70 when the main surface 10a is viewed from the front. . Cathode region 90 is exposed at main surface 10a, and the cathode electrode is in ohmic contact with the exposed surface. In the present embodiment, the cathode region 90 and the lower diffusion region 80 are formed by the same process, and the average impurity concentration is substantially the same.

The interelectrode region 91 is an N conductivity type semiconductor region formed between the upper diffusion region 70 and the cathode region 90. The interelectrode region 91 has an impurity concentration higher than that of the semiconductor substrate 10. The inter-electrode region 91 is formed so as to be exposed on the main surface 10a, whereby the region surrounded by the cathode region 90 is exposed on the main surface 10a of the N conductivity type region constituting the semiconductor substrate 10. Not done. In other words, on the main surface 10a, the distribution of the radial impurities seen from the center of the upper diffusion region 70 is the P conductivity type of the upper diffusion region 70 and the N conductivity type of the lower diffusion region 80 exposed on the main surface 10a. In addition, the N conductivity type of the inter-electrode region 91 and the N conductivity type of the cathode region 90 are spread concentrically.

In the semiconductor device 120 of the present embodiment, the interelectrode region 91 is formed as a separate process from the process of forming the lower diffusion region 80 and the cathode region 90. Therefore, the impurity concentration in the inter-electrode region 91 can be controlled independently of the lower diffusion region 80 and the cathode region 90, and is determined based on the intention of the designer. The impurity concentration of the interelectrode region 91 needs to be lower than that of the cathode region 90 to which the cathode electrode is connected, is higher than that of the semiconductor substrate 10, and is impurity concentration of the lower diffusion region 80. Preferably, the concentration is lower than the maximum value. The place where the impurity concentration of the lower diffusion region 80 in the present embodiment is the maximum is the maximum point of the impurity concentration, which is formed as a point (zero dimension) and becomes a breakpoint. The impurity concentration in the inter-electrode region 91 is set lower than this breakpoint. Thereby, breakdown in the vicinity of the inter-electrode region 91 is prevented. In other words, breakdown is intentionally generated in the lower diffusion region 80.

The method for manufacturing the semiconductor device 120 will be described with reference to FIGS. 14 to 16 with reference to the description regarding the method for manufacturing the semiconductor device 100 in the first embodiment.

First, a semiconductor substrate 10 having N conductivity type is prepared.

Thereafter, as shown in FIG. 14, the lower implantation region 81 is formed by ion implantation, as in the first embodiment. At this time, the counter electrode injection region 92 is formed by the same or different process as the lower injection region 81. Both lower injection region 81 and counter electrode injection region 92 are formed in the surface layer of main surface 10a. These regions are regions that become the lower diffusion region 80 and the cathode region 90 by an annealing process described later.

Then, an annealing process is performed to thermally diffuse impurities. As shown in FIG. 15, in the lower implantation region 81 and the counter electrode implantation region 92, impurities are diffused in the semiconductor substrate 10 to form a semiconductor region having a higher concentration than the semiconductor substrate 10 by the annealing process.

Thereafter, ions are implanted into the region where the lower implantation region 81 is thermally diffused by the annealing process, thereby forming a P conductivity type upper implantation region 71. Further, ions are implanted into the surface layer of the main surface 10 a surrounded by the lower implantation region 81 and the counter electrode implantation region 92 to form an N conductivity type interelectrode implantation region 93.

Thereafter, an annealing process is performed again to thermally diffuse impurities in each semiconductor region. As a result, the impurity distribution is as shown in FIG. Thereafter, the silicide block layer 40 is formed in an annular shape, and the semiconductor device 120 is manufactured. The silicide block layer 40 has an annular inner edge that covers the upper diffusion region 70 and an annular outer edge that covers the cathode region 90. That is, the exposed portion of the lower diffusion region 80 and the inter-electrode region 91 in the main surface 10 a are completely hidden by the silicide block layer 40.

The effect by adopting the semiconductor device 120 in this embodiment will be described.

As described above, the depletion layer when breakdown occurs may extend to a wide region outside the lower diffusion regions 30 and 60 in the surface layer of the semiconductor substrate 10, which is a surface trap in the surface layer of the semiconductor device 10. It is presumed to be caused. The semiconductor device 120 includes the cathode region 90 and the inter-electrode region 91 having a higher concentration than that of the semiconductor substrate 10 so that the N-conductivity type impurity layer constituting the semiconductor substrate 10 is not exposed in the semiconductor substrate 10a. Yes. As a result, it is possible to create a situation in which a depletion layer extending from the upper diffusion region 70 hardly enters the inter-electrode region 91. Therefore, an increase in electrical resistance between the upper diffusion region 70 and the cathode region 90 can be suppressed. Along with this, it is possible to suppress the variation with time of the Zener voltage.

(Fourth embodiment)
In the third embodiment, an example in which the interelectrode implantation region 93 is formed as a process different from the ion implantation for forming the lower diffusion region 80 and the cathode region 90 when forming the interelectrode region 91 has been described. By bringing the formation positions of the diffusion region 80 and the cathode region 90 close to each other, the step of forming the interelectrode injection region 93 can be omitted.

As shown in FIG. 17, in the semiconductor device 130 in the present embodiment, an interelectrode region 91 is formed as a portion where a lower diffusion region 80 and a cathode region 90 as a counter electrode region overlap. The inter-electrode region 91 is of N conductivity type, and is higher in concentration than the impurity concentration constituting the semiconductor substrate 10 as in the third embodiment.

In order to realize such an aspect, for example, in the formation of the lower injection region 81 and the counter electrode injection region 92 described in the third embodiment with reference to FIG. As a result, regions where impurities are thermally diffused by the annealing process after ion implantation overlap each other, and an inter-electrode region 91 is formed. By adopting this mode and method, it is possible to reduce the number of ion implantation steps for forming the interelectrode region 93 and to create a situation in which a depletion layer extending from the upper diffusion region 70 hardly enters the interelectrode region 91. it can.

(Other embodiments)
Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

In each of the above embodiments, the upper diffusion regions 20, 50, and 70 and the upper implantation regions 21, 51, and 71 are formed in a perfect circle shape with the axis A or the axis B as the symmetry axis. The shapes of the upper diffusion regions 20, 50, 70 and the upper injection regions 21, 51, 71 viewed from the front from the surface 10a are not limited to a perfect circle, and may be n-fold symmetrical shapes. Specifically, an ellipse, capsule shape (2 times symmetry), equilateral triangle (3 times symmetry), square (4 times symmetry), regular pentagon (5 times symmetry), regular hexagon (6 times symmetry), etc. are adopted. Also good.

Similarly, an example in which the lower diffusion regions 30, 60, 80 and the lower injection regions 31, 61, 81 are formed in a perfect circle shape with the axis A or the axis B as a symmetry axis is shown. The shapes of the lower diffusion regions 30, 60, 80 and the lower implantation regions 31, 61, 81 are not limited to a perfect circle, but may be any n-fold symmetrical shape. In the two-fold symmetrical shape, the maximum impurity concentration is not a point but a linear shape (one-dimensional) along the long side.

In addition, the lower diffusion regions 30, 60, 80 corresponding to the upper diffusion regions 20, 50, 70 are preferably similar in shape to each other when viewed from the main surface 10a. Since the upper diffusion regions 20, 50, 70 and the corresponding lower diffusion regions 30, 60, 80 have symmetry, the lower diffusion regions 30, 60, 80 break in one or zero dimensions lower than three dimensions. It is easy to form points.

In each of the above-described embodiments, the example in which the silicide block layer 40 is formed in the same center as the upper diffusion regions 20, 50, 70 and the lower diffusion regions 30, 60, 80 has been described. However, the formation center may be shifted. It should be noted that the silicide block layer 40 may be unnecessary if the electrode is not formed by silicide, and is not an essential element in such a form.

Further, in each of the above-described embodiments, the P conductivity type is adopted for the upper diffusion regions 20 and 50 and the N conductivity type is adopted for the lower diffusion regions 30 and 60. However, these conductivity types are configured to be reversed to each other. May be. In addition, although the example which employ | adopts an N conductivity type board | substrate was described as a semiconductor substrate, about the semiconductor substrate, N conductivity type and P conductivity were used irrespective of the conductivity type of the upper diffusion regions 20 and 50 and the lower diffusion regions 30 and 60. Any type of mold may be employed. However, when the inter-electrode region 91 is provided, the counter electrode region corresponding to the cathode region 90, the lower diffusion regions 30, 60, and 80, and the semiconductor substrate 10 need to be of the same conductivity type.

Further, in each of the above-described embodiments, the lower diffusion regions 30, 60, 80 are illustrated as being exposed to the main surface 10 a by completely covering the corresponding upper diffusion regions 20, 50, 70 inside the semiconductor substrate 10. However, the lower diffusion region may be positioned only below the upper diffusion region and not exposed to the main surface 10a. However, since the lower diffusion region completely covers the upper diffusion region and is exposed to the main surface 10a, in the surface layer of the main surface 10a, the P conductivity type upper diffusion regions 20, 50, 70 and N The spread of the depletion layer formed between the conductive type region in the direction along the main surface 10a can be suppressed as compared with the configuration in which the lower diffusion regions 30, 60, and 80 are not exposed on the main surface. Thereby, it is possible to suppress trapping of hot carriers at a level caused by surface defects existing in the vicinity of the main surface 10a, and it is possible to suppress an amount of fluctuation of the Zener voltage with time. In this respect, it is further advantageous to have the inter-electrode region 91.

In each of the above-described embodiments, the diode formation region Di in which a Zener diode is formed in the semiconductor substrate 10 has been described. However, another element is formed in the semiconductor substrate 10 in a region other than the diode formation region. I will not prevent it. For example, a MOSFET or IGBT may be separately formed on the same semiconductor substrate 10.

Further, in the third embodiment and the fourth embodiment, the joint surface between the upper diffusion regions 20, 50, 70 and the lower diffusion regions 30, 60, 80 has a concave shape, so that the lower diffusion regions 30, 60, 80 are formed. In the impurity concentration profile, the configuration in which the maximum point indicating the maximum concentration is formed has been described. However, the bonding surface between the upper diffusion regions 20, 50, 70 and the lower diffusion regions 30, 60, 80 is flat. In contrast to the conventional shape having the shape, the formation of the inter-electrode region 91 can provide an effect of suppressing the variation with time of the Zener voltage. In other words, the effect of providing the inter-electrode region 91 can be realized independently of the technical idea of forming a maximum point indicating the maximum concentration in the impurity concentration profile of the lower diffusion regions 30, 60, 80. .

Claims (28)

A semiconductor substrate (10) having a diode formation region (Di);
An upper diffusion region (20, 50, 70) of the first conductivity type formed in the surface layer of the main surface (10a) of the semiconductor substrate in the diode formation region;
A second conductivity type lower diffusion region (30, 60, 30) formed at a position deeper than the upper diffusion region with respect to the main surface in the depth direction of the semiconductor substrate and having an impurity concentration higher than that of the semiconductor substrate. 80)
The lower diffusion region forms a PN junction surface (S) with the upper diffusion region at a position deeper than the main surface,
A semiconductor device having a maximum point (P, P1, P2) indicating a maximum concentration in the impurity concentration profile of the lower diffusion region in the diode formation region. The upper diffusion region and the lower diffusion region are distributed rotationally symmetrically with an imaginary line passing through the maximum point and extending along the depth direction as symmetry axes (A, B), and the PN junction surface is a concave surface or a convex surface. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein the upper diffusion region and the lower diffusion region are similar to each other when the main surface is viewed from the front. 4. The semiconductor device according to claim 2, wherein the upper diffusion region and the lower diffusion region are distributed in a perfect circle centered on the symmetry axis when the main surface is viewed from the front. 5. The semiconductor device according to claim 1, wherein the lower diffusion region is formed so as to cover the upper diffusion region, and a part of the lower diffusion region is exposed to the main surface. A silicide block layer (40) provided on the main surface;
The silicide block layer is formed so as to straddle a PN junction line (L1, L2) between the upper diffusion region exposed on the main surface and the second conductivity type semiconductor region. The semiconductor device according to item. The semiconductor substrate is of a second conductivity type;
A second conductivity type counter electrode region (90) formed on a surface layer of the main surface in the diode formation region and having an impurity concentration higher than that of the semiconductor substrate;
The inter-electrode region (91) of the second conductivity type having a higher impurity concentration than the semiconductor substrate is formed in a surface layer of the main surface and between the upper diffusion region and the counter electrode region. 7. The semiconductor device according to any one of 1 to 6. 8. The semiconductor device according to claim 7, wherein the impurity concentration in the inter-electrode region is lower than the maximum point of the impurity concentration in the lower diffusion region. 9. The semiconductor device according to claim 7, wherein the inter-electrode region is formed as an impurity region independent of the lower diffusion region and the counter electrode region. 9. The semiconductor device according to claim 7, wherein the inter-electrode region is formed by overlapping impurities that cause the lower diffusion region and the counter electrode region to have a second conductivity type. A second conductivity type semiconductor substrate (10) having a diode formation region (Di);
An upper diffusion region (20, 50, 70) of the first conductivity type formed in the surface layer of the main surface (10a) of the semiconductor substrate in the diode formation region;
A second conductivity type lower diffusion region (30, 60, 30) formed at a position deeper than the upper diffusion region with respect to the main surface in the depth direction of the semiconductor substrate and having an impurity concentration higher than that of the semiconductor substrate. 80)
A second conductive type counter electrode region (90) formed on a surface layer of the main surface in the diode forming region and having an impurity concentration higher than that of the semiconductor substrate;
Further, a second conductivity type inter-electrode region (91) having an impurity concentration higher than that of the semiconductor substrate is formed in a surface layer of the main surface and between the upper diffusion region and the counter electrode region. Semiconductor device. 12. The semiconductor device according to claim 11, wherein the impurity concentration in the inter-electrode region is lower than the maximum impurity concentration in the lower diffusion region. 13. The semiconductor device according to claim 11, wherein the inter-electrode region is formed as an impurity region independent of the lower diffusion region and the counter electrode region. 13. The semiconductor device according to claim 11, wherein the interelectrode region is formed by overlapping impurities that cause the lower diffusion region and the counter electrode region to have a second conductivity type. Preparing a semiconductor substrate (10);
Impurities are implanted into the surface layer of the main surface of the semiconductor substrate, and the second conductivity type lower implantation in which the impurity concentration is higher than that of the semiconductor substrate so as to have a rotationally symmetrical shape when the main surface is viewed from the front. Forming regions (31, 61, 81);
After forming the lower implant region, diffusing the lower implant region by annealing;
After diffusion by annealing of the lower implantation region, impurities are implanted into the surface layer of the main surface of the semiconductor substrate, and concentric rotation with the lower implantation region is performed at a position shallower than the main surface than the lower implantation region. Forming an upper implantation region (21, 51, 71) of the first conductivity type so as to have a symmetrical shape;
After the formation of the upper implantation region, the lower implantation region is diffused by annealing to form a lower diffusion region (30, 60, 80), and the upper implantation region is diffused to diffuse the upper diffusion region (20, 50, 80). 70). A method for manufacturing a semiconductor device. The lower injection region and the upper injection region are formed in a similar shape so that the upper diffusion region and the lower diffusion region are similar to each other when the main surface is viewed from the front. Semiconductor device manufacturing method. The upper injection region and the lower injection region are formed so as to be distributed in a perfect circle centered on a rotational symmetry axis when the main surface is viewed from the front. A method for manufacturing a semiconductor device. 18. The method of manufacturing a semiconductor device according to claim 15, wherein impurities are implanted at a uniform depth in the formation of the upper implantation region. In the formation of the lower implantation region, the diameter (R) when the main surface is viewed from the front is set to be the same as the formation depth of the lower diffusion region in the depth direction of the semiconductor substrate. A method for manufacturing a semiconductor device according to claim 1. The silicide block layer (40) is further formed on the main surface so as to straddle the PN junction line between the upper diffusion region exposed to the main surface and the semiconductor region of the second conductivity type. 20. A method for manufacturing a semiconductor device according to any one of items 19 to 19. The semiconductor substrate is of a second conductivity type;
Furthermore, a second conductive type counter electrode implantation region (92) is formed by implanting impurities into a surface layer of the semiconductor substrate and spaced from the lower implantation region;
The inter-electrode region (91) having an impurity concentration higher than that of the semiconductor substrate is formed in a surface layer of the semiconductor substrate and between the counter electrode injection region and the lower injection region. A manufacturing method of a semiconductor device given in any 1 paragraph. The method of manufacturing a semiconductor device according to claim 21, wherein the impurity concentration in the inter-electrode region is lower than the maximum impurity concentration in the lower diffusion region. 23. The manufacturing method of a semiconductor device according to claim 21, wherein the interelectrode region is formed by forming an interelectrode injection region (93) independent of the lower injection region and the counter electrode injection region and performing diffusion by annealing. Method. 23. The method of manufacturing a semiconductor device according to claim 21, wherein the inter-electrode region is formed by an impurity diffused by annealing of the lower implantation region and an impurity diffused by annealing of the counter electrode implantation region. Preparing a second conductivity type semiconductor substrate (10);
Implanting impurities into the surface layer of the main surface of the semiconductor substrate to form a second conductivity type lower implantation region (31, 61, 81) having a higher impurity concentration than the semiconductor substrate;
After forming the lower implant region, diffusing the lower implant region by annealing;
After the diffusion of the lower implantation region by annealing, an impurity is implanted into the surface layer of the diffused lower implantation region, and the first conductivity type upper implantation region is located at a position shallower than the main surface than the lower implantation region. Forming (21, 51, 71),
After the formation of the upper implantation region, the lower implantation region is diffused by annealing to form a lower diffusion region (30, 60, 80), and the upper implantation region is diffused to diffuse the upper diffusion region (20, 50, 80). 70),
In addition, a second conductive type counter electrode injection region (92) is formed by injecting impurities into a surface layer of the semiconductor substrate and spaced from the lower injection region.
A method of manufacturing a semiconductor device comprising: forming an inter-electrode region (91) having a higher impurity concentration than the semiconductor substrate in a surface layer of the semiconductor substrate and between the counter-electrode injection region and the lower injection region. 26. The method of manufacturing a semiconductor device according to claim 25, wherein the impurity concentration in the inter-electrode region is lower than the maximum impurity concentration in the lower diffusion region. 27. The method of manufacturing a semiconductor device according to claim 25, wherein the interelectrode region is formed by forming an interelectrode injection region (93) independent of the lower injection region and the counter electrode injection region, and performing diffusion by annealing. Method. 27. The method of manufacturing a semiconductor device according to claim 25, wherein the inter-electrode region is formed by impurities diffused by annealing of the lower implantation region and impurities diffused by annealing of the counter electrode implantation region.

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