[go: up one dir, main page]

WO2018059075A1 - 移位寄存器单元、驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路及显示装置 Download PDF

Info

Publication number
WO2018059075A1
WO2018059075A1 PCT/CN2017/092712 CN2017092712W WO2018059075A1 WO 2018059075 A1 WO2018059075 A1 WO 2018059075A1 CN 2017092712 W CN2017092712 W CN 2017092712W WO 2018059075 A1 WO2018059075 A1 WO 2018059075A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock signal
control
output
transistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/092712
Other languages
English (en)
French (fr)
Inventor
李艳
时凌云
孙伟
谢晓波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US15/744,554 priority Critical patent/US10210791B2/en
Publication of WO2018059075A1 publication Critical patent/WO2018059075A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a driving method, a gate driving circuit, and a display device.
  • a gate drive circuit (also referred to as a shift register) includes a plurality of cascaded shift register cells, wherein each shift register cell is used to drive a row of pixel cells, and pixels of the display device are implemented by the plurality of shift register cells The progressive scan drive of the unit to display the image.
  • the gate driving circuit can scan the pixels of each row in the display device once in one frame time, wherein the scanning time for each row of pixel cells is determined by the frequency of the clock signal.
  • an embodiment of the present disclosure provides a shift register unit, where the shift register unit includes:
  • a first clock control circuit a second clock control circuit, an output control circuit, and an output circuit
  • the fourth clock signal end is connected to the output control circuit, wherein the first control signal end and the second control signal end are respectively configured to provide a first control signal and a second control signal, the first The clock signal end, the second clock signal end, the third clock signal end, and the fourth clock signal end are respectively configured to provide a first clock signal, a second clock signal, and a third time Clock signal and fourth clock signal;
  • the second clock control circuit and the first control signal end, the second control signal end, the first power signal end, the second power signal end, the first clock signal end, the second clock signal end, and the third clock signal end The fourth clock signal terminal is connected to the output circuit;
  • the output control circuit and the first clock control circuit, the input signal terminal, the reset signal terminal, the second power signal terminal, the third power signal terminal, the fourth power signal terminal, the pull-up node, and the output An end connection configured to control a potential of the pull-up node and the output terminal;
  • the output circuit is respectively connected to the second clock control circuit, the pull-up node and the output end, and configured to output the second output from the output terminal under the control of the pull-up node The signal of the clock control circuit;
  • the first clock control circuit is configured to be at a second control signal from the second control signal terminal, a third clock signal from the third clock signal terminal, and a fourth clock signal from the fourth clock signal terminal Controlling, alternately outputting the second clock signal and the first clock signal to the output control circuit, and correspondingly, the second clock control circuit is configured to be at the second control signal, the third Controlling, by the clock signal and the fourth clock signal, alternately outputting the first clock signal and the second clock signal to the output circuit;
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same frequency, and the phases are different from each other.
  • an embodiment of the present disclosure further provides a driving method of a shift register unit, where the shift register unit includes: a first clock control circuit, a second clock control circuit, an output control circuit, and an output circuit, and the method include:
  • the first control signal outputted by the first control signal terminal is a first potential
  • the second control signal outputted by the second control signal terminal is a second potential
  • the output control circuit outputs a second clock signal from the second clock signal end, and outputs a first clock signal from the first clock signal terminal to the output circuit through the second clock control circuit;
  • the first control signal outputted by the first control signal terminal is the second potential
  • the second control signal outputted by the second control signal terminal is the first potential
  • the third clock signal terminal outputs the third clock signal.
  • the fourth clock signal end outputs a fourth clock signal
  • the second clock signal and the first clock signal are alternately output to the output control circuit through the first clock control circuit
  • the The second clock control circuit alternately outputs the first clock signal and the second clock signal to the output circuit
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same frequency, and the phases are different from each other.
  • an embodiment of the present disclosure further provides a gate driving circuit, where the gate driving circuit includes: at least two cascaded shift register units, wherein each of the shift register units is as in the first aspect The shift register unit.
  • an embodiment of the present disclosure further provides a display device, comprising: the gate driving circuit according to the third aspect.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a second schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 3 is an exemplary circuit diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 4 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure
  • FIG. 5 is a timing diagram of signals in a shift register unit according to an embodiment of the present disclosure.
  • FIG. 6 is a second timing diagram of signals in a shift register unit according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the transistors employed in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the disclosed embodiment, the source is referred to as a first pole, the drain is referred to as a second pole, and the gate is referred to as a third pole. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the switching transistor employed in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor.
  • the P-type switching transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level
  • the N-type switching transistor is turned on when the gate is at a high level, and is turned off when the gate is at a low level.
  • the plurality of signals in various embodiments of the present disclosure correspond to a first potential and a second potential.
  • the first potential and the second potential only represent two state quantities of the potential of the signal, and do not mean that the first potential or the second potential has a specific value in the whole text, that is, the potential of the first potential (or the second potential) of each signal.
  • first clock signal, the second clock signal, the third clock signal, and the fourth clock signal in the embodiment of the present disclosure have the same frequency and different phases.
  • the duty ratios of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal may both be one-half; and the phase difference between the first clock signal and the second clock signal is 180.
  • the phase difference between the third clock signal and the fourth clock signal is 180 degrees, and the phase difference between the first clock signal and the third clock signal is 90 degrees.
  • Embodiments of the present disclosure provide a shift register unit, a driving method, a gate driving circuit, and a display device.
  • the shift register unit includes an output control circuit and an output circuit, and further includes two clock control circuits. Through the two clock control circuits, clock signals of different frequencies or different duty ratios can be respectively output to the output control circuit and the output circuit, so that the output circuit can output different frequencies or different duty ratios to the pixel unit through the output end.
  • the driving signal can further adjust the charging time of the shift register unit for each row of pixel units, thereby enriching the driving mode of the gate driving circuit to the display device and improving the driving flexibility.
  • the shift register unit includes: a first clock control circuit 10, a second clock control circuit 20, and an output control circuit 30. And an output circuit 40.
  • the control circuit 30 is connected.
  • the second clock control circuit 20 is respectively connected to the first control signal terminal EN1, the second control signal terminal EN2, the first power signal terminal VGH, the second power signal terminal VGL, the first clock signal terminal CK1, and the second clock signal terminal CK2.
  • the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are connected to the output circuit 40.
  • the output control circuit 30 and the first clock control circuit 10 the input signal terminal STV, the reset signal terminal RST, the second power signal terminal VGL, the third power signal terminal CN, the fourth power signal terminal CNB, and the pull-up node
  • the PU is connected to the output terminal OUT and configured to control the potential of the pull-up node PU and the output terminal OUT;
  • the output circuit 40 is respectively connected to the second clock control circuit 20, the pull-up node PU and the output terminal OUT And configured to output a signal from the second clock control circuit 20 to the output terminal OUT under the control of the pull-up node PU.
  • the first clock control circuit 10 is configured to output a second clock signal from the second clock signal terminal CK2 to the output control circuit 30 under the control of the first control signal from the first control signal terminal EN1.
  • the second clock control circuit 20 is configured to output a first clock signal from the first clock signal terminal CK1 to the output circuit 40 under the control of the first control signal.
  • the first clock control circuit 10 is configured to be at a second control signal from the second control signal terminal EN2, a third clock signal from the third clock signal terminal CK3, and a signal from the fourth clock signal terminal CK4.
  • the second clock signal and the first clock signal are alternately output to the output control circuit 30 under the control of the fourth clock signal.
  • the second clock control circuit 20 is configured to alternately output the first clock signal and the first output signal to the output circuit 40 under the control of the second control signal, the third clock signal and the fourth clock signal. Two clock signals.
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same frequency, and the phases are different from each other.
  • the embodiments of the present disclosure provide a shift register unit that includes an output control circuit and an output circuit, and further includes a clock control circuit.
  • the clock control circuit can output a first clock signal to the output circuit or alternately output the first clock signal and the second clock signal to the output circuit, so that the output circuit can be under the control of the signal output by the clock control circuit.
  • the driving signals of different frequencies or different duty ratios are output to the pixel unit, thereby adjusting the charging time of each row of pixel units, thereby enriching the driving mode of the gate driving circuit to the display device, and improving the driving flexibility.
  • FIG. 2 is another schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • the first clock control circuit 10 includes a first control sub-circuit 101, a second control sub-circuit 102, and a first output sub-circuit 103.
  • the first control sub-circuit 101 is respectively connected to the first control signal terminal EN1, the first power signal terminal VGH, the second power signal terminal VGL and the first output sub-circuit 103, and is configured to be from the first The first power supply signal from the first power supply signal terminal VGH and the second power supply signal from the second power supply signal terminal VGL are output to the first output sub-circuit 103 under the control of the first control signal of the control signal terminal EN1.
  • the second control sub-circuit 102 is respectively connected to the second control signal terminal EN2, the third clock signal terminal CK3, the fourth clock signal terminal CK4 and the first output sub-circuit 103, and is configured to be from the second
  • the third clock signal from the third clock signal terminal CK3 and the fourth clock signal from the fourth clock signal terminal CK4 are output to the first output sub-circuit 103 under the control of the second control signal of the control signal terminal EN2.
  • the first output sub-circuit 103 is respectively connected to the first control sub-circuit 101, the second control sub-circuit 102, the first clock signal terminal CK1, the second clock signal terminal CK2, and the output control circuit 30, and is configured. Outputting the second clock signal to the output control circuit 30 under control of the first power signal and the second power signal; or configured to be under the control of the third clock signal and the fourth clock signal The second clock signal and the first clock signal are alternately output to the output control circuit 30.
  • the second clock control circuit 20 may include a third control sub-circuit 201, a fourth control sub-circuit 202, and a second output sub-circuit 203.
  • the third control sub-circuit 201 is respectively connected to the first control signal terminal EN1, the first power signal terminal VGH, the second power signal terminal VGL and the second output sub-circuit 203, and is configured to be in the first control Under the control of the signal, the first power supply signal from the first power supply signal terminal VGH and the second power supply signal from the second power supply signal terminal VGL are output to the second output sub-circuit 203.
  • the fourth control sub-circuit 202 is respectively connected to the second control signal terminal EN2, the third clock signal terminal CK3, the fourth clock signal terminal CK4 and the second output sub-circuit 203, and is configured to be in the second control. Under the control of the signal, the third clock signal from the third clock signal terminal CK3 and the fourth clock signal from the fourth clock signal terminal CK4 are output to the second output sub-circuit 203.
  • the second output sub-circuit 203 is respectively connected to the third control sub-circuit 201, the fourth control sub-circuit 202, the first clock signal terminal CK1, the second clock signal terminal CK2, and the output circuit 40, and is configured to be configured as Outputting the first clock signal to the output circuit 40 under the control of the first power signal and the second power signal; or configured to be under the control of the third clock signal and the fourth clock signal
  • the output circuit 40 alternately outputs the first clock signal and the second clock signal.
  • FIG. 3 is a schematic diagram of a circuit structure of a shift register unit according to an embodiment of the present disclosure.
  • the first control sub-circuit 101 includes: a first transistor M1 and a second transistor M2; the second control sub-circuit 102 includes a third transistor M3 and a fourth transistor M4; the first output sub-circuit 103
  • the fifth transistor M5 and the sixth transistor M6 are included.
  • a gate of the first transistor M1 is connected to the first control signal terminal EN1, a first pole of the first transistor M1 is connected to the first power signal terminal VGH, and a second pole of the first transistor M1 is opposite to the fifth The gate of transistor M5 is connected.
  • a gate of the second transistor M2 is connected to the first control signal terminal EN1, a first pole of the second transistor M2 is connected to the second power signal terminal VGL, and a second pole of the second transistor M2 is opposite to the sixth
  • the gate of transistor M6 is connected.
  • a gate of the third transistor M3 is connected to the second control signal terminal EN2, a first pole of the third transistor M3 is connected to the third clock signal terminal CK3, and a second pole of the third transistor M3 is opposite to the fifth The gate of transistor M5 is connected.
  • a gate of the fourth transistor M4 is connected to the second control signal terminal EN2, a first pole of the fourth transistor M4 is connected to the fourth clock signal terminal CK4, and a second pole of the fourth transistor M4 is opposite to the sixth
  • the gate of transistor M6 is connected.
  • the first pole of the fifth transistor M5 is connected to the second clock signal terminal CK2, and the second pole of the fifth transistor M5 is connected to the output control circuit 30.
  • the first pole of the sixth transistor M6 is connected to the first clock signal terminal CK1, and the second pole of the sixth transistor M6 is connected to the output control circuit 30.
  • the third control sub-circuit 201 includes: a seventh transistor M7 and an eighth transistor M8;
  • the fourth control sub-circuit 202 includes: a ninth transistor M9 and a tenth transistor M10;
  • the second output sub-circuit 203 includes: an eleventh transistor M11 and a twelfth transistor M12.
  • a gate of the seventh transistor M7 is connected to the first control signal terminal EN1, the seventh transistor The first pole of M7 is connected to the first power signal terminal VGH, and the second pole of the seventh transistor M7 is connected to the gate of the eleventh transistor M11.
  • the gate of the eighth transistor M8 is connected to the first control signal terminal EN1, the first pole of the eighth transistor M8 is connected to the second power signal terminal VGL, and the second pole of the eighth transistor M8 is opposite to the tenth
  • the gate of the second transistor M12 is connected.
  • a gate of the ninth transistor M9 is connected to the second control signal terminal EN2, a first pole of the ninth transistor M9 is connected to the third clock signal terminal CK3, and a second pole of the ninth transistor M9 is opposite to the tenth
  • the gate of a transistor M11 is connected.
  • the gate of the tenth transistor M10 is connected to the second control signal terminal EN2, the first pole of the tenth transistor M10 is connected to the fourth clock signal terminal CK4, and the second pole of the tenth transistor M10 is opposite to the tenth
  • the gate of the second transistor M12 is connected.
  • the first pole of the eleventh transistor M11 is connected to the first clock signal terminal CK1, and the second pole of the eleventh transistor M11 is connected to the output circuit 40.
  • the first pole of the twelfth transistor M12 is connected to the second clock signal terminal CK2, and the second pole of the twelfth transistor M12 is connected to the output circuit 40.
  • the duty ratios of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are both one-half; a phase difference between the first clock signal and the second clock signal is 180 degrees, a phase difference between the third clock signal and the fourth clock signal is 180 degrees, and a phase difference between the first clock signal and the third clock signal It is 90 degrees.
  • the output control circuit 30 may include: a first output control transistor M13, a second output control transistor M14, a third output control transistor M15, a fourth output control transistor M16, and a The five output control transistor M17, the sixth output control transistor M18, and the seventh output control transistor M19.
  • the output circuit 40 includes an output transistor M20 and a capacitor C.
  • the gate of the first output control transistor M13 is connected to the input signal terminal STV, and the first electrode of the first output control transistor M13 is connected to the third power signal terminal CN, and the first output control transistor M13 is The two poles are connected to the pull-up node PU.
  • a gate of the second output control transistor M14 is connected to the reset signal terminal RST, and a first pole of the second output control transistor M14 is connected to the fourth power signal terminal CNB, the second output A second pole of the control transistor M14 is coupled to the pull-up node PU.
  • the gate of the third output control transistor M15 is connected to the pull-up node PU, the first pole of the third output control transistor M15 is connected to the second power signal terminal VGL, and the third output controls the second pole of the transistor M15. Connected to the drop-down node PD.
  • the gate of the fourth output control transistor M16 is connected to the output terminal OUT.
  • the first electrode of the fourth output control transistor M16 is connected to the second power signal terminal VGL.
  • the fourth output controls the second pole of the transistor M16.
  • the pulldown node PD is connected.
  • the gate and the first pole of the fifth output control transistor M17 are connected to the first clock control circuit 10, and the second pole of the fifth output control transistor M17 is connected to the pull-down node PD.
  • the gate and the first pole of the fifth output control transistor M17 are connected to both the second pole of the fifth transistor M5 of the first clock control circuit 10 and the second pole of the sixth transistor M6.
  • the gate of the sixth output control transistor M18 is connected to the pull-down node PD, the first pole of the sixth output control transistor M18 is connected to the second power signal terminal VGL, and the second output of the sixth output control transistor M18 is The pull-up node PU is connected.
  • a gate of the seventh output control transistor M19 is connected to the pull-down node PD, a first pole of the seventh output control transistor M19 is connected to the second power signal terminal VGL, and the seventh output controls the second pole of the transistor M19 The output terminal OUT is connected.
  • the gate of the output transistor M20 is connected to the pull-up node PU.
  • the first pole of the output transistor M20 is connected to the second clock control circuit 20.
  • the second pole of the output transistor M20 is connected to the output terminal OUT.
  • the first pole of the output transistor M20 is connected to the second pole of the eleventh transistor M11 of the second clock control circuit 20 and the second pole of the twelfth transistor M12.
  • One end of the capacitor C is connected to the pull-up node PU, and the other end is connected to the output terminal OUT.
  • the embodiments of the present disclosure provide a shift register unit that includes an output control circuit and an output circuit, and further includes a first clock control circuit and a second clock control circuit.
  • clock signals of different frequencies or different duty ratios can be respectively output to the output control circuit and the output circuit, so that the output circuit can be directed to the pixels under the control of the signal output by the second clock control circuit.
  • the unit outputs driving signals of different frequencies or different duty ratios, thereby adjusting the charging time of the shift register unit for each row of pixel units.
  • each transistor is an N-type transistor and the first potential is at a high potential with respect to the second potential.
  • the N-type transistor can be an amorphous silicon thin film transistor, and the process is relatively stable and the cost is low.
  • each transistor can also adopt a P-type transistor.
  • the first potential can be low relative to the second potential, and the potential change of each signal terminal can be compared with FIG. 5 below or The potential change shown in Fig. 6 is reversed (i.e., the phase difference between the two is 180 degrees).
  • FIG. 4 is a flowchart of a method for driving a shift register unit according to an embodiment of the present disclosure, which may be used to drive a shift register unit as shown in any of FIGS. 1 to 3.
  • the shift register unit may include a first clock control circuit 10, a second clock control circuit 20, an output control circuit 30, and an output circuit 40.
  • the method can include:
  • Step 301 In the first driving mode, the first control signal outputted by the first control signal terminal EN1 is the first potential, and the second control signal outputted by the second control signal terminal EN2 is the second potential, and is controlled by the first clock.
  • the circuit 10 outputs a second clock signal from the second clock signal terminal CK2 to the output control circuit 30, and the second clock signal from the first clock signal terminal CK1 is outputted to the output circuit 40 by the second clock control circuit 20.
  • Step 302 In the second driving mode, the first control signal outputted by the first control signal terminal EN1 is the second potential, the second control signal outputted by the second control signal terminal EN2 is the first potential, and the third clock signal terminal CK3 The third clock signal is output, and the fourth clock signal terminal CK4 outputs a fourth clock signal, and the second clock signal and the first clock signal are alternately output to the output control circuit 30 through the first clock control circuit 10, and the second clock signal is passed through the second clock signal.
  • the clock control circuit 20 alternately outputs the first clock signal and the second clock signal to the output circuit 40.
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same frequency, and the phases are different from each other.
  • the second potential can be low relative to the first potential.
  • the embodiments of the present disclosure provide a driving method of a shift register unit, and the driving method
  • the driving method includes two driving modes, and the signals output by the second clock control circuit to the output circuit are different in different driving modes, so that the output circuit can output driving signals of different frequencies or different duty ratios to the pixel unit, thereby further
  • the charging time of the shift register unit for each row of pixel units can be adjusted, thereby enriching the driving mode of the gate driving circuit to the display device, and improving the driving flexibility.
  • the first clock control circuit 10 includes a first control sub-circuit 101, a second control sub-circuit 102, and a first output sub-circuit 103.
  • the first control signal is a first potential
  • the first control sub-circuit 101 outputs the first power signal from the first power signal terminal VGH and the second power source to the first output sub-circuit 103.
  • the second power signal of the signal terminal VGL, the first output sub-circuit 103 outputs the second clock signal to the output control circuit 30 under the control of the first power signal and the second power signal.
  • the second control signal is a first potential
  • the second control sub-circuit 102 outputs the third clock signal and the fourth clock signal to the first output sub-circuit 103.
  • the third clock signal is at the first potential
  • the first output sub-circuit 103 outputs the second clock signal to the output control circuit 30;
  • the fourth clock signal is at the first potential, the first output sub-circuit 103 A first clock signal is output to the output control circuit 30.
  • the second clock control circuit 20 includes a third control sub-circuit 201, a fourth control sub-circuit 202, and a second output sub-circuit 203.
  • the first control signal is a first potential
  • the third control sub-circuit 201 outputs the first power signal from the first power signal terminal VGH and the second power source to the second output sub-circuit 203.
  • a second power signal of the signal terminal VGL the second output sub-circuit 203 outputs the first clock signal to the output circuit 40 under the control of the first power signal and the second power signal;
  • the second control signal is a first potential
  • the fourth control sub-circuit 202 outputs the third clock signal and the fourth clock signal to the second output sub-circuit 203.
  • the third clock signal is at the first potential
  • the second output sub-circuit 203 outputs the first clock signal to the output circuit 40;
  • the fourth clock signal is at the first potential
  • the second output sub-circuit 203 The output circuit 40 outputs the second clock signal.
  • the first control sub-circuit package in the first clock control circuit 10 The first transistor M1 and the second transistor M2 are included; the second control sub-circuit 102 includes a third transistor M3 and a fourth transistor M4; and the first output sub-circuit 103 includes a fifth transistor M5 and a sixth transistor M6.
  • the signal CK_N in FIG. 5 is a signal output by the second clock control circuit 20 to the output circuit 40, and the signal CKB_N is the first clock control circuit 10
  • the signal output from the control circuit 30 is output.
  • the first driving mode T1 the first control signal outputted by the first control signal terminal EN1 is a first potential, and the first transistor M1 and the second transistor M2 are turned on;
  • the signal terminal VGH outputs a first power signal to the gate of the fifth transistor M5, the first power signal is a first potential, and the fifth transistor M5 is turned on;
  • the second clock signal terminal CK2 passes through the fifth transistor M5.
  • the second power signal terminal VGL outputs a second power signal to the gate of the sixth transistor M6 through the second transistor M2, and the second power signal is the second potential
  • the sixth transistor M6 is turned off. Referring to FIG. 5, in the first driving mode T1, the waveform of the signal CKB_N output by the first clock control circuit 10 to the output control circuit 30 is the same as the waveform of the second clock signal.
  • the second control signal outputted by the second control signal terminal EN2 is the first potential, and the third transistor M3 and the fourth transistor M4 are turned on; the third clock signal terminal CK3
  • the third clock signal is output to the gate of the fifth transistor M5 through the third transistor M3, and the fourth clock signal terminal CK4 outputs the fourth clock signal to the gate of the sixth transistor M6 through the fourth transistor M4.
  • the third clock signal is at the first potential
  • the fifth transistor M5 is turned on, and the second clock signal terminal CK2 outputs the second clock signal to the output control circuit 30. For example, as shown in FIG.
  • the third clock signal outputted by the third clock signal terminal CK3 is at the first potential, and the output of the first clock control circuit is
  • the waveform of the signal CKB_N is the same as the waveform of the second clock signal.
  • the sixth transistor M6 When the fourth clock signal is at the first potential, the sixth transistor M6 is turned on, and the first clock signal terminal CK1 outputs the first clock signal to the output control circuit 30.
  • the fourth clock signal outputted by the fourth clock signal terminal CK4 when the fourth clock signal outputted by the fourth clock signal terminal CK4 is at the first potential, the third clock signal is at the second potential,
  • the waveform of the signal CKB_N output from the clock control circuit 10 to the output control circuit 30 is the same as the waveform of the first clock signal.
  • the fifth transistor M5 and the sixth transistor M6 can be alternately turned on, so that the first clock control circuit 10 can alternately output the second clock signal and the first clock signal to the output control circuit 30.
  • the third control sub-circuit 201 in the second clock control circuit 20 includes: a seventh transistor M7 and an eighth transistor M8; and the fourth control sub-circuit 202 includes: a ninth transistor M9 and a The tenth transistor M10; the second output sub-circuit 203 includes: an eleventh transistor M11 and a twelfth transistor M12.
  • the first control signal is a first potential
  • the seventh transistor M7, the eighth transistor M8 are turned on, and the first power signal terminal VGH is turned to the gate of the eleventh transistor M11.
  • the first power signal is a first potential
  • the eleventh transistor M11 is turned on
  • the first clock signal terminal CK1 outputs the first to the output circuit 40 through the eleventh transistor M11.
  • the second power signal terminal VGL outputs a second power signal to the gate of the twelfth transistor M12 through the eighth transistor M8, and the second power signal is a second potential, so that the twelfth transistor M12 is turned off.
  • the waveform of the signal CK_N output by the second clock control circuit 20 to the output circuit 40 is the same as the waveform of the first clock signal.
  • the second control signal is a first potential
  • the ninth transistor M9 and the tenth transistor M10 are turned on
  • the third clock signal terminal CK3 passes through the ninth transistor M9 to the eleventh transistor.
  • the gate of M11 outputs the third clock signal
  • the fourth clock signal terminal CK4 outputs the fourth clock signal to the gate of the twelfth transistor M12 through the tenth transistor M10.
  • the eleventh transistor M11 is turned on, and the first clock signal terminal CK1 outputs the first clock signal to the output circuit 40. For example, as shown in FIG.
  • the third clock signal outputted by the third clock signal terminal CK3 is at the first potential
  • the second clock control circuit 20 is The waveform of the signal CK_N output by the output circuit 40 is the same as the waveform of the first clock signal.
  • the twelfth transistor M12 When the fourth clock signal is at the first potential, the twelfth transistor M12 is turned on, and the second clock signal terminal CK2 outputs the second clock signal to the output circuit 40.
  • the third clock signal is at the second potential, at this time
  • the waveform of the signal CK_N output from the second clock control circuit 20 to the output circuit 40 is the same as the waveform of the second clock signal. It can also be seen from FIG.
  • the eleventh transistor M11 and the twelfth transistor M12 can be alternately turned on, thereby making the second clock control
  • the circuit 20 can alternately output the first clock signal and the second clock signal to the output circuit 20.
  • the frequency of the signal CK_N outputted by the second clock control circuit to the output circuit can be adjusted by adjusting the potential of the control signal outputted by the control signal terminal EN2.
  • the control signal of the control signal terminal EN2 is at the second potential (for example, each transistor is an N-type transistor, the second potential is low)
  • the shift register unit is in the first driving mode T1
  • the frequency of the signal CK_N is equal to the frequency of the first clock signal.
  • the frequency of the signal CK_N in the first driving mode is half of the second driving mode.
  • the charging time of the shift register unit for each row of pixel units is long, and the gate driving circuit pairs display
  • the time required for each row of pixel units in the device to scan once is twice the second driving mode.
  • the display resolution of the display device is low, and the low power consumption display of the display device can be realized.
  • the shift register unit When the control signal outputted by the control signal terminal EN2 is at the first potential (for example, each transistor is an N-type transistor, the first potential is high), the shift register unit is in the second driving mode T2, and the signal CK_N The frequency is twice that of the first driving mode T1, and the driving signal outputted when the shift register unit drives the pixel unit is the signal CK_N. Therefore, in the second driving mode T2, the shift register unit pairs The charging time of the row pixel unit is short.
  • the first potential for example, each transistor is an N-type transistor, the first potential is high
  • the time required for the gate driving circuit to scan each row of pixel units in the display device is half of the first driving mode, that is, the first driving in the gate driving circuit
  • the gate driving circuit can scan the pixels of each row in the display device twice in the second driving mode, so that the high-definition display of the display device can be realized.
  • the duty ratios of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal may both be one-half And a phase difference between the first clock signal and the second clock signal is 180 degrees, a phase difference between the third clock signal and the fourth clock signal is 180 degrees, and the first clock signal and the third clock The phase difference of the signal is 90 degrees.
  • the duty ratios of the first to fourth clock signals and the phase difference between the clock signals may be adjusted according to actual conditions, which is not limited in the embodiment of the present disclosure. Show for example, the timing charts of the first to fourth clock signals, the signal CK_N, and the signal CKB_N may also be as shown in FIG. 6 (only the timing of each signal in the second driving mode T2 is drawn in FIG.
  • the first The duty ratio of the first clock signal outputted by the clock signal terminal CK1 may be one quarter, and the duty ratio of the second clock signal outputted by the second clock signal terminal CK2 is also one quarter, the third clock The duty ratio of the clock signal outputted by the signal terminal CK3 and the fourth clock signal terminal CK4 is one-half, and the third clock signal and the fourth clock signal are equally inverted.
  • the frequency of the signal CK_N in the first driving mode and the second driving mode, the frequency of the signal CK_N does not change, but the duty ratio of the signal CK_N is in the first driving mode. It is one quarter and one half in the second drive mode.
  • the higher the duty ratio of the signal CK_N the longer the charging time for each row of pixel units, so it is also possible to realize the pixel for each row by changing the duty ratio of the driving signal of the shift register unit. Adjustment of the charging time of the unit.
  • any driving mode will be described by taking the shift register unit shown in FIG. 3 and the timing shown in FIG. 5 as an example.
  • the specific driving process of the shift register unit in any of the driving modes may include an input phase, an output phase, and a reset phase.
  • any of the driving modes may be the first driving mode or the second driving mode described above.
  • the input signal outputted from the input signal terminal STV is the first potential
  • the first output control transistor M13 is turned on
  • the third power signal signal terminal CN pulls up the node PU to output the third power signal, referring to FIG. 5,
  • the third The power signal is at a first potential, so that the potential of the pull-up node PU is pulled high.
  • the third output control transistor M15 and the output transistor M20 are turned on, and the second power signal terminal VGL outputs a second power signal to the pull-down node PD.
  • the six output control transistor M18 is turned off.
  • the output circuit 40 outputs a signal CK_N from the second clock control circuit 20 to the output terminal OUT, and the signal CK_N may be the second potential during the input phase.
  • the pull-up node maintains the first potential, and when the signal CK_N outputted by the second clock control circuit 20 to the output circuit 40 jumps to the first potential, the pull-up node PU has its potential due to the bootstrap effect. Further pulling up, at this time, the output transistor M20 is fully turned on, and the output circuit 40 outputs the signal CK_N from the second clock control circuit to the output terminal OUT, thereby enabling the opening of one row of pixel units (ie, driving the row of pixel units), The source driving circuit in the display device is enabled to charge the row of pixel units through the data line, which is the length of time during which the signal CK_N is at the first potential. Referring to FIG.
  • the signal CK_N has a longer duration at a first potential in each cycle in the first driving mode T1, and is first in each cycle in the second driving mode.
  • the duration of the potential is short, so that the shift register unit has different charging times for each row of pixel units in different driving modes, thereby realizing high definition display or low power consumption display of the display device.
  • the reset signal outputted by the reset signal terminal RST is also the first potential, so that the second output control transistor M14 is turned on, and the fourth power signal terminal CNB pulls up the node PU to output a fourth power signal, and the fourth power signal is a second potential, thereby pulling the potential of the pull-up node PU to a second potential, and the signal CK_N outputted by the second clock control circuit 20 to the output circuit 40 jumps again to a second potential, and the first clock control circuit
  • the signal CKB_N outputted from the output control circuit 30 is at the first potential
  • the fifth output control transistor M17 is turned on, the potential of the pull-down node PD is pulled high, and the sixth output control transistor M18 and the seventh output control transistor M19 are turned on
  • the second The power signal terminal VGL pulls up the node PU and the output terminal OUT respectively to output a second power signal, and the second power signal is a second potential, and the shift register unit is in a closed state to avoid abnormal output of the shift
  • the embodiments of the present disclosure provide a driving method of a shift register unit, where the driving method includes two driving modes, and in different driving modes, the shift register unit can output different frequencies or different pixels to the pixel unit.
  • the driving signal of the duty cycle can further adjust the charging time of the shift register unit for each row of pixel units.
  • the first driving mode when the frequency of the driving signal outputted by the shift register unit is low, the charging time for each row of pixel units is long, and the resolution of the display device is low, and the low power consumption of the display device can be realized.
  • the high-definition display enriches the driving method of the gate driving circuit to the display device, and improves the driving flexibility.
  • An embodiment of the present disclosure provides a gate driving circuit, which may include at least two cascaded shift register units, wherein each shift register unit may be as shown in any of FIGS. 1 to 3 . Shift register unit.
  • An embodiment of the present disclosure provides a display device, which may include a gate driving circuit, which may include at least two cascaded shift register units as shown in any of FIGS. 1 to 3.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。移位寄存器单元包括：第一时钟控制电路(10)、第二时钟控制电路(20)、输出控制电路(30)和输出电路(40)。第一时钟控制电路(10)被配置为在来自第二控制信号端(EN2)的第二控制信号、来自第三时钟信号端(CK3)的第三时钟信号和来自第四时钟信号端(CK4)的第四时钟信号的控制下，向输出控制电路(30)交替输出来自第二时钟信号端(CK2)的第二时钟信号和来自第一时钟信号端(CK1)的第一时钟信号。第二时钟控制电路(20)被配置为在第二控制信号、第三时钟信号和第四时钟信号的控制下，向输出电路(40)交替输出所述第一时钟信号和所述第二时钟信号。

Description

移位寄存器单元、驱动方法、栅极驱动电路及显示装置 技术领域
本公开实施例涉及一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。
背景技术
显示装置在显示图像时，需要利用栅极驱动电路(英文：Gate Driver on Array；简称：GOA)对像素单元进行驱动。栅极驱动电路(也称移位寄存器)包括多个级联的移位寄存器单元，其中，每个移位寄存器单元用于驱动一行像素单元，由多个移位寄存器单元实现对显示装置的像素单元的逐行扫描驱动，以显示图像。
在相关技术中，栅极驱动电路能够在一帧的时间内对显示装置中各行像素单元扫描一遍，其中，对每行像素单元的扫描时间是由时钟信号的频率决定的。
由于移位寄存器单元中所连接的时钟信号端输出的时钟信号的频率是固定的，因此该栅极驱动电路对像素单元进行驱动时，对每行像素单元的扫描时间也是固定的，驱动方式较为单一。
发明内容
第一方面，本公开实施例提供了一种移位寄存器单元，所述移位寄存器单元包括：
第一时钟控制电路、第二时钟控制电路、输出控制电路和输出电路；
所述第一时钟控制电路分别与第一控制信号端、第二控制信号端、第一电源信号端、第二电源信号端、第一时钟信号端、第二时钟信号端、第三时钟信号端、第四时钟信号端和所述输出控制电路连接，其中，所述第一控制信号端和所述第二控制信号端分别被配置为提供第一控制信号和第二控制信号，所述第一时钟信号端、所述第二时钟信号端、所述第三时钟信号端和所述第四时钟信号端分别被配置为提供第一时钟信号、第二时钟信号、第三时 钟信号和第四时钟信号；
所述第二时钟控制电路分别与第一控制信号端、第二控制信号端、第一电源信号端、第二电源信号端、第一时钟信号端、第二时钟信号端、第三时钟信号端、第四时钟信号端和所述输出电路连接；
所述输出控制电路分别与所述第一时钟控制电路、输入信号端、复位信号端、所述第二电源信号端、第三电源信号端、第四电源信号端、上拉节点和所述输出端连接，被配置为控制所述上拉节点和所述输出端的电位；
所述输出电路分别与所述第二时钟控制电路、所述上拉节点和所述输出端连接，被配置为在所述上拉节点的控制下，向所述输出端输出来自所述第二时钟控制电路的信号；
所述第一时钟控制电路被配置为在来自所述第二控制信号端的第二控制信号、来自所述第三时钟信号端的第三时钟信号和来自所述第四时钟信号端的第四时钟信号的控制下，向所述输出控制电路交替输出所述第二时钟信号和所述第一时钟信号，相应的，所述第二时钟控制电路被配置为在所述第二控制信号、所述第三时钟信号和所述第四时钟信号的控制下，向所述输出电路交替输出所述第一时钟信号和所述第二时钟信号；
其中，所述第一时钟信号、所述第二时钟信号所述第三时钟信号和所述第四时钟信号的频率相同，相位互不相同。
第二方面，本公开实施例还提供一种移位寄存器单元的驱动方法，所述移位寄存器单元包括：第一时钟控制电路、第二时钟控制电路、输出控制电路和输出电路，所述方法包括：
在第一驱动模式中，第一控制信号端输出的第一控制信号为第一电位，第二控制信号端输出的第二控制信号为第二电位，通过所述第一时钟控制电路向所述输出控制电路输出来自第二时钟信号端的第二时钟信号，通过所述第二时钟控制电路向所述输出电路输出来自第一时钟信号端的第一时钟信号；
在第二驱动模式中，第一控制信号端输出的第一控制信号为第二电位，第二控制信号端输出的第二控制信号为第一电位，第三时钟信号端输出第三时钟信号，第四时钟信号端输出第四时钟信号，通过所述第一时钟控制电路向所述输出控制电路交替输出所述第二时钟信号和所述第一时钟信号，通过 所述第二时钟控制电路向所述输出电路交替输出所述第一时钟信号和所述第二时钟信号；
其中，所述第一时钟信号、所述第二时钟信号所述第三时钟信号和所述第四时钟信号的频率相同，相位互不相同。
第三方面，本公开实施例还提供了一种栅极驱动电路，所述栅极驱动电路包括：至少两个级联的移位寄存器单元，其中各所述移位寄存器单元为如第一方面所述的移位寄存器单元。
第四方面，本公开实施例还提供了一种显示装置，所述显示装置包括：如第三方面所述的栅极驱动电路。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种移位寄存器单元的结构示意图之一；
图2是本公开实施例提供的一种移位寄存器单元的结构示意图之二；
图3是本公开实施例提供的一种移位寄存器单元的示例性电路图；
图4是本公开实施例提供的一种移位寄存器单元的驱动方法的流程图；
图5是本公开实施例提供的一种移位寄存器单元中各信号的时序图之一；以及
图6是本公开实施例提供的一种移位寄存器单元中各信号的时序图之二。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将源极称为第一极，漏极称为第二极，栅极称为第三极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种。P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位。第一电位和第二电位仅代表该信号的电位有2个状态量，不代表全文中第一电位或第二电位具有特定的数值，即各个信号的第一电位(或第二电位)的电位值可以相同也可以不同。进一步的，本公开实施例中的第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的频率相同，相位互不相同。例如，该第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的占空比可以均为二分之一；且该第一时钟信号与第二时钟信号的相位差为180度，第三时钟信号与第四时钟信号的相位差为180度，且第一时钟信号与第三时钟信号的相位差为90度。
本公开实施例提供了一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。该移位寄存器单元包括输出控制电路和输出电路，还包括两个时钟控制电路。通过该两个时钟控制电路，可以分别向输出控制电路和输出电路输出不同频率或者不同占空比的时钟信号，从而使得该输出电路可以通过输出端向像素单元输出不同频率或者不同占空比的驱动信号，进而可以调整移位寄存器单元对每行像素单元的充电时间，因此丰富了栅极驱动电路对显示装置的驱动方式，提高了驱动的灵活性。
图1是本公开实施例提供的一种移位寄存器单元的结构示意图，如图1所示，该移位寄存器单元包括：第一时钟控制电路10、第二时钟控制电路20、输出控制电路30和输出电路40。
该第一时钟控制电路10分别与第一控制信号端EN1、第二控制信号端EN2、第一电源信号端VGH、第二电源信号端VGL、第一时钟信号端CK1、第二时钟信号端CK2、第三时钟信号端CK3、第四时钟信号端CK4和该输 出控制电路30连接。该第二时钟控制电路20分别与第一控制信号端EN1、第二控制信号端EN2、第一电源信号端VGH、第二电源信号端VGL、第一时钟信号端CK1、第二时钟信号端CK2、第三时钟信号端CK3、第四时钟信号端CK4和该输出电路40连接。
该输出控制电路30分别与该第一时钟控制电路10、输入信号端STV、复位信号端RST、该第二电源信号端VGL、第三电源信号端CN、第四电源信号端CNB、上拉节点PU和该输出端OUT连接，被配置为控制该上拉节点PU和该输出端OUT的电位；该输出电路40分别与该第二时钟控制电路20、该上拉节点PU和该输出端OUT连接，被配置为在该上拉节点PU的控制下，向该输出端OUT输出来自该第二时钟控制电路20的信号。
该第一时钟控制电路10被配置为在来自该第一控制信号端EN1的第一控制信号的控制下，向该输出控制电路30输出来自该第二时钟信号端CK2的第二时钟信号。相应的，该第二时钟控制电路20被配置为在该第一控制信号的控制下，向该输出电路40输出来自该第一时钟信号端CK1的第一时钟信号。
或者，该第一时钟控制电路10被配置为在来自该第二控制信号端EN2的第二控制信号、来自该第三时钟信号端CK3的第三时钟信号和来自该第四时钟信号端CK4的第四时钟信号的控制下，向该输出控制电路30交替输出该第二时钟信号和该第一时钟信号。相应的，该第二时钟控制电路20被配置为在该第二控制信号、该第三时钟信号和该第四时钟信号的控制下，向该输出电路40交替输出该第一时钟信号和该第二时钟信号。
例如，该第一时钟信号、该第二时钟信号、该第三时钟信号和该第四时钟信号的频率相同，相位互不相同。
综上所述，本公开实施例提供了一种移位寄存器单元，该移位寄存器单元包括输出控制电路和输出电路，还包括时钟控制电路。通过该时钟控制电路，可以向输出电路输出第一时钟信号，或者向输出电路交替输出第一时钟信号和第二时钟信号，从而使得该输出电路可以在该时钟控制电路输出的信号的控制下，向像素单元输出不同频率或者不同占空比的驱动信号，进而可以调整对每行像素单元的充电时间，因此丰富了栅极驱动电路对显示装置的驱动方式，提高了驱动的灵活性。
图2是本公开实施例提供的一种移位寄存器单元的另一结构示意图。如图2所示，该第一时钟控制电路10包括：第一控制子电路101、第二控制子电路102和第一输出子电路103。
该第一控制子电路101分别与该第一控制信号端EN1、该第一电源信号端VGH、该第二电源信号端VGL和该第一输出子电路103连接，被配置为在来自该第一控制信号端EN1的第一控制信号的控制下，向该第一输出子电路103输出来自该第一电源信号端VGH的第一电源信号和来自该第二电源信号端VGL的第二电源信号。
该第二控制子电路102分别与该第二控制信号端EN2、该第三时钟信号端CK3、该第四时钟信号端CK4和该第一输出子电路103连接，被配置为在来自该第二控制信号端EN2的第二控制信号的控制下，向该第一输出子电路103输出来自该第三时钟信号端CK3的第三时钟信号和来自该第四时钟信号端CK4的第四时钟信号。
该第一输出子电路103分别与该第一控制子电路101、该第二控制子电路102、该第一时钟信号端CK1、该第二时钟信号端CK2和该输出控制电路30连接，被配置为在该第一电源信号和该第二电源信号的控制下，向该输出控制电路30输出该第二时钟信号；或者，被配置为在该第三时钟信号和该第四时钟信号的控制下，向该输出控制电路30交替输出该第二时钟信号和该第一时钟信号。
例如，如图2所示，该第二时钟控制电路20可以包括：第三控制子电路201、第四控制子电路202和第二输出子电路203。
该第三控制子电路201分别与该第一控制信号端EN1、该第一电源信号端VGH、该第二电源信号端VGL和该第二输出子电路203连接，被配置为在该第一控制信号的控制下，向该第二输出子电路203输出来自该第一电源信号端VGH的第一电源信号和来自该第二电源信号端VGL的第二电源信号。
该第四控制子电路202分别与该第二控制信号端EN2、该第三时钟信号端CK3、该第四时钟信号端CK4和该第二输出子电路203连接，被配置为在该第二控制信号的控制下，向该第二输出子电路203输出来自该第三时钟信号端CK3的第三时钟信号和来自该第四时钟信号端CK4的第四时钟信号。
该第二输出子电路203分别与该第三控制子电路201、该第四控制子电路202、该第一时钟信号端CK1、该第二时钟信号端CK2和该输出电路40连接，被配置为在该第一电源信号和该第二电源信号的控制下，向该输出电路40输出该第一时钟信号；或者，被配置为在该第三时钟信号和该第四时钟信号的控制下，向该输出电路40交替输出该第一时钟信号和该第二时钟信号。
图3是本公开实施例提供的一种移位寄存器单元的电路结构示意图。如图3所示，该第一控制子电路101包括：第一晶体管M1和第二晶体管M2；该第二控制子电路102包括第三晶体管M3和第四晶体管M4；该第一输出子电路103包括：第五晶体管M5和第六晶体管M6。
该第一晶体管M1的栅极与该第一控制信号端EN1连接，该第一晶体管M1的第一极与该第一电源信号端VGH连接，该第一晶体管M1的第二极与该第五晶体管M5的栅极连接。
该第二晶体管M2的栅极与该第一控制信号端EN1连接，该第二晶体管M2的第一极与该第二电源信号端VGL连接，该第二晶体管M2的第二极与该第六晶体管M6的栅极连接。
该第三晶体管M3的栅极与该第二控制信号端EN2连接，该第三晶体管M3的第一极与该第三时钟信号端CK3连接，该第三晶体管M3的第二极与该第五晶体管M5的栅极连接。
该第四晶体管M4的栅极与该第二控制信号端EN2连接，该第四晶体管M4的第一极与该第四时钟信号端CK4连接，该第四晶体管M4的第二极与该第六晶体管M6的栅极连接。
该第五晶体管M5的第一极与该第二时钟信号端CK2连接，该第五晶体管M5的第二极与该输出控制电路30连接。
该第六晶体管M6的第一极与该第一时钟信号端CK1连接，该第六晶体管M6的第二极与该输出控制电路30连接。
例如，参考图3，该第三控制子电路201包括：第七晶体管M7和第八晶体管M8；该第四控制子电路202包括：第九晶体管M9和第十晶体管M10；该第二输出子电路203包括：第十一晶体管M11和第十二晶体管M12。
该第七晶体管M7的栅极与该第一控制信号端EN1连接，该第七晶体管 M7的第一极与该第一电源信号端VGH连接，该第七晶体管M7的第二极与该第十一晶体管M11的栅极连接。
该第八晶体管M8的栅极与该第一控制信号端EN1连接，该第八晶体管M8的第一极与该第二电源信号端VGL连接，该第八晶体管M8的第二极与该第十二晶体管M12的栅极连接。
该第九晶体管M9的栅极与该第二控制信号端EN2连接，该第九晶体管M9的第一极与该第三时钟信号端CK3连接，该第九晶体管M9的第二极与该第十一晶体管M11的栅极连接。
该第十晶体管M10的栅极与该第二控制信号端EN2连接，该第十晶体管M10的第一极与该第四时钟信号端CK4连接，该第十晶体管M10的第二极与该第十二晶体管M12的栅极连接。
该第十一晶体管M11的第一极与该第一时钟信号端CK1连接，该第十一晶体管M11的第二极与该输出电路40连接。
该第十二晶体管M12的第一极与该第二时钟信号端CK2连接，该第十二晶体管M12的第二极与该输出电路40连接。
在本公开实施例的一种示例性的实现方式中，该第一时钟信号、该第二时钟信号、该第三时钟信号和该第四时钟信号的占空比均为二分之一；该第一时钟信号与该第二时钟信号的相位差为180度，该第三时钟信号与该第四时钟信号的相位差为180度，且该第一时钟信号与该第三时钟信号的相位差为90度。
作为一种示例性的实现方式，参考图3，该输出控制电路30可以包括：第一输出控制晶体管M13、第二输出控制晶体管M14、第三输出控制晶体管M15、第四输出控制晶体管M16、第五输出控制晶体管M17、第六输出控制晶体管M18和第七输出控制晶体管M19。该输出电路40包括：输出晶体管M20和电容器C。
例如，该第一输出控制晶体管M13的栅极与该输入信号端STV连接，该第一输出控制晶体管M13的第一极与该第三电源信号端CN连接，该第一输出控制晶体管M13的第二极与该上拉节点PU连接。
该第二输出控制晶体管M14的栅极与该复位信号端RST连接，该第二输出控制晶体管M14的第一极与该第四电源信号端CNB连接，该第二输出 控制晶体管M14的第二极与该上拉节点PU连接。
该第三输出控制晶体管M15的栅极与该上拉节点PU连接，该第三输出控制晶体管M15的第一极与该第二电源信号端VGL连接，该第三输出控制晶体管M15的第二极与下拉节点PD连接。
该第四输出控制晶体管M16的栅极与该输出端OUT连接，该第四输出控制晶体管M16的第一极与该第二电源信号端VGL连接，该第四输出控制晶体管M16的第二极与该下拉节点PD连接。
该第五输出控制晶体管M17的栅极和第一极与该第一时钟控制电路10连接，该第五输出控制晶体管M17的第二极与该下拉节点PD连接。例如，该第五输出控制晶体管M17的栅极和第一极与该第一时钟控制电路10的第五晶体管M5的第二极和第六晶体管M6的第二极均连接。
该第六输出控制晶体管M18的栅极与该下拉节点PD连接，该第六输出控制晶体管M18的第一极与该第二电源信号端VGL连接，该第六输出控制晶体管M18的第二极与该上拉节点PU连接。
该第七输出控制晶体管M19的栅极与该下拉节点PD连接，该第七输出控制晶体管M19的第一极与该第二电源信号端VGL连接，该第七输出控制晶体管M19的第二极与该输出端OUT连接。
该输出晶体管M20的栅极与该上拉节点PU连接，该输出晶体管M20的第一极与该第二时钟控制电路20连接，该输出晶体管M20的第二极与该输出端OUT连接。例如，该第输出晶体管M20的第一极与该第二时钟控制电路20的第十一晶体管M11的第二极和第十二晶体管M12的第二极均连接。该电容器C的一端与该上拉节点PU连接，另一端与该输出端OUT连接。
综上所述，本公开实施例提供了一种移位寄存器单元，该移位寄存器单元包括输出控制电路和输出电路，还包括第一时钟控制电路和第二时钟控制电路。通过该两个时钟控制电路，可以分别向输出控制电路和输出电路输出不同频率或者不同占空比的时钟信号，使得该输出电路可以在该第二时钟控制电路输出的信号的控制下，向像素单元输出不同频率或者不同占空比的驱动信号，进而可以调整移位寄存器单元对每行像素单元的充电时间。当输出电路输出的驱动信号的频率较高或者占空比较小时，对每行像素单元的充电 时间较短，此时显示装置的显示分辨率较高，可以实现显示装置的高清显示；当输出电路输出的驱动信号的频率较低或者占空比较高时，对每行像素单元的充电时间较长，此时显示装置的分辨率较低，可以实现显示装置的低功耗显示。因此，丰富了栅极驱动电路对显示装置的驱动方式，提高了驱动的灵活性。
需要说明的是，在本公开各个实施例中，均是以各晶体管为N型晶体管、且第一电位相对于该第二电位为高电位为例进行的说明。该N型晶体管可以为非晶硅薄膜晶体管，其制程比较稳定，成本较低。
当然，各晶体管还可以采用P型晶体管，当各晶体管采用P型晶体管时，该第一电位相对于该第二电位可以为低电位，且该各个信号端的电位变化可以与下述附图5或附图6所示的电位变化相反(即二者的相位差为180度)。
图4是本公开实施例提供的一种移位寄存器单元的驱动方法的流程图，该方法可以用于驱动如图1至图3任一所示的移位寄存器单元。参考图1，该移位寄存器单元可以包括：第一时钟控制电路10、第二时钟控制电路20、输出控制电路30和输出电路40。参考图4，该方法可以包括：
步骤301、在第一驱动模式中，第一控制信号端EN1输出的第一控制信号为第一电位，第二控制信号端EN2输出的第二控制信号为第二电位，通过该第一时钟控制电路10向该输出控制电路30输出来自第二时钟信号端CK2的第二时钟信号，通过该第二时钟控制电路20向该输出电路40输出来自第一时钟信号端CK1的第一时钟信号。
步骤302、在第二驱动模式中，第一控制信号端EN1输出的第一控制信号为第二电位，第二控制信号端EN2输出的第二控制信号为第一电位，第三时钟信号端CK3输出第三时钟信号，第四时钟信号端CK4输出第四时钟信号，通过该第一时钟控制电路10向该输出控制电路30交替输出该第二时钟信号和该第一时钟信号，通过该第二时钟控制电路20向该输出电路40交替输出该第一时钟信号和该第二时钟信号。
例如，该第一时钟信号、该第二时钟信号该第三时钟信号和该第四时钟信号的频率相同，相位互不相同。此外，该第二电位相对于该第一电位可以为低电位。
综上所述，本公开实施例提供了一种移位寄存器单元的驱动方法，该驱 动方法包括两种驱动模式，不同的驱动模式下第二时钟控制电路向输出电路输出的信号的频率不同，从而使得该输出电路可以向像素单元输出不同频率或者不同占空比的驱动信号，进而可以调整移位寄存器单元对每行像素单元的充电时间，因此丰富了栅极驱动电路对显示装置的驱动方式，提高了驱动的灵活性。
例如，参考图2，该第一时钟控制电路10包括：第一控制子电路101、第二控制子电路102和第一输出子电路103。
该第一驱动模式中，该第一控制信号为第一电位，该第一控制子电路101向该第一输出子电路103输出来自第一电源信号端VGH的第一电源信号和来自第二电源信号端VGL的第二电源信号，该第一输出子电路103在该第一电源信号和该第二电源信号的控制下，向该输出控制电路30输出该第二时钟信号。
该第二驱动模式中，该第二控制信号为第一电位，该第二控制子电路102向该第一输出子电路103输出该第三时钟信号和该第四时钟信号。当该第三时钟信号处于第一电位时，该第一输出子电路103向该输出控制电路30输出该第二时钟信号；当第四时钟信号处于第一电位时，该第一输出子电路103向该输出控制电路30输出第一时钟信号。
例如，参考图2，该第二时钟控制电路20包括：第三控制子电路201、第四控制子电路202和第二输出子电路203。
该第一驱动模式中，该第一控制信号为第一电位，该第三控制子电路201向该第二输出子电路203输出来自第一电源信号端VGH的第一电源信号和来自第二电源信号端VGL的第二电源信号，该第二输出子电路203在该第一电源信号和该第二电源信号的控制下，向该输出电路40输出该第一时钟信号；
该第二驱动模式中，该第二控制信号为第一电位，该第四控制子电路202向该第二输出子电路203输出该第三时钟信号和该第四时钟信号。当该第三时钟信号处于第一电位时，该第二输出子电路203向该输出电路40输出该第一时钟信号；当第四时钟信号处于第一电位时，该第二输出子电路203向该输出电路40输出该第二时钟信号。
进一步的，如图3所示，该第一时钟控制电路10中的第一控制子电路包 括：第一晶体管M1和第二晶体管M2；第二控制子电路102包括第三晶体管M3和第四晶体管M4；第一输出子电路103包括：第五晶体管M5和第六晶体管M6。
图5是本公开实施例提供的一种驱动方法的时序图，图5中信号CK_N为第二时钟控制电路20向该输出电路40输出的信号，信号CKB_N为该第一时钟控制电路10向该输出控制电路30输出的信号。从图5中可以看出，该第一驱动模式T1中，该第一控制信号端EN1输出的第一控制信号为第一电位，该第一晶体管M1和该第二晶体管M2开启；第一电源信号端VGH向该第五晶体管M5的栅极输出第一电源信号，该第一电源信号为第一电位，此时该第五晶体管M5开启；该第二时钟信号端CK2通过该第五晶体管M5向该输出控制电路30输出该第二时钟信号；该第二电源信号端VGL通过该第二晶体管M2向该第六晶体管M6的栅极输出第二电源信号，该第二电源信号为第二电位，该第六晶体管M6关断。参考图5可知，该第一驱动模式T1中，该第一时钟控制电路10向输出控制电路30输出的信号CKB_N的波形与该第二时钟信号的波形相同。
参考图5，该第二驱动模式T2中，该第二控制信号端EN2输出的第二控制信号为第一电位，此时第三晶体管M3和第四晶体管M4开启；该第三时钟信号端CK3通过该第三晶体管M3向该第五晶体管M5的栅极输出该第三时钟信号，该第四时钟信号端CK4通过该第四晶体管M4向该第六晶体管M6的栅极输出该第四时钟信号。当该第三时钟信号处于第一电位时，该第五晶体管M5开启，该第二时钟信号端CK2向该输出控制电路30输出该第二时钟信号。示例的，如图5所示，在第二驱动模式T2中的t1和t3阶段，该第三时钟信号端CK3输出的第三时钟信号处于第一电位，此时该第一时钟控制电路输出的信号CKB_N的波形与该第二时钟信号的波形相同。
当该第四时钟信号处于第一电位时，该第六晶体管M6开启，该第一时钟信号端CK1向该输出控制电路30输出该第一时钟信号。示例的，参考图5，在第二驱动模式T2的t2阶段中，该第四时钟信号端CK4输出的第四时钟信号处于第一电位时，该第三时钟信号处于第二电位，此时第一时钟控制电路10向输出控制电路30输出的信号CKB_N的波形与该第一时钟信号的波形相同。从图5中可以看出，由于该第三时钟信号和第四时钟信号同频反 相，因此该第五晶体管M5和该第六晶体管M6可以交替开启，从而使得该第一时钟控制电路10可以向该输出控制电路30交替输出第二时钟信号和第一时钟信号。
进一步的，如图3所示，该第二时钟控制电路20中的第三控制子电路201包括：第七晶体管M7和第八晶体管M8；第四控制子电路202包括：第九晶体管M9和第十晶体管M10；第二输出子电路203包括：第十一晶体管M11和第十二晶体管M12。
参考图5，该第一驱动模式T1中，该第一控制信号为第一电位，该第七晶体管M7、该第八晶体管M8开启，该第一电源信号端VGH向第十一晶体管M11的栅极输出第一电源信号，该第一电源信号为第一电位，此时该第十一晶体管M11开启，该第一时钟信号端CK1通过该第十一晶体管M11向该输出电路40输出该第一时钟信号。该第二电源信号端VGL通过该第八晶体管M8向该第十二晶体管M12的栅极输出第二电源信号，该第二电源信号为第二电位，使得该第十二晶体管M12关断。参考图5可知，该第一驱动模式T1中，该第二时钟控制电路20向输出电路40输出的信号CK_N的波形与该第一时钟信号的波形相同。
该第二驱动模式T2中，该第二控制信号为第一电位，该第九晶体管M9和该第十晶体管M10开启，该第三时钟信号端CK3通过该第九晶体管M9向该第十一晶体管M11的栅极输出该第三时钟信号，该第四时钟信号端CK4通过该第十晶体管M10向该第十二晶体管M12的栅极输出该第四时钟信号。当该第三时钟信号处于第一电位时，该第十一晶体管M11开启，该第一时钟信号端CK1向该输出电路40输出该第一时钟信号。示例的，如图5所示，在第二驱动模式T2中的t1和t3阶段，该第三时钟信号端CK3输出的第三时钟信号处于第一电位，此时该第二时钟控制电路20向输出电路40输出的信号CK_N的波形与该第一时钟信号的波形相同。
当该第四时钟信号处于第一电位时，该第十二晶体管M12开启，该第二时钟信号端CK2向该输出电路40输出该第二时钟信号。示例的，参考图5，在第二驱动模式T2中的t2阶段，该第四时钟信号端CK4输出的第四时钟信号处于第一电位时，该第三时钟信号处于第二电位，此时第二时钟控制电路20向输出电路40输出的信号CK_N的波形与该第二时钟信号的波形相同。 从图5中还可以看出，由于该第三时钟信号和第四时钟信号同频反相，因此该第十一晶体管M11和该第十二晶体管M12可以交替开启，从而使得该第二时钟控制电路20可以向该输出电路20交替输出第一时钟信号和第二时钟信号。
综上可知，在本公开实施例中，可以通过调整该控制信号端EN2输出的控制信号的电位，实现对第二时钟控制电路向输出电路输出的信号CK_N的频率的调整。参考图5，当控制信号端EN2的控制信号为第二电位时(例如，各晶体管均为N型晶体管，该第二电位为低电位)，该移位寄存器单元处于第一驱动模式T1，在该第一驱动模式下，信号CK_N的频率与该第一时钟信号的频率相等。从图5中可以看出，第一驱动模式中信号CK_N的频率为第二驱动模式中的一半，此时移位寄存器单元对每行像素单元的充电时间较长，该栅极驱动电路对显示装置中各行像素单元扫描一遍所需的时间为第二驱动模式的两倍，此时显示装置的显示分辨率较低，可以实现显示装置的低功耗显示。
当控制信号端EN2输出的控制信号为第一电位时(例如，各晶体管均为N型晶体管，该第一电位为高电位)，该移位寄存器单元处于第二驱动模式T2中，信号CK_N的频率为第一驱动模式T1中的两倍，由于移位寄存器单元对像素单元进行驱动时输出的驱动信号即为该信号CK_N，因此，在该第二驱动模式T2中，移位寄存器单元对每行像素单元的充电时间较短，此时该栅极驱动电路对显示装置中各行像素单元扫描一遍所需的时间为第一驱动模式的一半，也即是，在栅极驱动电路以第一驱动模式扫描一遍显示装置中各像素单元所需的时间内，栅极驱动电路在第二驱动模式下能够对显示装置中各行像素单元扫描两遍，因此可以实现显示装置的高清显示。
在本公开一种示例性的实施例中，参考图5，该第一时钟信号、该第二时钟信号、该第三时钟信号和该第四时钟信号的占空比可以均为二分之一；并且，该第一时钟信号与该第二时钟信号的相位差为180度，该第三时钟信号与该第四时钟信号的相位差为180度，且该第一时钟信号与该第三时钟信号的相位差为90度。
需要说明的是，该第一至第四时钟信号的占空比，以及各个时钟信号之间的相位差还可以根据实际情况进行调整，本公开实施例对此不做限定。示 例的，该第一至第四时钟信号、信号CK_N以及信号CKB_N的时序图还可以如图6所示(图6中仅绘制了第二驱动模式T2中各信号的时序)，其中，该第一时钟信号端CK1输出的第一时钟信号的占空比可以为四分之一，该第二时钟信号端CK2输出的第二时钟信号的占空比也为四分之一，该第三时钟信号端CK3和第四时钟信号端CK4输出的时钟信号的占空比均为二分之一，且该第三时钟信号和第四时钟信号等幅反相。对于图6所示的各个时钟信号的频率和占空比，在第一驱动模式和第二驱动模式下，信号CK_N的频率未发生改变，但该信号CK_N的占空比在第一驱动模式下为四分之一，在第二驱动模式下为二分之一。在频率相等的情况下，信号CK_N的占空比越高，对每行像素单元的充电时间越长，因此也可以通过改变该移位寄存器单元的驱动信号的占空比来实现对每行像素单元的充电时间的调整。
进一步的，以图3所示的移位寄存器单元以及图5所示的时序为例，对该移位寄存器单元在任一驱动模式下的工作原理进行介绍。该移位寄存器单元在任一驱动模式下的具体驱动过程均可以包括输入阶段、输出阶段和复位阶段。例如，该任一驱动模式可以为上述第一驱动模式或上述第二驱动模式。
在输入阶段中，从输入信号端STV输出的输入信号为第一电位，第一输出控制晶体管M13开启，第三电源信号端CN向上拉节点PU输出第三电源信号，参考图5，该第三电源信号为第一电位，使该上拉节点PU的电位被拉高，此时第三输出控制晶体管M15和输出晶体管M20开启，第二电源信号端VGL向下拉节点PD输出第二电源信号，第六输出控制晶体管M18关断。此时输出电路40向输出端OUT输出来自该第二时钟控制电路20的信号CK_N，在该输入阶段，该信号CK_N可以为第二电位。
在输出阶段中，该上拉节点保持第一电位，当第二时钟控制电路20向该输出电路40输出的信号CK_N跳变至第一电位时，上拉节点PU由于自举效应，其电位被进一步拉高，此时输出晶体管M20完全开启，输出电路40向输出端OUT输出来自该第二时钟控制电路的信号CK_N，从而实现对一行像素单元的开启(即对该行像素单元进行驱动)，使得显示装置中的源极驱动电路能够通过数据线对该行像素单元进行充电，该充电时间即为该信号CK_N处于第一电位的时长。参考图5可知，信号CK_N在第一驱动模式T1中每个周期处于第一电位的时长较长，在第二驱动模式中每个周期处于第一 电位的时长较短，因此移位寄存器单元在不同的驱动模式下，对每行像素单元的充电时间不同，由此可以实现显示装置的高清显示或者低功耗显示。
在复位阶段中，复位信号端RST输出的复位信号也为第一电位，使得第二输出控制晶体管M14开启，第四电源信号端CNB向上拉节点PU输出第四电源信号，该第四电源信号为第二电位，从而将该上拉节点PU的电位下拉为第二电位，并且当第二时钟控制电路20向输出电路40输出的信号CK_N再次跳变至第二电位，且该第一时钟控制电路10向输出控制电路30输出的信号CKB_N处于第一电位时，第五输出控制晶体管M17开启，下拉节点PD的电位被拉高，第六输出控制晶体管M18和第七输出控制晶体管M19开启，第二电源信号端VGL向上拉节点PU和输出端OUT分别输出第二电源信号，该第二电源信号为第二电位，此时该移位寄存器单元处于关闭状态，以避免移位寄存器单元的非正常输出对其他行的移位寄存器单元造成影响。
综上所述，本公开实施例提供了一种移位寄存器单元的驱动方法，该驱动方法包括两种驱动模式，在不同的驱动模式下，移位寄存器单元能够向像素单元输出不同频率或者不同占空比的驱动信号，进而可以调整移位寄存器单元对每行像素单元的充电时间。在第一驱动模式下，移位寄存器单元输出的驱动信号的频率较低时，对每行像素单元的充电时间较长，此时显示装置的分辨率较低，可以实现显示装置的低功耗显示；在第二驱动模式下，移位寄存器单元输出的驱动信号的频率较高时，对每行像素单元的充电时间较短，此时显示装置的显示分辨率较高，可以实现显示装置的高清显示，因此丰富了栅极驱动电路对显示装置的驱动方式，提高了驱动的灵活性。
本公开实施例提供了一种栅极驱动电路，该栅极驱动电路可以包括至少两个级联的移位寄存器单元，其中每个移位寄存器单元可以为如图1至图3任一所示的移位寄存器单元。
本公开实施例提供一种显示装置，该显示装置可以包括栅极驱动电路，该栅极驱动电路可以包括至少两个级联的如图1至图3任一所示的移位寄存器单元。该显示装置可以为：液晶面板、电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本公开的示例实施例，并不用以限制本公开，凡在本公开 的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
在本文中，诸如“第一”和“第二”等关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本公开要求于2016年9月30日递交的中国专利申请第201610875608.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种移位寄存器单元，包括：
    第一时钟控制电路、第二时钟控制电路、输出控制电路和输出电路；其中，
    所述第一时钟控制电路分别与第一控制信号端、第二控制信号端、第一电源信号端、第二电源信号端、第一时钟信号端、第二时钟信号端、第三时钟信号端、第四时钟信号端和所述输出控制电路连接，其中，所述第一控制信号端和所述第二控制信号端分别被配置为提供第一控制信号和第二控制信号，所述第一时钟信号端、所述第二时钟信号端、所述第三时钟信号端和所述第四时钟信号端分别被配置为提供第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号；
    所述第二时钟控制电路分别与所述第一控制信号端、所述第二控制信号端、所述第一电源信号端、所述第二电源信号端、所述第一时钟信号端、所述第二时钟信号端、所述第三时钟信号端、所述第四时钟信号端和所述输出电路连接；
    所述输出控制电路分别与所述第一时钟控制电路、输入信号端、复位信号端、所述第二电源信号端、第三电源信号端、第四电源信号端、上拉节点和所述输出端连接，被配置为控制所述上拉节点和所述输出端的电位；
    所述输出电路分别与所述第二时钟控制电路、所述上拉节点和所述输出端连接，被配置为在所述上拉节点的控制下，向所述输出端输出来自所述第二时钟控制电路的信号；
    所述第一时钟控制电路被配置为在来自所述第二控制信号端的第二控制信号、来自所述第三时钟信号端的第三时钟信号和来自所述第四时钟信号端的第四时钟信号的控制下，向所述输出控制电路交替输出所述第二时钟信号和所述第一时钟信号，以及所述第二时钟控制电路被配置为在所述第二控制信号、所述第三时钟信号和所述第四时钟信号的控制下，向所述输出电路交替输出所述第一时钟信号和所述第二时钟信号；
    其中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的频率相同，相位互不相同。
  2. 根据权利要求1所述的移位寄存器单元，其中，
    所述第一时钟控制电路还被配置为在来自所述第一控制信号端的第一控制信号的控制下，向所述输出控制电路输出来自所述第二时钟信号端的第二时钟信号；以及
    所述第二时钟控制电路被配置为在所述第一控制信号的控制下，向所述输出电路输出来自所述第一时钟信号端的第一时钟信号。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述第一时钟控制电路包括：第一控制子电路、第二控制子电路和第一输出子电路；
    所述第一控制子电路分别与所述第一控制信号端、所述第一电源信号端、所述第二电源信号端和所述第一输出子电路连接，被配置为在所述第一控制信号的控制下，向所述第一输出子电路输出来自所述第一电源信号端的第一电源信号和来自所述第二电源信号端的第二电源信号；
    所述第二控制子电路分别与所述第二控制信号端、所述第三时钟信号端、所述第四时钟信号端和所述第一输出子电路连接，被配置为在所述第二控制信号的控制下，向所述第一输出子电路输出所述第三时钟信号和所述第四时钟信号；
    所述第一输出子电路分别与所述第一控制子电路、所述第二控制子电路、所述第一时钟信号端、所述第二时钟信号端和所述输出控制电路连接，被配置为在所述第一电源信号和所述第二电源信号的控制下，向所述输出控制电路输出所述第二时钟信号；或者，所述第一输出子电路被配置为在所述第三时钟信号和所述第四时钟信号的控制下，向所述输出控制电路交替输出所述第二时钟信号和所述第一时钟信号。
  4. 根据权利要求1或2所述的移位寄存器单元，其中，所述第二时钟控制电路，包括：第三控制子电路、第四控制子电路和第二输出子电路；
    所述第三控制子电路分别与所述第一控制信号端、所述第一电源信号端、所述第二电源信号端和所述第二输出子电路连接，被配置为在所述第一控制信号的控制下，向所述第二输出子电路输出来自所述第一电源信号端的第一电源信号和来自所述第二电源信号端的第二电源信号；
    所述第四控制子电路分别与所述第二控制信号端、所述第三时钟信号端、所述第四时钟信号端和所述第二输出子电路连接，被配置为在所述第二控制 信号的控制下，向所述第二输出子电路输出所述第三时钟信号和所述第四时钟信号；
    所述第二输出子电路分别与所述第三控制子电路、所述第四控制子电路、所述第一时钟信号端、所述第二时钟信号端和所述输出电路连接，被配置为在所述第一电源信号和所述第二电源信号的控制下，向所述输出电路输出所述第一时钟信号；或者，所述第二输出子电路被配置为在所述第三时钟信号和所述第四时钟信号的控制下，向所述输出电路交替输出所述第一时钟信号和所述第二时钟信号。
  5. 根据权利要求3所述的移位寄存器单元，其中，所述第一控制子电路，包括：第一晶体管和第二晶体管；所述第二控制子电路包括第三晶体管和第四晶体管；所述第一输出子电路包括：第五晶体管和第六晶体管；
    所述第一晶体管的栅极与所述第一控制信号端连接，所述第一晶体管的第一极与所述第一电源信号端连接，所述第一晶体管的第二极与所述第五晶体管的栅极连接；
    所述第二晶体管的栅极与所述第一控制信号端连接，所述第二晶体管的第一极与所述第二电源信号端连接，所述第二晶体管的第二极与所述第六晶体管的栅极连接；
    所述第三晶体管的栅极与所述第二控制信号端连接，所述第三晶体管的第一极与所述第三时钟信号端连接，所述第三晶体管的第二极与所述第五晶体管的栅极连接；
    所述第四晶体管的栅极与所述第二控制信号端连接，所述第四晶体管的第一极与所述第四时钟信号端连接，所述第四晶体管的第二极与所述第六晶体管的栅极连接；
    所述第五晶体管的第一极与所述第二时钟信号端连接，所述第五晶体管的第二极与所述输出控制电路连接；
    所述第六晶体管的第一极与所述第一时钟信号端连接，所述第六晶体管的第二极与所述输出控制电路连接。
  6. 根据权利要求4所述的移位寄存器单元，其中，所述第三控制子电路包括：第七晶体管和第八晶体管；所述第四控制子电路包括：第九晶体管和第十晶体管；所述第二输出子电路包括：第十一晶体管和第十二晶体管；
    所述第七晶体管的栅极与所述第一控制信号端连接，所述第七晶体管的第一极与所述第一电源信号端连接，所述第七晶体管的第二极与所述第十一晶体管的栅极连接；
    所述第八晶体管的栅极与所述第一控制信号端连接，所述第八晶体管的第一极与所述第二电源信号端连接，所述第八晶体管的第二极与所述第十二晶体管的栅极连接；
    所述第九晶体管的栅极与所述第二控制信号端连接，所述第九晶体管的第一极与所述第三时钟信号端连接，所述第九晶体管的第二极与所述第十一晶体管的栅极连接；
    所述第十晶体管的栅极与所述第二控制信号端连接，所述第十晶体管的第一极与所述第四时钟信号端连接，所述第十晶体管的第二极与所述第十二晶体管的栅极连接；
    所述第十一晶体管的第一极与所述第一时钟信号端连接，所述第十一晶体管的第二极与所述输出电路连接；
    所述第十二晶体管的第一极与所述第二时钟信号端连接，所述第十二晶体管的第二极与所述输出电路连接。
  7. 根据权利要求1-6任一项所述的移位寄存器单元，其中，所述输出控制电路包括：第一输出控制晶体管、第二输出控制晶体管、第三输出控制晶体管、第四输出控制晶体管、第五输出控制晶体管、第六输出控制晶体管和第七输出控制晶体管；
    所述第一输出控制晶体管的栅极与所述输入信号端连接，所述第一输出控制晶体管的第一极与所述第三电源信号端连接，所述第一输出控制晶体管的第二极与所述上拉节点连接；
    所述第二输出控制晶体管的栅极与所述复位信号端连接，所述第二输出控制晶体管的第一极与所述第四电源信号端连接，所述第二输出控制晶体管的第二极与所述上拉节点连接；
    所述第三输出控制晶体管的栅极与所述上拉节点连接，所述第三输出控制晶体管的第一极与所述第二电源信号端连接，所述第三输出控制晶体管的第二极与下拉节点连接；
    所述第四输出控制晶体管的栅极与所述输出端连接，所述第四输出控制 晶体管的第一极与所述第二电源信号端连接，所述第四输出控制晶体管的第二极与所述下拉节点连接；
    所述第五输出控制晶体管的栅极和第一极与所述第一时钟控制电路连接，所述第五输出控制晶体管的第二极与所述下拉节点连接；
    所述第六输出控制晶体管的栅极与所述下拉节点连接，所述第六输出控制晶体管的第一极与所述第二电源信号端连接，所述第六输出控制晶体管的第二极与所述上拉节点连接；
    所述第七输出控制晶体管的栅极与所述下拉节点连接，所述第七输出控制晶体管的第一极与所述第二电源信号端连接，所述第七输出控制晶体管的第二极与所述输出端连接。
  8. 根据权利要求1-7任一项所述的移位寄存器单元，其中，所述输出电路包括：输出晶体管和电容器；
    所述输出晶体管的栅极与所述上拉节点连接，所述输出晶体管的第一极与所述第二时钟控制电路连接，所述输出晶体管的第二极与所述输出端连接；
    所述电容器的一端与所述上拉节点连接，另一端与所述输出端连接。
  9. 根据权利要求1至8任一所述的移位寄存器单元，其中，
    所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的占空比均为二分之一；
    所述第一时钟信号与所述第二时钟信号的相位差为180度，所述第三时钟信号与所述第四时钟信号的相位差为180度，且所述第一时钟信号与所述第三时钟信号的相位差为90度。
  10. 根据权利要求5至8任一所述的移位寄存器单元，其中，所述晶体管均为N型晶体管。
  11. 一种移位寄存器单元的驱动方法，其中，所述移位寄存器单元包括：第一时钟控制电路、第二时钟控制电路、输出控制电路和输出电路，所述方法包括：
    在第一驱动模式中，第一控制信号端输出的第一控制信号为第一电位，第二控制信号端输出的第二控制信号为第二电位，通过所述第一时钟控制电路向所述输出控制电路输出来自第二时钟信号端的第二时钟信号，通过所述第二时钟控制电路向所述输出电路输出来自第一时钟信号端的第一时钟信 号；
    在第二驱动模式中，第一控制信号端输出的第一控制信号为第二电位，第二控制信号端输出的第二控制信号为第一电位，第三时钟信号端输出第三时钟信号，第四时钟信号端输出第四时钟信号，通过所述第一时钟控制电路向所述输出控制电路交替输出所述第二时钟信号和所述第一时钟信号，通过所述第二时钟控制电路向所述输出电路交替输出所述第一时钟信号和所述第二时钟信号；
    其中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的频率相同，相位互不相同。
  12. 根据权利要求11所述的方法，其中，所述第一驱动模式和所述第二驱动模式中的任一驱动模式包括：
    输入阶段，其中，输入信号端输出的输入信号为第一电位，所述输出控制电路将上拉节点的电位上拉为第一电位；
    输出阶段，其中，所述上拉节点保持第一电位，所述输出电路接收并输出来自所述第二时钟控制电路的信号；
    复位阶段，其中，复位信号端输出的复位信号为第一电位，所述输出控制电路控制所述上拉节点的电位为第二电位。
  13. 根据权利要求11或12所述的方法，其中，
    所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的占空比均为二分之一；
    所述第一时钟信号与所述第二时钟信号的相位差为180度，所述第三时钟信号与所述第四时钟信号的相位差为180度，且所述第一时钟信号与所述第三时钟信号的相位差为90度。
  14. 一种栅极驱动电路，包括：
    至少两个级联的移位寄存器单元，其中各所述移位寄存器单元为如权利要求1至10任一所述的移位寄存器单元。
  15. 一种显示装置，包括：如权利要求14所述的栅极驱动电路。
PCT/CN2017/092712 2016-09-30 2017-07-13 移位寄存器单元、驱动方法、栅极驱动电路及显示装置 Ceased WO2018059075A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/744,554 US10210791B2 (en) 2016-09-30 2017-07-13 Shift register unit, driving method, gate driver on array and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610875608.8 2016-09-30
CN201610875608.8A CN106205461B (zh) 2016-09-30 2016-09-30 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Publications (1)

Publication Number Publication Date
WO2018059075A1 true WO2018059075A1 (zh) 2018-04-05

Family

ID=57521052

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/092712 Ceased WO2018059075A1 (zh) 2016-09-30 2017-07-13 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Country Status (3)

Country Link
US (1) US10210791B2 (zh)
CN (1) CN106205461B (zh)
WO (1) WO2018059075A1 (zh)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336291B (zh) * 2015-12-04 2018-11-02 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法与显示装置
CN106251804B (zh) * 2016-09-30 2018-12-21 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN106205461B (zh) 2016-09-30 2019-04-02 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN106710547B (zh) 2016-12-27 2019-03-12 武汉华星光电技术有限公司 Goa电路
CN106710561B (zh) * 2017-03-08 2019-09-17 京东方科技集团股份有限公司 一种移位寄存器、栅线集成驱动电路及显示装置
CN106875911B (zh) * 2017-04-12 2019-04-16 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法
CN106960652B (zh) 2017-04-21 2018-10-30 京东方科技集团股份有限公司 栅极驱动单元、驱动方法、栅极驱动电路和显示装置
CN107564473B (zh) * 2017-09-12 2019-12-13 北京大学深圳研究生院 栅极驱动电路
CN107731147B (zh) 2017-10-25 2020-03-31 深圳市华星光电半导体显示技术有限公司 扫描驱动器及扫描驱动器的驱动方法
CN108172192B (zh) * 2018-03-20 2020-11-03 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示设备
CN108806603B (zh) * 2018-06-29 2020-03-17 上海天马有机发光显示技术有限公司 一种有机发光显示面板及其驱动方法、有机发光显示装置
CN109036282B (zh) * 2018-08-24 2020-05-22 合肥鑫晟光电科技有限公司 栅极驱动输出级电路、栅极驱动单元及驱动方法
CN109473055A (zh) * 2018-12-11 2019-03-15 深圳市华星光电半导体显示技术有限公司 显示装置及其驱动方法
CN109410881B (zh) * 2018-12-20 2020-06-02 深圳市华星光电技术有限公司 信号传输系统及信号传输方法
CN112150974B (zh) * 2019-06-26 2021-08-27 京东方科技集团股份有限公司 显示方法、时序控制器和显示装置
CN111508433B (zh) * 2020-05-28 2021-08-31 京东方科技集团股份有限公司 信号生成电路、信号生成方法、信号生成模组和显示装置
KR102788776B1 (ko) * 2020-07-30 2025-04-01 삼성디스플레이 주식회사 스캔 드라이버 및 표시 장치
CN112700745B (zh) * 2021-01-19 2023-05-05 Tcl华星光电技术有限公司 显示面板的驱动方法及显示面板
CN113570998B (zh) * 2021-07-30 2022-05-10 惠科股份有限公司 显示面板的控制电路和显示装置
CN113570996B (zh) 2021-07-30 2022-05-10 惠科股份有限公司 显示面板的驱动电路和显示装置
KR102832243B1 (ko) * 2021-12-29 2025-07-10 엘지디스플레이 주식회사 표시장치 및 이의 구동방법
KR20240139437A (ko) * 2023-03-14 2024-09-23 에스케이하이닉스 주식회사 파워 게이팅 제어 회로, 이를 이용하는 반도체 장치 및 반도체 시스템
CN119091797A (zh) * 2023-06-06 2024-12-06 武汉华星光电半导体显示技术有限公司 栅极驱动单元及显示装置
CN121354491A (zh) * 2023-06-25 2026-01-16 武汉华星光电半导体显示技术有限公司 一种栅极驱动模块和显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110150169A1 (en) * 2009-12-22 2011-06-23 Au Optronics Corp. Shift register
CN103198781A (zh) * 2013-03-01 2013-07-10 合肥京东方光电科技有限公司 移位寄存器单元、栅极驱动装置及显示装置
CN103730089A (zh) * 2013-12-26 2014-04-16 京东方科技集团股份有限公司 栅极驱动电路、方法、阵列基板行驱动电路和显示装置
CN104269145A (zh) * 2014-09-05 2015-01-07 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
US20150301415A1 (en) * 2012-11-05 2015-10-22 Sharp Kabushiki Kaisha Liquid crystal display device
CN106205461A (zh) * 2016-09-30 2016-12-07 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101137880B1 (ko) * 2004-12-31 2012-04-20 엘지디스플레이 주식회사 쉬프트 레지스터 및 그 구동 방법
CN102982777B (zh) * 2012-12-07 2015-10-07 京东方科技集团股份有限公司 显示装置的栅极驱动电路
JP2014142457A (ja) * 2013-01-23 2014-08-07 Japan Display Inc 表示装置
CN103413514A (zh) * 2013-07-27 2013-11-27 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
KR102268520B1 (ko) * 2014-12-10 2021-06-24 엘지디스플레이 주식회사 표시 장치 및 표시 장치의 구동 방법
CN104485086A (zh) * 2015-01-04 2015-04-01 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路及显示器件
CN104867438B (zh) * 2015-06-24 2018-02-13 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110150169A1 (en) * 2009-12-22 2011-06-23 Au Optronics Corp. Shift register
US20150301415A1 (en) * 2012-11-05 2015-10-22 Sharp Kabushiki Kaisha Liquid crystal display device
CN103198781A (zh) * 2013-03-01 2013-07-10 合肥京东方光电科技有限公司 移位寄存器单元、栅极驱动装置及显示装置
CN103730089A (zh) * 2013-12-26 2014-04-16 京东方科技集团股份有限公司 栅极驱动电路、方法、阵列基板行驱动电路和显示装置
CN104269145A (zh) * 2014-09-05 2015-01-07 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN106205461A (zh) * 2016-09-30 2016-12-07 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Also Published As

Publication number Publication date
US20190005866A1 (en) 2019-01-03
CN106205461A (zh) 2016-12-07
US10210791B2 (en) 2019-02-19
CN106205461B (zh) 2019-04-02

Similar Documents

Publication Publication Date Title
WO2018059075A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN104715734B (zh) 移位寄存器、栅极驱动电路及显示装置
WO2018059159A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN104464600B (zh) 移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置
CN104575430B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
US9293223B2 (en) Shift register unit, gate driving circuit and display device
US10629151B2 (en) Shift register unit, gate driving circuit, display and gate driving method
WO2020024641A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN110503927B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
WO2020015641A1 (zh) 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN108573668B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN110930942B (zh) 移位寄存器及其控制方法、显示面板
WO2017107285A1 (zh) 用于窄边框液晶显示面板的goa电路
WO2018233306A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2016169141A1 (zh) 移位寄存器及其驱动方法、栅极驱动装置、显示面板
CN105788553B (zh) 基于ltps半导体薄膜晶体管的goa电路
WO2018218886A1 (zh) 移位寄存器、栅极驱动电路、显示装置
WO2015089954A1 (zh) 移位寄存器单元、栅极驱动电路及显示器件
WO2021022478A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
WO2017118136A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路以及显示装置
CN108538237B (zh) 一种栅极驱动电路、方法及显示装置
CN105489189A (zh) 栅极驱动单元、栅极驱动电路及其驱动方法和显示装置
WO2019010956A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US11227525B2 (en) Shift register unit and method for driving the same, gate driving circuit and method for driving the same, and display apparatus
JP2020531877A (ja) シフトレジスタユニット、シフトレジスタユニットの駆動方法、ゲートドライバオンアレイ及び表示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17854529

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 11/07/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17854529

Country of ref document: EP

Kind code of ref document: A1