[go: up one dir, main page]

WO2018051943A1 - Dispositif d'affichage - Google Patents

Dispositif d'affichage Download PDF

Info

Publication number
WO2018051943A1
WO2018051943A1 PCT/JP2017/032656 JP2017032656W WO2018051943A1 WO 2018051943 A1 WO2018051943 A1 WO 2018051943A1 JP 2017032656 W JP2017032656 W JP 2017032656W WO 2018051943 A1 WO2018051943 A1 WO 2018051943A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate lines
display device
circuit
feedback signal
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2017/032656
Other languages
English (en)
Japanese (ja)
Inventor
圭祐 神田
裕昭 杉山
哲 関戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of WO2018051943A1 publication Critical patent/WO2018051943A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to a display device, and more particularly to a display device capable of switching a scanning direction.
  • Patent Document 1 discloses a display device including a drive circuit having a first input / output terminal and a second input / output terminal.
  • a start pulse is taken in from the first input / output terminal and output from the second input / output terminal in the first scanning direction (for example, upward direction), or started from the second input / output terminal.
  • the scanning direction can be switched to the second scanning direction (for example, the downward direction) in which a pulse is captured and output from the first input / output terminal.
  • a gate driver for selecting a row of pixels and supplying a drive signal (selection signal) has been conventionally formed outside the display area (so-called frame area). Recently, however, a configuration in which all or at least a part of the circuit elements constituting the gate driver is arranged in the display area is also known.
  • the present invention provides a display device in which at least a part of circuit elements constituting a gate driver is arranged in a display region, and can detect a signal abnormality when the scanning direction is switched. For the purpose.
  • a display device is a display device including a display panel having a display region in which a plurality of gate lines and a plurality of source lines are arranged in a matrix.
  • at least a part of circuit elements constituting a gate driver for driving the plurality of gate lines is arranged in the display area.
  • the display device includes a first scanning mode in which the plurality of gate lines are sequentially driven in a first direction, and a second direction in which the plurality of gate lines are sequentially driven in a second direction opposite to the first direction.
  • a scanning mode is a display panel having a display region in which a plurality of gate lines and a plurality of source lines are arranged in a matrix.
  • the display device outputs a start pulse for controlling the driving timing of the plurality of gate lines to the display panel, and receives a feedback signal from the display panel when the driving of the plurality of gate lines is completed.
  • a control unit a control unit.
  • the display device includes a booster circuit that generates a selection signal to be supplied to each of the plurality of gate lines by boosting a power supply voltage to a predetermined voltage between the control unit and the display panel. In each of the first scan mode and the second scan mode, when the selection signal is supplied to the gate line driven last among the plurality of gate lines, the selection signal is stepped down to generate a feedback signal, And a step-down circuit that outputs the generated feedback signal to the control unit.
  • a display device in which at least a part of circuit elements constituting a gate driver is arranged in a display area, and a display capable of detecting a display signal abnormality simultaneously with switching a scanning direction.
  • An apparatus can be provided.
  • FIG. 1 is a diagram illustrating a schematic configuration of a liquid crystal display device according to an embodiment.
  • FIG. 2 is a top view showing a schematic configuration of an active matrix substrate included in the liquid crystal display device according to the present embodiment.
  • FIG. 3 is a top view illustrating a schematic configuration of an active matrix substrate included in the liquid crystal display device according to the present embodiment.
  • FIG. 4 is a block diagram showing an extracted display control circuit and a display panel of the liquid crystal display device according to the present embodiment.
  • FIG. 5 is an explanatory diagram illustrating the relationship between the scanning direction of the gate lines GL, the terminals of the timing controller, and the switches of the switching circuit in the display panel.
  • FIG. 6 is a waveform diagram showing waveforms of various signals in the forward direction scanning mode and the backward direction scanning mode.
  • FIG. 7 is a waveform diagram showing a high voltage selection signal (a), a low voltage start pulse signal and a feedback signal (b) supplied to the gate lines.
  • FIG. 8 is a circuit diagram showing an example of the configuration of the level-down circuit.
  • FIG. 9 is a circuit diagram showing another example of the configuration of the level-down circuit.
  • FIG. 10 is a circuit diagram showing another example of the configuration of the level-down circuit.
  • a display device is a display device including a display panel having a display region in which a plurality of gate lines and a plurality of source lines are arranged in a matrix, and the plurality of gate lines. At least a part of the circuit elements constituting the gate driver for driving is arranged in the display area.
  • the display device includes a first scanning mode in which the plurality of gate lines are sequentially driven in a first direction, and a second direction in which the plurality of gate lines are sequentially driven in a second direction opposite to the first direction.
  • a scanning mode is a display panel having a display region in which a plurality of gate lines and a plurality of source lines are arranged in a matrix, and the plurality of gate lines. At least a part of the circuit elements constituting the gate driver for driving is arranged in the display area.
  • the display device includes a first scanning mode in which the plurality of gate lines are sequentially driven in a first direction, and a second direction in which the plurality of gate lines are sequentially driven in a second
  • the display device outputs a start pulse for controlling the driving timing of the plurality of gate lines to the display panel, and receives a feedback signal from the display panel when the driving of the plurality of gate lines is completed.
  • a control unit a control unit.
  • the display device includes a booster circuit that generates a selection signal to be supplied to each of the plurality of gate lines by boosting a power supply voltage to a predetermined voltage between the control unit and the display panel. In each of the first scan mode and the second scan mode, when the selection signal is supplied to the gate line driven last among the plurality of gate lines, the selection signal is stepped down to generate a feedback signal, And a step-down circuit that outputs the generated feedback signal to the control unit.
  • the booster circuit and the step-down circuit are provided between the control unit and the display panel, at least a part of the circuit elements constituting the gate driver is arranged in the display region.
  • the step-down circuit steps down the selection signal to generate a feedback signal.
  • a display error or the like can be detected based on the feedback signal.
  • the step-down circuit when the step-down circuit supplies the selection signal to the gate line of the last row in the first direction among the plurality of gate lines in the first scanning mode, the selection signal A first step-down circuit for generating a feedback signal by outputting the generated feedback signal to the control unit, and a final scan in the second direction among the plurality of gate lines in the second scanning mode.
  • a second voltage step-down circuit configured to step down the selection signal to generate a feedback signal when the selection signal is supplied to the gate line of the row, and to output the generated feedback signal to the control unit; (Second configuration).
  • a switching circuit provided between the control unit, the booster circuit, and the step-down circuit may be further provided (third configuration).
  • the switching circuit includes: a first switch that switches connection / disconnection between the first terminal of the control unit and the booster circuit; and a connection / disconnection between the second terminal of the control unit and the booster circuit.
  • a fourth switch for switching connection / disconnection with the circuit and in the first scanning mode, the control unit outputs the start pulse from the first terminal and the feedback from the second terminal. In the second scanning mode, the control unit outputs the start pulse from the second terminal and receives the feedback signal from the first terminal.
  • the voltages of the start pulse and the feedback signal are equal (fourth configuration). Further, in the fourth configuration, it is preferable that voltages of the start pulse and the feedback signal are equal to the power supply voltage (fifth configuration).
  • FIG. 1 is a schematic diagram showing a schematic configuration of the liquid crystal display device according to the present embodiment.
  • the liquid crystal display device 1 includes a display panel 2, a source driver 3, a display control circuit 4, and a power supply 5.
  • the display panel 2 includes an active matrix substrate 20a, a counter substrate 20b, and a liquid crystal layer (not shown) sandwiched between these substrates.
  • polarizing plates are provided on the lower surface side of the active matrix substrate 20a and the upper surface of the counter substrate 20b.
  • a color filter and a common electrode are formed on the counter substrate 20b.
  • the active matrix substrate 20a is connected to a source driver 3 formed on a flexible substrate.
  • the display control circuit 4 is electrically connected to the display panel 2, the source driver 3, and the power source 5.
  • the display control circuit 4 outputs control signals to the source driver 3 and a gate driver described later.
  • the control signal includes a reset signal, a clock signal, a data signal, and the like for displaying an image on the display panel 2 in accordance with an image signal and timing signal input from the outside.
  • the power supply 5 is electrically connected to the display panel 2, the source driver 3, and the display control circuit 4, and supplies a power supply voltage signal to each.
  • FIGS. 2 and 3 are top views showing a schematic configuration of the active matrix substrate 20a of the display panel 2.
  • FIG. As shown in FIGS. 2 and 3, the active matrix substrate 20a has a plurality of gate lines GL formed in parallel along one direction (X direction in FIG. 2) of the active matrix substrate 20a.
  • a plurality of source lines SL are formed so as to intersect with the gate lines GL.
  • a region surrounded by the gate line GL and the source line SL forms one pixel. The area where the pixels are formed becomes the display area of the display panel 1.
  • a pixel TFT (not shown) is formed in the vicinity of the intersection of the gate line GL and the source line SL.
  • the gate of the pixel TFT is connected to the gate line GL, the source is connected to the source line SL, and the drain is connected to the pixel electrode (not shown).
  • the gate lines GL are selected one by one by a gate driver described later.
  • the pixel TFT connected to the selected gate line GL is turned on, and a pixel signal corresponding to the gradation to be displayed is supplied from the source line SL, whereby each pixel displays a desired gradation.
  • the display panel 2 is provided with n gate lines.
  • the respective gate lines are referred to as GL1, GL2,... GLn as shown in FIG.
  • the side on which GL1 is disposed is referred to as the upper side of the display panel 2
  • the side on which GLn is disposed is referred to as the lower side of the display panel 2.
  • the forward scanning mode in which the gate lines GL of the display panel 2 are sequentially selected from the top to the bottom, and the gate lines GL are sequentially selected from the bottom to the top.
  • a reverse scanning mode That is, in the forward direction scanning mode, the gate lines GL are selected in the order of GL1, GL2,. In the reverse scanning mode, the gate lines GL are selected in the order of GLn, GLn-1, GLn-2, ..., GL2, GL1.
  • the gate driver 11 is formed between adjacent gate lines GL in the display area of the active matrix substrate 20a.
  • the gate driver 11 is shown as one block. However, the actual gate driver 11 is not provided in one place like an integrated circuit.
  • the circuit elements (transistors and the like) to be configured are distributed in the pixel region.
  • a plurality of gate drivers 11 are provided for each of the gate lines GL.
  • a plurality of gate drivers 11 connected to one gate line GL are synchronized, and one gate line GL is driven by a selection signal (gate signal) output simultaneously from these gate drivers 11.
  • Signals such as control signals and power supply voltage signals output from the display control circuit 4 and the power supply 5 are terminal portions 12 formed outside the display area on the side where the source driver 3 of the active matrix substrate 20a is provided. Is input. Signals such as a control signal and a power supply voltage signal input to the terminal unit 12 are supplied to each gate driver 11 via the signal wiring 15L.
  • the signal line 15L is formed substantially in parallel with the source line SL.
  • FIG. 4 is a block diagram in which the display control circuit 4 and the display panel 2 in the liquid crystal display device 1 are extracted and shown.
  • the display control circuit 4 includes a switching circuit 41, a timing controller 42 (control unit), a level shifter 43 (boost circuit), and a level down circuit 44 (voltage drop circuit).
  • the level shifter 43 and the level down circuit 44 can be provided between the timing controller 42 and the display panel 2 and outside the display panel 2 (for example, on a flexible substrate).
  • the level down circuit 44 includes a first level down circuit 44a and a second level down circuit 44b.
  • the first level down circuit 44a is connected to a gate line (gate line GL1 in the present embodiment) that is last driven in the backward scanning mode.
  • the second level down circuit 44b is connected to the gate line (gate line GLn in the present embodiment) that is last driven in the forward scanning mode.
  • the timing controller 42 includes two terminals STV_D and STD_U, and switches input / output of these terminals according to the scanning direction of the gate line GL in the display panel 2.
  • the switching circuit 41 includes four switches SW1 to SW4 as shown in FIG.
  • the switch SW1 switches connection / disconnection between the terminal STV_D of the timing controller 42 and the level shifter 43.
  • the switch SW2 switches connection / disconnection between the terminal STV_U of the timing controller 42 and the level shifter 43.
  • the switch SW3 switches connection / disconnection between the terminal STV_D of the timing controller 42 and the first level down circuit 44a.
  • the switch SW4 switches connection / disconnection between the terminal STV_U of the timing controller 42 and the second level down circuit 44b.
  • the switches SW1 to SW4 can be configured with analog switches. Each of the switches SW1 to SW4 is switched on or off according to the scanning direction of the gate line GL in the display panel 2.
  • FIG. 5 is an explanatory diagram showing the relationship between the scanning direction of the gate lines GL in the display panel 2, the terminals of the timing controller 42, and the switches SW1 to SW4 of the switching circuit 41.
  • the timing controller 42 sets STV_D as the output terminal of the start pulse of the video signal, and sets STV_U to Used as an input terminal for a feedback signal.
  • the switch SW1 and the switch SW4 are turned on, and the switch SW2 and the switch SW3 are turned off.
  • the terminal STV_D of the timing controller 42 and the level shifter 43 are connected, and the terminal STV_U of the timing controller 42 and the second level down circuit 44b are connected.
  • STV_U is used as an output terminal of the start pulse of the video signal
  • STV_D is a feedback signal. Input terminal.
  • the switch SW2 and the switch SW3 are turned on, and the switch SW1 and the switch SW4 are turned off.
  • the terminal STV_U of the timing controller 42 and the level shifter 43 are connected, and the terminal STV_D of the timing controller 42 and the first level down circuit 44a are connected.
  • the start pulse STv is output from the terminal STV_D of the timing controller 42 to the level shifter 43 via the switch SW1.
  • the level shifter 43 generates a high voltage selection signal SS based on the start pulse STv.
  • the selection signal SS is supplied from the gate driver 11 connected to the uppermost gate line GL1 to the gate line GL1. Thereafter, the selection signal SS is sequentially supplied to the gate lines GL2, GL3,.
  • the selection signal SS is dropped by the second level down circuit 44b and used as a feedback signal RS as a terminal of the timing controller 42. Detected with STV_U.
  • the feedback signal RS is used for detecting a display error or the like as a signal indicating that the last stage of the display panel 2 has been displayed.
  • the start pulse STv is output from the terminal STV_U of the timing controller 42 to the level shifter 43 via the switch SW2.
  • the level shifter 43 generates a high voltage selection signal SS based on the start pulse STv.
  • This selection signal SS is supplied to the gate line GLn from the gate driver 11 connected to the lowermost gate line GLn. Thereafter, the selection signal SS is sequentially supplied to the gate lines GLn-1, GLn-2,... GL2, GL1.
  • the selection signal SS When the selection signal SS is supplied to the uppermost stage of the display panel 2 (that is, the gate line GL1), the selection signal SS is dropped by the first level down circuit 44a, and is used as a feedback signal RS as a terminal of the timing controller 42. Detected with STV_D.
  • the high voltage selection signal SS output from the level shifter 43 is a signal having an amplitude of, for example, 28 V (+21 V to ⁇ 7 V) as shown in FIG.
  • the selection signal SS is generated by amplifying the low voltage start pulse STv by the level shifter 43.
  • the start pulse STv is a signal having an amplitude of, for example, 3.3 V (0 V to +3.3 V).
  • the level down circuit 44 drops the high voltage selection signal SS to generate a low voltage feedback signal RS.
  • the feedback signal RS is also a signal having an amplitude of, for example, 3.3 V (0 V to +3.3 V), similarly to the start pulse STv shown in FIG. That is, the feedback signal RS must be dropped to a voltage as low as a digital signal in order to be processed by the timing controller 42.
  • the first level down circuit 44a and the second level down circuit 44b of the level down circuit 44 are respectively shown in FIG. It can be realized by a simple transistor configuration, an operational amplifier configuration as shown in FIG. 9, or a diode configuration as shown in FIG.
  • the first level down circuit 44a (or the second level down circuit 44b) has an input terminal Vin, an output terminal Vout, resistors R1 to R6, and transistors T1 to T3.
  • the transistor T1 is a pnp bipolar transistor, and the transistors T2 and T3 are npn bipolar transistors.
  • One end of a resistor R1 and a resistor R3 is connected to the base of the transistor T1.
  • One ends of a resistor R2 and a resistor R4 are connected to the base of the transistor T2.
  • the other ends of the resistors R1 and R2 are connected to the input terminal Vin.
  • the other end of the resistor R3 and the emitter of the transistor T1 are connected to a low-voltage (for example, 3.3 V) power supply voltage Vcc.
  • the other end of the resistor R4 is connected to the emitter of the transistor T2.
  • the collectors of the transistors T1 and T2 are connected to one end of the resistor R5.
  • the other end of the resistor R5 is connected to the base of the transistor T3.
  • the collector of the transistor T3 is connected to the power supply voltage Vcc via the resistor R6.
  • An output terminal Vout is connected between the resistor R6 and the collector of the transistor T3.
  • the first level down circuit 44 a and the second level down circuit 44 b convert the high voltage signal for driving the gate line of the display panel 2 into a low voltage signal handled by the timing controller 42.
  • the voltage can be lowered.
  • the first level down circuit 44a (or the second level down circuit 44b) includes an input terminal Vin, an output terminal Vout, resistors R11 to R14, an operational amplifier OP1, and a capacitor C1. ing.
  • a resistor R11 is connected to the input terminal Vin.
  • the other end of the resistor R11 is connected to one end of the resistor R12 and the + terminal of the operational amplifier OP1.
  • the other end of the resistor R12 is connected to a reference potential (GND).
  • One end of the resistor R14 is connected to the-terminal of the operational amplifier OP1 and one end of the resistor R13.
  • the other end of the resistor R14 is connected to the reference potential.
  • the other end of the resistor R13 is connected to the positive power supply terminal Vcc of the operational amplifier OP1 and one end of the capacitor C1.
  • the negative power supply terminal of the operational amplifier is connected to the reference potential.
  • the other end of the capacitor C1 is connected to a reference potential.
  • the first level down circuit 44a and the second level down circuit 44b are configured to use a high voltage signal for driving the gate line of the display panel 2 as a low voltage signal handled by the timing controller 42.
  • the voltage can be dropped to
  • the first level down circuit 44a (or the second level down circuit 44b) has an input terminal Vin, an output terminal Vout, resistors R21 and R22, and a diode D1.
  • One end of a resistor R21 is connected to the input terminal Vin.
  • the other end of the resistor R21 is connected to the anode end of the diode D1.
  • the cathode end of the diode D1 is connected to the reference potential (GND) via the resistor 22.
  • An output terminal Vout is connected between the cathode end of the diode D1 and the resistor R22.
  • the first level-down circuit 44a and the second level-down circuit 44b use the low-voltage signal handled by the timing controller 42 as a high-voltage signal for driving the gate line of the display panel 2.
  • the voltage can be dropped to
  • the scanning direction of the gate lines can be switched between the forward direction and the reverse direction.
  • the feedback signal is generated by dropping the high voltage selection signal applied to the gate line (GL1) driven last by the level down circuit. And the feedback signal is detected by the timing controller. Thereby, even when the scanning direction is reversed, it is possible to detect a display error or the like using the feedback signal.
  • a rectangular display panel is illustrated, but the shape of the display panel is not limited to a rectangle and is arbitrary.
  • the circuit elements constituting the gate driver By disposing the circuit elements constituting the gate driver in the display region, the length of the gate line can be partially changed, so that the end of the display panel in the width direction (X direction shown in FIG. 2)
  • the shape can be designed freely. Thereby, for example, an elliptical or semicircular display panel can be realized.
  • the configuration in which all the circuit elements constituting the gate driver are arranged in the display area is exemplified.
  • a part of the circuit elements constituting the gate driver is provided in a frame area or the like outside the display area. It is good also as the structure comprised.
  • the level down circuit 44 includes the first level down circuit 44a connected to the gate line GL1 and the second level down circuit 44b connected to the gate line GLn. Illustrated. Then, the switching circuit 41 provided on the output terminal side of the level down circuit 44 causes the feedback signal output from the first level down circuit 44a to be received at the terminal STV_D and output from the second level down circuit 44b. The feedback signal is received at the terminal STV_U.
  • a changeover switch may be provided on both the input side and the output side of the level down circuit.
  • the amplitude of the start pulse STv is equal to the power supply voltage Vcc.
  • the amplitude of the start pulse STv and the power supply voltage Vcc may be different.
  • SYMBOLS 1 Liquid crystal display device, 2 ... Display panel, 3 ... Source driver, 4 ... Display control circuit, 5 ... Power supply, 41 ... Switching circuit, 42 ... Timing controller, 43 ... Level shifter, 44 ... Level down circuit, 44a ... 1st Level down circuit, 44b... Second level down circuit

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention concerne un dispositif d'affichage dans lequel au moins une partie d'un élément de circuit constituant des pilotes de grille est disposée dans une zone d'affichage, une opération pouvant être effectuée dans deux modes de balayage, notamment un premier mode de balayage dans lequel une pluralité de lignes de grille sont commandées séquentiellement dans une première direction et un second mode de balayage dans lequel la pluralité de lignes de grille sont commandées séquentiellement dans une seconde direction qui est opposée à la première direction, des anomalies d'affichage pouvant être détectées dans les deux modes de balayage à l'aide d'un signal de rétroaction. Le dispositif d'affichage comprend une unité de commande de synchronisation (42) qui génère une impulsion de démarrage permettant de contrôler la synchronisation de commande de la pluralité de lignes de grille et qui reçoit un signal de rétroaction lorsqu'un cycle de commande de la pluralité de lignes de grille est terminé. Le dispositif d'affichage comprend également : un dispositif de décalage de niveau (43) qui génère un signal de sélection de ligne de grille en élevant une tension d'alimentation électrique à une tension prédéterminée ; et des circuits d'abaissement de niveau qui génèrent un signal de rétroaction en abaissant le signal de sélection lorsque le signal de sélection est fourni à la ligne de grille qui est commandée en dernier parmi la pluralité de lignes de grille dans le premier et le second mode de balayage.
PCT/JP2017/032656 2016-09-13 2017-09-11 Dispositif d'affichage Ceased WO2018051943A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-178675 2016-09-13
JP2016178675 2016-09-13

Publications (1)

Publication Number Publication Date
WO2018051943A1 true WO2018051943A1 (fr) 2018-03-22

Family

ID=61619157

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/032656 Ceased WO2018051943A1 (fr) 2016-09-13 2017-09-11 Dispositif d'affichage

Country Status (1)

Country Link
WO (1) WO2018051943A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020103205A1 (fr) * 2018-11-21 2020-05-28 惠科股份有限公司 Circuit d'attaque et panneau d'affichage

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0962232A (ja) * 1995-08-29 1997-03-07 Sony Corp 液晶表示装置
JP2003271109A (ja) * 2002-03-18 2003-09-25 Sharp Corp 表示装置およびその走査回路検査方法
JP2009025426A (ja) * 2007-07-18 2009-02-05 Sharp Corp 表示装置、表示パネルの検査装置および検査方法
JP2009210835A (ja) * 2008-03-04 2009-09-17 Sharp Corp 液晶パネルおよび液晶表示装置
WO2014142183A1 (fr) * 2013-03-15 2014-09-18 シャープ株式会社 Substrat à matrice active, procédé de fabrication de substrat à matrice active et panneau d'affichage
US20160111040A1 (en) * 2014-10-16 2016-04-21 Lg Display Co., Ltd. Panel array for display device with narrow bezel
WO2016140281A1 (fr) * 2015-03-02 2016-09-09 シャープ株式会社 Substrat à matrice active et dispositif d'affichage équipé de celui-ci

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0962232A (ja) * 1995-08-29 1997-03-07 Sony Corp 液晶表示装置
JP2003271109A (ja) * 2002-03-18 2003-09-25 Sharp Corp 表示装置およびその走査回路検査方法
JP2009025426A (ja) * 2007-07-18 2009-02-05 Sharp Corp 表示装置、表示パネルの検査装置および検査方法
JP2009210835A (ja) * 2008-03-04 2009-09-17 Sharp Corp 液晶パネルおよび液晶表示装置
WO2014142183A1 (fr) * 2013-03-15 2014-09-18 シャープ株式会社 Substrat à matrice active, procédé de fabrication de substrat à matrice active et panneau d'affichage
US20160111040A1 (en) * 2014-10-16 2016-04-21 Lg Display Co., Ltd. Panel array for display device with narrow bezel
WO2016140281A1 (fr) * 2015-03-02 2016-09-09 シャープ株式会社 Substrat à matrice active et dispositif d'affichage équipé de celui-ci

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020103205A1 (fr) * 2018-11-21 2020-05-28 惠科股份有限公司 Circuit d'attaque et panneau d'affichage
US11443666B2 (en) 2018-11-21 2022-09-13 HKC Corporation Limited Drive circuit for adjusting a voltage required for aging detection using a feedback circuit, and display panel

Similar Documents

Publication Publication Date Title
US8248357B2 (en) Pixel driving circuit and a display device having the same
US7327338B2 (en) Liquid crystal display apparatus
JP5047640B2 (ja) 表示装置の駆動装置及びこれを有する表示装置
US20080192032A1 (en) Display apparatus and method of driving the same
US20080284758A1 (en) Liquid crystal display and method of driving the same
US10726756B2 (en) Display device
JP2009128825A (ja) 液晶表示装置
JP2000221942A (ja) 有機ｅｌ素子駆動装置
JP2003107520A (ja) 液晶表示装置
JP2004013153A (ja) Ｌｃｄパネルのフリッカーを減少させる方法と回路
JP2007034305A (ja) 表示装置
CN1949355B (zh) 用于降低串扰的液晶显示器驱动装置
US8542180B2 (en) Method of driving display panel and display apparatus for performing the same
JP2011170300A (ja) 表示装置制御回路
JP2007034306A (ja) 表示装置の駆動装置及びこれを含む表示装置
US20070018933A1 (en) Driving circuit for display device and display device having the same
WO2018051943A1 (fr) Dispositif d'affichage
JP4664466B2 (ja) 表示装置
JP2002358050A (ja) 液晶駆動装置
JP4363881B2 (ja) 液晶表示装置
CN100474047C (zh) 液晶显示装置
JP4640951B2 (ja) 液晶表示装置
JP2006047848A (ja) ゲート線駆動回路
CN110223621B (zh) 信号调制方法、装置及显示装置
US7952550B2 (en) Liquid crystal driver, liquid crystal display device, and liquid crystal driving method

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17850845

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17850845

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP