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WO2018040563A1 - Novel polycrystalline silicon thin-film zener diode and fabrication method therefor - Google Patents

Novel polycrystalline silicon thin-film zener diode and fabrication method therefor Download PDF

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Publication number
WO2018040563A1
WO2018040563A1 PCT/CN2017/079845 CN2017079845W WO2018040563A1 WO 2018040563 A1 WO2018040563 A1 WO 2018040563A1 CN 2017079845 W CN2017079845 W CN 2017079845W WO 2018040563 A1 WO2018040563 A1 WO 2018040563A1
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region
passivation layer
polysilicon film
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electrode
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Chinese (zh)
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何志
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Foshan Tk Semiconductor Co Ltd
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Foshan Tk Semiconductor Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/20Breakdown diodes, e.g. avalanche diodes
    • H10D8/25Zener diodes 

Definitions

  • the invention relates to the field of manufacturing semiconductor devices, in particular to a novel polysilicon film Zener diode and a manufacturing method thereof.
  • the Zener diode acts as a reference voltage source in a regulated power supply or as a protection diode in an overvoltage protection circuit due to its regulation.
  • the N-type and P-type doped regions are obtained by annealing in a high-temperature furnace in a vacuum environment.
  • conventional high temperature furnace annealed Zener diodes have the following disadvantages:
  • Heating and annealing of high-temperature furnace requires high-temperature furnace annealing in a vacuum environment for a long time.
  • the environment is relatively complicated and time-consuming is long. In terms of production, it is not conducive to the increase of output.
  • the high temperature annealing process can only be performed before metallization of power devices such as GaN, which limits the integration process.
  • the present invention provides a novel polysilicon film Zener diode and a fabrication method thereof, the main feature of which is to activate the N-type dopant and the P-type dopant by laser annealing, thereby improving the activation of the conventional high-temperature furnace.
  • Process problems, short time and high flexibility can effectively solve problems in the background art.
  • a novel polysilicon film Zener diode comprising:
  • a passivation layer B located in an upper surface region of the polysilicon film
  • a P-region electrode on the P-type doped region the electrode being above the P-type doped region and above the portion of the passivation layer B.
  • the material of the substrate is Si material
  • the material of the passivation layer A is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3
  • the polysilicon film is an in-situ doped or intrinsic polysilicon film
  • the logarithm of the PN junction is 1, or any integer greater than one.
  • the material of the N-region electrode is Si, Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN and any combination therebetween; the material of the P-region electrode is Si, Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN and any combination therebetween.
  • the present invention also designs a novel polysilicon film Zener diode manufacturing method, including the following steps:
  • a passivation layer A is grown on the substrate, and a polysilicon film is formed on the passivation layer A;
  • the material of the substrate is Si, diamond or SiC material; the polysilicon film is grown in a high temperature CVD mode; the polysilicon film has a thickness of 10 nm to 1 ⁇ m; and the dopant concentration of the N-doped region 10 17 -10 22 /cm -3 ; the activation process of the dopant of the N-type doping region is laser annealing; the dopant concentration of the P-type doping region is 10 17 -10 22 /cm - 3 .
  • the material of the passivation layer B above the polysilicon film is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc2O3, TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 .
  • the N-type doped region electrode and the P-type doped region electrode are prepared by sputtering or evaporation; the N-type doped region is doped by in-situ doping or implantation; The dopant of the doped region is an impurity such as phosphorus or arsenic; and the dopant of the N-type doping region is doped by in-situ doping or implantation.
  • the method further comprises the step of forming a mesa on the same wafer by etching to isolate the other novel polysilicon film Zener diodes.
  • the activation mode of the dopant of the P-type doping region is laser annealing activation; the P-type doping region is doped by in-situ doping or implant doping.
  • the dopant of the P-type doping region is boron or other impurity source.
  • the annealing time is short, the speed is fast, and the efficiency is high, which is beneficial to the reduction of the device preparation cost
  • the preparation of the Zener diode can be compatible with the preparation process of power devices such as GaN, realize on-chip integration, and has wide application prospects.
  • FIG. 1 is a schematic view showing a structure of a novel polysilicon film Zener diode according to an embodiment of the present invention
  • 2 to 13 are flow charts of a preparation process according to an embodiment (taking implant doping as an example, and the number of PN junctions is greater than 1).
  • a passivation layer A200 is deposited on the substrate 100.
  • the passivation layer A200 is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 .
  • the passivation layer A200 is deposited by sputtering or chemical vapor deposition or the like.
  • the passivation layer A200 has a thickness of 20 nm to 1 ⁇ m;
  • a polysilicon film 300 is deposited on the passivation layer A200 by a process such as CVD. 20 nm-1 ⁇ m of the polysilicon film 300;
  • a sacrificial layer 305 is deposited on the polysilicon thin film layer 300.
  • the sacrificial layer 305 is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 .
  • the passivation layer B400 is deposited by sputtering or chemical vapor deposition or the like. The thickness of the sacrificial layer 305 is 5 nm - 100 nm
  • the implanted impurity source is phosphorus or arsenic, and the implantation dose is E13 to E18/cm3, and the implantation energy is 20 to 400 keV;
  • the sacrificial layer is removed by an etch etching process and activated by a laser annealing process.
  • a portion of the polysilicon film region is etched by photolithography, plasma dry etching or wet etching to form a mesa 304 to achieve isolation between the devices.
  • a P-type implantation sacrificial layer 305 is deposited in the polysilicon film 300 region, and the sacrificial layer 305 is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO. 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 and the like.
  • the sacrificial layer 305 is deposited by sputtering or chemical vapor deposition or the like.
  • the sacrificial layer 305 has a thickness of 20 nm to 1 ⁇ m.
  • the P-type injecting window 306 is implanted by a process such as photolithography, dry etching, or wet etching.
  • N-doping implantation is performed, and the implanted impurity source is boron or gallium, and the implantation dose is E13 to E18/cm3, and the implantation energy is 20 to 400 keV;
  • the sacrificial layer is removed by an etch etching process and activated by a laser annealing process.
  • a passivation layer B400 is deposited.
  • the passivation layer B400 is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 .
  • the passivation layer B400 is deposited by sputtering or chemical vapor deposition or the like.
  • the passivation layer B400 has a thickness of 20 nm to 1 ⁇ m;
  • a pattern partial passivation layer A 401 and a partial passivation layer B 402 are formed on the passivation layer B400 by photolithography, plasma dry etching or wet etching.
  • the N-region electrode 500 and the P-region electrode 600 are separately formed in the partial passivation layer A 401 and the partial passivation layer B 402 by photolithography, electron beam evaporation or sputtering techniques, respectively.
  • the metals of the N-region electrode 500 and the P-region electrode 600 are Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN, and any combination therebetween.
  • the N-region electrode 500 and the P-region electrode 600 form an ohmic contact with the N-type doping region 301 and the P-type doping region 302, respectively.

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Abstract

Disclosed are a polycrystalline silicon thin-film Zener diode and a fabrication method therefor, comprising: a substrate (100), and a passivation layer A (200) and a polycrystalline silicon thin film (300) sequentially grown on the substrate (100), wherein an N-type doped region (301) is formed in a part of the polycrystalline silicon thin film (300), and a P-type doped region (302) is formed in another part of the polycrystalline silicon thin film (300); a passivation layer B (400), located in an upper surface region of the polycrystalline silicon thin film (300); an electrode (500) on the N-type doped region (301), the electrode (500) being located above the N-type doped region (301) and above a portion of the passivation layer (401); an electrode (600) on the P-type doped region (302), the electrode (600) being located above the P-type doped region (302) and above a portion of the passivation layer (402). Activating N-type dopants and P-type dopants by using laser annealing may improve the activation processes in a traditional high-temperature furnace, while featuring a short time and high flexibility.

Description

一种新型多晶硅薄膜齐纳二极管及制作方法Novel polysilicon film Zener diode and manufacturing method thereof 技术领域Technical field

本发明涉及半导体器件的制作领域,具体涉及一种新型多晶硅薄膜齐纳二极管及制作方法。The invention relates to the field of manufacturing semiconductor devices, in particular to a novel polysilicon film Zener diode and a manufacturing method thereof.

背景技术Background technique

齐纳二极管由于其稳压作用,在稳压电源中作为基准电压源或用在过电压保护电路中作为保护二极管。The Zener diode acts as a reference voltage source in a regulated power supply or as a protection diode in an overvoltage protection circuit due to its regulation.

传统的齐纳二极管掺杂后,多采用在真空环境中,高温炉中退火处理得到N型与P型掺杂区。结合器件的制备工艺、生产成本以及与GaN等功率器件等集成问题,传统高温炉退火齐纳二极管存在以下几个缺点:After the conventional Zener diode is doped, the N-type and P-type doped regions are obtained by annealing in a high-temperature furnace in a vacuum environment. In combination with the fabrication process, production cost, and integration of power devices such as GaN, conventional high temperature furnace annealed Zener diodes have the following disadvantages:

(1)高温炉加热退火,晶格损伤修复率低,电激活率低,而且杂质也会因为热扩散而发生改变。(1) Heating and annealing of high temperature furnace, the lattice damage repair rate is low, the electric activation rate is low, and the impurities are also changed due to thermal diffusion.

(2)高温炉加热退火,需要在真空环境高温炉长时间退火,环境相对复杂,耗时也比较长,在生产方面,不利于产量的提高。(2) Heating and annealing of high-temperature furnace requires high-temperature furnace annealing in a vacuum environment for a long time. The environment is relatively complicated and time-consuming is long. In terms of production, it is not conducive to the increase of output.

(3)高温炉处理,容易引起硅片变形,增加后面工艺加工的难度。(3) The treatment of the high temperature furnace easily causes the deformation of the silicon wafer and increases the difficulty of the subsequent processing.

(4)若与GaN等功率器件片内集成实现稳压作用时,高温退火工艺只能在GaN等功率器件金属化前进行,限制了集成工艺。(4) If integrated with GaN and other power devices to achieve voltage regulation, the high temperature annealing process can only be performed before metallization of power devices such as GaN, which limits the integration process.

发明内容Summary of the invention

针对以上问题,本发明提供了一种新型多晶硅薄膜齐纳二极管及制作方法,其主要特征是在利用激光退火对N型掺杂剂与P型掺杂剂进行激活,改善了传统的高温炉激活工艺问题,时间短,灵活性高,可以有效解决背景技术中的问题。In view of the above problems, the present invention provides a novel polysilicon film Zener diode and a fabrication method thereof, the main feature of which is to activate the N-type dopant and the P-type dopant by laser annealing, thereby improving the activation of the conventional high-temperature furnace. Process problems, short time and high flexibility can effectively solve problems in the background art.

为了实现上述目的,本发明采用的技术方案如下:一种新型多晶硅薄膜齐纳二极管,包括:In order to achieve the above object, the technical solution adopted by the present invention is as follows: A novel polysilicon film Zener diode, comprising:

衬底以及在衬底上依次生长的钝化层A和多晶硅薄膜;在多晶硅薄膜部分区形成的N型掺杂区;在多晶硅薄膜另一部分形成的P型掺杂区;a substrate and a passivation layer A and a polysilicon film sequentially grown on the substrate; an N-type doped region formed in a portion of the polysilicon film; and a P-type doped region formed in another portion of the polysilicon film;

钝化层B,该钝化层位于多晶硅薄膜的上表面区域;a passivation layer B, the passivation layer being located in an upper surface region of the polysilicon film;

N型掺杂区上的N区电极,该电极位于N型掺杂区的上方以及部分钝化层A的上方;An N-region electrode on the N-type doped region, the electrode being above the N-type doped region and above the portion of the passivation layer A;

P型掺杂区上的P区电极,该电极位于P型掺杂区的上方以及部分钝化层B的上方。 A P-region electrode on the P-type doped region, the electrode being above the P-type doped region and above the portion of the passivation layer B.

优选的,所述衬底的材料为Si材料;所述钝化层A的材料为SiO2、Si3N4、AlN、Al2O3、MgO、Sc2O3、TiO2、HfO2、BCB、ZrO2、Ta2O5和La2O3;所述多晶硅薄膜为原位掺杂或者本征多晶硅薄膜;PN结的对数为1,或者大1的任何整数。Preferably, the material of the substrate is Si material; the material of the passivation layer A is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 ; the polysilicon film is an in-situ doped or intrinsic polysilicon film; the logarithm of the PN junction is 1, or any integer greater than one.

优选的,所述N区电极的材料为Si、Ti、Al、Ni、Mo、Pt、Pd、Au、W、TiW、TiN及它们之间的任意组合;所述P区电极的材料为Si、Ti、Al、Ni、Mo、Pt、Pd、Au、W、TiW、TiN及它们之间的任意组合。Preferably, the material of the N-region electrode is Si, Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN and any combination therebetween; the material of the P-region electrode is Si, Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN and any combination therebetween.

另外本发明还设计了一种新型多晶硅薄膜齐纳二极管的制作方法,包括以下步骤:In addition, the present invention also designs a novel polysilicon film Zener diode manufacturing method, including the following steps:

S1、在衬底上生长钝化层A,在钝化层A上形成多晶硅薄膜;S1, a passivation layer A is grown on the substrate, and a polysilicon film is formed on the passivation layer A;

S2、在多晶硅薄膜的部分区形成N型掺杂区;S2, forming an N-type doped region in a partial region of the polysilicon film;

S3、在多晶硅薄膜区的另一部分区域形成P型掺杂区;S3, forming a P-type doped region in another portion of the polysilicon film region;

S4、在多晶硅薄膜区上方形成钝化层B;S4, forming a passivation layer B over the polysilicon film region;

S5、在N型掺杂区形成N区电极;S5, forming an N-region electrode in the N-type doping region;

S6、在P型掺杂区形成P区电极。S6, forming a P-region electrode in the P-type doping region.

优选的,所述衬底的材料为Si、金刚石或SiC材料;所述多晶硅薄膜生长方式为高温CVD方式;所述多晶硅薄膜厚度为10nm~1μm;所述N型掺杂区的掺杂剂浓度为1017-1022/cm-3;所述N型掺杂区的掺杂剂的激活工艺为激光退火;所述P型掺杂区的掺杂剂浓度为1017-1022/cm-3Preferably, the material of the substrate is Si, diamond or SiC material; the polysilicon film is grown in a high temperature CVD mode; the polysilicon film has a thickness of 10 nm to 1 μm; and the dopant concentration of the N-doped region 10 17 -10 22 /cm -3 ; the activation process of the dopant of the N-type doping region is laser annealing; the dopant concentration of the P-type doping region is 10 17 -10 22 /cm - 3 .

优选的,所述多晶硅薄膜上方钝化层B的材料为的材料为SiO2、Si3N4、AlN、Al2O3、MgO、Sc2O3、TiO2、HfO2、BCB、ZrO2、Ta2O5和La2O3Preferably, the material of the passivation layer B above the polysilicon film is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc2O3, TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 .

优选的,所述N型掺杂区电极、P型掺杂区电极的制备方法为溅射或蒸发;所述N型掺杂区通过原位掺杂或者注入的方式进行掺杂;所述N型掺杂区的掺杂剂为磷、砷等杂质;所述N型掺杂区的掺杂剂通过原位掺杂或者注入的方式进行掺杂。Preferably, the N-type doped region electrode and the P-type doped region electrode are prepared by sputtering or evaporation; the N-type doped region is doped by in-situ doping or implantation; The dopant of the doped region is an impurity such as phosphorus or arsenic; and the dopant of the N-type doping region is doped by in-situ doping or implantation.

优选的,还包括在同一晶片上通过刻蚀形成台面与其他新型多晶硅薄膜齐纳二极管隔离的步骤。Preferably, the method further comprises the step of forming a mesa on the same wafer by etching to isolate the other novel polysilicon film Zener diodes.

优选的,所述P型掺杂区的掺杂剂的激活方式为激光退火激活;所述P型掺杂区通过原位掺杂或者注入掺杂的方式进行掺杂。Preferably, the activation mode of the dopant of the P-type doping region is laser annealing activation; the P-type doping region is doped by in-situ doping or implant doping.

优选的,所述P型掺杂区的掺杂剂为硼或者其他杂质源。Preferably, the dopant of the P-type doping region is boron or other impurity source.

本发明的有益效果:The beneficial effects of the invention:

(1)利用激光退火工艺,改善传统工艺中损伤修复率与电激活率;(1) Using the laser annealing process to improve the damage repair rate and the electrical activation rate in the conventional process;

(2)利用激光退火工艺,退火时间短,速度快,效率高,有利于器件制备成本的降低; (2) Using the laser annealing process, the annealing time is short, the speed is fast, and the efficiency is high, which is beneficial to the reduction of the device preparation cost;

(3)采用激光退火工艺,在退火过程中无需真空环境,可以在大气中进行,条件简化;(3) The laser annealing process is adopted, no vacuum environment is needed in the annealing process, and it can be carried out in the atmosphere, and the conditions are simplified;

(4)省略高温炉处理,避免硅片变形,同时可以使该齐纳二极管的制备与GaN等功率器件的制备工艺兼容,实现片内集成,具有广泛的应用前景。(4) Omit the high temperature furnace treatment to avoid deformation of the silicon wafer, and at the same time, the preparation of the Zener diode can be compatible with the preparation process of power devices such as GaN, realize on-chip integration, and has wide application prospects.

附图说明DRAWINGS

为使本发明的目的、内容、优点更加清楚明白,下面将参照附图结合优选实施例进行详细说明,其中:In order to make the objects, contents and advantages of the present invention more comprehensible, the detailed description will

图1为本发明施例的新型多晶硅薄膜齐纳二极管结构的示意图;1 is a schematic view showing a structure of a novel polysilicon film Zener diode according to an embodiment of the present invention;

图2-图13为依据实施方案制备工艺流程图(以注入掺杂为例,且PN结对数大于1)。2 to 13 are flow charts of a preparation process according to an embodiment (taking implant doping as an example, and the number of PN junctions is greater than 1).

图中的标号为:The labels in the figure are:

100-衬底;200-钝化层A;300-多晶硅薄膜;400-钝化层B;100-substrate; 200-passivation layer A; 300-polysilicon film; 400-passivation layer B;

500-N区电极;600-P区电极;301-N型掺杂区;302-P型掺杂区;500-N zone electrode; 600-P zone electrode; 301-N type doped zone; 302-P type doped zone;

401-部分钝化层A;402-部分钝化层B。401-partial passivation layer A; 402-partial passivation layer B.

具体实施方式detailed description

需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本发明。It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments.

为了使本发明的目的、技术方案及优点更加清楚明白,以下结合实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。In order to make the objects, technical solutions and advantages of the present invention more comprehensible, the present invention will be further described in detail below with reference to the embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

实施方案:implementation plan:

如图2所示,在衬底100上淀积钝化层A200。钝化层A200为SiO2、Si3N4、AlN、Al2O3、MgO、Sc2O3、TiO2、HfO2、BCB、ZrO2、Ta2O5和La2O3。淀积钝化层A200的方式为溅射或者是化学气相沉积等。钝化层A200的厚度为20nm-1μm;As shown in FIG. 2, a passivation layer A200 is deposited on the substrate 100. The passivation layer A200 is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 . The passivation layer A200 is deposited by sputtering or chemical vapor deposition or the like. The passivation layer A200 has a thickness of 20 nm to 1 μm;

如图2所示,在钝化层A200上淀积多晶硅薄膜300,淀积的方式为CVD等工艺。多晶硅薄膜300的20nm-1μm;As shown in FIG. 2, a polysilicon film 300 is deposited on the passivation layer A200 by a process such as CVD. 20 nm-1 μm of the polysilicon film 300;

如图3所示,在多晶硅薄膜层300上淀积牺牲层305,牺牲层305为SiO2、Si3N4、AlN、Al2O3、MgO、Sc2O3、TiO2、HfO2、BCB、ZrO2、Ta2O5和La2O3。淀积钝化层B400的方式为溅射或者是化学气相沉积等。牺牲层305的厚度为5nm-100nmAs shown in FIG. 3, a sacrificial layer 305 is deposited on the polysilicon thin film layer 300. The sacrificial layer 305 is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 . The passivation layer B400 is deposited by sputtering or chemical vapor deposition or the like. The thickness of the sacrificial layer 305 is 5 nm - 100 nm

如图4所示,进行N掺杂注入,注入的杂质源为磷或者砷,注入的剂量为E13~E18/cm3,注入能量为20~400千电子伏; As shown in FIG. 4, N-doping is performed, and the implanted impurity source is phosphorus or arsenic, and the implantation dose is E13 to E18/cm3, and the implantation energy is 20 to 400 keV;

如图5所示,利用刻蚀腐蚀工艺去除牺牲层,并利用激光退火工艺进行激活。As shown in FIG. 5, the sacrificial layer is removed by an etch etching process and activated by a laser annealing process.

如图6所示,利用光刻、等离子体干法刻蚀技术或者湿法腐蚀技术,刻蚀部分多晶硅薄膜区,形成台面304,实现器件之间的隔离。As shown in FIG. 6, a portion of the polysilicon film region is etched by photolithography, plasma dry etching or wet etching to form a mesa 304 to achieve isolation between the devices.

如图7所示,在多晶硅薄膜300区淀积P型注入牺牲层305,牺牲层305为SiO2、Si3N4、AlN、Al2O3、MgO、Sc2O3、TiO2、HfO2、BCB、ZrO2、Ta2O5和La2O3等。淀积牺牲层305的方式为溅射或者是化学气相沉积等。牺牲层305的厚度为20nm-1μm。As shown in FIG. 7, a P-type implantation sacrificial layer 305 is deposited in the polysilicon film 300 region, and the sacrificial layer 305 is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO. 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 and the like. The sacrificial layer 305 is deposited by sputtering or chemical vapor deposition or the like. The sacrificial layer 305 has a thickness of 20 nm to 1 μm.

如图8所示,利用光刻、干法刻蚀或者湿发腐蚀等工艺,为P型注入开窗口306。As shown in FIG. 8, the P-type injecting window 306 is implanted by a process such as photolithography, dry etching, or wet etching.

如图9所示,进行N掺杂注入,注入的杂质源为硼或者镓等,注入的剂量为E13~E18/cm3,注入能量为20~400kev;As shown in FIG. 9, N-doping implantation is performed, and the implanted impurity source is boron or gallium, and the implantation dose is E13 to E18/cm3, and the implantation energy is 20 to 400 keV;

如图10所示,利用刻蚀腐蚀工艺去除牺牲层,并利用激光退火工艺进行激活。As shown in FIG. 10, the sacrificial layer is removed by an etch etching process and activated by a laser annealing process.

如图11所示,淀积钝化层B400。钝化层B400为SiO2、Si3N4、AlN、Al2O3、MgO、Sc2O3、TiO2、HfO2、BCB、ZrO2、Ta2O5和La2O3。淀积钝化层B400的方式为溅射或者是化学气相沉积等。钝化层B400的厚度为20nm-1μm;As shown in FIG. 11, a passivation layer B400 is deposited. The passivation layer B400 is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 . The passivation layer B400 is deposited by sputtering or chemical vapor deposition or the like. The passivation layer B400 has a thickness of 20 nm to 1 μm;

如图12所示,利用光刻,等离子体干法刻蚀技术或者湿法腐蚀技术,在钝化层B400上制备图形部分钝化层A 401与部分钝化层B 402。As shown in FIG. 12, a pattern partial passivation layer A 401 and a partial passivation layer B 402 are formed on the passivation layer B400 by photolithography, plasma dry etching or wet etching.

如图13所示,利用光刻,电子束蒸发或者溅射技术,在部分钝化层A 401与部分钝化层B 402中分别制备N区电极500和P区电极600。N区电极500和P区电极600的金属为Ti、Al、Ni、Mo、Pt、Pd、Au、W、TiW、TiN及它们之间的任意组合。N区电极500和P区电极600分别与N型掺杂区301与P型掺杂区302形成欧姆接触。As shown in FIG. 13, the N-region electrode 500 and the P-region electrode 600 are separately formed in the partial passivation layer A 401 and the partial passivation layer B 402 by photolithography, electron beam evaporation or sputtering techniques, respectively. The metals of the N-region electrode 500 and the P-region electrode 600 are Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN, and any combination therebetween. The N-region electrode 500 and the P-region electrode 600 form an ohmic contact with the N-type doping region 301 and the P-type doping region 302, respectively.

以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。 The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. Within the scope.

Claims (10)

一种多晶硅薄膜齐纳二极管,其特征在于,包括:A polysilicon film Zener diode, comprising: 衬底(100)以及在衬底(100)上依次生长的钝化层A(200)和多晶硅薄膜(300);在多晶硅薄膜部分区形成的N型掺杂区(301);在多晶硅薄膜另一部分形成的P型掺杂区(302);a substrate (100) and a passivation layer A (200) and a polysilicon film (300) sequentially grown on the substrate (100); an N-type doped region (301) formed in a partial region of the polysilicon film; a portion of the formed P-type doped region (302); 钝化层B(400),该钝化层位于多晶硅薄膜(300)的上表面区域;a passivation layer B (400), the passivation layer being located in an upper surface region of the polysilicon film (300); N型掺杂区(301)上的N区电极(500),该电极位于N型掺杂区(301)的上方以及部分钝化层A(401)的上方;An N-region electrode (500) on the N-type doped region (301), the electrode being above the N-type doped region (301) and above the portion of the passivation layer A (401); P型掺杂区(302)上的P区电极(600),该电极位于P型掺杂区(302)的上方以及部分钝化层B(402)的上方。A P-region electrode (600) on the P-type doped region (302) is above the P-type doped region (302) and above the portion of the passivation layer B (402). 根据权利要求1所述的一种多晶硅薄膜齐纳二极管,其特征在于,所述衬底(100)的材料为Si材料;所述钝化层A(200)的材料为SiO2、Si3N4、AlN、Al2O3、MgO、Sc2O3、TiO2、HfO2、BCB、ZrO2、Ta2O5和La2O3;所述多晶硅薄膜(300)为原位掺杂或者本征多晶硅薄膜;PN结的对数为1,或者大1的任何整数。The polysilicon thin film Zener diode according to claim 1, wherein the material of the substrate (100) is Si material; the material of the passivation layer A (200) is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 ; the polysilicon film (300) is doped in situ or Intrinsic polysilicon film; the logarithm of the PN junction is 1, or any integer greater than one. 根据权利要求1所述的一种多晶硅薄膜齐纳二极管,其特征在于,所述N区电极(500)的材料为Si、Ti、Al、Ni、Mo、Pt、Pd、Au、W、TiW、TiN及它们之间的任意组合;所述P区电极(600)的材料为Si、Ti、Al、Ni、Mo、Pt、Pd、Au、W、TiW、TiN及它们之间的任意组合。The polysilicon thin film Zener diode according to claim 1, wherein the material of the N-region electrode (500) is Si, Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN and any combination therebetween; the material of the P-region electrode (600) is Si, Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN and any combination therebetween. 一种多晶硅薄膜齐纳二极管的制作方法,其特征在于,包括以下步骤:A method for fabricating a polysilicon film Zener diode, comprising the steps of: S1、在衬底(100)上生长钝化层A(200),在钝化层A(200)上形成多晶硅薄膜(300);S1, a passivation layer A (200) is grown on the substrate (100), and a polysilicon film (300) is formed on the passivation layer A (200); S2、在多晶硅薄膜(300)的部分区形成N型掺杂区(301);S2, forming an N-type doped region (301) in a partial region of the polysilicon film (300); S3、在多晶硅薄膜区(300)的另一部分区域形成P型掺杂区(302);S3, forming a P-type doped region (302) in another portion of the polysilicon film region (300); S4、在多晶硅薄膜区(300)上方形成钝化层B(400);S4, forming a passivation layer B (400) above the polysilicon film region (300); S5、在N型掺杂区(301)形成N区电极(500);S5, forming an N-region electrode (500) in the N-type doping region (301); S6、在P型掺杂区(302)形成P区电极(600)。S6, forming a P-region electrode (600) in the P-type doping region (302). 根据权利要求4所述的制作方法,其特征在于,所述衬底(100)的材料为Si、金刚石或SiC材料;所述多晶硅薄膜(300)生长方式为高温CVD方式;所述多晶硅薄(300)膜厚度为10nm~1μm;所述N型掺杂区(301)的掺杂剂浓度为1017-1022/cm-3;所述N型掺杂区(301)的掺杂剂的激活工艺为激光退火;所述P型掺杂区(302)的掺杂剂浓度为1017-1022/cm-3The manufacturing method according to claim 4, wherein the material of the substrate (100) is Si, diamond or SiC material; the polysilicon film (300) is grown by a high temperature CVD method; 300) a film thickness of 10 nm to 1 μm; a dopant concentration of the N-type doping region (301) of 10 17 -10 22 /cm -3 ; a dopant of the N-type doping region (301) The activation process is laser annealing; the dopant concentration of the P-type doping region (302) is 10 17 -10 22 /cm -3 . 根据权利要求4所述的制作方法,其特征在于,所述多晶硅薄膜上方钝化层B(400)的材料为的材料为SiO2、Si3N4、AlN、Al2O3、MgO、Sc2O3、TiO2、HfO2、BCB、ZrO2、Ta2O5和La2O3The manufacturing method according to claim 4, wherein the material of the passivation layer B (400) above the polysilicon film is SiO 2 , Si 3 N 4 , AlN, Al 2 O 3 , MgO, Sc 2 O 3 , TiO 2 , HfO 2 , BCB, ZrO 2 , Ta 2 O 5 and La 2 O 3 . 根据权利要求4所述的制作方法,其特征在于,所述N型掺杂区电极(601)、P型掺杂区电极(602)的制备方法为溅射或蒸发;所述N型掺杂区(301)通过原位掺杂或者注入的方式进行掺杂;所述N型掺杂区(301)的掺杂剂为磷、砷等杂质;所述N型掺杂区(301)的掺杂剂通过原位掺杂或者注入的方式进行掺杂。The manufacturing method according to claim 4, wherein the N-type doping region electrode (601) and the P-type doping region electrode (602) are prepared by sputtering or evaporation; the N-type doping The region (301) is doped by in-situ doping or implantation; the dopant of the N-type doping region (301) is an impurity such as phosphorus or arsenic; and the doping of the N-type doping region (301) The dopant is doped by in-situ doping or implantation. 根据权利要求4所述的制作方法,其特征在于,还包括在同一晶片上通过刻蚀形成台面(304)与其他新型多晶硅薄膜齐纳二极管隔离的步骤。The fabricating method according to claim 4, further comprising the step of isolating the mesa (304) on the same wafer from the other novel polysilicon thin film Zener diodes by etching. 根据权利要求4所述的制作方法,其特征在于,所述P型掺杂区(302)的掺杂剂的激活方式为激光退火激活;所述P型掺杂区(302)通过原位掺杂或者注入掺杂的方式进行掺杂。The fabrication method according to claim 4, wherein the activation mode of the dopant of the P-type doping region (302) is laser annealing activation; the P-type doping region (302) is doped by in-situ Doping is carried out by means of impurities or implant doping. 根据权利要求4所述的制作方法,其特征在于,所述P型掺杂区(302)的掺杂剂为硼或者其他杂质源。 The method according to claim 4, wherein the dopant of the P-type doping region (302) is boron or other impurity source.
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