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WO2017221519A1 - Élément semi-conducteur au nitrure, substrat semi-conducteur au nitrure, procédé de fabrication d'un élément semi-conducteur au nitrure et procédé de fabrication d'un substrat semi-conducteur au nitrure - Google Patents

Élément semi-conducteur au nitrure, substrat semi-conducteur au nitrure, procédé de fabrication d'un élément semi-conducteur au nitrure et procédé de fabrication d'un substrat semi-conducteur au nitrure Download PDF

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WO2017221519A1
WO2017221519A1 PCT/JP2017/014762 JP2017014762W WO2017221519A1 WO 2017221519 A1 WO2017221519 A1 WO 2017221519A1 JP 2017014762 W JP2017014762 W JP 2017014762W WO 2017221519 A1 WO2017221519 A1 WO 2017221519A1
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layer
nitride semiconductor
plane
superlattice
semiconductor substrate
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Japanese (ja)
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中山　雄介
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/3211—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures characterised by special cladding layers, e.g. details on band-discontinuities
    • H01S5/3216—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures characterised by special cladding layers, e.g. details on band-discontinuities quantum well or superlattice cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/34333—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/815—Bodies having stress relaxation structures, e.g. buffer layers
    • H10P14/24—
    • H10P14/2908—
    • H10P14/2926—
    • H10P14/3216—
    • H10P14/3416—

Definitions

  • the present disclosure relates to a nitride semiconductor device, a nitride semiconductor substrate, a method for manufacturing a nitride semiconductor device, and a method for manufacturing a nitride semiconductor substrate.
  • a nitride semiconductor substrate having a semipolar plane or nonpolar plane inclined by 20 ° or more in the a-axis direction from the c-plane as a main plane of crystal growth misfit dislocations of the substrate are the starting points. Pits occurred, causing current leakage and non-light emission due to the pits. Accordingly, it is possible to provide a nitride semiconductor device, a nitride semiconductor substrate, a method for manufacturing a nitride semiconductor device, and a method for manufacturing a nitride semiconductor substrate capable of suppressing the occurrence of current leakage and non-luminescence due to pits. Is desirable.
  • a first nitride semiconductor device includes a nitride semiconductor substrate having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane, and the main surface And a superlattice layer formed as a crystal growth surface.
  • composition ratio of the Al x1 In y1 Ga z1 N layer and the Al x2 In y2 Ga z2 N layer satisfies at least one of the expressions x1 ⁇ x2 and y1 ⁇ y2.
  • a nitride semiconductor substrate includes a nitride semiconductor substrate having a principal surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane, and the principal surface is crystallized. And a superlattice layer formed as a growth surface.
  • composition ratio of the Al x1 In y1 Ga z1 N layer and the Al x2 In y2 Ga z2 N layer satisfies at least one of the expressions x1 ⁇ x2 and y1 ⁇ y2.
  • a nitride semiconductor having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane The superlattice layer is formed on the main surface of the substrate. Thereby, generation
  • a first nitride semiconductor substrate manufacturing method includes a nitride semiconductor substrate having a principal surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane.
  • the method includes a step of forming a superlattice layer using the main surface as a crystal growth surface.
  • composition ratio of the Al x1 In y1 Ga z1 N layer and the Al x2 In y2 Ga z2 N layer satisfies at least one of the expressions x1 ⁇ x2 and y1 ⁇ y2.
  • a nitride semiconductor substrate having a principal surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane The superlattice layer is formed on the main surface.
  • a second nitride semiconductor device includes a nitride semiconductor layer having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane, and the main And a junction structure layer formed with the surface as a crystal growth surface.
  • the junction structure layer includes a lower cladding layer, an active layer, and an upper cladding layer in this order from the nitride semiconductor layer side.
  • the main surface of the nitride semiconductor layer having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane.
  • the junction structure layer is formed. Thereby, generation
  • a method for manufacturing a first nitride semiconductor device includes the following four steps.
  • (A1) A superlattice layer is formed on a nitride semiconductor substrate having a principal surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane with the principal surface as a crystal growth surface.
  • the composition ratio of the Al x1 In y1 Gaz1 N layer and the Al x2 In y2 Gaz2 N layer satisfies at least one of the expressions x1 ⁇ x2 and y1 ⁇ y2.
  • the junction structure layer includes a lower cladding layer, an active layer, and an upper cladding layer in this order from the nitride semiconductor substrate side.
  • a nitride semiconductor layer having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane is provided.
  • the superlattice layer is formed on the main surface, and the junction structure layer is formed on the superlattice layer via a bulk layer.
  • a second method for manufacturing a nitride semiconductor device is provided on a nitride semiconductor substrate having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane.
  • the method includes a step of forming a junction structure layer using the main surface as a crystal growth surface.
  • the junction structure layer includes a lower cladding layer, an active layer, and an upper cladding layer in this order from the nitride semiconductor substrate side.
  • a nitride semiconductor substrate having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane is provided.
  • the junction structure layer is formed on the main surface.
  • the first nitride semiconductor device, the nitride semiconductor substrate, and the first nitride semiconductor substrate manufacturing method according to an embodiment of the present disclosure ⁇ ° or more (20 ° ⁇ 20 ° in the a-axis direction from the c-plane. ( ⁇ ⁇ 90 °) Since the superlattice layer is formed on the main surface of the nitride semiconductor substrate having the inclined main surface, current leakage and non-light emission caused by pits can be suppressed. Can do. In addition, the effect of this indication is not necessarily limited to the effect described here, Any effect described in this specification may be sufficient.
  • the main component of the nitride semiconductor layer having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane. Since the bonding structure layer is formed on the surface, it is possible to suppress the occurrence of current leakage and non-luminescence due to the pits. In addition, the effect of this indication is not necessarily limited to the effect described here, Any effect described in this specification may be sufficient.
  • a nitride semiconductor having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane.
  • the superlattice layer is formed on the main surface of the layer, and the junction structure layer is formed on the superlattice layer via a bulk layer. Occurrence can be suppressed.
  • the effect of this indication is not necessarily limited to the effect described here, Any effect described in this specification may be sufficient.
  • a nitride semiconductor having a principal surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane Since the junction structure layer is formed on the main surface of the substrate, it is possible to suppress the occurrence of current leakage and non-luminescence due to pits.
  • the effect of this indication is not necessarily limited to the effect described here, Any effect described in this specification may be sufficient.
  • FIG. 1 illustrates a cross-sectional configuration example of a semiconductor light emitting element 1 according to the present embodiment.
  • the semiconductor light emitting device 1 can be suitably applied as a blue to green light source.
  • the semiconductor light emitting element 1 includes, for example, a substrate 10, a superlattice layer 20, and a junction structure layer 30.
  • the superlattice layer 20 is formed using the main surface of the substrate 10 as a crystal growth surface.
  • the junction structure layer 30 is formed by using the surface of the superlattice layer 20 as a crystal growth surface.
  • the superlattice layer 20 and the junction structure layer 30 are formed by an epitaxial crystal growth method such as MOCVD (Metal Organic Chemical Vapor Deposition).
  • the substrate 10 is a nitride semiconductor substrate and is made of, for example, n-type GaN.
  • the nitride semiconductor substrate used for the substrate 10 has a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane.
  • the crystal plane of the main surface is, for example, the (11-20) plane, the (11-22) plane, or the (11-24) plane.
  • the substrate 10 is doped with an n-type impurity such as silicon (Si).
  • the “main surface of the substrate 10” refers to a crystal plane inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane.
  • the junction structure layer 30 has, for example, a double hetero junction structure.
  • the double heterojunction structure refers to a structure in which a heterogeneous semiconductor (an active layer 34 described later) with a narrow band gap is sandwiched between pn semiconductors (a lower cladding layer 32 and an upper cladding layer 36 described later) of the same material. Yes.
  • the junction structure layer 30 includes, for example, a base layer 31, a lower cladding layer 32, a lower guide layer 33, an active layer 34, an upper guide layer 35, an upper cladding layer 36, and a contact layer 37.
  • the junction structure layer 30 includes a base layer 31, a lower clad layer 32, a lower guide layer 33, an active layer 34, an upper guide layer 35, an upper clad layer 36, and a contact layer 37 in this order from the superlattice layer 20 side. Has been.
  • the underlayer 31 is made of n-type GaN, for example.
  • the lower cladding layer 32 is made of, for example, n-type AlGaN.
  • the lower guide layer 33 is made of, for example, n-type InGaN.
  • the underlayer 31, the lower cladding layer 32, and the lower guide layer 33 are doped with an n-type impurity such as silicon (Si).
  • the active layer 34 has, for example, a multiple quantum well (MQW) structure in which well layers made of InGaN and barrier layers made of AlGaN are alternately and repeatedly stacked.
  • the active layer 34 may be composed of a single layer.
  • the upper guide layer 35 is made of, for example, undoped InGaN.
  • the upper cladding layer 36 is made of, for example, p-type AlGaN.
  • the contact layer 37 is made of, for example, p-type GaN.
  • the upper cladding layer 36 and the contact layer 37 are doped with a p-type impurity such as magnesium (Mg).
  • the semiconductor light emitting device 1 may further include a lower electrode that is in contact with the substrate 10 or the lower cladding layer 32 and is electrically connected to the lower cladding layer 32.
  • the semiconductor light emitting device 1 may further include an upper electrode that is in contact with the contact layer 37 and is electrically connected to the upper cladding layer 36.
  • the bonding structure layer 30 may have a layer other than the above. In the bonding structure layer 30, the lower guide layer 33 and the upper guide layer 35 may be omitted, and the base layer 31 may be omitted. Further, a stripe-shaped ridge portion or a columnar mesa portion may be provided for the bonding structure layer 30.
  • FIG. 2 illustrates a cross-sectional configuration example of the superlattice layer 20.
  • the superlattice layer 20 is formed by using the main surface of the substrate 10 as a crystal growth surface. Therefore, no layer such as an underlayer is provided between the main surface of the substrate 10 and the superlattice layer 20.
  • the composition ratio of the Al x1 In y1 Gaz1 N layer 20A and the Al x2 In y2 Gaz2 N layer 20B satisfies at least one of the expressions x1 ⁇ x2 and y1 ⁇ y2.
  • the degree of lattice mismatch between the Al x1 In y1 Ga z1 N layer 20A and the Al x2 In y2 Ga z2 N layer 20B is 0.00048 or more.
  • the Al x1 In y1 Ga z1 N layer 20A is composed of Al 0.08 Ga 0.02 N with a thickness of 2.0 nm
  • the Al x2 In y2 Ga z2 N layer 20B is composed of GaN with a thickness of 2.0 nm.
  • the film thicknesses of the Al x1 In y1 Ga z1 N layer 20A and the Al x2 In y2 Ga z2 N layer 20B are 1 nm or more and 10 nm or less, respectively. It is preferable.
  • the number of stacked layers in the superlattice layer 20 is preferably 10 pairs or more, and more preferably 100 pairs or more.
  • FIG. 3A shows an example of the manufacturing process of the semiconductor light emitting device 1.
  • FIG. 3B shows an example of the manufacturing process following FIG. 3A.
  • nitride semiconductors are collectively formed on a substrate 10 made of, for example, GaN by an epitaxial crystal growth method such as an MOCVD method.
  • a substrate 10 made of, for example, GaN by an epitaxial crystal growth method such as an MOCVD method.
  • MOCVD method for example, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn), ammonia (NH 3 ) or the like is used as a compound semiconductor material, and monosilane (SiH) is used as a source material for donor impurities. 4 ) and the acceptor impurity material is, for example, biscyclopentadienylmagnesium (Cp 2 Mg) is used.
  • TMAl trimethylaluminum
  • TMGa trimethylgallium
  • TMIn trimethylindium
  • NH 3 ammonia
  • SiH monosilane
  • the acceptor impurity material is, for example, biscyclopenta
  • a substrate 10 having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane is prepared.
  • the superlattice layer 20 is formed on the substrate 10 with the main surface of the substrate 10 as a crystal growth surface.
  • the junction structure layer 30 is formed using the surface of the superlattice layer 20 as a crystal growth surface.
  • an upper electrode and a lower electrode are formed as necessary. In this way, the semiconductor light emitting element 1 is manufactured.
  • the laser beam having the oscillation wavelength ⁇ is emitted to the outside from the end surface having a relatively low reflectance.
  • the light generated in the active layer 34 Reflected by the layer 32 and the upper cladding layer 36 laser oscillation occurs at a predetermined oscillation wavelength ⁇ .
  • laser light having an oscillation wavelength ⁇ is emitted from the upper surface of the bonding structure layer 30 to the outside.
  • the junction structure layer 30 does not have a resonator structure and spontaneous emission light is output
  • light having an emission wavelength ⁇ generated in the active layer 34 is externally transmitted from the upper surface of the junction structure layer 30. Is emitted.
  • superlattice layer 20 is formed on the main surface of substrate 10 having the main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from c-plane.
  • strain stress is generated by the Al x1 In y1 Ga z1 N layer 20A and the Al x2 In y2 Ga z2 N layer 20B.
  • This strain stress causes misfit dislocations of the substrate to the superlattice layer 20 as a starting point. It is possible to suppress the occurrence of pits. As a result, it is possible to suppress the generation of pits even in the bonding structure layer 30 formed on the superlattice layer 20. Therefore, it is possible to suppress the occurrence of current leakage and non-light emission due to the pits.
  • the lattice mismatch between the Al x1 In y1 Ga z1 N layer 20A and the Al x2 In y2 Ga z2 N layer 20B has a 0.00048 or more.
  • the strain stress generated in the superlattice layer 20 is small. Since it is difficult to suppress generation of pit starting points between the main surface of the substrate 10 and the superlattice layer 20, pits may be formed while the superlattice layer 20 is grown. High nature.
  • the junction structure layer 30 when the junction structure layer 30 is formed with the (11-20) plane, the (11-22) plane, or the (11-24) plane as the crystal growth plane, the m plane (1-100) is used as the cleavage plane.
  • the bonding structure layer 30 is formed directly on the (11-20) plane, the (11-22) plane, or the (11-24) plane of the substrate 10, pits are likely to be generated in the bonding structure layer 30. .
  • the superlattice layer 20 is formed on the (11-20) plane, the (11-22) plane, or the (11-24) plane of the substrate 10 and then the junction structure layer 30 is formed. Therefore, the occurrence of pits in the bonding structure layer 30 can be suppressed.
  • a light-emitting element having an m-plane (1-100) as a cleavage plane can be put into practical use.
  • the junction structure layer 30 including the lower cladding layer 32, the active layer 34, and the upper cladding layer 36 in this order is formed on the main surface of the substrate 10 via the superlattice layer 20. Yes.
  • a light-emitting element having an m-plane (1-100) as a cleavage plane can be put into practical use.
  • FIG. 4 illustrates a cross-sectional configuration example of the semiconductor light emitting element 2 according to the present embodiment.
  • the semiconductor light emitting element 2 can be suitably applied as a blue to green light source.
  • the semiconductor light emitting element 2 includes, for example, a substrate 10, a superlattice layer 20, and a junction structure layer 40.
  • the superlattice layer 20 is formed using the main surface of the substrate 10 as a crystal growth surface.
  • the junction structure layer 40 is formed using the surface of the superlattice layer 20 as a crystal growth surface.
  • the superlattice layer 20 and the junction structure layer 40 are formed by an epitaxial crystal growth method such as an MOCVD method, for example.
  • the junction structure layer 40 has, for example, one heterojunction structure in a double heterojunction.
  • the bonding structure layer 40 has a configuration in which the base layer 31 and the lower cladding layer 32 are omitted from the bonding structure layer 30 of the above embodiment.
  • the superlattice layer 20 also serves as the lower cladding layer 32 of the above embodiment. Accordingly, the superlattice layer 20 and the junction structure layer 40 constitute a double heterojunction.
  • the superlattice layer 20 is formed by a method similar to the method described in the first embodiment.
  • the superlattice layer with respect to the main surface of the substrate 10 having the main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane. 20 is formed.
  • strain stress is generated by the Al x1 In y1 Ga z1 N layer 20A and the Al x2 In y2 Ga z2 N layer 20B.
  • This strain stress causes misfit dislocations of the substrate to the superlattice layer 20 as a starting point. It is possible to suppress the occurrence of pits. As a result, the generation of pits can be suppressed even in the bonding structure layer 40 formed on the superlattice layer 20. Therefore, it is possible to suppress the occurrence of current leakage and non-light emission due to the pits.
  • the lattice mismatch degree between the Al x1 In y1 Ga z1 N layer 20A and the Al x2 In y2 Ga z2 N layer 20B is 0.00048 or more, as in the above embodiment.
  • the junction structure layer 30 of the above embodiment is formed using the (11-20) plane, the (11-22) plane, or the (11-24) plane as the crystal growth plane, the m plane ( 1-100) can be used.
  • the junction structure layer 30 is formed directly on the (11-20) plane, the (11-22) plane, or the (11-24) plane, pits are easily generated in the junction structure layer 30.
  • the superlattice layer 20 is formed on the (11-20) plane, the (11-22) plane, or the (11-24) plane, the junction structure layer 40 is formed, and the superlattice layer is formed.
  • the layer 20 is also used as the lower clad layer 32 of the above embodiment, it is possible to suppress the generation of pits in the superlattice layer 20 and the junction structure layer 40.
  • a light-emitting element having an m-plane (1-100) as a cleavage plane can be put into practical use.
  • FIG. 5 illustrates a cross-sectional configuration example of the semiconductor substrate 3 according to the present embodiment.
  • the semiconductor substrate 3 can be suitably applied as a substrate (so-called seed substrate) for crystal growth of the bonding structure layer 30 or the like that can function as a blue to green light source.
  • the semiconductor substrate 3 includes, for example, a base material 38, a superlattice layer 20, and a bulk layer 39.
  • the superlattice layer 20 is formed by using the main surface of the substrate 38 as a crystal growth surface.
  • the bulk layer 39 is formed using the surface of the superlattice layer 20 as a crystal growth surface.
  • the base material 38 is a nitride semiconductor wafer and is made of, for example, n-type GaN.
  • the nitride semiconductor wafer used for the base material 38 has a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane.
  • the crystal plane of the main surface is, for example, the (11-20) plane, the (11-22) plane, or the (11-24) plane.
  • the base material 38 is doped with an n-type impurity such as silicon (Si).
  • the “main surface of the substrate 38” refers to a crystal plane inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane.
  • the bulk layer 39 is a nitride semiconductor layer and is made of, for example, n-type GaN.
  • the bulk layer 39 has a thickness of, for example, millimeter order.
  • the bulk layer 39 has a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane, like the base material 38.
  • the bulk layer 39 is formed by an epitaxial crystal growth method such as MOCVD method or HVPE (HydrideydVapor Phase Epitaxy) method.
  • the bulk layer 39 is doped with an n-type impurity such as silicon (Si).
  • FIG. 6A shows an example of the manufacturing process of the semiconductor substrate 3.
  • FIG. 6B shows an example of the manufacturing process following FIG. 6A.
  • nitride semiconductors are collectively formed on the base material 38 made of, for example, GaN by an epitaxial crystal growth method such as MOCVD method or HVPE method.
  • MOCVD method atomic layer deposition method
  • HVPE method epitaxial crystal growth method
  • trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn), ammonia (NH 3 ), or the like is used as a compound semiconductor material
  • monosilane (SiH) is used as a source material for donor impurities. 4
  • acceptor impurity material for example, biscyclopentadienylmagnesium (Cp 2 Mg) is used.
  • a base material 38 having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane is prepared.
  • the superlattice layer 20 is formed on the substrate 38 with the main surface of the substrate 38 as a crystal growth surface.
  • the bulk layer 39 is formed using the surface of the superlattice layer 20 as a crystal growth surface. In this way, the semiconductor substrate 3 is manufactured.
  • the superlattice layer 20 is formed on the main surface of the base material 38 having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane. .
  • strain stress is generated by the Al x1 In y1 Ga z1 N layer 20A and the Al x2 In y2 Ga z2 N layer 20B.
  • This strain stress causes misfit dislocations of the substrate to the superlattice layer 20 as a starting point. It is possible to suppress the occurrence of pits. As a result, generation of pits can be suppressed also for the bulk layer 39 formed on the superlattice layer 20. Therefore, for example, as shown in FIG.
  • the junction structure layer 30 is formed by using the main surface of the bulk layer 39 (a crystal plane inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane) as a crystal growth surface. is there.
  • the degree of lattice mismatch between the Al x1 In y1 Ga z1 N layer 20A and the Al x2 In y2 Ga z2 N layer 20B is 0.00048 or more.
  • the junction structure layer 30 of the above embodiment is formed using the (11-20) plane, the (11-22) plane, or the (11-24) plane as the crystal growth plane, the m plane ( 1-100) can be used.
  • the bonding structure layer 30 is formed directly on the (11-20) surface, the (11-22) surface, or the (11-24) surface of the substrate 38, pits are generated in the bonding structure layer 30.
  • Cheap On the other hand, for example, as shown in FIG. 7, when the bonding structure layer 30 is formed on the semiconductor substrate 3 (bulk layer 39), the generation of pits in the bonding structure layer 30 can be suppressed.
  • a light-emitting element having an m-plane (1-100) as a cleavage plane can be put into practical use.
  • a semiconductor substrate 4 made of a bulk layer 39 may be used instead of the semiconductor substrate 3, for example, as shown in FIGS. 8 and 9, a semiconductor substrate 4 made of a bulk layer 39 may be used.
  • the semiconductor substrate 4 is composed of, for example, a bulk layer 39 left by removing the base material 38 and the superlattice layer 20 from the semiconductor substrate 3.
  • the semiconductor light-emitting device 1 shown in FIG. 8 includes a semiconductor substrate 4 composed of a bulk layer 39 and a crystal tilted by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane. And a bonding structure layer 30 formed with the crystal plane as a crystal growth plane.
  • the junction structure layer 30 includes a lower clad layer 32, a lower guide layer 33, an active layer 34, an upper guide layer 35, an upper clad layer 36, and a contact layer 37 in this order from the semiconductor substrate 4 side. 7, for example, as shown in FIG.
  • the bonding structure layer 30 is formed on the semiconductor substrate 4 with the main surface of the semiconductor substrate 4 as the crystal growth surface. It may be formed. Even when the bonding structure layer 30 is formed by any method, in the bonding structure layer 30, it is possible to suppress the occurrence of current leakage and non-light emission due to the pits as in the above embodiment.
  • this indication can take the following composition.
  • a nitride semiconductor device in which a composition ratio of the Al x1 In y1 Gaz1 N layer and the Al x2 In y2 Gaz2 N layer satisfies at least one of x1 ⁇ x2 and y1 ⁇ y2.
  • the degree of lattice mismatch between the Al x1 In y1 Ga z1 N layer and the Al x2 In y2 Ga z2 N layer is 0.00048 or more.
  • the junction structure layer includes an active layer and an upper clad layer in this order from the superlattice layer side,
  • the superlattice layer also serves as a lower cladding layer.
  • the nitride semiconductor device according to any one of (1) to (3).
  • a nitride semiconductor substrate having a principal surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane;
  • a superlattice layer formed using the main surface as a crystal growth surface, The superlattice layer includes an Al x1 In y1 Ga z1 N layer (0 ⁇ x1 ⁇ 1, 0 ⁇ y1 ⁇ 1, 0 ⁇ z1 ⁇ 1, x1 + y1 + z1 1) and an Al x2 In y2 Ga z2 N layer (0 ⁇ x2).
  • a method for manufacturing a nitride semiconductor substrate wherein a composition ratio of the Al x1 In y1 Gaz1 N layer and the Al x2 In y2 Gaz2 N layer satisfies at least one of x1 ⁇ x2 and y1 ⁇ y2.
  • a nitride semiconductor layer having a principal surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane;
  • a junction structure layer formed using the main surface as a crystal growth surface,
  • the junction structure layer includes a lower clad layer, an active layer, and an upper clad layer in this order from the nitride semiconductor layer side.
  • the composition ratio of the Al x1 In y1 Gaz1 N layer and the Al x2 In y2 Gaz2 N layer satisfies at least one of the expressions x1 ⁇ x2 and y1 ⁇ y2.
  • the junction structure layer includes a lower cladding layer, an active layer, and an upper cladding layer in this order from the nitride semiconductor substrate side.
  • junction structure layer (10) forming a junction structure layer with respect to a nitride semiconductor substrate having a main surface inclined by ⁇ ° or more (20 ° ⁇ ⁇ ⁇ 90 °) in the a-axis direction from the c-plane with the main surface as a crystal growth surface.
  • the junction structure layer includes a lower clad layer, an active layer, and an upper clad layer in this order from the nitride semiconductor substrate side.

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Abstract

Selon un mode de réalisation de la présente invention, un élément semi-conducteur au nitrure est pourvu: d'un substrat semi-conducteur au nitrure ayant une surface principale qui est inclinée dans la direction de l'axe a à un angle θ° ou plus (20° ≤ θ ≤ 90°) à partir du plan c; et une couche super-réseau formée en ayant la surface principale en tant que surface de croissance cristalline. La couche super-réseau est configurée par stratification alternée des N couches de Al x1In y1 Ga z1 (0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1, 0 ≤ z1 ≤ 1, x1 + y1 + z1 =1) et des N couches de Al x2 Iny2Gaz2 (0 ≤ x2 ≤ 1, 0 ≤ y2 ≤ 1, 0 ≤ z2 ≤ 1, x2 + y2 + z2 = 1). Le rapport de composition des N couches d'Al x1 Iny1Gaz1 et les N couches d'Alx2Iny2Gaz2 satisfont la formule de x1 ≠ x2 et/ou y1 ≠ y2.
PCT/JP2017/014762 2016-06-20 2017-04-11 Élément semi-conducteur au nitrure, substrat semi-conducteur au nitrure, procédé de fabrication d'un élément semi-conducteur au nitrure et procédé de fabrication d'un substrat semi-conducteur au nitrure Ceased WO2017221519A1 (fr)

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DE112017003057.9T DE112017003057T5 (de) 2016-06-20 2017-04-11 Nitridhalbleiterelement, nitridhalbleitersubstrat, herstellungsverfahren für ein nitridhalbleiterelement und herstellungsverfahren für ein nitridhalbleitersubstrat
JP2018523352A JPWO2017221519A1 (ja) 2016-06-20 2017-04-11 窒化物半導体素子、窒化物半導体基板、窒化物半導体素子の製造方法、および窒化物半導体基板の製造方法

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