WO2017211240A1 - Processor chip and method for prefetching instruction cache - Google Patents

Abstract

A processor chip (200) comprises a central processing unit (CPU) core (202) and a cache memory (204). The cache memory (204) comprises an L1 instruction cache (L1 I-cache) (2042) and a cache controller (2044). The L1 I-cache (2042) comprises at least one cache line. Each cache line comprises a tag domain, data, a flag bit, and an extension bit for storing an offset information of an access address. The CPU core (202) is configured to obtain an access address of a first instruction and access the L1 I-cache (2042) according to the access address of the first instruction. The cache controller (2044) is configured to read offset information of an access address in an extension bit of a first cache line if the first cache line corresponding to the access address of the first instruction in the L1 I-cache is hit and perform a calculation according to the offset information of the access address and the access address of the first instruction to obtain an access address of a second instruction. The CPU core (202) is further configured to prefetch the second instruction according to the access address of the second instruction.

Description

Processor chip and prefetching method of instruction cache Technical field

The present invention relates to the field of computer technologies, and in particular, to a processor chip and a prefetching method for an instruction cache.

Background technique

In the architecture of modern computers, the cache is a storage unit at a higher level in the computer storage hierarchy, and its main function is to serve as a bridge between the low-level storage unit and the central processing unit (CPU). The latency of the data directly accessed by the CPU from a low-level storage unit such as main memory or disk. The cache consists of several independent cache modules, including Instruction Cache (I-Cache), Data Cache (D-Cache), and Translation Lookaside Buffer (TLB). At present, most mainstream CPUs have L1 Cache and L2 Cache, and a few high-end processors also integrate L3 cache. Among them, the level 1 cache can be divided into a level one instruction cache (L1 I-Cache) and a level one data cache (L1 D-Cache).

The modern computer CPU obtains the instruction to be executed by directly accessing its L1 I-Cache. The CPU accesses the L1 I-Cache by accessing the address. When the instruction corresponding to the access address exists in the L1 I-Cache, it is called a hit ( Cache hit); and when the instruction corresponding to the access address cannot be found in the L1 I-Cache, it is called a cache mi ss. When a defect occurs, the CPU goes to the next level of storage to find it. However, accessing lower-level storage units directly leads to a significant increase in access latency, causing stalls in the execution of CPU instructions, which affects the performance of the computer. Therefore, the cache prefetch technique is proposed. The main idea is to prefetch the instructions that may be accessed into the L1 I-Cache before the CPU fetches instructions, so as to avoid CPU blocking caused by the missing.

In order to solve the instruction fetch caused by the CPU instruction in the L1 I-Cache missing, a typical solution is to insert a stream buffer called L1 I-Cache and L2 I-Cache. A functional unit, which is actually a First Input First Output (FIFO) queue. When accessing the instructions in the L1 I-Cache continuously, missing in the L1 I-Cache but being able to hit in the stream buffer, then it is directly taken from the stream buffer, greatly reducing the loss of the lower-level storage unit. (For example: L2 I-Cache) The delay caused by fetching instructions.

In the above solution, since the stream buffer is a FIFO queue, there is only one comparator in the head of the stream buffer (the first column in the FIFO queue). When the L1 I-Cache is missing, if it is in the head of the stream buffer. In the data (head entry), the corresponding instruction can not be found by the comparator comparison. Even if the required instruction is in the original stream buffer (not at the head), the entire stream buffer will be reset, and then Re-fetch from the stream buffer. This results in a low utilization of the stream buffer, and the prefetched instructions are likely to be accessed, so the prefetch accuracy of the instruction cache is low.

Summary of the invention

The embodiment of the invention provides a processor chip and a prefetching method of the instruction cache, which can improve the prefetching accuracy of the instruction cache.

A first aspect of the embodiments of the present invention provides a processor chip, which includes a processor core CPU core and a cache Cache, and the Cache includes a first-level instruction cache L1 I-Cache and a Cache controller. To improve the processing performance of the CPU core, the Cache may also include a secondary instruction cache L2 I-Cache. The Cache can be implemented with a high-speed static memory chip or integrated into the CPU chip to store instructions or operational data that the CPU frequently accesses. The L1 I-Cache stores instructions frequently accessed by the CPU. The L1 I-Cache includes at least one cache unit cache line. Each cache line has a unified data structure, and the data structure of the cache line may include a tag tag field, data, and a flag. Bit.

On the basis of this, the embodiment of the present invention expands the data structure of the cache line. Therefore, the difference from the traditional cache line is that the new cache line includes the data structure of each cache line introduced above. An extension bit for storing offset information of the access address, the offset information of the access address being an address change amount of an access address included in two adjacent access instructions issued by the CPU core to the L1 I-Cache. In this way, a new cache line data structure is formed.

Optionally, before the CPU Core obtains the access address of the first instruction, the Cache controller calculates offset information between the access address of the first instruction and the access address of the second instruction, and writes the offset information into the first instruction. The access address corresponds to the extension bit of the cache line. In this way, the pre-configuration of the L1 I-Cache is completed, and the continuity of instruction prefetching is improved.

When calling the data, the CPU core needs to obtain an access address of the first instruction, and access the L1 I-Cache according to the access address of the first instruction.

The CPU core accesses the L1 I-Cache through the access address of the first instruction. If the access address of the first instruction exists in the L1 I-Cache, the first cache line corresponding to the access address of the first instruction is in the L1 I-Cache. Was hit. At this time, the Cache controller reads the offset information of the access address in the extension bit of the first cache line, and calculates the access address of the second instruction according to the offset information of the access address and the access address of the first instruction.

Optionally, if the access address of the first instruction does not exist in the L1 I-Cache, the first cache line corresponding to the access address of the first instruction is not hit in the L1 I-Cache, and at this time, the Cache controller The location of the first instruction may be searched according to the access address of the first instruction, and the first instruction is prefetched into the L1 I-Cache. Therefore, the first instruction corresponding to the missed cache line is prefetched into the L1 I-Cache to improve the access rate after the instruction prefetch.

After calculating the access address of the second instruction, the CPU core can search for the location of the second instruction by using the access address of the second instruction, and perform prefetching on the second instruction.

Since each cache line further includes an extension bit for storing offset information of the access address, the offset information of the access address is an access included by two adjacent access instructions issued by the processor core CPU core to the L1 I-Cache. The address change amount of the address; therefore, the Cache controller determines that the first cache line corresponding to the access address of the first instruction in the L1 I-Cache is hit, and can read the offset of the access address in the extension bit of the first cache line Transmitting information, and calculating an access address of the second instruction according to the offset information of the access address and the access address of the first instruction; and the CPU core executing the access instruction of the second instruction calculated by the Cache controller to execute the second instruction Prefetching. The access rate of the instruction prefetched by the offset information of the access address is high, and therefore, the prefetch accuracy of the instruction cache can be improved.

Optionally, the Cache may further include a second-level instruction cache L2 I-Cache. When the storage space in the L1 I-Cache is full, the CPU Core performs an eviction operation on the cache space in the L1 I-Cache, and the L1 I-Cache is used. Second in The cache line is deported to the L2 I-cache. The Cache controller sets the eviction weight for the second cache line, and the eviction weight is used to mark the priority of the second cache line being evicted in the L2 I-cache. Improve the utilization of the eviction cache line by setting the eviction weight.

Optionally, for the eviction cache line, the inheritance and sharing of the prefetching experience may be implemented. When the access address of the CPU Core execution instruction is determined to correspond to the second cache line deported to the L2 I-cache, the eviction will be deported to The second cache line in the L2 I-Cache is prefetched into the L1 I-Cache. In this way, the information saved by the second cache line that is deported to the L2 I-Cache is directly taken, saving configuration resources and improving the utilization of the cache line.

A second aspect of the embodiments of the present invention provides a prefetching method for an instruction cache, which is applied to a processor chip. The processor chip includes a processor core CPU core and a cache Cache, and the Cache includes a first-level instruction cache L1 I- The Cache and the Cache controller, the L1 I-Cache includes at least one cache unit cache line, each cache line includes a tag tag field, data, and a flag bit, wherein each cache line further includes offset information for storing the access address. The extension bit, the offset information of the access address is the address change amount of the access address included in the adjacent two access instructions sent by the processor core CPU core to the L1I-Cache; the method includes:

When the CPU core calls the data, it needs to obtain the access address of the first instruction, and access the L1 I-Cache according to the access address of the first instruction.

The CPU core accesses the L1 I-Cache through the access address of the first instruction. If the access address of the first instruction exists in the L1 I-Cache, the first cache line corresponding to the access address of the first instruction is in the L1 I-Cache. Was hit. At this time, the Cache controller reads the offset information of the access address in the extension bit of the first cache line, and calculates the access address of the second instruction according to the offset information of the access address and the access address of the first instruction.

After calculating the access address of the second instruction, the CPU core can search for the location of the second instruction by using the access address of the second instruction, and perform prefetching on the second instruction.

Since each cache line further includes an extension bit for storing offset information of the access address, the offset information of the access address is an access included by two adjacent access instructions issued by the processor core CPU core to the L1 I-Cache. The address change amount of the address; therefore, the Cache controller determines that the first cache line corresponding to the access address of the first instruction in the L1 I-Cache is hit, and can read the offset of the access address in the extension bit of the first cache line Transmitting information, and calculating an access address of the second instruction according to the offset information of the access address and the access address of the first instruction; and the CPU core executing the access instruction of the second instruction calculated by the Cache controller to execute the second instruction Prefetching. The access rate of the instruction prefetched by the offset information of the access address is high, and therefore, the prefetch accuracy of the instruction cache can be improved.

Optionally, before the CPU Core obtains the access address of the first instruction, the Cache controller calculates offset information between the access address of the first instruction and the access address of the second instruction, and writes the offset information into the first instruction. The access address corresponds to the extension bit of the cache line. In this way, the pre-configuration of the L1 I-Cache is completed, and the continuity of instruction prefetching is improved.

Optionally, if the access address of the first instruction does not exist in the L1 I-Cache, the first cache line corresponding to the access address of the first instruction is not hit in the L1 I-Cache, and at this time, the Cache controller The location of the first instruction may be searched according to the access address of the first instruction, and the first instruction is prefetched into the L1 I-Cache. Therefore, the first instruction corresponding to the missed cache line is prefetched into the L1 I-Cache to improve the access rate after the instruction prefetch.

Optionally, the Cache may further include a second-level instruction cache L2 I-Cache. When the storage space in the L1 I-Cache is full, the CPU Core performs an eviction operation on the cache space in the L1 I-Cache, and the L1 I-Cache is used. The second cache line is deported to the L2 I-cache. The Cache controller sets the eviction weight for the second cache line, and the eviction weight is used to mark the priority of the second cache line being evicted in the L2 I-cache. Improve the utilization of the eviction cache line by setting the eviction weight.

Optionally, the Cache may further include a second-level instruction cache L2 I-Cache. When the storage space in the L1 I-Cache is full, the CPU Core performs an eviction operation on the cache space in the L1 I-Cache, and the L1 I-Cache is used. The second cache line is deported to the L2 I-cache. The Cache controller sets the eviction weight for the second cache line, and the eviction weight is used to mark the priority of the second cache line being evicted in the L2 I-cache. In this way, the information saved by the second cache line that is deported to the L2 I-Cache is directly taken, saving configuration resources and improving the utilization of the cache line.

A third aspect of the embodiments of the present invention provides a data structure of a cache unit cache line, where the cache line includes a tag tag field, data, and a flag bit. In addition, the cache line further includes an extension for storing offset information of the access address. The offset information of the bit and the access address is the address change amount of the access address included in the adjacent two access instructions issued by the processor core CPU Core to the level 1 instruction cache L1 I-Cache.

A fourth aspect of the embodiments of the present invention provides a storage medium, where the program code is stored, and when the program code is executed by the processor chip, the instruction provided by any one of the second aspect or the second aspect is executed. The prefetch method of the cache. The storage medium includes, but is not limited to, a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

DRAWINGS

1 is a schematic structural diagram of an embodiment of a processor chip provided by the present invention;

2 is a schematic flowchart of an embodiment of a prefetching method for an instruction cache provided by the present invention;

3 is a schematic structural diagram of an embodiment of a cache unit cache line provided by the present invention;

FIG. 4 is a schematic flowchart diagram of an embodiment of a method for configuring offset information of an access address according to the present invention.

detailed description

The terms "first", "second" and the like in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a particular order or order. It is to be understood that the data so used may be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than what is illustrated or described herein. In addition, the terms "comprises" and "comprises" and "the" and "the" are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to Those steps or units may include other steps or units not explicitly listed or inherent to such processes, methods, products or devices.

The technical solutions in the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Throughout this specification, an effective instruction cache prefetch technique should have two basic qualities: a higher prediction accuracy rate. And enough hardware and software overhead. Higher prediction accuracy can improve the hit rate of I-Cache and improve the performance of CPU execution instructions. At the same time, it introduces enough hardware and software overhead to reduce the impact of prefetch on Cache performance. At present, the typical computer cache prefetching technology can be roughly divided into two categories: software-based prefetching and hardware-based prefetching. Typical prefetch mechanisms include: OBL (One Block Lookahead), adaptive sequential prefetching, stream buffer, history-based prefetching techniques, and more.

Stream buffer is a typical instruction prefetching technology. By inserting a stream buffer directly into L1 I-Cache and L2 I-Cache to temporarily store prefetched instruction data, it can effectively avoid cache pollution. Prefetch data is saved so that it can be accessed by the L1 cache with low latency when needed.

History guided prefetch is another typical instruction prefetching mechanism based on historical information of instruction execution (including instruction execution history, branch prediction history or cache miss history), through certain analysis and prediction algorithms. Compile instructions that may be executed and prefetch them.

There are two main problems in the prior art: First, for instruction sequences with complex access rules, the existing methods cannot guarantee effective analytical learning and accurate prediction, and the hardware and software required for pre-fetch prediction to achieve a certain accuracy rate. The overhead depends on the characteristics of the input instruction sequence itself. Secondly, for the prefetch mechanism that uses historical information for prediction, there is generally a long initialization time that cannot be ignored for analysis and learning, which is time consuming. At the same time, a prefetch operation with a lower accuracy rate may be generated, which impairs the execution performance of the CPU instruction.

The problem solved by the present invention and the difference from the prior art is that the present invention extends the bit width in the cache line of the I-Cache, and adds the address of the next instruction to the address of the instruction in the cache line. Offset information and prefetch the corresponding instruction when this cache line hits. The hardware mechanism is different from the various prefetching mechanisms mentioned above, and can adapt to the instruction sequences of various access rules, and reduce the training overhead of prefetching, and effectively improve the accuracy of prefetching.

1 is a schematic structural diagram of a processor chip 200 according to an embodiment of the present invention. The processor chip 200 includes a processor core CPU core 202 and a cache Cache 204. The Cache includes a first-level instruction cache L1 I. The Cache 204 and the Cache Controller 2044, in order to improve the processing performance of the CPU core 202, the Cache 204 may further include a Level 2 Instruction Cache L2 I-Cache 2046. The processor chip 200 can also include a bus 208 and a communication interface 206.

The CPU core 202, the Cache 204, and the communication interface 206 can implement communication connection with each other through the bus 208, and can also implement communication by other means such as wireless transmission.

The Cache 204 in the embodiment of the present invention may be a random-access memory (RAM); specifically, it may be a static random-access memory (SRAM). In practical applications, the Cache basically uses RAM, and the SRAM is a memory with static access function, which can save the data stored therein without refreshing the circuit, so the SRAM has high performance. The Cache 204 can be implemented with a high speed static memory chip or integrated into the CPU chip to store instructions or operational data that the CPU frequently accesses. According to the data reading order and the tightness combined with the CPU, the CPU cache can be divided into a level 1 cache, a level 2 cache, and some high-end CPUs also have a level 3 cache. In general, the level 1 cache can be divided into a level 1 data cache and a level 1 instruction cache. The two are used to store data and decode the instructions for executing the data, and the two can be accessed by the CPU at the same time, which reduces the conflict caused by the contention cache and improves the processor performance.

The L1 I-Cache 2042 in the embodiment of the present invention includes at least one cache unit cache line (shown in FIG. 1). A plurality of cache units 1 to cache units n), each of the existing cache lines has a unified data structure, and the data structure of the cache line may include a tag tag field, data, and flag bits. On this basis, the data structure of the cache line shown in FIG. 3 extends the data structure of the conventional cache line, that is, the extra bits for storing the offset information of the access address are added. The offset information of the access address is the address change amount of the access address included in the adjacent two access instructions issued by the processor core CPU core 202 to the L1 I-Cache 2042.

The Cache controller 2044 in the embodiment of the present invention calculates the offset information between the access address of the first instruction and the access address of the second instruction, and writes the offset information, before the CPU Core 202 acquires the access address of the first instruction. The access address of the first instruction corresponds to the extension bit of the cache line. For example, referring to the flow diagram of calculating the offset information of the access address shown in FIG. 4, the CPU Core 202 accesses the cache line in the L1 I-Cache 2042, and queries the cache controller 2044 whether the address register is empty: if it is empty, it indicates The cache line is the first cache line in the access sequence. The Cache Controller 2044 writes the current access address cur_addr to the address register and waits for the next cache line access; if not, the Cache Controller 2044 will address the address register. The value (for example, the cur_addr of the previous access) is given as last_addr, and the current access address is written to the address register as the new cur_addr.

It can be understood that the address register is empty, indicating that the cache line in the L1 I-Cache 2042 is not accessed. Therefore, after being accessed for the first time, the access address of the first instruction is written into the address register, waiting for the next instruction. After accessing the address, access the cache line in L1 I-Cache 2042 again.

For example, after the first access address (cur_addr) is written to the address register after the first access, the address register is non-empty, and when the cache line in the L1 I-Cache 2042 is accessed again, the read address register is written. The access address of the first instruction that is entered (since the current access to the L1 I-Cache 2042 is not necessarily the access address of the first instruction, the access address of the first instruction stored in the address register can be understood as last_addr) . The Cache controller 2044 updates the access address (last_addr) written in the address register to the access address of the second instruction accessed again (at this time, since the current access address is the access address of the second instruction, therefore, The access address of the second instruction is understood as cur_addr). In this case, the access address of the second instruction is the access address of another instruction acquired by the CPU Core 202 when accessing the L1 I-Cache 2042 for the second time after the first access to the L1 I-Cache 2042.

The Cache controller 2044 calculates the address change amount Δ=cur_addr-last_addr according to the last_addr and the current access address (ie, the new cur_addr) given above, and writes the address change amount Δ to the last access (the first instruction in the scenario) The access address corresponds to the extension bits of the cache line.

When calling the data, the CPU core 202 in the embodiment of the present invention reads the instruction for executing the data for instant decoding, wherein each instruction has an access address, and the location where the instruction is stored can be found by the access address. . Therefore, when the data is called, the CPU core 202 needs to acquire the access address of the first instruction, and accesses the L1 I-Cache 2042 according to the access address of the first instruction; by executing the first instruction, the corresponding data can be called.

The CPU core 202 accesses the L1 I-Cache 2042 through the access address of the first instruction. If the access address of the first instruction exists in the L1 I-Cache 2042, the first cache line corresponding to the access address of the first instruction is at L1 I- Cache 2042 will be hit. At this time, the Cache controller 2044 reads the offset information of the access address in the extension bit of the first cache line, and calculates the access address of the second instruction according to the offset information of the access address and the access address of the first instruction.

If the access address of the first instruction does not exist in the L1 I-Cache 2042, the first cache line corresponding to the access address of the first instruction is not hit in the L1 I-Cache 2042. At this time, the Cache controller 2044 may Finding the location of the first instruction according to the access address of the first instruction, and prefetching the first instruction to the L1 I-Cache 2042.

After calculating the access address of the second instruction, the CPU core 202 can search for the location of the second instruction by using the access address of the second instruction, and perform prefetching on the second instruction, for example, by using the calculated access address of the second instruction. When the second instruction is in the L2 I-Cache, the second instruction is prefetched from the L2 I-Cache into the L1 I-Cache.

The cache line provided by the embodiment of the present invention further includes an extension bit for storing offset information of the access address, and the offset information of the access address is two adjacent times sent by the processor core CPU core 202 to the L1 I-Cache 2042. Accessing the address change amount of the access address included in the instruction; therefore, the Cache controller 2044 determines that the first cache line can be read when the first cache line corresponding to the access address of the first instruction is hit in the L1 I-Cache 2042 The offset information of the access address in the extension bit, and the access address of the second instruction is calculated according to the offset information of the access address and the access address of the first instruction; the second command calculated by the CPU core 202 according to the Cache controller 2044 The access address performs prefetching of the second instruction. The access rate of the instruction prefetched by the offset information of the access address is high, and therefore, the prefetch accuracy of the instruction cache can be improved.

The Cache 204 may further include a secondary instruction cache L2 I-Cache 2046. When the storage space in the L1 I-Cache 2042 is full, the CPU Core 202 performs a eviction operation on the cache space in the L1 I-Cache 2042. For example, the second cache line in the L1 I-Cache 2042 (for convenience of explanation, the cache line to be evicted is named as the second cache line, the same below) is deported into the L2 I-Cache 2046. The Cache Controller 2044 sets the eviction weight for the second cache line, the eviction weight being used to mark the priority of the second cache line being evicted in the L2 I-Cache 2046.

For the above eviction phase, when the processor core CPU Core 202 performs the eviction operation on the L1 I-Cache 2042, the Cache controller 2044 analyzes the extra bits of the cache line to be eviction: when the extension bits (Extra bits) When it is empty (null), it can be left unprocessed; when the extra bits are non-null (non-null), set the cache line's expulsion weight in L2 I-Cache 2046 to be the lowest, so that it is as far as possible The location is saved in the L2 I-Cache 2046. Among them, the eviction weight varies according to the eviction strategy used. Common eviction strategies include Least Recently Used (LRU), Least Frequently Used (LFU) and Adaptive Cache. Replace (Adaptive Replacement Cache, ARC) and so on.

For example, in the embodiment of the present invention, the L2 I-Cache records and stores the eviction weight value “age bits” of each cache line, and whenever there is a cache, the LRU is used as an example. When the line is accessed, then the "age bits" of the cache line in all other L2 I-Caches are incremented by one. Then, it can be considered that the cache line with the largest eviction weight value "age bits" has the highest priority (ie, the first eviction) in the L2 I-cache. When the cache line with the extra bits is evicted from the L1 I-Cache, then only the "age bits" of the cache line with the extra bits in the L2 I-Cache are needed. The value is set to 0 so that the cache line is deported in the L2 I-cache with the lowest priority (ie, the last eviction). Therefore, the priority of the cache line being evicted in the L2 I-cache (ie, the order of being evicted) can be achieved by setting the size of the "age bits" value of the cache line.

In the LFU, for example, if the Cache uses the LFU eviction algorithm, in the embodiment of the present invention, each cache line stored in the L2 I-Cache is set with a counter, and when a cache line is accessed, then the The counter corresponding to the cache line is incremented by 1. Then it can be considered that the cache line corresponding to the minimum value in the counter has the highest priority (ie, the first eviction) in the L2 I-cache. When the cache line with the extra bits is evicted from the L1 I-Cache, then only the corresponding counter value of the cache line with the extra bits in the L2 I-Cache is set. Is the maximum value of all counters in the current L2 I-Cache so that the cache line is The expelled in L2 I-Cache has the lowest priority (that is, the last eviction). Therefore, the priority of the cache line being evicted in the L2 I-Cache (ie, the order of being evicted) can be achieved by setting the size of the counter value corresponding to the cache line.

Taking ARC as an example, the ARC eviction algorithm is a compromise and balance between LRU and LFU. The Cache contains two tables T1 and T2. T1 stores the cache line using LRU, and T2 saves the cache line using LFU. T1 and T2 are common. Formed the entire Cache. The ARC algorithm adaptively adjusts each eviction selection based on the history of the cache line being evicted from T1 or T2. For example, the cache line located in the middle of the L2 I-Cache, that is, away from T1 and T2, is the lowest priority (ie, the last eviction) in the L2 I-cache. When there is an extension bit (Extra) When the cache line of bits) is evicted from the L1 I-Cache, then only the cache line with the extra bits is inserted in the middle of the L2 I-Cache, that is, away from T1 and T2. The location of the region so that the cache line is deported in the L2 I-Cache with the lowest priority (ie, the last eviction). Therefore, the cache line can be implemented in L2 by setting the location of the cache line in the L2 I-Cache. The priority of being evicted in the I-Cache (ie, the order in which they were evicted).

For the eviction cache line, the inheritance and sharing of the prefetch experience can be implemented. When it is determined that the access address of the CPU core 202 execution instruction corresponds to the second cache line deported to the L2 I-Cache 2046, it will be deported to L2 I. The second cache line in the -Cache 2046 is prefetched into the L1 I-Cache 2042.

For example, the access address of the processor core CPU core 202 executing the instruction corresponds to the second cache line deported to the L2 I-Cache 2046, and the cache line can be prefetched from the L2 I-Cache to directly acquire the CPU. The cache line generated by core202 stores the extra bits, which realizes the inheritance of prefetching "experience".

Based on the processor chip 200 provided in FIG. 1 , in the embodiment of the present invention, the processor chip 200 can also integrate multiple processor core CPU cores, and each CPU core can be configured with one L1 I-Cache, so each CPU core The L1 I-Cache 2046 can be configured independently. All CPU cores can be configured with one L2 I-Cache 2046. Therefore, each CPU core shares the same L2 I-Cache 2046 to implement resource sharing of the L2 I-Cache 2046. For example, in the case where the processor chip has multiple processor core CPU cores, sharing of multi-core prefetching experience can be implemented for the cached cache line, for example, when other processor cores (such as CPU core 2) execute instructions. When the access address is also corresponding to the second cache line deported to the L2 I-Cache 2046, the cache line may be prefetched from the L2 I-Cache 2046 to implement multi-core prefetch "experience" sharing.

The embodiment of the present invention further provides a prefetching method of the instruction cache. The processor chip 200 in FIG. 1 executes the method during operation, and the flow chart is shown in FIG. 2 .

402. The CPU core acquires an access address of the first instruction, and accesses the L1 I-Cache according to the access address of the first instruction.

When the CPU core in the embodiment of the present invention calls the data, it reads the instruction to execute the data for instant decoding, wherein each instruction has an access address, and the location where the instruction is stored can be found through the access address. Therefore, when calling data, the CPU core needs to acquire the access address of the first instruction, and access the L1 I-Cache according to the access address of the first instruction; by executing the first instruction, the corresponding data can be called.

In order to improve the continuity of instruction prefetching, the initialized Cache can be configured in advance. Optionally, before the CPU core obtains the access address of the first instruction, the method further includes:

The Cache controller calculates offset information between the access address of the first instruction and the access address of the second instruction, and writes the offset information into the extension address of the cache line corresponding to the access address of the first instruction.

For example, referring to the flow diagram of calculating the offset information of the access address shown in FIG. 4, the CPU Core accesses the L1 I-Cache. In the cache line, the Cache controller queries whether the address register is empty: if it is empty, it indicates that the cache line is the first cache line in the access sequence, and the Cache controller writes the current access address cur_addr into the address register. And wait for the next cache line access; if not empty, the Cache controller assigns the value of the address register (for example, the cur_addr of the previous access) to last_addr, and writes the current access address as a new cur_addr to the address register. The related description refers to the device part and will not be described here.

404. The Cache controller determines, when the first cache line corresponding to the access address of the first instruction is hit in the L1 I-Cache, reads the offset information of the access address in the extension bit of the first cache line, and according to the access address. The offset information and the access address of the first instruction are calculated to obtain the access address of the second instruction.

The CPU core accesses the L1 I-Cache through the access address of the first instruction. If the access address of the first instruction exists in the L1 I-Cache, the first cache line corresponding to the access address of the first instruction is in the L1 I-Cache. Was hit. At this time, the Cache controller reads the offset information of the access address in the extension bit of the first cache line, and calculates the access address of the second instruction according to the offset information of the access address and the access address of the first instruction.

If the access address of the first instruction does not exist in the L1 I-Cache, the first cache line corresponding to the access address of the first instruction is not hit in the L1 I-Cache. At this time, the Cache controller may be based on the first The access address of the instruction finds the location of the first instruction and prefetches the first instruction into the L1 I-Cache.

406. The CPU core performs prefetching of the second instruction according to the access address of the second instruction calculated by the Cache controller.

After calculating the access address of the second instruction, the CPU core may search for the location of the second instruction by using the access address of the second instruction, and perform prefetching on the second instruction, for example, by using the calculated access address of the second instruction. The second instruction is in the L2 I-Cache, and the second instruction is prefetched from the L2 I-Cache into the L1 I-Cache.

For example, the Cache controller calculates offset information between the access address of the first instruction and the access address of the second instruction, and writes the offset information into the extension address of the cache line corresponding to the access address of the first instruction, the cache unit The address change amount Δn of the access address in the extension line (Extra bits) in the cache line is as follows:

Table 1

Extra bits Address Hit/miss Prefetch addr Δ0 A Yes A+Δ0 Δ1 B=A+Δ0 Yes B+Δ1 Δ2 C=B+Δ1 No None Δ3 D Yes D+Δ3 Δ4 E=D+Δ3 Yes E+Δ4

Table 1 lists the address change amounts Δn of the access addresses in the extended bits (extra bits) of the five cache lines, which are: Δ0, Δ1, Δ2, Δ3, and Δ4, respectively.

Taking the address change amount Δn of the access address written in Table 1 as an example, the CPU core needs to access the cache line with the address A, hit the cache line in the L1 I-Cache, and read the access saved in the Extra bits field. The address change amount Δ0 of the address is calculated as the address of the next cache line as A+Δ0=B, and the instruction corresponding to the access address B is prefetched into the L1 I-Cache.

The CPU core needs to access the cache line with the address B, hit the cache line in the L1 I-Cache, read the address change amount Δ1 stored in the Extra bits field, and calculate the address of the next cache line as B+Δ1= C, prefetch the instruction corresponding to the access address C into the L1 I-Cache.

The CPU core needs to access the cache line with address X. This cache line is missing in the L1 I-Cache and is not prefetched.

The CPU core needs to access the cache line with the address D, hit the cache line in the L1 I-Cache, read the address change amount Δ3 stored in the Extra bits field, and calculate the address of the next cache line as D+Δ3= E. Prefetch the instruction corresponding to the access address E into the L1 I-Cache.

The CPU core needs to access the cache line with the address E, hit the cache line in the L1 I-Cache, read the address change amount Δ4 stored in the Extra bits field, and calculate the address of the next cache line as E+Δ4. The instruction corresponding to the access address E+Δ4 is prefetched into the L1 I-Cache.

In the prefetch phase, a suitable prefetch depth can be set (prefetch_depth). For example, accessing the current cache line and calculating the access address of the instruction that may be executed by the next access data is calculated by the offset information of the access address in the cache line. If the cache line corresponding to the access address of this instruction is hit in the L1 I-Cache, the instruction is prefetched into the L1 I-Cache through the access address of the instruction. According to the prefetching depth, the prefetching of the prefetched instruction is continued, and the offset information of the access address of the cache line in which the instruction prefetched into the L1 I-Cache is read, and the prefetching of the next access data may be performed. The access address of the instruction (ie, performing a loop prefetch). The pre-fetch depth may be determined according to the type of the workload. Different workload types may be applied to different pre-fetch depths. Therefore, it may be necessary to test and set different typical applications. Some default values. Note that the prefetch depth needs to be set appropriately. Too small affects the prefetching effect and reduces locality. If it is too large, it may cause cache pollution or prefetched data to be overwritten.

The cache line provided by the embodiment of the present invention further includes an extension bit for storing offset information of the access address, where the offset information of the access address is an adjacent two access instruction sent by the processor core to the L1 I-Cache. The address change amount of the included access address; therefore, the Cache controller determines that the first cache line corresponding to the access address of the first instruction is hit in the L1 I-Cache, and the extension bit of the first cache line can be read. Accessing the offset information of the address, and calculating the access address of the second instruction according to the offset information of the access address and the access address of the first instruction; the CPU core performs the pair according to the access address of the second instruction calculated by the Cache controller. Prefetching of the second instruction. The access rate of the instruction prefetched by the offset information of the access address is high, and therefore, the prefetch accuracy of the instruction cache can be improved.

The Cache 204 may further include a secondary instruction cache L2 I-Cache. When the storage space in the L1 I-Cache is full, the CPU Core performs an eviction operation on the cache space in the L1 I-Cache. For example, the second cache line in the L1 I-Cache (for convenience of explanation, the cache line to be evicted is named as the second cache line, the same below) is deported to the L2 I-cache. The Cache controller sets the eviction weight for the second cache line, and the eviction weight is used to mark the priority of the second cache line being evicted in the L2 I-cache. For the description of the deportation weights in the expulsion phase, refer to the device section, which will not be described here.

For the eviction cache line, the inheritance and sharing of prefetching experience can be implemented. When the access address of the CPU Core execution instruction is determined to correspond to the second cache line deported to the L2 I-cache, it will be deported to the L2 I-Cache. The second cache line is prefetched into the L1 I-Cache. The related description refers to the device part and will not be described here.

In the case where there are multiple processor cores in the processor chip, the sharing of the multi-core prefetch experience can be implemented for the cached cache line, for example, when the access addresses of other processor cores (such as CPU Core 2) execute instructions are also corresponding. When the above is expelled to the second cache line in the L2 I-cache, the cache line can also be prefetched from the L2 I-Cache to realize the sharing of the multi-core prefetch "experience". The related description refers to the device part and will not be described here.

An embodiment of the present invention further provides a computer storage medium, wherein the computer storage medium can store a program, where The program execution includes some or all of the steps of the prefetching method of the instruction cache described in the above method embodiments.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present invention, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention, which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium. A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the embodiments are modified, or the equivalents of the technical features are replaced by the equivalents of the technical solutions of the embodiments of the present invention.

Claims (10)

A processor chip, comprising: a processor core CPU core and a cache cache, the cache includes a first level instruction cache L1 I-Cache and a Cache controller, and the L1 I-Cache includes at least one a cache unit cache line, each of the cache lines includes a tag tag field, data, and a flag bit. Each of the cache lines further includes an extension bit for storing offset information of the access address, where the offset information of the access address is an adjacent two access command sent by the CPU core to the L1 I-Cache. The amount of address change of the included access address; The CPU core is configured to obtain an access address of the first instruction, and access the L1 I-Cache according to the access address of the first instruction; The Cache controller is configured to: when the first cache line corresponding to the access address of the first instruction is hit in the L1 I-Cache, read an access address in an extension bit of the first cache line Offset information, and calculating an access address of the second instruction according to the offset information of the access address and the access address of the first instruction; The CPU core is further configured to perform prefetching of the second instruction according to the access address of the second instruction calculated by the Cache controller. The chip of claim 1 wherein: The Cache controller is further configured to: when the first cache line corresponding to the access address of the first instruction is not hit in the L1 I-Cache, searching for the first address according to the access address of the first instruction The location of the first instruction and prefetching the first instruction into the L1 I-Cache. The chip according to claim 1 or 2, wherein The Cache controller is further configured to calculate offset information between an access address of the first instruction and an access address of the second instruction, and obtain the offset, before acquiring an access address of the first instruction The access address of the information written to the first instruction corresponds to the extension bit of the cache line. The chip according to any one of claims 1 to 3, wherein the Cache further comprises a second level instruction cache L2 I-Cache, The Cache controller is further configured to: when the second cache line in the L1 I-Cache performs eviction to the L2 I-Cache operation, set an eviction weight for the second cache line, where The eviction weight is used to mark the priority of the second cache line being evicted in the L2 I-Cache. The chip according to claim 4, wherein The Cache controller is further configured to prefetch the second cache line that is deported to the L2 I-Cache when determining that the access address of the CPU Core execution instruction corresponds to the second cache line In the L1 I-Cache. A prefetching method for an instruction cache is applied to a processor chip, the processor chip including a processor a core CPU core and a cache Cache, the Cache includes a first level instruction cache L1 I-Cache and a Cache controller, the L1 I-Cache including at least one cache unit cache line, each of the cache lines including a tag tag Domain, data, and flag bits, characterized in that Each of the cache lines further includes an extension bit for storing offset information of the access address, where the offset information of the access address is an adjacent two access command sent by the CPU core to the L1 I-Cache. The amount of address change of the included access address; the method includes: The CPU core acquires an access address of the first instruction, and accesses the L1 I-Cache according to the access address of the first instruction; Determining, by the Cache controller, the offset of the access address in the extension bit of the first cache line when the first cache line corresponding to the access address of the first instruction is hit in the L1 I-Cache Information, and calculating an access address of the second instruction according to the offset information of the access address and the access address of the first instruction; The CPU core performs prefetching of the second instruction according to the access address of the second instruction calculated by the Cache controller. The method of claim 6 wherein the method further comprises: Determining, by the Cache controller, that the first cache line corresponding to the access address of the first instruction is not hit in the L1 I-Cache, searching for the first instruction according to the access address of the first instruction Positioning and prefetching the first instruction into the L1 I-Cache. The method according to claim 6 or 7, wherein before the CPU core acquires an access address of the first instruction, the method further includes: The Cache controller calculates offset information between the access address of the first instruction and the access address of the second instruction, and writes the offset information to an extension of the cache address corresponding to the access address of the first instruction In the bit. The method according to any one of claims 6 to 8, wherein the Cache further comprises a secondary instruction cache L2 I-Cache, the method further comprising: The Cache controller sets an eviction weight for the second cache line when performing eviction of the second cache line in the L1 I-Cache to the L2 I-Cache operation, and the eviction weight is used for Marking the priority of the second cache line being evicted in the L2 I-Cache. The method of claim 9 wherein the method further comprises: The Cache controller prefetches the second cache line that is deported to the L2 I-Cache to the L1 I when determining that the access address of the CPU Core execution instruction corresponds to the second cache line -Cache.

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