[go: up one dir, main page]

WO2017206588A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2017206588A1
WO2017206588A1 PCT/CN2017/079210 CN2017079210W WO2017206588A1 WO 2017206588 A1 WO2017206588 A1 WO 2017206588A1 CN 2017079210 W CN2017079210 W CN 2017079210W WO 2017206588 A1 WO2017206588 A1 WO 2017206588A1
Authority
WO
WIPO (PCT)
Prior art keywords
array substrate
conductive structure
insulating layer
display area
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/079210
Other languages
English (en)
French (fr)
Inventor
李东朝
李京鹏
李建
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US15/551,525 priority Critical patent/US10388673B2/en
Publication of WO2017206588A1 publication Critical patent/WO2017206588A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G02F1/133784—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by rubbing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • TFT-LCD thin film transistor liquid crystal display
  • the main structure of the TFT-LCD is a liquid crystal display panel, and the liquid crystal display panel includes an array substrate and a color filter substrate of the pair of boxes, and a liquid crystal filled between the array substrate and the color filter substrate.
  • an alignment film is coated on the inner surface of the display region of the array substrate and the color filter substrate, and an alignment groove is formed on the alignment film by a rubbing alignment process to provide a certain amount for the liquid crystal molecules. Pretilt angle.
  • the rubbing alignment process in the related art has a problem of poor rubbing orientation due to static electricity difference or the like.
  • the present disclosure provides an array substrate, a manufacturing method thereof, and a display device for solving the problem of poor orientation of the alignment film due to static electricity.
  • an embodiment of the present disclosure provides an array substrate including a display area and a non-display area located at a periphery of the display area, the array substrate includes an insulating layer, and the insulating layer includes at least one of the non-displays An opening of the region, the array substrate further comprising at least one conductive structure in the non-display region, the opening being in a pair with the position of the conductive structure
  • the electrically conductive structure is located within the opening.
  • the conductive structure is made of a transparent conductive material.
  • the array substrate as described above, optionally, the array substrate further includes a gate line and a data line for defining a plurality of pixel regions;
  • the array substrate further includes a first metal line in the non-display area and in the same layer as the gate line, and a second metal line in the same layer as the data line, the first metal line and the first Two metal wires are corresponding to one another and electrically connected;
  • the first metal line and the second metal line are in one-to-one correspondence with the conductive structure and are electrically connected.
  • the array substrate as described above, optionally, the array substrate further includes a gate line and a data line for defining a plurality of pixel regions;
  • the array substrate further includes a first metal line in the non-display area and in the same layer as the gate line, the first metal line and the conductive structure are in one-to-one correspondence and electrically connected.
  • the array substrate as described above, optionally, the array substrate further includes a gate line and a data line for defining a plurality of pixel regions;
  • the array substrate further includes a second metal line in the non-display area and in the same layer as the data line, and the second metal line is in one-to-one correspondence with the conductive structure and is electrically connected.
  • the array substrate as described above, optionally, the array substrate further includes a substrate; the insulating layer is formed on the substrate and located in the non-display area; the insulating layer is based on the substrate The height is greater than the height of the electrically conductive structure.
  • the array substrate as described above, optionally, the array substrate further includes a groove formed on the insulating layer and used for mounting at least one of the integrated chip and the flexible circuit board; the insulating layer further includes a plurality of An opening; the groove is in communication with the plurality of openings.
  • a display device including the array substrate as described above is also provided in the embodiment of the present disclosure.
  • the display device further includes at least one of a chip and a circuit board; the array substrate further comprising a layer formed on the insulating layer and used for mounting the chip and the circuit board At least one groove; the insulating layer further includes a plurality of the openings; the groove is in communication with the plurality of openings; and a pin on the at least one of the chip and the circuit board is inserted into the corresponding one Inside the opening and in contact with the corresponding conductive structure inside the corresponding opening.
  • the manufacturing method includes:
  • the manufacturing method as described above, optionally, the manufacturing method specifically includes:
  • the conductive structure is formed within the opening.
  • the manufacturing method as described above, optionally, the manufacturing method specifically includes:
  • the opening is formed in the insulating layer.
  • the fabrication method may alternatively form the conductive structure using a transparent conductive material.
  • the array substrate further includes a substrate; and the forming the insulating layer comprises: forming the insulating layer on the substrate and in the non-display region.
  • the forming the at least one conductive structure in the non-display area comprises: forming the at least one conductive structure on the substrate and in the non-display area, The height of the insulating layer is greater than the height of the conductive structure based on the substrate.
  • the array substrate includes an insulating layer and a conductive structure located in the non-display area, the insulating layer includes at least one opening in the non-display area, and the opening has a one-to-one correspondence with the position of the conductive structure.
  • the conductive structure is located in the opening such that the surface of the conductive structure is lower than the surface of the insulating layer, so that during the rubbing orientation of the oriented film, the rubbing cloth is not in contact with the conductive material, and the rubbing cloth is in contact with each other. Insulation material, there is no difference in static electricity generated by high-speed friction, and there is no difference in the influence of the cloth on the friction cloth, ensuring the quality of the friction orientation and improving the picture quality.
  • FIG. 1 is a partial cross-sectional view showing a terminal area of an array substrate in the related art
  • FIG. 2 is a partial plan view showing a terminal area of an array substrate in the related art
  • FIG. 3 is a partial cross-sectional view 1 of an array substrate in an embodiment of the present disclosure
  • Figure 5 shows a partial cross-sectional view 3 of the array substrate in the embodiment of the present disclosure
  • Figure 6 shows a partial cross-sectional view 4 of the array substrate in the embodiment of the present disclosure
  • FIG. 7 is a partial plan view showing a terminal area of an array substrate in an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram showing a connection relationship between an array substrate and a circuit board in an embodiment of the present disclosure
  • Fig. 9 is a schematic view showing a display device in an embodiment of the present disclosure.
  • Fig. 1 is a partial cross-sectional view showing a terminal region of an array substrate in the related art.
  • Fig. 2 is a partial plan view showing a terminal area of an array substrate in the related art. 1 and 2, the array substrate includes a protective layer 10' and a terminal 1' located in a non-display area. Since the protective layer 10' is made of an insulating material and the terminal 1' is made of a conductive material, static electricity generated at the time of high-speed rubbing differs during the rubbing alignment of the oriented film.
  • the difference in static electricity further causes a difference in the influence of static electricity on the cloth of the rubbing cloth, which causes the cloth to be disordered and causes the direction of the cloth at the junction between the protective layer 10' and the terminal 1' to be inconsistent, thereby directly causing poor friction and affecting the picture. quality.
  • the present disclosure provides an array substrate, a manufacturing method thereof, and a display device for solving the problem of poor orientation of the alignment film due to static electricity.
  • an array substrate is provided in this embodiment, including a display area 210 (see FIG. 9) and a non-display area 220 (see FIG. 9) located at the periphery of the display area.
  • the array substrate further includes a substrate 100, and at least one guide disposed in the non-display area and disposed on the substrate 100 Electrical structure 1.
  • the electrically conductive structure is typically made of a transparent electrically conductive material because the transparent electrically conductive material is less susceptible to oxidation relative to the metallic material.
  • the conductive structure 1 can be fabricated in the same layer as the pixel electrode or the common electrode to simplify the manufacturing process and reduce the cost.
  • the array substrate further includes an insulating layer 11 disposed on the substrate 100.
  • the insulating layer 11 includes at least one opening 12 in the non-display area, the opening 12 is in one-to-one correspondence with the position of the conductive structure 1, and the conductive structure 1 is located in the opening 12.
  • the surface of the conductive structure 1 away from the substrate 100 is brought closer to the substrate 100 than the surface of the insulating layer 11 away from the substrate 100.
  • the conductive structure 1 is located in the opening 12 such that the top surface 930 of the conductive structure 1 away from the substrate 100 is closer to the substrate 100 than the top surface 940 of the insulating layer 11 away from the substrate 100, that is, the top surface of the conductive structure 1 is lower than The top surface of the insulating layer 11.
  • the height of the insulating layer 11 is greater than the height of the conductive structure 1 based on the substrate 100.
  • the rubbing cloth is not in contact with the conductive material, that is, the conductive structure 1, and the insulating cloth, that is, the insulating layer 11 is in contact with the rubbing cloth, and there is no difference in static electricity generated by high-speed friction, and thus the rubbing cloth There is no difference in the influence of the cloth wool, ensuring the quality of the rubbing orientation and improving the picture quality.
  • the array substrate further includes display film layer structures located in the display region, such as a gate line 950, a data line 960, a pixel electrode 970, and the like.
  • the gate line and the data line are used to define a plurality of pixel regions 980.
  • Each of the pixel regions includes the pixel electrode, and an electric field that drives deflection of liquid crystal molecules is formed between the pixel electrode and the common electrode.
  • the alignment film is used to orient liquid crystal molecules to regularly align liquid crystal molecules.
  • the common electrode may be disposed on the array substrate or may be disposed on the color filter substrate.
  • the conductive structure 1 When the common electrode is disposed on the array substrate, the conductive structure 1 may be fabricated in the same layer as the common electrode; when the common electrode is disposed on the color filter substrate, the conductive structure 1 may be fabricated in the same layer as the pixel electrode To simplify the production process. In addition, the conductive structure 1 is made of a transparent conductive material and is exposed to the outside and is not easily oxidized.
  • the non-display area of the array substrate further includes a first metal line 2 in the same layer as the gate line and/or a second metal line 3 in the same layer as the data line. Used to transmit signals.
  • the array substrate illustrated in FIGS. 3 and 5 the array substrate further includes first metal wires 2 and second metal wires 3 in a non-display region, positions of the first metal wires 2 and the second metal wires 3 One-to-one and electrically connected, an insulating layer 10 is disposed between the first metal wire 2 and the second metal wire 3, and the first metal wire 2 and the second metal wire 3 are specifically passed through the via 102 in the insulating layer 10. Sexual connection.
  • the conductive structure 1 is in one-to-one correspondence with the first metal wire 2 and the second metal wire 3 and is electrically connected.
  • the array substrate illustrated in FIGS. 4 and 6 in the non-display area of the array substrate, the array substrate includes only one of the first metal line 2 and the second metal line, for example, including only the first The first metal wire 2 of the metal wire 2 and the second metal wire has a conductive structure that is in one-to-one correspondence with the first metal wire and is electrically connected.
  • the array substrate may include only the first metal line 2 and the second metal line of the second metal line, which is similar to FIG. 4 and FIG. No longer indicate.
  • the gate lines and the data lines are made of a metal material, such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and the like, and alloys of these metals, have a small transmission resistance, Reduce power consumption.
  • the technical solution of the present disclosure is to provide an insulating layer 11 in which the conductive structure 1 is located to overcome the problem of poor rubbing orientation caused by static electricity differences.
  • the specific implementation structure may be: after the opening 12 is formed in the insulating layer 11, a transparent conductive material is formed in the opening 12, and the conductive structure 1 is formed by the transparent conductive material, that is, the conductive structure 1 is filled in the opening 12, and is electrically conductive.
  • the surface of the structure 1 is lower than the surface of the insulating layer 11, see Figs. 3 and 4.
  • the insulating layer 11 covering the conductive structure 1 may be formed, and then the opening 12 is opened on the insulating layer 11 to expose the conductive structure 1, that is, the insulating layer 11 is disposed on the conductive structure 1, see FIG. And Figure 6 shows.
  • the technical solution of the present disclosure is applicable to all conductive structures that are exposed in the non-display area, for example, as shown in FIG. 8, the conductive structure connected to the integrated chip and the flexible circuit board 990, and the conductive structure 1 and The positions of the pins 992 of the integrated chip or flexible circuit board 990 are in one-to-one correspondence. Since the conductive structure 1 is located in the opening 12 of the insulating layer 11, in order to facilitate the mounting of the integrated chip and the flexible circuit board, a recess 20 may be formed on the insulating layer 11, as shown in FIGS.
  • the recess 20 and the integrated chip In cooperation with the shape of the flexible circuit board, the recess 20 is in communication with the plurality of openings 12, and when the integrated chip and the flexible circuit board are placed in the recess 20, the pins 992 are inserted into the corresponding openings 12 to fit the conductive structure 1. , to achieve the installation of integrated chips and flexible circuit boards.
  • Some embodiments of the present disclosure further provide a display device 800, as shown in FIG. 9, including the above array substrate to improve the rubbing orientation quality of the alignment film and improve display quality.
  • the display device may specifically be any product or component having a display function, such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a method for fabricating the above array substrate is further provided.
  • the array substrate includes a display area and a non-display area located at a periphery of the display area, and the manufacturing method includes:
  • At least one opening in the non-display area is formed in the insulating layer, the opening being in one-to-one correspondence with a position of the conductive structure, the conductive structure being located in the opening.
  • the array substrate formed by the above steps has a conductive structure located in the opening of the insulating layer, so that the rubbing cloth is not in contact with the conductive material during the rubbing orientation of the oriented film, and the insulating cloth is in contact with the rubbing cloth, and the high-speed friction is generated. There is no difference in static electricity, and there is no difference in the influence of the cloth on the rubbing cloth, ensuring the quality of the rubbing orientation and improving the picture quality.
  • the insulating layer is formed before the alignment of the alignment film.
  • the opening may be formed before rubbing the alignment film, or after rubbing the alignment film.
  • the conductive structure is formed using a transparent conductive material (eg, indium zinc oxide, indium tin oxide) to improve the oxidation resistance of the conductive structure.
  • a transparent conductive material eg, indium zinc oxide, indium tin oxide
  • the conductive structure and the common electrode are formed by a patterning process on the same transparent conductive layer; when the common electrode is disposed on the color filter substrate, the same transparent A patterning process of the conductive layer forms the conductive structure and the pixel electrode to simplify the fabrication process.
  • the method for fabricating the array substrate specifically includes:
  • a conductive structure 1 is formed within the opening 12.
  • the above steps first form an insulating layer and form an opening in the insulating layer, and then fill the opening with a conductive material to form the conductive structure, and ensure that the conductive structure is away from the top surface 930 of the substrate 100 away from the insulating layer 11.
  • the top surface 940 of the substrate 100 is closer to the substrate 100, that is, the top surface 930 of the conductive structure 1 is lower than the top surface 940 of the insulating layer 11, so that the rubbing cloth does not contact the conductive structure when the alignment film is subjected to rubbing orientation, Overcome the problem of poor friction caused by static electricity differences.
  • the array substrate is manufactured.
  • the method specifically includes:
  • Openings 12 are formed in the insulating layer 11, and the openings 12 are in one-to-one correspondence with the positions of the conductive structures 1, exposing the corresponding conductive structures 1.
  • the above steps first form the conductive structure, then form an insulating layer, and form an opening in the insulating layer to expose the conductive structure, since the surface of the conductive structure is lower than the surface of the insulating layer, thereby performing the alignment film In the rubbing orientation, the rubbing cloth is not in contact with the conductive structure, and the problem of poor friction caused by the difference in static electricity is overcome.
  • the conductive structure formed by the above two specific embodiments is exposed, and due to the action of the insulating layer, the rubbing cloth is not in contact with the conductive structure during the rubbing orientation of the alignment film, thereby overcoming the rubbing orientation caused by the static difference. Bad problems.
  • the opening is formed before the alignment film is rubbed, and the manufacturing process of forming the opening is prevented from affecting the orientation of the alignment film.
  • the mask is defaulted, which reduces the production cost.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板及其制作方法、显示装置。所述阵列基板包括绝缘层（11）和位于非显示区域（220）的导电结构（1），所述绝缘层（11）包括至少一个位于非显示区域（220）的开口（12），所述开口（12）与所述导电结构（1）的位置一一对应，所述导电结构（1）位于所述开口（12）内，使得所述导电结构（1）的表面低于所述绝缘层（11）的表面。

Description

阵列基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2016年6月1日在中国提交的中国专利申请号No.201610382094.2的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是涉及一种阵列基板及其制作方法、显示装置。
背景技术
目前，薄膜晶体管液晶显示器(TFT-LCD)已成为主流的显示产品，其显示品质随制造工艺技术的进步而不断优化，随着对产品品质要求的不断提高，继而对制作工艺的要求也越来越高。
TFT-LCD的主体结构为液晶显示面板，液晶显示面板包括对盒的阵列基板和彩膜基板，以及填充在阵列基板和彩膜基板之间的液晶。为了使液晶分子能够正确地取向，会在阵列基板和彩膜基板的显示区域的内侧表面涂上一层取向膜，并通过摩擦取向工艺在取向膜上形成取向沟槽，为液晶分子提供一定的预倾角。
然而，相关技术中的摩擦取向工艺存在由于静电差异等导致的摩擦取向不良问题。
发明内容
本公开提供一种阵列基板及其制作方法、显示装置，用以解决因静电差异导致的取向膜摩擦取向不良问题。
为解决上述技术问题，本公开实施例中提供一种阵列基板，包括显示区域和位于显示区域外围的非显示区域，所述阵列基板包括绝缘层，所述绝缘层包括至少一个位于所述非显示区域的开口，所述阵列基板还包括位于所述非显示区域中的至少一个导电结构，所述开口与所述导电结构的位置一一对 应，所述导电结构位于所述开口内。
如上所述的阵列基板，可选的是，所述导电结构由透明导电材料制得。
如上所述的阵列基板，可选的是，所述阵列基板还包括栅线和数据线，用于限定多个像素区域；
所述阵列基板还包括位于所述非显示区域中并与所述栅线同层的第一金属线和与所述数据线同层的第二金属线，所述第一金属线和所述第二金属线一一对应且电性连接；
所述第一金属线和第二金属线与所述导电结构一一对应且电性连接。
如上所述的阵列基板，可选的是，所述阵列基板还包括栅线和数据线，用于限定多个像素区域；
所述阵列基板还包括位于所述非显示区域中并与所述栅线同层的第一金属线，所述第一金属线与所述导电结构一一对应且电性连接。
如上所述的阵列基板，可选的是，所述阵列基板还包括栅线和数据线，用于限定多个像素区域；
所述阵列基板还包括位于所述非显示区域中并与所述数据线同层的第二金属线，所述第二金属线与所述导电结构一一对应且电性连接。
如上所述的阵列基板，可选的是，所述阵列基板还包括基底；所述绝缘层形成于所述基底上并位于所述非显示区域中；以所述基底为基准，所述绝缘层的高度大于所述导电结构的高度。
如上所述的阵列基板，可选的是，所述阵列基板还包括形成在所述绝缘层上并用于安装集成芯片和柔性电路板中至少一个的凹槽；所述绝缘层还包括多个所述开口；所述凹槽与所述多个开口连通。
本公开实施例中还提供一种显示装置，包括如上所述的阵列基板。
如上所述的显示装置，可选的是，所述显示装置还包括芯片和电路板中的至少一个；所述阵列基板还包括形成在所述绝缘层上并用于安装所述芯片和电路板中至少一个的凹槽；所述绝缘层还包括多个所述开口；所述凹槽与所述多个开口连通；所述芯片和电路板中的至少一个之上的引脚插入对应的所述开口内并在对应的所述开口内部与对应的所述导电结构接触。
本公开实施例中还提供如上所述的阵列基板的制作方法，所述阵列基板 包括显示区域和位于显示区域外围的非显示区域，所述制作方法包括：
形成绝缘层；
在所述绝缘层中形成至少一个位于所述非显示区域的开口；
在所述非显示区域形成至少一个导电结构，所述开口与所述导电结构的位置一一对应，所述导电结构位于所述开口内。
如上所述的制作方法，可选的是，所述制作方法具体包括：
形成所述绝缘层；
在所述绝缘层中形成所述开口；
在所述开口内形成所述导电结构。
如上所述的制作方法，可选的是，所述制作方法具体包括：
形成所述导电结构；
在所述导电结构上形成所述绝缘层；
在所述绝缘层中形成所述开口。
如上所述的制作方法，可选的是，利用透明导电材料形成所述导电结构。
如上所述的制作方法，可选的是，所述阵列基板还包括基底；所述形成绝缘层包括：在所述基底上并在所述非显示区域中形成所述绝缘层。
如上所述的制作方法，可选的是，所述在所述非显示区域形成至少一个导电结构包括：在所述基底上并在所述非显示区域形成所述至少一个导电结构，以所述基底为基准所述绝缘层的高度大于所述导电结构的高度。
本公开的上述技术方案的有益效果如下：
上述技术方案中，所述阵列基板包括绝缘层和位于非显示区域的导电结构，所述绝缘层包括至少一个位于非显示区域的开口，所述开口与所述导电结构的位置一一对应，所述导电结构位于所述开口内，使得所述导电结构的表面低于所述绝缘层的表面，从而在取向膜的摩擦取向过程中，摩擦布不与导电材料接触，与摩擦布接触的均为绝缘材料，高速摩擦产生的静电不存在差异，进而对摩擦布的布毛的影响不存在差异，保证摩擦取向质量，提高画面品质。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1表示相关技术中阵列基板的端子区域的局部剖视图；
图2表示相关技术中阵列基板的端子区域的局部俯视图；
图3表示本公开实施例中阵列基板的局部剖视图一；
图4表示本公开实施例中阵列基板的局部剖视图二；
图5表示本公开实施例中阵列基板的局部剖视图三；
图6表示本公开实施例中阵列基板的局部剖视图四；
图7表示本公开实施例中阵列基板的端子区域的局部俯视图；
图8表示本公开实施例中阵列基板与电路板的连接关系示意图；
图9表示本公开实施例中显示装置的示意图。
具体实施方式
图1表示相关技术中阵列基板的端子区域的局部剖视图。图2表示相关技术中阵列基板的端子区域的局部俯视图。结合图1和图2所示，阵列基板包括位于非显示区域的保护层10′和端子1′。由于保护层10′由绝缘材料制成而端子1′由导电材料制成，因此，在取向膜的摩擦取向过程中，高速摩擦时产生的静电有所差异。静电差异进一步导致静电对摩擦布的布毛的影响存在差异，这将会导致布毛紊乱并造成保护层10′和端子1′相接处的布毛方向不一致，因而直接造成摩擦不良、影响画面品质。
本公开提供一种阵列基板及其制作方法、显示装置，用以解决因静电差异导致的取向膜摩擦取向不良问题。下面将结合附图和实施例，对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
结合图3-图6所示，本实施例中提供一种阵列基板，包括显示区域210(见图9)和位于显示区域外围的非显示区域220(见图9)。阵列基板还包括基底100，以及位于所述非显示区域中并设置在基底100上的至少一个导 电结构1。所述导电结构通常由透明导电材料制得，因为相对于金属材料，透明导电材料不易被氧化。其中，导电结构1可以与像素电极或公共电极同层制作，以简化制作工艺，降低成本。
所述阵列基板还包括设置在基底100上的绝缘层11，绝缘层11包括至少一个位于非显示区域的开口12，开口12与导电结构1的位置一一对应，导电结构1位于开口12内，使得导电结构1远离基底100的表面相对于绝缘层11远离基底100的表面更靠近基底100。
上述阵列基板，导电结构1位于开口12内，使得导电结构1远离基底100的顶表面930相对于绝缘层11远离基底100的顶表面940更靠近基底100，即，导电结构1的顶表面低于绝缘层11的顶表面。换言之，以基底100为基准，绝缘层11的高度大于导电结构1的高度。如此，在取向膜的摩擦取向过程中，摩擦布不与导电材料即导电结构1接触，与摩擦布接触的均为绝缘材料即绝缘层11，高速摩擦产生的静电不存在差异，进而对摩擦布的布毛的影响不存在差异，保证摩擦取向质量，提高画面品质。
所述阵列基板还包括位于显示区域的各显示膜层结构，如：栅线950、数据线960、像素电极970等。其中，所述栅线和数据线用于限定多个像素区域980，每一像素区域包括所述像素电极，所述像素电极与公共电极之间形成驱动液晶分子偏转的电场。所述取向膜用于对液晶分子进行取向，使液晶分子规则排列。所述公共电极可以设置在阵列基板上，也可以设置在彩膜基板上。当所述公共电极设置在阵列基板上时，导电结构1可以与所述公共电极同层制作；当所述公共电极设置在彩膜基板上时，导电结构1可以与所述像素电极同层制作，以简化制作工艺。另外，导电结构1由透明导电材料制得，暴露在外，不易被氧化。
为了降低传输电阻，本实施例中，所述阵列基板的非显示区域还包括与所述栅线同层的第一金属线2和/或与所述数据线同层的第二金属线3，用于传输信号。在图3和图5中示意的阵列基板中，所述阵列基板进一步包括位于非显示区域中的第一金属线2和第二金属线3，第一金属线2和第二金属线3的位置一一对应且电性连接，第一金属线2与第二金属线3之间具有绝缘层10，第一金属线2和第二金属线3具体通过绝缘层10中的过孔102电 性连接。导电结构1与第一金属线2和第二金属线3一一对应且电性连接。在图4和图6中示意的阵列基板中，在所述阵列基板的非显示区域中，所述阵列基板仅包括第一金属线2和第二金属线中之一，例如，仅包括第一金属线2和第二金属线中的第一金属线2，导电结构与第一金属线一一对应且电性连接。在其它实施例中，在所述阵列基板的非显示区域中，所述阵列基板可以仅包括第一金属线2和第二金属线中的第二金属线，这与图4和图6类似，不再示意。由于栅线和数据线由金属材料制得，如：Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，具有较小的传输电阻，降低功耗。
本公开的技术方案通过设置绝缘层11，导电结构1位于开口12内，以克服静电差异导致的摩擦取向不良问题。具体的实现结构可以为：在绝缘层11中形成开口12后，在开口12内形成透明导电材料，由所述透明导电材料形成导电结构1，即，导电结构1填充在开口12内，且导电结构1的表面低于绝缘层11的表面，参见图3和图4所示。也可以在形成导电结构1后，再形成覆盖导电结构1的绝缘层11，然后在绝缘层11上开设开口12，露出导电结构1，即，绝缘层11设置在导电结构1上，参见图5和图6所示。
需要说明的是，本公开的技术方案适用于位于非显示区域的所有需要暴露在外的导电结构，例如：如图8所示，与集成芯片、柔性电路板990连接的导电结构，导电结构1与集成芯片或柔性电路板990的引脚992的位置一一对应。由于导电结构1位于绝缘层11的开口12内，为了方便集成芯片和柔性电路板的安装，可以在绝缘层11上形成凹槽20，如图7和图8所示，凹槽20与集成芯片和柔性电路板的形状配合，凹槽20与多个开口12连通，将集成芯片和柔性电路板放置在凹槽20内时，其引脚992插入对应的开口12内，与导电结构1贴合，实现集成芯片和柔性电路板的安装。
本公开一些实施例中还提供一种显示装置800，如图9所示，包括上述的阵列基板，以提高取向膜的摩擦取向质量，提高显示品质。
所述显示装置具体可以为：液晶显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开一些实施例中还提供一种上述阵列基板的制作方法，所述阵列基板包括显示区域和位于显示区域外围的非显示区域，所述制作方法包括：
形成绝缘层；
在所述绝缘层中形成至少一个位于非显示区域的开口，所述开口与所述导电结构的位置一一对应，所述导电结构位于所述开口内。
通过上述步骤形成的阵列基板，其导电结构位于绝缘层的开口内，从而在取向膜的摩擦取向过程中，摩擦布不与导电材料接触，与摩擦布接触的均为绝缘材料，高速摩擦产生的静电不存在差异，进而对摩擦布的布毛的影响不存在差异，保证摩擦取向质量，提高画面品质。
为了实现上述目的，在对取向膜进行摩擦取向之前形成所述绝缘层。具体可以在对取向膜进行摩擦之前形成所述开口，或在对取向膜进行摩擦之后形成所述开口。
可选的，利用透明导电材料(如：铟锌氧化物、铟锡氧化物)形成所述导电结构，以提高导电结构的抗氧化性。进一步地，当公共电极设置在阵列基板上时，通过对同一透明导电层的构图工艺形成所述导电结构和所述公共电极；当所述公共电极设置在彩膜基板上时，通过对同一透明导电层的构图工艺形成所述导电结构和所述像素电极，以简化制作工艺。
在一个具体的实施方式中，结合图3和图4所示，所述阵列基板的制作方法具体包括：
形成绝缘层11；
在绝缘层11中形成开口12；
在开口12内形成导电结构1。
上述步骤首先形成绝缘层，并在绝缘层中形成开口，然后在所述开口中填充导电材料，形成所述导电结构，并保证所述导电结构远离基底100的顶表面930相对于绝缘层11远离基底100的顶表面940更靠近基底100，即，导电结构1的顶表面930低于绝缘层11的顶表面940，从而在对取向膜进行摩擦取向时，摩擦布不与所述导电结构接触，克服了静电差异造成的摩擦不良问题。
在另一个具体的实施方式中，结合图5和图6所示，所述阵列基板的制 作方法具体包括：
形成导电结构1；
在导电结构1上形成绝缘层11；
在绝缘层11中形成开口12，开口12与导电结构1的位置一一对应，暴露出对应导电结构1。
上述步骤首先形成所述导电结构，然后再形成绝缘层，并在所述绝缘层中形成开口，暴露出所述导电结构，由于导电结构的表面低于绝缘层的表面，从而在对取向膜进行摩擦取向时，摩擦布不与所述导电结构接触，克服了静电差异造成的摩擦不良问题。
上面两个具体实施方式形成的导电结构暴露在外，并且由于绝缘层的作用，在对取向膜进行摩擦取向的过程中，摩擦布不与所述导电结构接触，克服了因静电差异导致的摩擦取向不良问题。可选的，在对取向膜进行摩擦之前形成所述开口，防止形成所述开口的制作工艺影响取向膜的取向作用。另外，在图3和图4所示的具体实施方式中，形成所述导电结构时，缺省了掩膜板，降低了生产成本。
应当理解，本说明书所描述的多个实施例仅用于说明和解释本公开，并不用于限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
以上所述仅是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本公开的保护范围。

Claims (15)

  1. 一种阵列基板，包括显示区域和位于显示区域外围的非显示区域，其中，所述阵列基板包括绝缘层，所述绝缘层包括至少一个位于所述非显示区域的开口，所述阵列基板还包括位于所述非显示区域中的至少一个导电结构，所述开口与所述导电结构的位置一一对应，所述导电结构位于所述开口内。
  2. 根据权利要求1所述的阵列基板，其中，所述导电结构为透明导电材料。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括栅线和数据线，用于限定多个像素区域；
    所述阵列基板还包括位于所述非显示区域中并与所述栅线同层的第一金属线和与所述数据线同层的第二金属线，所述第一金属线和所述第二金属线一一对应且电性连接；
    所述第一金属线和所述第二金属线与所述导电结构一一对应且电性连接。
  4. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括栅线和数据线，用于限定多个像素区域；
    所述阵列基板还包括位于所述非显示区域中并与所述栅线同层的第一金属线，所述第一金属线与所述导电结构一一对应且电性连接。
  5. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括栅线和数据线，用于限定多个像素区域；
    所述阵列基板还包括位于所述非显示区域中并与所述数据线同层的第二金属线，所述第二金属线与所述导电结构一一对应且电性连接。
  6. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括基底；所述绝缘层形成于所述基底上并位于所述非显示区域中；以所述基底为基准，所述绝缘层的高度大于所述导电结构的高度。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括形成在所述绝缘层上并用于安装集成芯片和柔性电路板中至少一个的凹槽；所述绝缘层还包括多个所述开口；所述凹槽与所述多个开口连通。
  8. 一种显示装置，包括权利要求6所述的阵列基板。
  9. 根据权利要求8所述的显示装置，其中，所述显示装置还包括芯片和电路板中的至少一个；
    所述阵列基板还包括形成在所述绝缘层上并用于安装所述芯片和电路板中至少一个的凹槽；所述绝缘层还包括多个所述开口；所述凹槽与所述多个开口连通；
    所述芯片和电路板中的至少一个之上的引脚插入对应的所述开口内并在对应的所述开口内部与对应的所述导电结构接触。
  10. 一种权利要求1-7任一项所述的阵列基板的制作方法，所述阵列基板包括显示区域和位于显示区域外围的非显示区域，所述制作方法包括：
    形成绝缘层；
    在所述绝缘层中形成至少一个开口；
    在所述非显示区域形成至少一个导电结构，所述开口与所述导电结构的位置一一对应，所述导电结构的位于所述开口内。
  11. 根据权利要求10所述的制作方法，其中，所述制作方法具体包括：
    形成所述绝缘层；
    在所述绝缘层中形成所述开口；
    在所述开口内形成所述导电结构。
  12. 根据权利要求10所述的制作方法，其中，所述制作方法具体包括：
    形成所述导电结构；
    在所述导电结构上形成所述绝缘层；
    在所述绝缘层中形成所述开口。
  13. 根据权利要求10所述的制作方法，其中，利用透明导电材料形成所述导电结构。
  14. 根据权利要求10所述的制作方法，其中，所述阵列基板还包括基底；
    所述形成绝缘层包括：在所述基底上并在所述非显示区域中形成所述绝缘层。
  15. 根据权利要求14所述的制作方法，其中，所述在所述非显示区域形成至少一个导电结构包括：在所述基底上并在所述非显示区域形成所述至少 一个导电结构，以所述基底为基准所述绝缘层的高度大于所述导电结构的高度。
PCT/CN2017/079210 2016-06-01 2017-04-01 阵列基板及其制作方法、显示装置 Ceased WO2017206588A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/551,525 US10388673B2 (en) 2016-06-01 2017-04-01 Array substrate, method for manufacturing the same and display device including the array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610382094.2A CN105824162B (zh) 2016-06-01 2016-06-01 阵列基板及其制作方法、显示装置
CN201610382094.2 2016-06-01

Publications (1)

Publication Number Publication Date
WO2017206588A1 true WO2017206588A1 (zh) 2017-12-07

Family

ID=56531868

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/079210 Ceased WO2017206588A1 (zh) 2016-06-01 2017-04-01 阵列基板及其制作方法、显示装置

Country Status (3)

Country Link
US (1) US10388673B2 (zh)
CN (1) CN105824162B (zh)
WO (1) WO2017206588A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105824162B (zh) 2016-06-01 2020-09-01 北京京东方光电科技有限公司 阵列基板及其制作方法、显示装置
CN116360149A (zh) * 2021-12-28 2023-06-30 昇印光电（昆山）股份有限公司 mini LED背光模组和显示装置
CN114384731B (zh) * 2021-12-29 2024-06-28 重庆惠科金渝光电科技有限公司 阵列基板及液晶显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202523709U (zh) * 2012-04-28 2012-11-07 北京京东方光电科技有限公司 一种阵列基板和显示装置
CN203084394U (zh) * 2013-02-20 2013-07-24 北京京东方光电科技有限公司 一种阵列基板及液晶显示装置
CN104570493A (zh) * 2015-01-22 2015-04-29 合肥京东方光电科技有限公司 一种阵列基板母板及其制作方法、静电消除设备
US20150226992A1 (en) * 2013-05-24 2015-08-13 Samsung Display Co., Ltd Array substrate and method of manufacturing the same
CN105206624A (zh) * 2015-10-22 2015-12-30 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板和显示装置
CN105824162A (zh) * 2016-06-01 2016-08-03 北京京东方光电科技有限公司 阵列基板及其制作方法、显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020065690A (ko) * 2001-02-07 2002-08-14 삼성전자 주식회사 액정 표시 장치용 박막 트랜지스터 기판 및 그 제조 방법
JP4517063B2 (ja) * 2003-05-27 2010-08-04 日本電気株式会社 液晶表示装置
JP4082413B2 (ja) * 2005-02-07 2008-04-30 セイコーエプソン株式会社 電気光学装置及びその製造方法、並びに電子機器
US20100289997A1 (en) * 2008-01-21 2010-11-18 Nec Corporation Display device
CN100570896C (zh) * 2008-04-07 2009-12-16 友达光电股份有限公司 薄膜晶体管、主动阵列基板及其制造方法
JP4618337B2 (ja) * 2008-06-17 2011-01-26 ソニー株式会社 表示装置およびその製造方法、ならびに半導体装置およびその製造方法
CN202794786U (zh) * 2012-07-20 2013-03-13 北京京东方光电科技有限公司 一种阵列基板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202523709U (zh) * 2012-04-28 2012-11-07 北京京东方光电科技有限公司 一种阵列基板和显示装置
CN203084394U (zh) * 2013-02-20 2013-07-24 北京京东方光电科技有限公司 一种阵列基板及液晶显示装置
US20150226992A1 (en) * 2013-05-24 2015-08-13 Samsung Display Co., Ltd Array substrate and method of manufacturing the same
CN104570493A (zh) * 2015-01-22 2015-04-29 合肥京东方光电科技有限公司 一种阵列基板母板及其制作方法、静电消除设备
CN105206624A (zh) * 2015-10-22 2015-12-30 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板和显示装置
CN105824162A (zh) * 2016-06-01 2016-08-03 北京京东方光电科技有限公司 阵列基板及其制作方法、显示装置

Also Published As

Publication number Publication date
CN105824162B (zh) 2020-09-01
US10388673B2 (en) 2019-08-20
CN105824162A (zh) 2016-08-03
US20190088682A1 (en) 2019-03-21

Similar Documents

Publication Publication Date Title
US20180246369A1 (en) Liquid Crystal Display Panel, Manufacturing Method Thereof and Display Device
CN111952331A (zh) 微发光二极管显示基板及其制作方法
CN105824161B (zh) 一种液晶显示面板及液晶显示装置
WO2015188492A1 (zh) 阵列基板及显示装置
CN111900176A (zh) 一种阵列基板及其制备方法以及显示面板
WO2019000912A1 (zh) 显示面板及其制造方法、显示装置
US10199397B2 (en) Electrical connection structure, array substrate and display device
CN105093759A (zh) 一种阵列基板及其制备方法、显示面板、显示装置
WO2020215617A1 (zh) 显示装置
CN107833895B (zh) 显示面板及其制造方法、显示装置
WO2015184756A1 (zh) 柔性基板及其制造方法、柔性显示装置
US20260023289A1 (en) Display panel and display device
CN115598891B (zh) 显示面板及显示装置
CN104183607A (zh) 阵列基板及其制造方法、显示装置
WO2017206588A1 (zh) 阵列基板及其制作方法、显示装置
WO2017140058A1 (zh) 阵列基板及其制作方法、显示面板及显示装置
JP2013218126A (ja) 表示装置
CN104020621B (zh) 一种阵列基板及其制备方法、显示装置
US10026758B2 (en) Array substrate, manufacturing method thereof, display panel, and display device
CN103985671B (zh) 阵列基板制备方法和阵列基板、显示装置
CN104409510A (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN109709731B (zh) 一种阵列基板及显示装置
CN110010698B (zh) 薄膜晶体管及其制备方法、显示基板、显示装置
CN204178081U (zh) 彩膜基板、显示面板、显示装置
CN105895637A (zh) 一种阵列基板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17805533

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17805533

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 05/07/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17805533

Country of ref document: EP

Kind code of ref document: A1