WO2017112772A1 - Electrochemical etching of multiple silicon materials - Google Patents

Abstract

Embodiments of the present disclosure pertain to methods of making a plurality of porous silicon materials by exposing a plurality of silicon substrates to hydrofluoric acid in the presence of a current in order to result in the etching of the surfaces of the silicon substrates and the formation of the porous silicon materials from the silicon substrates. The exposure of the silicon substrates to hydrofluoric acid in the presence of a current can occur simultaneously and under ambient conditions. The exposure may also occur in a solution of hydrofluoric acid in a container that houses the silicon substrates. The container may also include an anode and a cathode at opposite ends for supplying current. The methods of the present disclosure may also include a step of separating the porous silicon material from the silicon substrate by gradually increasing the electric current in sequential increments.

Description

TITLE

ELECTROCHEMICAL ETCHING OF MULTIPLE SILICON MATERIALS

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 62/270,312, filed on December 21, 2015. The entirety of the aforementioned application is incorporated herein by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

[0002] Not applicable.

BACKGROUND

[0003] Current methods of making porous silicon materials have numerous limitations, including limited yield and limited scalability. Various embodiments of the present disclosure address the aforementioned limitations.

SUMMARY

[0004] In some embodiments, the present disclosure pertains to methods of making a plurality of porous silicon materials by exposing a plurality of silicon substrates to hydrofluoric acid in the presence of a current. In some embodiments, the exposure results in the etching of the surfaces of the silicon substrates to form the porous silicon materials from the silicon substrates.

[0005] In some embodiments, the exposure of the silicon substrates to hydrofluoric acid in the presence of a current occurs simultaneously and under ambient conditions (e.g., room temperature). In some embodiments, the exposure occurs in a solution of hydrofluoric acid in a container that houses the silicon substrates. In some embodiments, the container contains an anode and a cathode at opposite ends of the container for supplying current. In some embodiments, the silicon substrates are positioned between the anode and the cathode.

[0006] The silicon substrates may be separated from one another by various distances during etching. For instance, in some embodiments, the silicon substrates are separated by distances that range from about 0.5 cm to about 10 cm. In some embodiments, the silicon substrates are separated by distances that range from about 0.5 cm to about 2 cm.

[0007] In some embodiments, the silicon substrates are etched by electrochemical etching under a constant current. In some embodiments, the current ranges from about 50 mA to about 500 mA. In some embodiments, the current ranges from about 50 mA to about 100 mA.

[0008] In some embodiments, the methods of the present disclosure also include a step of separating the porous silicon material from the silicon substrate. In some embodiments, the separation occurs by a gradual increase of the electric current in sequential increments. In some embodiments, the gradual increase of the electric current during the separation step includes an increase of the electric current by about 1-100 mA per sequential increment. In some embodiments, each sequential increment takes from about 1 minute to about 60 minutes.

[0009] In some embodiments, the methods of the present disclosure also include a step of incorporating the porous silicon material as a component of an energy storage device. For instance, in some embodiments, the porous silicon material is utilized as an electrode in the energy storage device. In some embodiments, the porous silicon material is utilized as an anode in the energy storage device. In some embodiments, the energy storage device is a battery.

[0010] The methods of the present disclosure can be utilized to form various types of porous silicon materials. For instance, in some embodiments, the porous silicon materials include a plurality of pores that include nanopores, mesopores, micropores, and combinations thereof.

[0011] In some embodiments, the porous silicon materials include pores that span at least 50% of a thickness of the porous silicon material. In some embodiments, the porous silicon material includes pores that span an entire thickness of the porous silicon material. In some embodiments, the porous silicon materials have a thickness ranging from about 10 micrometers to about 200 micrometers.

FIGURES

[0012] FIGURES 1A-1B provide a scheme of a method of making a plurality of porous silicon materials (FIG. 1A) and an apparatus for making the porous silicon materials (FIG. IB).

[0013] FIGURE 2 shows an exemplary experimental set up for etching a single silicon wafer. [0014] FIGURE 3 shows setups and images related to the etching of multiple silicon wafers. FIG. 3A shows an image of an etching chamber for etching multiple silicon wafers. FIG. 3B shows a bipolar electrode diagram of the etching chamber in FIG. 3A. FIG. 3C shows images of the etched 2-inch diameter silicon wafers. The images are shown from left to right in the same order as in the etching chamber.

[0015] FIGURE 4 shows additional setups and images related to the etching of multiple silicon wafers. FIG. 4A shows an image of an etching chamber for etching multiple silicon wafers. FIGS. 4B-C show images of the electrodes in the etching chamber, including the teflon supported plutonium (pt) mesh cathode (FIG. 4B) and the gold coated anode (FIG. 4C). FIG. 4D shows images of the etched 4-inch diameter silicon wafers. The images are shown from left to right in the same order as in the etching chamber.

[0016] FIGURE 5 provides schematics of an etching chamber for etching multiple silicon wafers. A top view (FIG. 5A) and a side view (FIG. 5B) are shown.

[0017] FIGURE 6 shows a side view schematic of an immersion tank for etching multiple silicon wafers.

[0018] FIGURE 7 shows a top view schematic of an etching chamber for etching multiple silicon wafers.

[0019] FIGURE 8 shows simulation setups for two multiple-wafer etching processes. The simulation geometry (FIG. 8A) and mesh (FIG. 8B) for a first simulation setup that utilizes 2- inch diameter wafers are shown. Also shown is a simulation setup for etching shards of 4-inch diameter wafers (FIG. 8C).

[0020] FIGURE 9 illustrates a mechanism by which separation of porous silicon layers from silicon wafers can occur.

[0021] FIGURE 10 shows an etching chamber for etching four silicon wafers that were placed between two floating electrodes.

[0022] FIGURE 11 shows images of porous silicon wafers formed from etching the silicon wafers in the etching chamber in FIG. 10. The images in FIGS. 11A-C are shown from left to right in the same order as in the etching chamber. [0023] FIGURE 12 shows more detailed images of porous silicon wafers formed from etching silicon wafers in the etching chamber in FIG. 10, including a full image of a silicon wafer (FIG. 12A) and scanning electron microscopy (SEM) images of the silicon wafer (FIGS. 12B-D).

[0024] FIGURE 13 shows additional setups and images related to the etching of multiple silicon wafers. FIGS. 13A-B show images of an etching chamber for etching multiple silicon wafers. FIG. 13C shows images of the etched silicon wafers. The images are shown from left to right in the same order as in the etching chamber.

[0025] FIGURE 14 shows additional setups and images related to the etching of multiple silicon wafers. FIG. 14A shows an image of an etching chamber for etching multiple silicon wafers. FIG. 14B shows images of the etched silicon wafers. The images are shown from left to right in the same order as in the etching chamber.

[0026] FIGURE 15 shows additional images related to the etching of multiple silicon wafers. FIG. 15A shows an image of the etched silicon wafers. The images are shown from left to right in the same order as in the etching chamber. FIGS. 15B-C show SEM images of the etched silicon wafers.

DETAILED DESCRIPTION

[0027] It is to be understood that both the foregoing general description and the following detailed description are illustrative and explanatory, and are not restrictive of the subject matter, as claimed. In this application, the use of the singular includes the plural, the word "a" or "an" means "at least one", and the use of "or" means "and/or", unless specifically stated otherwise. Furthermore, the use of the term "including", as well as other forms, such as "includes" and "included", is not limiting. Also, terms such as "element" or "component" encompass both elements or components comprising one unit and elements or components that comprise more than one unit unless specifically stated otherwise.

[0028] The section headings used herein are for organizational purposes and are not to be construed as limiting the subject matter described. All documents, or portions of documents, cited in this application, including, but not limited to, patents, patent applications, articles, books, and treatises, are hereby expressly incorporated herein by reference in their entirety for any purpose. In the event that one or more of the incorporated literature and similar materials defines a term in a manner that contradicts the definition of that term in this application, this application controls.

[0029] Porous silicon materials are useful for a number of applications. For instance, porous silicon materials find applications in electrochemical systems, such as batteries and supercapacitors. Porous silicon materials also find applications for use as filters and solar cell devices.

[0030] It has been shown that porous silicon materials can be successfully synthesized from a single silicon wafer using an electrochemical hydrofluoric acid (HF) etching process. However, a need exists for methods to increase the yield of porous silicon materials by scaling up the etching process to a multi-wafer design. Various embodiments of the present disclosure address this need.

[0031] In some embodiments, the present disclosure pertains to methods of making a plurality of porous silicon materials at the same time. In some embodiments illustrated in FIG. 1A, the methods of the present disclosure include a step of exposing a plurality of silicon substrates to hydrofluoric acid in the presence of a current (step 10) to result in the etching of the surfaces of the silicon substrates (step 12) and thereby form the plurality of the porous silicon materials from the silicon substrates (step 14). In some embodiments, the methods of the present disclosure also include a step of separating the formed porous silicon materials from the silicon substrate (step 16). In additional embodiments, the methods of the present disclosure also include a step of incorporating the formed porous silicon materials as a component of an energy storage device (step 18).

[0032] Various methods and apparatus may be utilized to form the porous silicon materials of the present disclosure. For instance, in some embodiments illustrated in FIG. IB, container 22 can be utilized to form porous silicon materials. Container 22 includes a solution of hydrofluoric acid 23. Container 22 also includes floating anode 24 and floating cathode 34. In operation, silicon substrates 26, 28, 30, and 32 are placed in container 22 between floating anode 24 and floating cathode 34. This results in the exposure of hydrofluoric acid in solution 23 to the surfaces of silicon substrates 26, 28, 30, and 32. Thereafter, the anode and cathode are utilized to supply a current that results in the electrochemical etching of the surfaces of the silicon substrates, and the formation of the porous silicon materials from the silicon substrates.

[0033] Additional variations of the methods of forming porous silicon materials are set forth herein. In particular, various methods may be utilized to expose various types of silicon substrates to various concentrations of hydrofluoric acid in the presence of various amounts of current to form various types of porous silicon materials. Various methods may also be utilized to separate the formed porous silicon materials from the silicon substrates.

[0034] Hydrofluoric Acid Solutions

[0035] Various methods may be utilized to expose silicon substrates to hydrofluoric acid and current. For instance, in some embodiments, the exposure occurs in a solution that includes hydrofluoric acid (e.g., solution 23 in FIG. IB). In some embodiments, the concentration of the hydrofluoric acid in the solution ranges from about 5% by weight to about 75% by weight of the solution. In some embodiments, the concentration of the hydrofluoric acid in the solution ranges from about 5% by weight to about 50% by weight of the solution. In some embodiments, the concentration of the hydrofluoric acid in the solution ranges from about 10% by weight to about 20% by weight of the solution. In some embodiments, the concentration of the hydrofluoric acid in the solution ranges from about 10% by weight to about 15% by weight of the solution.

[0036] In some embodiments, the solution containing hydrofluoric acid is an electrolyte solution. In some embodiments, the electrolyte solution includes hydrofluoric acid (HF) and N, N- dimethylformamide (DMF). In some embodiments, the DMF to HF ratio in the electrolyte solution can range from about 5: 1 to about 8: 1. In some embodiments, the DMF to HF ratio in the electrolyte solution includes ratios of 5: 1, 7: 1, 7.5: 1, or 8: 1.

[0037] Reaction Conditions

[0038] The exposure of silicon substrates to hydrofluoric acid and current can occur in various environments and under various conditions. For instance, in some embodiments, the exposure of silicon substrates to hydrofluoric acid in the presence of a current occurs simultaneously, where all the silicon substrates are exposed to hydrofluoric acid and current at the same time. In some embodiments, the exposure of the silicon substrates to hydrofluoric acid in the presence of a current occurs under ambient conditions, such as room temperature and atmospheric pressure.

[0039] In some embodiments, the exposure of the silicon substrates to hydrofluoric acid in the presence of a current occurs in a container that houses the silicon substrates (e.g., container 22 in FIG. IB, which houses silicon substrates 26, 28, 30, and 32). In some embodiments, the container includes individual slots for immobilizing the silicon substrates. In some embodiments, the container includes an anode and a cathode at opposite ends (e.g., cathode 34 and anode 24 in FIG. IB). In some embodiments, the silicon substrates are positioned between the anode and the cathode (e.g., silicon substrates 26, 28, 30, and 32 positioned between cathode 34 and anode 24, as shown in FIG. IB).

[0040] In some embodiments, the cathode and the anode are utilized to supply current to the silicon substrates. Various cathodes and anodes may be utilized. For instance, in some embodiments, the cathode is a platinum-based cathode. In some embodiments, the cathode is in the form of a platinum mesh. In some embodiments, the anode is an aluminum-based or gold- based anode. The use of additional cathodes and anodes of various materials, such as copper or carbon nanotubes, can also be envisioned.

[0041] The cathodes and anodes of the present disclosure can have various shapes. For instance, in some embodiments, the cathodes or anodes can be in the shapes of solid foils, meshes, spiral structures, and combinations thereof.

[0042] Currents

[0043] The silicon substrates of the present disclosure can be exposed to various types of currents. For instance, in some embodiments, the silicon substrates of the present disclosure can be exposed to a constant current. In some embodiments, the silicon substrates of the present disclosure can be exposed to a variant current. In some embodiments, the silicon substrates of the present disclosure can be exposed to a gradually increasing current.

[0044] In some embodiments, the silicon substrates of the present disclosure can be exposed to a current between about 50 mA to about 500 mA. In some embodiments, the silicon substrates of the present disclosure can be exposed to a current between about 50 niA to about 250 niA. In some embodiments, the silicon substrates of the present disclosure can be exposed to a current between about 50 mA to about 100 mA. In some embodiments, the silicon substrates of the present disclosure can be exposed to a current between about 60 mA to about 75 mA. In some embodiments, the silicon substrates of the present disclosure are exposed to a constant current of about 60 mA. Additional currents can also be envisioned.

[0045] The silicon substrates of the present disclosure can be exposed to a current for various periods of time. In some embodiments, the silicon substrates of the present disclosure are exposed to a current for a time sufficient to etch the surfaces of the porous silicon materials. In some embodiments, the silicon substrates of the present disclosure are exposed to a current from about 10 minutes to about 10 hours. In some embodiments, the silicon substrates of the present disclosure are exposed to a current from about 10 minutes to about 3 hours. In some embodiments, the silicon substrates of the present disclosure are exposed to a current from about 10 minutes to about 30 minutes.

[0046] In some embodiments, the exposure time of silicon substrates to a current is correlated to the strength of the applied current. For instance, in some embodiments, shorter times are used for higher currents while longer times are used for weaker currents.

[0047] Silicon Substrates

[0048] Various types of silicon substrates may be exposed to hydrofluoric acid and current. For instance, in some embodiments, the silicon substrates include, without limitation, silicon wafers, n-type silicon substrates, p-type silicon substrates, polished silicon substrates, metal-coated silicon substrates, and combinations thereof.

[0049] In some embodiments, the silicon substrates include p-type silicon substrates. In some embodiments, the silicon substrates include metal-coated silicon substrates. In some embodiments, the metal-coated silicon substrates include copper-coated silicon substrates, such as copper plated silicon wafers.

[0050] In some embodiments, the silicon substrates of the present disclosure include polished silicon substrates. In some embodiments, the polished silicon substrates include a polished surface. In some embodiments, the methods of the present disclosure also include a step of polishing the surface of a silicon substrate before its exposure to current and hydrofluoric acid. In some embodiments, the polished surface of a silicon substrate faces a cathode (e.g., polished surfaces of silicon substrates 26, 28, 30 and 32 facing cathode 34, as shown in FIG. IB).

[0051] Various numbers of silicon substrates may be simultaneously exposed to hydrofluoric acid and current. For instance, in some embodiments, at least two silicon substrates are exposed to hydrofluoric acid and current. In some embodiments, more than two silicon substrates are exposed to hydrofluoric acid and current. In some embodiments, at least three silicon substrates are exposed to hydrofluoric acid and current. In some embodiments, at least four silicon substrates are exposed to hydrofluoric acid and current. The use of additional numbers of silicon substrates can also be envisioned.

[0052] The silicon substrates may be separated from one another by various distances during exposure to current and hydrofluoric acid. For instance, in some embodiments, the silicon substrates are separated by distances that range from about 0.5 cm to about 10 cm. In some embodiments, the silicon substrates are separated by distances that range from about 0.5 cm to about 2 cm. In some embodiments, the silicon substrates are separated by about 0.5 cm.

[0053] The plurality of silicon substrates may be aligned in various manners during exposure to current and hydrofluoric acid. For instance, in some embodiments, the silicon substrates may be aligned in different directions. In some embodiments, the silicon substrates may be aligned in the same direction (e.g., silicon substrates 26, 28, 30 and 32 being aligned in the same direction, as shown in FIG. IB).

[0054] The porous silicon substrates of the present disclosure can have various resistivities. For instance, in some embodiments, the porous silicon substrates of the present disclosure can have resistivities that range from about 0.1 ohm-cm to about 25 ohm-cm. In some embodiments, the porous silicon substrates of the present disclosure can have resistivities that range from about 0.1 ohm-cm to about 20 ohm-cm. In some embodiments, the porous silicon substrates of the present disclosure can have resistivities that range from about 0.1 ohm-cm to about 10 ohm-cm. In some embodiments, the porous silicon substrates of the present disclosure can have resistivities that range from about 10 ohm-cm to about 20 ohm-cm. [0055] Etching of Silicon Substrates

[0056] The exposure of silicon substrates to hydrofluoric acid in the presence of a current results in the etching of the surfaces of the silicon substrates and the formation of porous silicon materials from the silicon substrates. Without being bound by theory, it is envisioned that etching can occur by various mechanisms.

[0057] For instance, in some embodiments, etching occurs by electrochemical etching. In some embodiments, etching occurs when fluoride ions from hydrogen fluoride etch the silicon substrate surface as a current is passed through the silicon substrate in a hydrofluoric acid solution. In some embodiments, the fluoride ions etch the side of a silicon substrate facing the negative electrode while the other side of the silicon substrate remains unetched. In some embodiments, the fluoride ions etch the entire thickness of silicon substrates. In some embodiments, the fluoride ions etch a partial thickness of silicon substrates.

[0058] In some embodiments, the depth of etching may be directly related to the strength of the current and the exposure time. For instance, in some embodiments where silicon substrates (e.g., silicon wafers) are 250 microns thick, the etch depths ranged from 10-150 microns.

[0059] Separation of Porous Silicon Materials from Silicon Substrates

[0060] The etching of silicon substrates forms porous silicon materials from the silicon substrates. In additional embodiments, the methods of the present disclosure also include a step of separating the formed porous silicon materials from the silicon substrates. Various methods may be used to separate the formed porous silicon materials from the silicon substrates. For instance, in some embodiments, the separation occurs by physically separating the porous silicon materials from the silicon substrates.

[0061] In some embodiments, the separation of porous silicon materials from silicon substrates occurs by gradually increasing the electric current in sequential increments. In such embodiments, a "lift-off process is implemented, where the increased current results in the separation of the porous silicon materials from the silicon substrates. In some embodiments, a multi-step scheme in which the current is step-wise increased incrementally may be required to achieve the lift-off. [0062] A current can be increased in an amount and for a time period to provide for the separation of porous silicon materials from the silicon substrates. For instance, in some embodiments, the gradual increase of the electric current during the separating step includes an increase of the electric current by about 1-100 mA per sequential increment. In some embodiments, the gradual increase of the electric current during the separating step includes an increase of the electric current by about 1-50 mA per sequential increment. In some embodiments, the gradual increase of the electric current during the separating step includes an increase of the electric current by about 25-50 mA per sequential increment.

[0063] In some embodiments, each sequential increment takes from about 1 minute to about 60 minutes. In some embodiments, each sequential increment takes from about 10 minutes to about 30 minutes. In some embodiments, each sequential increment takes from about 10 minutes to about 20 minutes.

[0064] In more specific embodiments, silicon substrates are exposed to about 75 mA of current for about 3 hours to form porous silicon materials. The "lift off of the porous silicon materials from the silicon substrates is then implemented by increasing the current to about 100 mA for 30 minutes, and then increasing the current to 125 mA for about 10 minutes.

[0065] In additional embodiments, silicon substrates are exposed to about 60 mA of current for about 3 hours to form porous silicon materials. The "lift off of the porous silicon materials from the silicon substrates is then implemented by increasing the current to about 100 mA for 30 minutes, then increasing the current to 150 mA for about 20 minutes, and then increasing the current to 200 mA for another 20 minutes.

[0066] Incorporation of Porous Silicon Materials into Energy Storage Devices

[0067] In some embodiments, the methods of the present disclosure also include a step of incorporating the formed porous silicon materials of the present disclosure into an energy storage device. The formed porous silicon materials of the present disclosure may be utilized as one or more components of energy storage devices. For instance, in some embodiments, the formed porous silicon materials are utilized as an electrode in the energy storage device. In some embodiments, the porous silicon materials may be utilized as an anode in the energy storage device.

[0068] The porous silicon materials of the present disclosure may be incorporated into various energy storage devices. For instance, in some embodiments, the energy storage device includes, without limitation, capacitors, batteries, photovoltaic devices, photovoltaic cells, transistors, current collectors, fuel cell devices, water- splitting devices, and combinations thereof. In some embodiments, the energy storage device includes batteries, such as lithium-ion batteries.

[0069] Porous Silicon Materials

[0070] The methods of the present disclosure can be utilized to form various types of porous silicon materials. In general, the porous silicon materials of the present disclosure include a plurality of pores. In some embodiments, the pores include, without limitation, nanopores, mesopores, micropores, and combinations thereof. In some embodiments, the pores include diameters between about 1 nanometer to about 5 micrometers. In some embodiments, the pores include diameters between about 500 nanometers to about 3 micrometers. In some embodiments, the pores include diameters between about 1 micrometer to about 5 micrometers.

[0071] The porous silicon materials of the present disclosure can also have various porosities. For instance, in some embodiments, the porous silicon materials of the present disclosure have porosities that range from about 10% to about 75%. In some embodiments, the porous silicon materials of the present disclosure have porosities that range from about 25% to about 60%. In some embodiments, the porous silicon materials of the present disclosure have porosities that range from about 40% to about 60%. In some embodiments, the porous silicon materials of the present disclosure have porosities that range from about 45% to about 55%.

[0072] The porous silicon materials of the present disclosure can also have various types of pore spans. For instance, in some embodiments, the porous silicon materials of the present disclosure include pores that span at least 50% of a thickness of the porous silicon material. In some embodiments, the porous silicon materials of the present disclosure include pores that span an entire thickness of the porous silicon material. [0073] The porous silicon materials of the present disclosure can have various thicknesses. For instance, in some embodiments, the porous silicon materials of the present disclosure have a thickness ranging from about 10 micrometers to about 200 micrometers. In some embodiments, the porous silicon materials of the present disclosure have a thickness ranging from about 10 micrometers to about 50 micrometers. In some embodiments, the porous silicon materials of the present disclosure have a thickness ranging from about 20 micrometers to about 25 micrometers.

[0074] The porous silicon materials of the present disclosure can also be in various forms. For instance, in some embodiments, the porous silicon materials of the present disclosure are in the form of a porous silicon layer. In some embodiments, the porous silicon materials of the present disclosure are in the form of a porous silicon film. In some embodiments, the porous silicon materials of the present disclosure are in crystalline form.

[0075] Applications and Advantages

[0076] The methods of the present disclosure can be utilized to form various types of porous silicon materials in a scalable manner. Furthermore, the methods of the present disclosure can occur without requiring multiple steps. For instance, in the some embodiments, the methods of the present disclosure can occur without requiring patterning through lithography. In some embodiments, the methods of the present disclosure can occur under ambient conditions and without requiring vacuum technology.

[0077] Furthermore, the steps in the methods of the present disclosure can be varied in order to produce desired types of porous silicon materials. For instance, in some embodiments, hydrogen fluoride concentration can be varied in order affect mass etch rate, pore width, and pore location. In some embodiments, etching time can be varied in order to affect the pore depth and pore volume. In some embodiments, the substrate (e.g., silicon wafer) doping and environmental conditions, such as temperature, can be used to vary the silicon etch rate and porosity.

[0078] As such, the methods of the present disclosure can be utilized to produce large quantities of porous silicon materials with uniform morphological features while consuming limited time and energy. Moreover, the formed porous silicon materials can be utilized in various devices and structures. For instance, in some embodiments, the formed porous silicon materials of the present disclosure can be used in energy storage devices (e.g., lithium ion batteries, super capacitors, and the like), filters, membranes, sensors, photovoltaic devices, and combinations thereof.

[0079] Additional Embodiments

[0080] Reference will now be made to more specific embodiments of the present disclosure and experimental results that provide support for such embodiments. However, Applicants note that the disclosure herein is for illustrative purposes only and is not intended to limit the scope of the claimed subject matter in any way.

[0081] Example 1. Simultaneous etching of multiple silicon wafers in an HF solution

[0082] In this Example, Applicants demonstrate that the etching of silicon in a hydrofluoric acid (HF) solution can occur with a supply of positive charges (holes) from a silicon substrate. There are different methods of electrochemical etching of silicon in an HF electrolyte depending on the applied current density and HF concentration. At low current density (small amount of holes) and high HF concentration (high amount of fluoride-ions), silicon atoms are selectively dissolved from the silicon substrate with consumption of two holes per silicon atom (e.g. with reaction valence of 2). In this way, pores of various shapes are etched into silicon, and porous silicon is formed. The skeleton of porous silicon remains crystalline.

[0083] In particular, Applicants describe in this Example a process that combines the principles of electrochemical etching and bipolar electrodes (typically used in electro refining, electro winning, and electrolysis). In this process, a p-type silicon wafer is used as the working electrode and platinum is used as the counter electrode in an electrolyte bath of hydrofluoric acid (HF) and N, N-dimethylformamide (DMF). A constant current or voltage is then applied to etch the wafer. Thereafter, F^" ions from HF etch the silicon wafer according to the following equations:

At silicon: Si+6F^"+2H⁺+2h⁺ SiF₆ ^2" + H₂ Eq. 1

Eq. 2

At platinum: 2H⁺ + 2e → H₂ [0084] P-type silicon wafers (10-20 Ohm-cm, (lOO)-Si, thickness ca. 200 μιη) were used in the experiments. The etching process was performed in an assembly of Teflon chamber filled with an electrolyte mixture of HF and DMF (HF/DMF=1:5). A 4 inch silicon wafer sat between a Pt ring cathode on the top and an Al sheet anode beneath (wafer in contact with Al anode). The cathode was grounded and a 60 mA current was supplied through the anode.

[0085] The aforementioned setup, which is illustrated in FIG. 2, can achieve a uniform etching rate across the whole wafer surface to produce a good yield of porous silicon structure, which can subsequently be separated from the un-etched part of the wafer by a "lift-off process using increased current density.

[0086] Applicants envision that the etching rate and the etched pore width are controlled by the electric current density and the ion density. In addition, Applicants envision that the aforementioned parameters are in turn affected by the voltage (electric potential) and the HF concentration in the electrolyte solution. In the single-wafer etching process, the uniform electric current density distribution on the wafer guaranteed the uniform etching rate in favor of porous silicon synthesis, as shown in FIG. 2.

[0087] According to bipolar electrode principle, when an electrically conductive material X is inserted between the anode and the cathode in an ionically conductive solution, the side of X facing the anode becomes cathodic and the other side becomes anodic when an electric current passes. Similarly, when a current is passed through a stack of silicon wafers in an electrolyte solution, the F^" ions etch the side of the wafers facing the negative electrode while the other side of the wafers remains unetched. The etch pattern is similar to a single wafer etching except that in multi-wafer etching there is a possibility of a shunt/leak current. This can be avoided by using adequate seals around the edges of the wafers. The etch produces a layer of porous silicon with a porosity of 30-50% and a pore size of 1-5 μιη, depending on the experimental parameters such as current density, wafer resistivity, electrolyte concentration, and etching time.

[0088] Following the success of single-wafer etching, a multi-wafer etching system was assembled and tested (FIGS. 3-4). The multi-wafer etching was performed in an open-top Teflon chamber with slots to anchor the silicon wafers. The Teflon chamber was filled with an electrolyte solution that contained an HF to DMF ratio of about 1:5. A high surface area platinum (Pt) mesh was used as a cathode at one end of the chamber and a gold (Au)-coated stainless steel plate was used as anode at the other end. About 60 mA of current was applied through the electrodes. Two setups were used: setup A shown in FIG. 3 and setup B shown in FIG. 4.

[0089] In setup A (FIG. 3), four 2 inch silicon wafers were uniformly placed in a chamber with 2 cm spacings in between (FIGS. 3A-B). The wafers were completely immersed in the electrolyte solution. However, not all immersed silicon surfaces were etched as in the single- wafer setup. Only centered areas were etched, leaving a blank band around the edge of each wafer, as shown in FIG. 3C. One hypothesis is that, because the wafers cannot completely block the area facing plate electrodes, there is shunt current in the unblocked region near the corners of the Teflon chamber, which results in the unetched band near the wafer edge.

[0090] To further verify the shunt-current hypothesis, a multi- wafer etching setup B was tested (FIGS. 4A-C). In setup B, a 4-inch silicon wafer was broken into 4 identical shards, and they were uniformly placed in the Teflon etching chamber with the same 2 cm spacing as in setup A in FIGS. 3A-B. In particular, shard #2 was misplaced in the opposite manner of the other three in order to completely block the shunt-current in the corner regions. The same electrolyte concentration and current density as in setup A was used in the experiments.

[0091] The images of the etched wafer in FIG. 4D indicate that shard #1 and #2 were poorly etched while shard #3 and shard #4 had a much larger etched area, which exceeds that of setup A. Applicants envision that the misplaced #2 shard played a role in creating a more uniform current density behind it, and therefore resulted in better etching performance.

[0092] Example 1.1. Apparatus for simultaneously etching multiple silicon wafers

[0093] Silicon wafers (2", boron doped, p-type, single-side polished, 275 + 25 micron thick, and 10-20 Ω cm with face orientation of (100)) were cleaned with a methanol and HF solution (2: 1) and stacked on a holder with all the polished sides facing one direction (FIGS. 5A-B). The distance between the wafers was around 2 cm. The holder was then transferred to a tank (FIG. 6). The master platinum electrodes were placed on either side of the stack. The electrode facing the polished side of the wafers was connected to the negative terminal and the other electrode to the positive terminal (FIG. 7).

[0094] An electrolyte mixture of HF and DMF (1:5) was then slowly poured into the tank. A constant current (60-75mA) was applied between the master electrodes for a determined time depending on the depth of porous silicon layer required. For example, etching the wafers at 60 mA for 3 hours produced a 20-25μιη thick porous silicon layer. In order to remove this porous layer from the underlying bulk wafer, additional steps were required. Incrementally higher current was applied for every few minutes until the porous layer was separated from the bulk silicon.

[0095] Example 1.2. Simulation of current density distribution

[0096] Steady-state simulations of the current density distribution in the etching chamber at equilibrium state were conducted for both multiple-wafer setups A and B. As a first step, a three-dimensional geometry was built to closely simulate the Teflon etching chamber (L x W x H=10cm x 5.85cm x 4.5cm) and inserted silicon wafers. The geometry of the models consists of the following domains, as shown in FIGS. 8A-C: electrodes (end surfaces), silicon wafer surfaces (blue region in the middle), and electrolytes (the bulk volume). Due to the symmetry in setup A, only half of the etching chamber was simulated. However, in setup B, a full-size model was established.

[0097] The three-dimensional geometry was converted to a free-triangle mesh using the default physics-controlled method in the software COMSOL. Finer mesh grids were generated on the electrodes and wafer surface where electrochemical reactions occur. Coarser mesh grids were generated in the bulk electrolyte volume where change was not as significant as on the interface.

The Electric Currents (ec) physics interface (built-in of COMSOL) has been applied to all domains for simulation of the current flow in the model. Electric potential on the anode is fixed at 3V. Other parameters were calculated or measured from the following experimental setup: (1) diameter of wafer: 2 inches; (2) thickness of the wafer: 0.3 mm; (3) conductivity of the Si wafer:

10 S/m; (4) conductivity of electrolyte: 1000 S/m; (5) relative permittivity of Si wafer: 11.68; and (6) relative permittivity of electrolyte: 80.1. The simulation was run on a multi-core PC with Windows 8 OS, COMSOL 4.4, CPU i7-3630QM, and 8G Memory.

[0098] Example 1.3. Separation of porous silicon layers from silicon wafers

[0099] As depicted in FIG. 9, and without being bound by theory, Applicants envision that separation of porous silicon layers from silicon wafers occurs when fluoride ions in HF react with silicon according to current density in accordance with Equation 3 (Eq. 3).

Si(s) + 6HF(aq) H₂SiF₆(aq) + 2H₂(g) Eq. 3

[00100] Thereafter, a "lift off process separates porous silicon (pSi) from unetched wafer by increasing current density.

[00101] Example 2. Multi- wafer etching through the use of floating electrodes

[00102] In this Example, Applicants utilized the experimental setup illustrated in FIG. 10 to etch four 2-inch boron-doped silicon wafers with resistivities that ranged from 10 - 20 ohm-cm and were 279 + 25 microns thick. The wafers were placed between two floating electrodes (i.e., a platinum-based cathode and an anode wire) with the polished wafer sides facing the platinum- based cathode. The wafers were spaced 2 cm apart. Three tests were conducted. In the first test, an electrolyte solution containing 300 ml of DMF and 42 ml of HF was utilized. In the second and third tests, an electrolyte solution containing 300 ml of DMF and 60 ml of HF were utilized. The current applied to the batch of 2-inch silicon wafers for the first test were 66 mA, 75 mA, 80 mA, and 96 mA. This corresponds to current densities of 3.25 mA/cm 2 , 3.8 mA/cm 2 , 3.95 mA/cm 2 , and 4.74 mA/cm 2 , respectively. The current applied to the batch of 2-inch silicon wafers for the second test were 60 mA, 75 mA, 100 mA, 120 mA, 150 mA, 200 mA, and 250 mA. This corresponds to current densities of 2.96 mA/cm 2 , 3.70 mA/cm 2 , 4.93 mA/cm 2 , 5.92 mA/cm 2 , 7.40 mA/cm 2 , 9.87 mA/cm 2 , and 12.33 mA/cm 2. The current applied to the batch of 2- inch silicon wafers for the third test were 75 mA, 100 mA, 150 mA, 200 mA, and 250 mA. This corresponds to current densities of 3.70 mA/cm 2 , 4.93 mA/cm 2 , 7.40 mA/cm 2 , 9.87 mA/cm 2 , and 12.33 mA/cm , respectively. [00103] Images of the formed products are shown in FIGS. 11-12. In particular, images of the etched wafers from the first test, the second test and the third test are shown in FIGS. 11A, 11B, and llC, respectively. A focused image of an etched wafer is shown in FIG. 12A. Scanning electron microscopy images of the etched wafer are shown in FIGS. 12B-D.

[00104] Example 3. Multi-wafer etching through the use of a modified etch unit

[00105] In this Example, Applicants utilized a modified etching unit illustrated in FIGS. 13A-B to etch multiple silicon wafers. In particular, the etching unit was modified to accommodate less electrolyte using chemically inert microcrystalline wax and PTFE sheets. In this example, 2-inch boron-doped silicon wafers with resistivities that ranged from 0.1 - 0.9 ohm - cm or 10-20 ohm- cm and were 279 + 25 microns thick were used.

[00106] The modified etch unit also reduced the gap between the test cell and electrodes, thereby minimizing shunt current. The etch cell was 5.5 cm wide, 10 cm long, and 4.5 cm deep. In addition, a high surface area platinum mesh was used to provide fast removal of hydrogen bubbles typically generated during the etch process and improve the efficiency of the cell. Furthermore, silicon wafers were coated with copper by using a copper platant solution (i.e., via dip coating) to reduce the resistance.

[00107] Applicants observed that the electrolyte required was greatly reduced by the aforementioned modifications. Previously, Applicants used 360 ml of an electrolyte solution to immerse up to half the height of silicon wafers. In this Example, Applicants only needed 204 ml of an electrolyte solution to immerse the entire wafer.

[00108] Although the etch unit was tested with deionized (DI) water to check leakage before test, the unit started to leak during etching. This was accompanied by an increase in the voltage. At the end of 3 hours at a current of 70mA, only a portion of the wafer was under the electrolyte. The level of the electrolyte is equal to the top part of the etched portion. Under the immersed portion, the etch is not uniform (sides were left unetched). Images of the etched wafers are shown in FIG. 13C.

[00109] A similar etching unit illustrated in FIG. 14A was utilized to etch four silicon wafers under similar conditions. The electrolyte solution contained 150 ml of DMF and 30 ml of HF (i.e., a DMF:HF ratio of 5: 1). The silicon wafers were etched using a constant current of 75 niA for 3 hours, 100 niA for 30 minutes, and 125 mA for 10 minutes.

[00110] The images of the etched wafers are shown in FIG. 14B. Applicants observed an increase in the area under the electrolyte. Applicants also observed an increase in the etched area. In addition, the etched areas were brown, similar to single wafer etches. The etched wafer resistivity was about 10-20 ohm-cm.

[00111] The etching unit illustrated in FIG. 14A was also utilized to etch four silicon wafers under slightly different conditions. The electrolyte solution contained 150 ml of DMF and 30 ml of HF (i.e., a DMF:HF ratio of 5: 1). The silicon wafers were etched at a constant current of 60 mA for 3 hours, 100 mA for 30 minutes, 150 mA for 20 minutes, and 200 mA for 20 minutes. The images of the etched wafers are shown in FIG. 15A. Applicants observed an increase in the area under the electrolyte. Applicants also observed an increase in the etched area, where the etched area is grey. In addition, the etched areas were brown, similar to single wafer etches. The etched wafer resistivity was about 0.1 - 0.9 ohm - cm. Scanning electron microscopy images of the fourth etched wafer in FIG. 15A are shown in FIGS. 15B-C.

[00112] Without further elaboration, it is believed that one skilled in the art can, using the description herein, utilize the present disclosure to its fullest extent. The embodiments described herein are to be construed as illustrative and not as constraining the remainder of the disclosure in any way whatsoever. While the embodiments have been shown and described, many variations and modifications thereof can be made by one skilled in the art without departing from the spirit and teachings of the invention. Accordingly, the scope of protection is not limited by the description set out above, but is only limited by the claims, including all equivalents of the subject matter of the claims. The disclosures of all patents, patent applications and publications cited herein are hereby incorporated herein by reference, to the extent that they provide procedural or other details consistent with and supplementary to those set forth herein.

Claims

WHAT IS CLAIMED IS:

1. A method of making a plurality of porous silicon materials, said method comprising: exposing a plurality of silicon substrates to hydrofluoric acid in the presence of a current, wherein the exposing results in the etching of the surfaces of the silicon substrates to form the porous silicon materials from the silicon substrates.

2. The method of claim 1, wherein the exposing of the plurality of silicon substrates to hydrofluoric acid in the presence of a current occurs simultaneously.

3. The method of claim 1, wherein the exposing of the plurality of silicon substrates to hydrofluoric acid in the presence of a current occurs in a solution comprising hydrofluoric acid.

4. The method of claim 1, wherein the exposing of the plurality of silicon substrates to hydrofluoric acid in the presence of a current occurs in a container housing the plurality of silicon substrates.

5. The method of claim 4, wherein the container contains an anode and a cathode at opposite ends of the container, and wherein the plurality of silicon substrates are positioned between the anode and the cathode.

6. The method of claim 5, wherein the cathode and the anode supply the current.

7. The method of claim 1, wherein the exposing of the plurality of silicon substrates to hydrofluoric acid in the presence of a current occurs under ambient conditions.

8. The method of claim 1, wherein the exposing of the plurality of silicon substrates to hydrofluoric acid in the presence of a current occurs at room temperature.

9. The method of claim 1, wherein the exposing of the plurality of silicon substrates to hydrofluoric acid in the presence of a current occurs from about 10 minutes to about 10 hours.

10. The method of claim 1, wherein the exposing of the plurality of silicon substrates to hydrofluoric acid in the presence of a current occurs from about 10 minutes to about 3 hours.

11. The method of claim 1, wherein the exposing of the plurality of silicon substrates to hydrofluoric acid in the presence of a current occurs from about 10 minutes to about 30 minutes.

12. The method of claim 1, wherein the etching comprises electrochemical etching.

13. The method of claim 1, wherein the plurality of silicon substrates comprise at least two silicon substrates.

14. The method of claim 1, wherein the plurality of silicon substrates comprise at least four silicon substrates.

15. The method of claim 1, wherein the plurality of silicon substrates are separated by distances that range from about 0.5 cm to about 10 cm.

16. The method of claim 1, wherein the plurality of silicon substrates are separated by distances that range from about 0.5 cm to about 2 cm.

17. The method of claim 1, wherein the plurality of silicon substrates are selected from the group consisting of silicon wafers, n-type silicon substrates, p-type silicon substrates, polished silicon substrates, metal-coated silicon substrates, and combinations thereof.

18. The method of claim 1, wherein the plurality of silicon substrates comprise p-type silicon substrates.

19. The method of claim 1, wherein the plurality of silicon substrates comprise polished surfaces.

20. The method of claim 19, wherein the polished surfaces face a cathode source.

21. The method of claim 1, wherein the current comprises a constant current.

22. The method of claim 1, wherein the current comprises a variant current.

23. The method of claim 1, wherein the current ranges from about 50 mA to about 500 mA.

24. The method of claim 1, wherein the current ranges from about 50 mA to about 250 mA.

25. The method of claim 1, wherein the current ranges from about 50 mA to about 100 mA.

26. The method of claim 1, further comprising a step of separating the porous silicon material from the silicon substrate.

27. The method of claim 26, wherein the separating comprises a gradual increase of the electric current in sequential increments.

28. The method of claim 27, wherein the gradual increase of the electric current during the separating step comprises an increase of the electric current by about 1-100 mA per sequential increment.

29. The method of claim 27, wherein the gradual increase of the electric current during the separating step comprises an increase of the electric current by about 1-50 mA per sequential increment.

30. The method of claim 27, wherein each sequential increment takes from about 1 minute to about 60 minutes.

31. The method of claim 27, wherein each sequential increment takes from about 10 minutes to about 30 minutes.

32. The method of claim 1, wherein the porous silicon material comprises a plurality of pores selected from the group consisting of nanopores, mesopores, micropores, and combinations thereof.

33. The method of claim 1, wherein the porous silicon material comprises pores with diameters between about 1 nanometers to about 5 micrometers.

34. The method of claim 1, wherein the porous silicon material comprises pores with diameters between about 500 nanometers to about 3 micrometers.

35. The method of claim 1, wherein the porous silicon material comprises pores with diameters between about 1 micrometer to about 5 micrometers.

36. The method of claim 1, wherein the porous silicon material has a thickness ranging from about 10 micrometers to about 200 micrometers.

37. The method of claim 1, wherein the porous silicon material has a thickness ranging from about 10 micrometers to about 50 micrometers.

38. The method of claim 1, wherein the porous silicon material has a thickness ranging from about 20 micrometers to about 25 micrometers.

39. The method of claim 1, wherein the porous silicon material comprises pores that span at least 50% of a thickness of the porous silicon material.

40. The method of claim 1, wherein the porous silicon material comprises pores that span an entire thickness of the porous silicon material.

41. The method of claim 1, further comprising a step of incorporating the porous silicon material as a component of an energy storage device.

42. The method of claim 41, wherein the porous silicon material is utilized as an electrode in the energy storage device.

43. The method of claim 41, wherein the porous silicon material is utilized as an anode in the energy storage device.

44. The method of claim 41, wherein the energy storage device is a battery.